trial-ttcn3_bts_tests:oc2g 93

Took 50 min

All Failed Tests

Name	Age	Duration
TC_chan_act_a51	3	39 sec
TC_chan_act_a52	3	39 sec
TC_chan_act_a53	26	40 sec
TC_chan_act_stress	3	35 sec
TC_chopped_ipa_payload	1	1 min 0 sec
TC_conn_fail_crit	4	39 sec
TC_deact_sacch	26	31 sec
TC_encr_cmd_a51	3	39 sec
TC_encr_cmd_a52	4	40 sec
TC_encr_cmd_a53	26	39 sec
TC_ho_rach	26	41 sec
TC_meas_res_sign_sdcch4	26	40 sec
TC_meas_res_sign_sdcch8	26	40 sec
TC_meas_res_sign_tchf	26	27 sec
TC_meas_res_sign_tchh	26	39 sec
TC_meas_res_sign_tchh_toa256	26	39 sec
TC_ms_pwr_ctrl_constant	1	40 sec
TC_paging_imsi_200percent	3	39 sec
TC_paging_imsi_80percent	3	39 sec
TC_paging_tmsi_200percent	3	40 sec
TC_paging_tmsi_80percent	3	39 sec
TC_rach_content	3	40 sec
TC_rach_content_emerg	3	39 sec
TC_rach_count	3	40 sec
TC_rach_load_count	26	2 sec
TC_rach_load_idle_below_thresh	26	2 sec
TC_rach_load_idle_thresh0	26	2 sec
TC_rach_max_ta	26	39 sec
TC_rll_est_ind	3	29 sec
TC_rll_est_req_ACCH_3	26	40 sec
TC_rll_est_req_DCCH_3	3	39 sec
TC_rll_rel_ind_ACCH_0	26	40 sec
TC_rll_rel_ind_ACCH_3	26	39 sec
TC_rll_rel_ind_DCCH_0	3	39 sec
TC_rll_rel_ind_DCCH_3	3	39 sec
TC_rll_rel_req	26	40 sec
TC_rll_unit_data_ind_ACCH	4	39 sec
TC_rll_unit_data_ind_DCCH	3	40 sec
TC_rll_unit_data_req_ACCH	26	39 sec
TC_rll_unit_data_req_DCCH	3	39 sec
TC_rsl_bs_pwr_static_ass	3	31 sec
TC_rsl_bs_pwr_static_power_control	3	39 sec
TC_rsl_chan_initial_ms_pwr	26	29 sec
TC_rsl_chan_initial_ta	26	40 sec
TC_rsl_modify_encr	26	40 sec
TC_rsl_ms_pwr_ctrl	3	39 sec
TC_rsl_ms_pwr_dyn_active	26	29 sec
TC_rsl_ms_pwr_dyn_active2	26	17 sec
TC_rsl_ms_pwr_dyn_ass_updown	26	17 sec
TC_rsl_ms_pwr_dyn_down	26	17 sec
TC_rsl_ms_pwr_dyn_max	26	17 sec
TC_rsl_ms_pwr_dyn_up	26	17 sec
TC_sacch_chan_act	26	39 sec
TC_sacch_chan_act_ho_async	26	39 sec
TC_sacch_chan_act_ho_sync	26	40 sec
TC_sacch_filling	26	39 sec
TC_sacch_info_mod	26	39 sec
TC_sacch_multi	26	39 sec
TC_sacch_multi_chg	26	40 sec
TC_si_sched_1	3	39 sec
TC_si_sched_13	3	39 sec
TC_si_sched_13_2bis_2ter_2quater	26	40 sec
TC_si_sched_2bis	3	40 sec
TC_si_sched_2quater	26	39 sec
TC_si_sched_2ter	3	39 sec
TC_si_sched_2ter_2bis	3	39 sec
TC_si_sched_default	3	29 sec
TC_tch_sign_l2_fill_frame	26	27 sec
TC_tch_sign_l2_fill_frame_dtxd	26	39 sec
TC_tx_power_ramp_adm_state_change	26	21 sec
TC_tx_power_start_ramp_down_bcch	26	30 sec
TC_tx_power_start_ramp_up_bcch	26	40 sec

All Tests

Class	Failed	Skipped	Passed	Total	Duration
ttcn3_bts_tests	72+1	0	21	93 +1	50 min