ttcn3_bts_tests 93

Took 46 min

All Tests

Name	Age	Duration
TC_chan_act_a51 Regression	3	36 sec
TC_chan_act_a52	3	36 sec
TC_chan_act_a53	26	37 sec
TC_chan_act_react	0	21 sec
TC_chan_act_stress	3	31 sec
TC_chan_act_wrong_nr	0	14 sec
TC_chan_deact_not_active	0	12 sec
TC_chopped_ipa_payload	1	1 min 0 sec
TC_chopped_ipa_ping	0	42 sec
TC_conn_fail_crit Regression	4	36 sec
TC_deact_sacch	26	51 sec
TC_dyn_ipa_pdch_tchf_act	0	12 sec
TC_dyn_ipa_pdch_tchf_act_pdch_act_nack	0	13 sec
TC_dyn_osmo_pdch_tchf_act	0	12 sec
TC_dyn_osmo_pdch_tchh_act	0	12 sec
TC_dyn_osmo_pdch_unsol_deact	0	12 sec
TC_encr_cmd_a51	0	27 sec
TC_encr_cmd_a52	4	22 sec
TC_encr_cmd_a53	26	28 sec
TC_err_rep_wrong_mdisc	0	22 sec
TC_err_rep_wrong_msg_type	0	13 sec
TC_err_rep_wrong_sequence	0	13 sec
TC_ho_rach	26	29 sec
TC_ipa_crcx_mdcx_dlcx_not_active	0	12 sec
TC_ipa_crcx_mdcx_mdcx_dlcx_not_active	0	12 sec
TC_ipa_crcx_sdcch_not_active	0	12 sec
TC_ipa_crcx_twice_not_active	0	12 sec
TC_ipa_dlcx_not_active	0	22 sec
TC_lapdm_selftest	0	24 ms
TC_meas_res_sign_sdcch4	26	37 sec
TC_meas_res_sign_sdcch8	26	37 sec
TC_meas_res_sign_tchf	26	24 sec
TC_meas_res_sign_tchh	26	36 sec
TC_meas_res_sign_tchh_toa256	26	37 sec
TC_ms_pwr_ctrl_constant	1	23 sec
TC_paging_imsi_200percent Regression	3	37 sec
TC_paging_imsi_80percent Regression	3	36 sec
TC_paging_tmsi_200percent	3	37 sec
TC_paging_tmsi_80percent	3	36 sec
TC_rach_content	0	1 min 7 sec
TC_rach_content_emerg	0	1 min 18 sec
TC_rach_count	0	1 min 23 sec
TC_rach_load_count	26	2 sec
TC_rach_load_idle_below_thresh	26	2 sec
TC_rach_load_idle_thresh0	26	2 sec
TC_rach_max_ta	26	23 sec
TC_rll_est_ind Regression	3	29 sec
TC_rll_est_req_ACCH_3	26	37 sec
TC_rll_est_req_DCCH_3 Regression	3	36 sec
TC_rll_rel_ind_ACCH_0	26	36 sec
TC_rll_rel_ind_ACCH_3	26	36 sec
TC_rll_rel_ind_DCCH_0 Regression	3	37 sec
TC_rll_rel_ind_DCCH_3 Regression	3	37 sec
TC_rll_rel_req	26	37 sec
TC_rll_unit_data_ind_ACCH Regression	4	42 sec
TC_rll_unit_data_ind_DCCH Regression	3	37 sec
TC_rll_unit_data_req_ACCH	26	37 sec
TC_rll_unit_data_req_DCCH Regression	3	37 sec
TC_rsl_bs_pwr_static_ass Regression	3	29 sec
TC_rsl_bs_pwr_static_power_control Regression	3	36 sec
TC_rsl_chan_initial_ms_pwr	26	28 sec
TC_rsl_chan_initial_ta	26	36 sec
TC_rsl_ie_content_error	0	12 sec
TC_rsl_mand_ie_error	0	12 sec
TC_rsl_modify_encr	26	42 sec
TC_rsl_ms_pwr_ctrl	3	37 sec
TC_rsl_ms_pwr_dyn_active	26	22 sec
TC_rsl_ms_pwr_dyn_active2	26	12 sec
TC_rsl_ms_pwr_dyn_ass_updown	26	12 sec
TC_rsl_ms_pwr_dyn_down	26	12 sec
TC_rsl_ms_pwr_dyn_max	26	12 sec
TC_rsl_ms_pwr_dyn_up	26	12 sec
TC_rsl_protocol_error	0	22 sec
TC_sacch_chan_act	26	37 sec
TC_sacch_chan_act_ho_async	26	21 sec
TC_sacch_chan_act_ho_sync	26	13 sec
TC_sacch_filling	26	40 sec
TC_sacch_info_mod	26	40 sec
TC_sacch_multi	26	58 sec
TC_sacch_multi_chg	26	59 sec
TC_si_sched_1 Regression	3	36 sec
TC_si_sched_13	3	37 sec
TC_si_sched_13_2bis_2ter_2quater	26	47 sec
TC_si_sched_2bis	3	37 sec
TC_si_sched_2quater	26	37 sec
TC_si_sched_2ter Regression	3	37 sec
TC_si_sched_2ter_2bis Regression	3	37 sec
TC_si_sched_default Regression	3	27 sec
TC_tch_sign_l2_fill_frame	26	19 sec
TC_tch_sign_l2_fill_frame_dtxd	26	32 sec
TC_tx_power_ramp_adm_state_change	26	16 sec
TC_tx_power_start_ramp_down_bcch	26	24 sec
TC_tx_power_start_ramp_up_bcch	26	37 sec