trial-ttcn3_bts_tests:trx 128

Took 37 min

All Failed Tests

Name	Age	Duration
TC_chan_act_a53	26	13 sec
TC_deact_sacch	26	46 sec
TC_encr_cmd_a53	26	14 sec
TC_ho_rach	26	16 sec
TC_ipa_crcx_sdcch_not_active	3	10 sec
TC_meas_res_sign_sdcch4	26	11 sec
TC_meas_res_sign_sdcch8	26	12 sec
TC_meas_res_sign_tchf	26	7.8 sec
TC_meas_res_sign_tchh	26	12 sec
TC_meas_res_sign_tchh_toa256	26	11 sec
TC_ms_pwr_ctrl_constant	1	11 sec
TC_pcu_data_ind_lqual_cb	8	14 sec
TC_pcu_ext_rach_content	8	13 sec
TC_pcu_oml_alert	8	13 sec
TC_pcu_ptcch	8	19 sec
TC_pcu_socket_connect_si3gprs	4	18 sec
TC_pcu_socket_nsvc_ipv4	8	2 sec
TC_pcu_socket_nsvc_ipv6	8	2 sec
TC_pcu_socket_verify_info_ind	2	13 sec
TC_rach_load_count	26	2 sec
TC_rach_load_idle_below_thresh	26	2 sec
TC_rach_load_idle_thresh0	26	2 sec
TC_rach_max_ta	26	11 sec
TC_rll_est_req_ACCH_3	26	15 sec
TC_rll_rel_ind_ACCH_0	26	16 sec
TC_rll_rel_ind_ACCH_3	26	17 sec
TC_rll_rel_ind_DCCH_3	3	19 sec
TC_rll_rel_req	26	21 sec
TC_rll_unit_data_req_ACCH	26	15 sec
TC_rsl_chan_initial_ms_pwr	26	15 sec
TC_rsl_chan_initial_ta	26	12 sec
TC_rsl_modify_encr	26	11 sec
TC_rsl_ms_pwr_ctrl	3	1 min 14 sec
TC_rsl_ms_pwr_dyn_active	26	11 sec
TC_rsl_ms_pwr_dyn_active2	26	10 sec
TC_rsl_ms_pwr_dyn_ass_updown	26	10 sec
TC_rsl_ms_pwr_dyn_down	26	10 sec
TC_rsl_ms_pwr_dyn_max	26	10 sec
TC_rsl_ms_pwr_dyn_up	26	10 sec
TC_sacch_chan_act	26	26 sec
TC_sacch_chan_act_ho_async	26	10 sec
TC_sacch_chan_act_ho_sync	26	10 sec
TC_sacch_filling	26	21 sec
TC_sacch_info_mod	26	27 sec
TC_sacch_multi	26	18 sec
TC_sacch_multi_chg	26	48 sec
TC_si_sched_13_2bis_2ter_2quater	26	26 sec
TC_si_sched_2quater	26	26 sec
TC_tch_sign_l2_fill_frame	26	17 sec
TC_tch_sign_l2_fill_frame_dtxd	26	12 sec
TC_tx_power_ramp_adm_state_change	26	6.8 sec
TC_tx_power_start_ramp_down_bcch	26	12 sec
TC_tx_power_start_ramp_up_bcch	26	10 sec

All Tests

Class	Failed	Skipped	Passed	Total	Duration
ttcn3_bts_tests	53-55	0	75+56	128 +1	37 min