trial-ttcn3_bts_tests:oc2g 96

Took 52 min

All Failed Tests

Name	Age	Duration
TC_chan_act_a51	1	39 sec
TC_chan_act_a52	1	40 sec
TC_chan_act_a53	27	40 sec
TC_chan_act_stress	1	35 sec
TC_chopped_ipa_payload	1	1 min 0 sec
TC_conn_fail_crit	1	40 sec
TC_deact_sacch	27	31 sec
TC_encr_cmd_a51	1	39 sec
TC_encr_cmd_a52	1	40 sec
TC_encr_cmd_a53	27	40 sec
TC_ho_rach	27	40 sec
TC_meas_res_sign_sdcch4	27	40 sec
TC_meas_res_sign_sdcch8	27	39 sec
TC_meas_res_sign_tchf	27	40 sec
TC_meas_res_sign_tchh	27	39 sec
TC_meas_res_sign_tchh_toa256	27	39 sec
TC_meas_res_speech_tchf	1	28 sec
TC_meas_res_speech_tchh	1	39 sec
TC_ms_pwr_ctrl_constant	2	40 sec
TC_ms_pwr_ctrl_pf_ewma	1	39 sec
TC_paging_imsi_200percent	1	40 sec
TC_paging_imsi_80percent	1	40 sec
TC_paging_tmsi_200percent	1	40 sec
TC_paging_tmsi_80percent	1	39 sec
TC_rach_content	1	40 sec
TC_rach_content_emerg	1	39 sec
TC_rach_count	1	40 sec
TC_rach_load_count	27	2 sec
TC_rach_load_idle_below_thresh	27	2 sec
TC_rach_load_idle_thresh0	27	2 sec
TC_rach_max_ta	27	40 sec
TC_rll_est_ind	1	29 sec
TC_rll_est_req_ACCH_3	27	40 sec
TC_rll_est_req_DCCH_3	1	39 sec
TC_rll_rel_ind_ACCH_0	27	39 sec
TC_rll_rel_ind_ACCH_3	27	40 sec
TC_rll_rel_ind_DCCH_0	1	39 sec
TC_rll_rel_ind_DCCH_3	4	40 sec
TC_rll_rel_req	27	39 sec
TC_rll_unit_data_ind_ACCH	1	40 sec
TC_rll_unit_data_ind_DCCH	1	40 sec
TC_rll_unit_data_req_ACCH	27	39 sec
TC_rll_unit_data_req_DCCH	1	39 sec
TC_rsl_bs_pwr_static_ass	1	31 sec
TC_rsl_bs_pwr_static_power_control	1	39 sec
TC_rsl_chan_initial_ms_pwr	27	29 sec
TC_rsl_chan_initial_ta	27	40 sec
TC_rsl_modify_encr	27	39 sec
TC_rsl_ms_pwr_ctrl	4	39 sec
TC_rsl_ms_pwr_dyn_active	27	29 sec
TC_rsl_ms_pwr_dyn_active2	27	17 sec
TC_rsl_ms_pwr_dyn_ass_updown	27	17 sec
TC_rsl_ms_pwr_dyn_down	27	17 sec
TC_rsl_ms_pwr_dyn_max	27	17 sec
TC_rsl_ms_pwr_dyn_up	27	17 sec
TC_sacch_chan_act	27	40 sec
TC_sacch_chan_act_ho_async	27	39 sec
TC_sacch_chan_act_ho_sync	27	39 sec
TC_sacch_filling	27	39 sec
TC_sacch_info_mod	27	40 sec
TC_sacch_multi	27	39 sec
TC_sacch_multi_chg	27	39 sec
TC_si_sched_1	1	39 sec
TC_si_sched_13	1	40 sec
TC_si_sched_13_2bis_2ter_2quater	27	39 sec
TC_si_sched_2bis	1	40 sec
TC_si_sched_2quater	27	39 sec
TC_si_sched_2ter	1	39 sec
TC_si_sched_2ter_2bis	1	40 sec
TC_si_sched_default	1	29 sec
TC_tch_sign_l2_fill_frame	27	27 sec
TC_tch_sign_l2_fill_frame_dtxd	27	39 sec
TC_tx_power_ramp_adm_state_change	27	21 sec
TC_tx_power_start_ramp_down_bcch	27	30 sec
TC_tx_power_start_ramp_up_bcch	27	40 sec

All Tests

Class	Failed	Skipped	Passed	Total	Duration
ttcn3_bts_tests	75+3	0	21	96 +3	52 min