ttcn3_bts_tests 96

Took 43 min

All Tests

Name	Age	Duration
TC_chan_act_a51	1	30 sec
TC_chan_act_a52	1	30 sec
TC_chan_act_a53	27	30 sec
TC_chan_act_react	0	21 sec
TC_chan_act_stress	1	31 sec
TC_chan_act_wrong_nr	0	14 sec
TC_chan_deact_not_active	0	12 sec
TC_chopped_ipa_payload	1	1 min 0 sec
TC_chopped_ipa_ping	0	42 sec
TC_conn_fail_crit Fixed	0	39 sec
TC_deact_sacch	27	51 sec
TC_dyn_ipa_pdch_tchf_act	0	12 sec
TC_dyn_ipa_pdch_tchf_act_pdch_act_nack	0	12 sec
TC_dyn_osmo_pdch_tchf_act	0	12 sec
TC_dyn_osmo_pdch_tchh_act	0	12 sec
TC_dyn_osmo_pdch_unsol_deact	0	13 sec
TC_encr_cmd_a51 Regression	1	30 sec
TC_encr_cmd_a52	1	30 sec
TC_encr_cmd_a53	27	40 sec
TC_err_rep_wrong_mdisc	0	22 sec
TC_err_rep_wrong_msg_type	0	12 sec
TC_err_rep_wrong_sequence	0	13 sec
TC_ho_rach	27	19 sec
TC_ipa_crcx_mdcx_dlcx_not_active	0	12 sec
TC_ipa_crcx_mdcx_mdcx_dlcx_not_active	0	12 sec
TC_ipa_crcx_sdcch_not_active	0	12 sec
TC_ipa_crcx_twice_not_active	0	12 sec
TC_ipa_dlcx_not_active	0	21 sec
TC_lapdm_selftest	0	26 ms
TC_meas_res_sign_sdcch4	27	17 sec
TC_meas_res_sign_sdcch8	27	17 sec
TC_meas_res_sign_tchf	27	31 sec
TC_meas_res_sign_tchh	27	23 sec
TC_meas_res_sign_tchh_toa256	27	16 sec
TC_meas_res_speech_tchf	1	8.9 sec
TC_meas_res_speech_tchh	1	16 sec
TC_ms_pwr_ctrl_constant	2	23 sec
TC_ms_pwr_ctrl_pf_ewma	1	14 sec
TC_paging_imsi_200percent Fixed	0	55 sec
TC_paging_imsi_80percent Fixed	0	44 sec
TC_paging_tmsi_200percent	1	49 sec
TC_paging_tmsi_80percent	1	43 sec
TC_rach_content	0	1 min 16 sec
TC_rach_content_emerg	0	1 min 18 sec
TC_rach_count	0	1 min 13 sec
TC_rach_load_count	27	2 sec
TC_rach_load_idle_below_thresh	27	2 sec
TC_rach_load_idle_thresh0	27	2 sec
TC_rach_max_ta	27	23 sec
TC_rll_est_ind	1	21 sec
TC_rll_est_req_ACCH_3	27	30 sec
TC_rll_est_req_DCCH_3	1	30 sec
TC_rll_rel_ind_ACCH_0	27	30 sec
TC_rll_rel_ind_ACCH_3	27	30 sec
TC_rll_rel_ind_DCCH_0	1	30 sec
TC_rll_rel_ind_DCCH_3	4	30 sec
TC_rll_rel_req	27	30 sec
TC_rll_unit_data_ind_ACCH	1	30 sec
TC_rll_unit_data_ind_DCCH	1	30 sec
TC_rll_unit_data_req_ACCH	27	30 sec
TC_rll_unit_data_req_DCCH	1	30 sec
TC_rsl_bs_pwr_static_ass Fixed	0	18 sec
TC_rsl_bs_pwr_static_power_control Fixed	0	20 sec
TC_rsl_chan_initial_ms_pwr	27	26 sec
TC_rsl_chan_initial_ta	27	21 sec
TC_rsl_ie_content_error	0	12 sec
TC_rsl_mand_ie_error	0	12 sec
TC_rsl_modify_encr	27	22 sec
TC_rsl_ms_pwr_ctrl	4	1 min 21 sec
TC_rsl_ms_pwr_dyn_active	27	22 sec
TC_rsl_ms_pwr_dyn_active2	27	12 sec
TC_rsl_ms_pwr_dyn_ass_updown	27	12 sec
TC_rsl_ms_pwr_dyn_down	27	12 sec
TC_rsl_ms_pwr_dyn_max	27	12 sec
TC_rsl_ms_pwr_dyn_up	27	12 sec
TC_rsl_protocol_error	0	21 sec
TC_sacch_chan_act	27	36 sec
TC_sacch_chan_act_ho_async	27	21 sec
TC_sacch_chan_act_ho_sync	27	13 sec
TC_sacch_filling	27	33 sec
TC_sacch_info_mod	27	47 sec
TC_sacch_multi	27	49 sec
TC_sacch_multi_chg	27	59 sec
TC_si_sched_1 Fixed	0	28 sec
TC_si_sched_13	1	30 sec
TC_si_sched_13_2bis_2ter_2quater	27	36 sec
TC_si_sched_2bis Fixed	0	28 sec
TC_si_sched_2quater	27	36 sec
TC_si_sched_2ter Fixed	0	28 sec
TC_si_sched_2ter_2bis Fixed	0	28 sec
TC_si_sched_default Fixed	0	20 sec
TC_tch_sign_l2_fill_frame	27	18 sec
TC_tch_sign_l2_fill_frame_dtxd	27	30 sec
TC_tx_power_ramp_adm_state_change	27	16 sec
TC_tx_power_start_ramp_down_bcch	27	16 sec
TC_tx_power_start_ramp_up_bcch	27	15 sec