ttcn3_bts_tests 131

Took 42 min

All Tests

Name	Age	Duration
TC_chan_act_a51 Regression	1	23 sec
TC_chan_act_a52 Regression	1	22 sec
TC_chan_act_a53	27	23 sec
TC_chan_act_react	0	10 sec
TC_chan_act_stress	0	21 sec
TC_chan_act_wrong_nr	0	12 sec
TC_chan_deact_not_active	0	10 sec
TC_chopped_ipa_payload	0	43 sec
TC_chopped_ipa_ping	0	31 sec
TC_conn_fail_crit Regression	1	22 sec
TC_deact_sacch	27	46 sec
TC_dyn_ipa_pdch_act_deact	0	13 sec
TC_dyn_ipa_pdch_act_tchf_act_nack	0	10 sec
TC_dyn_ipa_pdch_tchf_act	0	10 sec
TC_dyn_ipa_pdch_tchf_act_pdch_act_nack	0	10 sec
TC_dyn_osmo_pdch_act_deact	0	14 sec
TC_dyn_osmo_pdch_double_act	0	10 sec
TC_dyn_osmo_pdch_tchf_act	0	5.4 sec
TC_dyn_osmo_pdch_tchh_act	0	10 sec
TC_dyn_osmo_pdch_unsol_deact	0	6.6 sec
TC_encr_cmd_a51 Regression	1	22 sec
TC_encr_cmd_a52 Regression	1	22 sec
TC_encr_cmd_a53	27	22 sec
TC_err_rep_wrong_mdisc	0	11 sec
TC_err_rep_wrong_msg_type	0	10 sec
TC_err_rep_wrong_sequence	0	10 sec
TC_ho_rach	27	15 sec
TC_ipa_crcx_mdcx_dlcx_not_active	0	10 sec
TC_ipa_crcx_mdcx_mdcx_dlcx_not_active	0	10 sec
TC_ipa_crcx_sdcch_not_active	4	10 sec
TC_ipa_crcx_twice_not_active	0	11 sec
TC_ipa_dlcx_not_active	0	11 sec
TC_lapdm_selftest	0	32 ms
TC_meas_res_sign_sdcch4	27	22 sec
TC_meas_res_sign_sdcch8	27	22 sec
TC_meas_res_sign_tchf	27	22 sec
TC_meas_res_sign_tchh	27	22 sec
TC_meas_res_sign_tchh_toa256	27	22 sec
TC_meas_res_speech_tchf	1	18 sec
TC_meas_res_speech_tchh	1	22 sec
TC_ms_pwr_ctrl_constant	2	22 sec
TC_ms_pwr_ctrl_pf_ewma	1	23 sec
TC_paging_imsi_200percent Regression	1	22 sec
TC_paging_imsi_80percent Regression	1	22 sec
TC_paging_tmsi_200percent Regression	1	22 sec
TC_paging_tmsi_80percent Regression	1	22 sec
TC_pcu_act_req	0	13 sec
TC_pcu_act_req_wrong_bts	0	16 sec
TC_pcu_act_req_wrong_trx	0	16 sec
TC_pcu_act_req_wrong_ts	0	16 sec
TC_pcu_data_ind_lqual_cb	9	22 sec
TC_pcu_data_req_agch Regression	1	23 sec
TC_pcu_data_req_imm_ass_pch Regression	1	22 sec
TC_pcu_data_req_pch Regression	1	22 sec
TC_pcu_deact_req	0	18 sec
TC_pcu_deact_req_wrong_ts	0	14 sec
TC_pcu_ext_rach_content	9	22 sec
TC_pcu_info_ind_fh_params	0	10 sec
TC_pcu_oml_alert	9	13 sec
TC_pcu_paging_from_rsl	0	12 sec
TC_pcu_ptcch	9	22 sec
TC_pcu_rach_content Regression	1	22 sec
TC_pcu_rr_suspend Regression	1	22 sec
TC_pcu_rts_req	0	18 sec
TC_pcu_socket_connect_multi	0	15 sec
TC_pcu_socket_connect_si3gprs	5	22 sec
TC_pcu_socket_connect_si4gprs Regression	1	23 sec
TC_pcu_socket_disconnect_nosi3gprs Regression	1	22 sec
TC_pcu_socket_disconnect_nosi4gprs Regression	1	22 sec
TC_pcu_socket_noconnect_nosi3gprs Regression	1	18 sec
TC_pcu_socket_noconnect_nosi4gprs Regression	1	18 sec
TC_pcu_socket_nsvc_ipv4	9	2 sec
TC_pcu_socket_nsvc_ipv6	9	2 sec
TC_pcu_socket_reconnect	0	12 sec
TC_pcu_socket_verify_info_ind	3	13 sec
TC_pcu_time_ind	0	18 sec
TC_pcu_ver_si13	0	10 sec
TC_rach_content	0	1 min 8 sec
TC_rach_content_emerg	0	1 min 10 sec
TC_rach_count	0	1 min 4 sec
TC_rach_load_count	27	2 sec
TC_rach_load_idle_below_thresh	27	2 sec
TC_rach_load_idle_thresh0	27	2 sec
TC_rach_max_ta	27	12 sec
TC_rll_est_ind Regression	1	22 sec
TC_rll_est_req_ACCH_3	27	22 sec
TC_rll_est_req_DCCH_3 Regression	1	23 sec
TC_rll_rel_ind_ACCH_0	27	22 sec
TC_rll_rel_ind_ACCH_3	27	22 sec
TC_rll_rel_ind_DCCH_0 Regression	1	22 sec
TC_rll_rel_ind_DCCH_3	4	22 sec
TC_rll_rel_req	27	22 sec
TC_rll_unit_data_ind_ACCH Regression	1	22 sec
TC_rll_unit_data_ind_DCCH Regression	1	22 sec
TC_rll_unit_data_req_ACCH	27	22 sec
TC_rll_unit_data_req_DCCH Regression	1	22 sec
TC_rsl_bs_pwr_static_ass Regression	1	22 sec
TC_rsl_bs_pwr_static_power_control Regression	1	23 sec
TC_rsl_chan_initial_ms_pwr	27	22 sec
TC_rsl_chan_initial_ta	27	23 sec
TC_rsl_ie_content_error	0	10 sec
TC_rsl_mand_ie_error	0	10 sec
TC_rsl_modify_encr	27	22 sec
TC_rsl_ms_pwr_ctrl	4	22 sec
TC_rsl_ms_pwr_dyn_active	27	11 sec
TC_rsl_ms_pwr_dyn_active2	27	10 sec
TC_rsl_ms_pwr_dyn_ass_updown	27	10 sec
TC_rsl_ms_pwr_dyn_down	27	10 sec
TC_rsl_ms_pwr_dyn_max	27	10 sec
TC_rsl_ms_pwr_dyn_up	27	10 sec
TC_rsl_protocol_error	0	11 sec
TC_sacch_chan_act	27	27 sec
TC_sacch_chan_act_ho_async	27	11 sec
TC_sacch_chan_act_ho_sync	27	10 sec
TC_sacch_filling	27	21 sec
TC_sacch_info_mod	27	28 sec
TC_sacch_multi	27	41 sec
TC_sacch_multi_chg	27	50 sec
TC_si_sched_1 Regression	1	22 sec
TC_si_sched_13 Regression	1	22 sec
TC_si_sched_13_2bis_2ter_2quater	27	22 sec
TC_si_sched_2bis Regression	1	22 sec
TC_si_sched_2quater	27	22 sec
TC_si_sched_2ter Regression	1	22 sec
TC_si_sched_2ter_2bis Regression	1	22 sec
TC_si_sched_default Regression	1	22 sec
TC_tch_sign_l2_fill_frame	27	20 sec
TC_tch_sign_l2_fill_frame_dtxd	27	23 sec
TC_tx_power_ramp_adm_state_change	27	12 sec
TC_tx_power_start_ramp_down_bcch	27	13 sec
TC_tx_power_start_ramp_up_bcch	27	22 sec