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osmo-gsm-tester_ttcn3
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trial-ttcn3_bts_tests:oc2g
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trial-ttcn3_bts_tests:oc2g
97
79
18
Took 52 min
All Failed Tests
Name
Age
Duration
TC_chan_act_a51
2
39 sec
TC_chan_act_a52
2
40 sec
TC_chan_act_a53
28
39 sec
TC_chan_act_react
Regression
1
18 sec
TC_chan_act_stress
1
10 sec
TC_conn_fail_crit
2
39 sec
TC_deact_sacch
28
31 sec
TC_dyn_ipa_pdch_tchf_act
Regression
1
17 sec
TC_dyn_ipa_pdch_tchf_act_pdch_act_nack
Regression
1
17 sec
TC_encr_cmd_a51
2
40 sec
TC_encr_cmd_a52
2
40 sec
TC_encr_cmd_a53
28
40 sec
TC_err_rep_wrong_msg_type
Regression
1
17 sec
TC_ho_rach
28
40 sec
TC_meas_res_sign_sdcch4
28
40 sec
TC_meas_res_sign_sdcch8
28
39 sec
TC_meas_res_sign_tchf
28
40 sec
TC_meas_res_sign_tchh
28
39 sec
TC_meas_res_sign_tchh_toa256
28
40 sec
TC_meas_res_speech_tchf
2
27 sec
TC_meas_res_speech_tchh
2
39 sec
TC_meas_res_speech_tchh_toa256
1
39 sec
TC_ms_pwr_ctrl_constant
3
39 sec
TC_ms_pwr_ctrl_pf_ewma
2
39 sec
TC_paging_imsi_200percent
2
40 sec
TC_paging_imsi_80percent
2
40 sec
TC_paging_tmsi_200percent
2
39 sec
TC_paging_tmsi_80percent
2
39 sec
TC_rach_content
1
40 sec
TC_rach_content_emerg
1
39 sec
TC_rach_count
1
40 sec
TC_rach_load_count
28
2 sec
TC_rach_load_idle_below_thresh
28
2 sec
TC_rach_load_idle_thresh0
28
2 sec
TC_rach_max_ta
28
39 sec
TC_rll_est_ind
2
29 sec
TC_rll_est_req_ACCH_3
28
40 sec
TC_rll_est_req_DCCH_3
2
39 sec
TC_rll_rel_ind_ACCH_0
28
40 sec
TC_rll_rel_ind_ACCH_3
28
39 sec
TC_rll_rel_ind_DCCH_0
2
39 sec
TC_rll_rel_ind_DCCH_3
5
40 sec
TC_rll_rel_req
28
39 sec
TC_rll_unit_data_ind_ACCH
2
40 sec
TC_rll_unit_data_ind_DCCH
2
39 sec
TC_rll_unit_data_req_ACCH
28
40 sec
TC_rll_unit_data_req_DCCH
2
39 sec
TC_rsl_bs_pwr_static_ass
2
31 sec
TC_rsl_bs_pwr_static_power_control
2
39 sec
TC_rsl_chan_initial_ms_pwr
28
29 sec
TC_rsl_chan_initial_ta
28
40 sec
TC_rsl_modify_encr
28
40 sec
TC_rsl_ms_pwr_ctrl
5
40 sec
TC_rsl_ms_pwr_dyn_active
28
28 sec
TC_rsl_ms_pwr_dyn_active2
28
17 sec
TC_rsl_ms_pwr_dyn_ass_updown
28
17 sec
TC_rsl_ms_pwr_dyn_down
28
17 sec
TC_rsl_ms_pwr_dyn_max
28
17 sec
TC_rsl_ms_pwr_dyn_up
28
17 sec
TC_sacch_chan_act
28
39 sec
TC_sacch_chan_act_ho_async
28
40 sec
TC_sacch_chan_act_ho_sync
28
39 sec
TC_sacch_filling
28
39 sec
TC_sacch_info_mod
28
40 sec
TC_sacch_multi
28
39 sec
TC_sacch_multi_chg
28
40 sec
TC_si_sched_1
2
39 sec
TC_si_sched_13
2
40 sec
TC_si_sched_13_2bis_2ter_2quater
28
40 sec
TC_si_sched_2bis
2
40 sec
TC_si_sched_2quater
28
39 sec
TC_si_sched_2ter
2
40 sec
TC_si_sched_2ter_2bis
2
40 sec
TC_si_sched_default
2
29 sec
TC_tch_sign_l2_fill_frame
28
27 sec
TC_tch_sign_l2_fill_frame_dtxd
28
39 sec
TC_tx_power_ramp_adm_state_change
28
21 sec
TC_tx_power_start_ramp_down_bcch
28
30 sec
TC_tx_power_start_ramp_up_bcch
28
39 sec
All Tests
Class
Failed
Skipped
Passed
Total
Duration
ttcn3_bts_tests
79
+4
0
18
-3
97
+1
52 min