trial-ttcn3_bts_tests:sysmo 97

Took 48 min

All Failed Tests

Name	Age	Duration
TC_chan_act_a51	2	36 sec
TC_chan_act_a52	2	36 sec
TC_chan_act_a53	28	37 sec
TC_chan_act_react Regression	1	16 sec
TC_chan_act_stress	1	5 sec
TC_conn_fail_crit Regression	2	36 sec
TC_deact_sacch	28	30 sec
TC_dyn_ipa_pdch_tchf_act Regression	1	15 sec
TC_dyn_ipa_pdch_tchf_act_pdch_act_nack Regression	1	15 sec
TC_encr_cmd_a51	2	37 sec
TC_encr_cmd_a52	2	37 sec
TC_encr_cmd_a53	28	37 sec
TC_err_rep_wrong_msg_type Regression	1	15 sec
TC_ho_rach	28	37 sec
TC_meas_res_sign_sdcch4	28	36 sec
TC_meas_res_sign_sdcch8	28	36 sec
TC_meas_res_sign_tchf	28	37 sec
TC_meas_res_sign_tchh	28	37 sec
TC_meas_res_sign_tchh_toa256	28	37 sec
TC_meas_res_speech_tchf	2	24 sec
TC_meas_res_speech_tchh	2	36 sec
TC_meas_res_speech_tchh_toa256	1	37 sec
TC_ms_pwr_ctrl_constant	3	37 sec
TC_ms_pwr_ctrl_pf_ewma	2	36 sec
TC_paging_imsi_200percent Regression	2	37 sec
TC_paging_imsi_80percent Regression	2	37 sec
TC_paging_tmsi_200percent	2	36 sec
TC_paging_tmsi_80percent	2	36 sec
TC_rach_content Regression	1	37 sec
TC_rach_content_emerg Regression	1	36 sec
TC_rach_count Regression	1	38 sec
TC_rach_load_count	28	2 sec
TC_rach_load_idle_below_thresh	28	2 sec
TC_rach_load_idle_thresh0	28	2 sec
TC_rach_max_ta	28	37 sec
TC_rll_est_ind	2	27 sec
TC_rll_est_req_ACCH_3	28	37 sec
TC_rll_est_req_DCCH_3	2	36 sec
TC_rll_rel_ind_ACCH_0	28	37 sec
TC_rll_rel_ind_ACCH_3	28	37 sec
TC_rll_rel_ind_DCCH_0	2	37 sec
TC_rll_rel_ind_DCCH_3	5	37 sec
TC_rll_rel_req	28	37 sec
TC_rll_unit_data_ind_ACCH	2	36 sec
TC_rll_unit_data_ind_DCCH	2	36 sec
TC_rll_unit_data_req_ACCH	28	37 sec
TC_rll_unit_data_req_DCCH	2	37 sec
TC_rsl_bs_pwr_static_ass Regression	2	29 sec
TC_rsl_bs_pwr_static_power_control Regression	2	36 sec
TC_rsl_chan_initial_ms_pwr	28	27 sec
TC_rsl_chan_initial_ta	28	36 sec
TC_rsl_modify_encr	28	37 sec
TC_rsl_ms_pwr_ctrl	5	37 sec
TC_rsl_ms_pwr_dyn_active	28	26 sec
TC_rsl_ms_pwr_dyn_active2	28	15 sec
TC_rsl_ms_pwr_dyn_ass_updown	28	15 sec
TC_rsl_ms_pwr_dyn_down	28	15 sec
TC_rsl_ms_pwr_dyn_max	28	15 sec
TC_rsl_ms_pwr_dyn_up	28	15 sec
TC_sacch_chan_act	28	37 sec
TC_sacch_chan_act_ho_async	28	37 sec
TC_sacch_chan_act_ho_sync	28	37 sec
TC_sacch_filling	28	36 sec
TC_sacch_info_mod	28	36 sec
TC_sacch_multi	28	37 sec
TC_sacch_multi_chg	28	37 sec
TC_si_sched_1 Regression	2	36 sec
TC_si_sched_13	2	37 sec
TC_si_sched_13_2bis_2ter_2quater	28	37 sec
TC_si_sched_2bis Regression	2	36 sec
TC_si_sched_2quater	28	36 sec
TC_si_sched_2ter Regression	2	37 sec
TC_si_sched_2ter_2bis Regression	2	37 sec
TC_si_sched_default Regression	2	27 sec
TC_tch_sign_l2_fill_frame	28	25 sec
TC_tch_sign_l2_fill_frame_dtxd	28	36 sec
TC_tx_power_ramp_adm_state_change	28	19 sec
TC_tx_power_start_ramp_down_bcch	28	28 sec
TC_tx_power_start_ramp_up_bcch	28	37 sec

All Tests

Class	Failed	Skipped	Passed	Total	Duration
ttcn3_bts_tests	79+17	0	18-16	97 +1	48 min