ttcn3_bts_tests 101

Took 47 min

All Tests

Name	Age	Duration
TC_chan_act_a51	1	33 sec
TC_chan_act_a52	1	30 sec
TC_chan_act_a53	30	23 sec
TC_chan_act_react	0	24 sec
TC_chan_act_stress	1	24 sec
TC_chan_act_wrong_nr	0	17 sec
TC_chan_deact_not_active	0	15 sec
TC_chopped_ipa_payload	0	43 sec
TC_chopped_ipa_ping	0	39 sec
TC_conn_fail_crit Fixed	0	42 sec
TC_deact_sacch	30	28 sec
TC_dyn_ipa_pdch_tchf_act	0	15 sec
TC_dyn_ipa_pdch_tchf_act_pdch_act_nack	0	16 sec
TC_dyn_osmo_pdch_tchf_act	0	15 sec
TC_dyn_osmo_pdch_tchh_act	0	15 sec
TC_dyn_osmo_pdch_unsol_deact	0	15 sec
TC_encr_cmd_a51 Fixed	0	24 sec
TC_encr_cmd_a52	2	25 sec
TC_encr_cmd_a53	30	24 sec
TC_err_rep_wrong_mdisc	0	19 sec
TC_err_rep_wrong_msg_type	0	15 sec
TC_err_rep_wrong_sequence	0	16 sec
TC_ho_rach	30	22 sec
TC_ipa_crcx_mdcx_dlcx_not_active	0	15 sec
TC_ipa_crcx_mdcx_mdcx_dlcx_not_active	0	15 sec
TC_ipa_crcx_sdcch_not_active	0	15 sec
TC_ipa_crcx_twice_not_active	0	15 sec
TC_ipa_dlcx_not_active	0	24 sec
TC_lapdm_selftest	0	23 ms
TC_meas_res_sign_sdcch4	30	19 sec
TC_meas_res_sign_sdcch8	30	20 sec
TC_meas_res_sign_tchf	30	20 sec
TC_meas_res_sign_tchh	30	19 sec
TC_meas_res_sign_tchh_toa256	30	19 sec
TC_meas_res_speech_tchf	4	11 sec
TC_meas_res_speech_tchf_facch	1	19 sec
TC_meas_res_speech_tchh	4	19 sec
TC_meas_res_speech_tchh_facch	1	19 sec
TC_meas_res_speech_tchh_toa256	3	19 sec
TC_ms_pwr_ctrl_constant	5	26 sec
TC_ms_pwr_ctrl_pf_ewma	4	17 sec
TC_paging_imsi_200percent	0	58 sec
TC_paging_imsi_80percent	0	47 sec
TC_paging_tmsi_200percent	1	1 min 1 sec
TC_paging_tmsi_80percent	1	46 sec
TC_rach_content	0	1 min 10 sec
TC_rach_content_emerg	0	1 min 20 sec
TC_rach_count	0	1 min 17 sec
TC_rach_load_count	30	2 sec
TC_rach_load_idle_below_thresh	30	2 sec
TC_rach_load_idle_thresh0	30	2 sec
TC_rach_max_ta	30	25 sec
TC_rll_est_ind Fixed	0	48 sec
TC_rll_est_req_ACCH_3	30	23 sec
TC_rll_est_req_DCCH_3 Fixed	0	27 sec
TC_rll_rel_ind_ACCH_0	30	24 sec
TC_rll_rel_ind_ACCH_3	30	32 sec
TC_rll_rel_ind_DCCH_0 Fixed	0	24 sec
TC_rll_rel_ind_DCCH_3 Fixed	0	21 sec
TC_rll_rel_req	30	38 sec
TC_rll_unit_data_ind_ACCH Fixed	0	27 sec
TC_rll_unit_data_ind_DCCH Fixed	0	27 sec
TC_rll_unit_data_req_ACCH	30	27 sec
TC_rll_unit_data_req_DCCH Fixed	0	29 sec
TC_rsl_bs_pwr_static_ass	0	21 sec
TC_rsl_bs_pwr_static_power_control	0	23 sec
TC_rsl_chan_initial_ms_pwr	30	20 sec
TC_rsl_chan_initial_ta	30	21 sec
TC_rsl_ie_content_error	0	15 sec
TC_rsl_mand_ie_error	0	15 sec
TC_rsl_modify_encr	30	25 sec
TC_rsl_ms_pwr_ctrl	2	1 min 24 sec
TC_rsl_ms_pwr_dyn_active	30	25 sec
TC_rsl_ms_pwr_dyn_active2	30	15 sec
TC_rsl_ms_pwr_dyn_ass_updown	30	15 sec
TC_rsl_ms_pwr_dyn_down	30	15 sec
TC_rsl_ms_pwr_dyn_max	30	15 sec
TC_rsl_ms_pwr_dyn_up	30	15 sec
TC_rsl_protocol_error	0	24 sec
TC_sacch_chan_act	30	39 sec
TC_sacch_chan_act_ho_async	30	25 sec
TC_sacch_chan_act_ho_sync	30	16 sec
TC_sacch_filling	30	44 sec
TC_sacch_info_mod	30	41 sec
TC_sacch_multi	30	1 min 0 sec
TC_sacch_multi_chg	30	1 min 2 sec
TC_si_sched_1	0	33 sec
TC_si_sched_13	1	33 sec
TC_si_sched_13_2bis_2ter_2quater	30	48 sec
TC_si_sched_2bis	0	32 sec
TC_si_sched_2quater	30	39 sec
TC_si_sched_2ter	0	31 sec
TC_si_sched_2ter_2bis	0	31 sec
TC_si_sched_default Regression	1	25 sec
TC_speech_no_rtp_tchf Fixed	0	27 sec
TC_speech_no_rtp_tchh Fixed	0	35 sec
TC_tch_sign_l2_fill_frame	30	22 sec
TC_tch_sign_l2_fill_frame_dtxd	30	27 sec
TC_tx_power_ramp_adm_state_change	30	19 sec
TC_tx_power_start_ramp_down_bcch	30	26 sec
TC_tx_power_start_ramp_up_bcch	30	39 sec