trial-ttcn3_bts_tests:oc2g 101

Took 55 min

All Failed Tests

Name	Age	Duration
TC_chan_act_a51	1	39 sec
TC_chan_act_a52	3	39 sec
TC_chan_act_a53	32	40 sec
TC_chan_act_stress	2	29 sec
TC_conn_fail_crit	4	39 sec
TC_deact_sacch	32	31 sec
TC_encr_cmd_a51	1	39 sec
TC_encr_cmd_a52	2	40 sec
TC_encr_cmd_a53	32	39 sec
TC_ho_rach	32	40 sec
TC_meas_res_sign_sdcch4	32	39 sec
TC_meas_res_sign_sdcch8	32	39 sec
TC_meas_res_sign_tchf	32	40 sec
TC_meas_res_sign_tchh	32	40 sec
TC_meas_res_sign_tchh_toa256	32	40 sec
TC_meas_res_speech_tchf	6	27 sec
TC_meas_res_speech_tchf_facch	3	39 sec
TC_meas_res_speech_tchh	6	39 sec
TC_meas_res_speech_tchh_facch	3	40 sec
TC_meas_res_speech_tchh_toa256	5	39 sec
TC_ms_pwr_ctrl_constant	7	39 sec
TC_ms_pwr_ctrl_pf_ewma	6	39 sec
TC_paging_imsi_200percent	3	40 sec
TC_paging_imsi_80percent	3	39 sec
TC_paging_tmsi_200percent	3	40 sec
TC_paging_tmsi_80percent	3	39 sec
TC_rach_content	1	39 sec
TC_rach_content_emerg	1	39 sec
TC_rach_count	1	40 sec
TC_rach_load_count	32	2 sec
TC_rach_load_idle_below_thresh	32	2 sec
TC_rach_load_idle_thresh0	32	2 sec
TC_rach_max_ta	32	39 sec
TC_rll_est_ind	1	29 sec
TC_rll_est_req_ACCH_3	32	39 sec
TC_rll_est_req_DCCH_3	1	39 sec
TC_rll_rel_ind_ACCH_0	32	39 sec
TC_rll_rel_ind_ACCH_3	32	40 sec
TC_rll_rel_ind_DCCH_0	1	40 sec
TC_rll_rel_ind_DCCH_3	1	40 sec
TC_rll_rel_req	32	39 sec
TC_rll_unit_data_ind_ACCH	1	40 sec
TC_rll_unit_data_ind_DCCH	1	40 sec
TC_rll_unit_data_req_ACCH	32	39 sec
TC_rll_unit_data_req_DCCH	1	40 sec
TC_rsl_bs_pwr_static_ass	3	31 sec
TC_rsl_bs_pwr_static_power_control	3	39 sec
TC_rsl_chan_initial_ms_pwr	32	29 sec
TC_rsl_chan_initial_ta	32	40 sec
TC_rsl_modify_encr	32	40 sec
TC_rsl_ms_pwr_ctrl	4	40 sec
TC_rsl_ms_pwr_dyn_active	32	28 sec
TC_rsl_ms_pwr_dyn_active2	32	17 sec
TC_rsl_ms_pwr_dyn_ass_updown	32	17 sec
TC_rsl_ms_pwr_dyn_down	32	17 sec
TC_rsl_ms_pwr_dyn_max	32	17 sec
TC_rsl_ms_pwr_dyn_up	32	17 sec
TC_sacch_chan_act	32	40 sec
TC_sacch_chan_act_ho_async	32	39 sec
TC_sacch_chan_act_ho_sync	32	40 sec
TC_sacch_filling	32	39 sec
TC_sacch_info_mod	32	40 sec
TC_sacch_multi	32	40 sec
TC_sacch_multi_chg	32	39 sec
TC_si_sched_1	3	39 sec
TC_si_sched_13	3	40 sec
TC_si_sched_13_2bis_2ter_2quater	32	40 sec
TC_si_sched_2bis	3	39 sec
TC_si_sched_2quater	32	39 sec
TC_si_sched_2ter	3	40 sec
TC_si_sched_2ter_2bis	3	40 sec
TC_si_sched_default	3	29 sec
TC_speech_no_rtp_tchf	1	40 sec
TC_speech_no_rtp_tchh	1	40 sec
TC_tch_sign_l2_fill_frame	32	27 sec
TC_tch_sign_l2_fill_frame_dtxd	32	39 sec
TC_tx_power_ramp_adm_state_change	32	21 sec
TC_tx_power_start_ramp_down_bcch	32	30 sec
TC_tx_power_start_ramp_up_bcch	32	40 sec

All Tests

Class	Failed	Skipped	Passed	Total	Duration
ttcn3_bts_tests	79	0	22	101	55 min