trial-ttcn3_bts_tests:trx 136

Took 40 min

All Failed Tests

Name	Age	Duration
TC_chan_act_a53	32	13 sec
TC_deact_sacch	32	46 sec
TC_encr_cmd_a53	32	15 sec
TC_ho_rach	32	16 sec
TC_ipa_crcx_sdcch_not_active Regression	1	10 sec
TC_meas_res_sign_sdcch4	32	11 sec
TC_meas_res_sign_sdcch8	32	11 sec
TC_meas_res_sign_tchf	32	13 sec
TC_meas_res_sign_tchh	32	12 sec
TC_meas_res_sign_tchh_toa256	32	11 sec
TC_meas_res_speech_tchf	6	14 sec
TC_meas_res_speech_tchf_facch	3	13 sec
TC_meas_res_speech_tchh	6	13 sec
TC_meas_res_speech_tchh_facch	3	12 sec
TC_meas_res_speech_tchh_toa256	5	12 sec
TC_ms_pwr_ctrl_constant	7	11 sec
TC_ms_pwr_ctrl_pf_ewma	6	11 sec
TC_pcu_data_ind_lqual_cb	1	14 sec
TC_pcu_ext_rach_content	1	13 sec
TC_pcu_oml_alert	1	13 sec
TC_pcu_ptcch	1	19 sec
TC_pcu_socket_nsvc_ipv4	1	2 sec
TC_pcu_socket_nsvc_ipv6	1	2 sec
TC_pcu_socket_verify_info_ind	1	14 sec
TC_rach_load_count	32	2 sec
TC_rach_load_idle_below_thresh	32	2 sec
TC_rach_load_idle_thresh0	32	2 sec
TC_rach_max_ta	32	11 sec
TC_rll_est_req_ACCH_3	32	15 sec
TC_rll_rel_ind_ACCH_0	32	16 sec
TC_rll_rel_ind_ACCH_3	32	18 sec
TC_rll_rel_ind_DCCH_3	1	19 sec
TC_rll_rel_req	32	22 sec
TC_rll_unit_data_req_ACCH	32	17 sec
TC_rsl_chan_initial_ms_pwr	32	14 sec
TC_rsl_chan_initial_ta	32	10 sec
TC_rsl_modify_encr	32	11 sec
TC_rsl_ms_pwr_dyn_active	32	11 sec
TC_rsl_ms_pwr_dyn_active2	32	10 sec
TC_rsl_ms_pwr_dyn_ass_updown	32	10 sec
TC_rsl_ms_pwr_dyn_down	32	10 sec
TC_rsl_ms_pwr_dyn_max	32	10 sec
TC_rsl_ms_pwr_dyn_up	32	10 sec
TC_sacch_chan_act	32	26 sec
TC_sacch_chan_act_ho_async	32	11 sec
TC_sacch_chan_act_ho_sync	32	10 sec
TC_sacch_filling	32	21 sec
TC_sacch_info_mod	32	27 sec
TC_sacch_multi	32	42 sec
TC_sacch_multi_chg	32	50 sec
TC_si_sched_13_2bis_2ter_2quater	32	26 sec
TC_tch_sign_l2_fill_frame	32	16 sec
TC_tch_sign_l2_fill_frame_dtxd	32	12 sec
TC_tx_power_ramp_adm_state_change	32	12 sec
TC_tx_power_start_ramp_down_bcch	32	12 sec
TC_tx_power_start_ramp_up_bcch	32	10 sec

All Tests

Class	Failed	Skipped	Passed	Total	Duration
ttcn3_bts_tests	56-35	0	80+35	136	40 min