ttcn3_bts_tests 136

Took 40 min

All Tests

Name	Age	Duration
TC_chan_act_a51 Fixed	0	13 sec
TC_chan_act_a52 Fixed	0	12 sec
TC_chan_act_a53	32	13 sec
TC_chan_act_react	0	10 sec
TC_chan_act_stress	0	18 sec
TC_chan_act_wrong_nr	0	12 sec
TC_chan_deact_not_active	0	11 sec
TC_chopped_ipa_payload	0	43 sec
TC_chopped_ipa_ping	0	30 sec
TC_conn_fail_crit Fixed	0	28 sec
TC_deact_sacch	32	46 sec
TC_dyn_ipa_pdch_act_deact	0	13 sec
TC_dyn_ipa_pdch_act_tchf_act_nack	0	10 sec
TC_dyn_ipa_pdch_tchf_act	0	10 sec
TC_dyn_ipa_pdch_tchf_act_pdch_act_nack	0	10 sec
TC_dyn_osmo_pdch_act_deact	0	14 sec
TC_dyn_osmo_pdch_double_act	0	10 sec
TC_dyn_osmo_pdch_tchf_act	0	5.5 sec
TC_dyn_osmo_pdch_tchh_act	0	10 sec
TC_dyn_osmo_pdch_unsol_deact	0	6.6 sec
TC_encr_cmd_a51	0	14 sec
TC_encr_cmd_a52	0	15 sec
TC_encr_cmd_a53	32	15 sec
TC_err_rep_wrong_mdisc	0	10 sec
TC_err_rep_wrong_msg_type	0	10 sec
TC_err_rep_wrong_sequence	0	10 sec
TC_ho_rach	32	16 sec
TC_ipa_crcx_mdcx_dlcx_not_active	0	10 sec
TC_ipa_crcx_mdcx_mdcx_dlcx_not_active	0	10 sec
TC_ipa_crcx_sdcch_not_active Regression	1	10 sec
TC_ipa_crcx_twice_not_active	0	10 sec
TC_ipa_dlcx_not_active	0	10 sec
TC_lapdm_selftest	0	29 ms
TC_meas_res_sign_sdcch4	32	11 sec
TC_meas_res_sign_sdcch8	32	11 sec
TC_meas_res_sign_tchf	32	13 sec
TC_meas_res_sign_tchh	32	12 sec
TC_meas_res_sign_tchh_toa256	32	11 sec
TC_meas_res_speech_tchf	6	14 sec
TC_meas_res_speech_tchf_facch	3	13 sec
TC_meas_res_speech_tchh	6	13 sec
TC_meas_res_speech_tchh_facch	3	12 sec
TC_meas_res_speech_tchh_toa256	5	12 sec
TC_ms_pwr_ctrl_constant	7	11 sec
TC_ms_pwr_ctrl_pf_ewma	6	11 sec
TC_paging_imsi_200percent Fixed	0	44 sec
TC_paging_imsi_80percent Fixed	0	32 sec
TC_paging_tmsi_200percent Fixed	0	37 sec
TC_paging_tmsi_80percent Fixed	0	33 sec
TC_pcu_act_req	0	13 sec
TC_pcu_act_req_wrong_bts	0	16 sec
TC_pcu_act_req_wrong_trx	0	16 sec
TC_pcu_act_req_wrong_ts	0	16 sec
TC_pcu_data_ind_lqual_cb	1	14 sec
TC_pcu_data_req_agch Fixed	0	14 sec
TC_pcu_data_req_imm_ass_pch Fixed	0	11 sec
TC_pcu_data_req_pch Fixed	0	14 sec
TC_pcu_deact_req	0	18 sec
TC_pcu_deact_req_wrong_ts	0	14 sec
TC_pcu_ext_rach_content	1	13 sec
TC_pcu_info_ind_fh_params	0	10 sec
TC_pcu_oml_alert	1	13 sec
TC_pcu_paging_from_rsl	0	11 sec
TC_pcu_ptcch	1	19 sec
TC_pcu_rach_content Fixed	0	1 min 8 sec
TC_pcu_rr_suspend Fixed	0	11 sec
TC_pcu_rts_req	0	18 sec
TC_pcu_socket_connect_multi	0	15 sec
TC_pcu_socket_connect_si3gprs Fixed	0	13 sec
TC_pcu_socket_connect_si4gprs Fixed	0	14 sec
TC_pcu_socket_disconnect_nosi3gprs Fixed	0	16 sec
TC_pcu_socket_disconnect_nosi4gprs Fixed	0	14 sec
TC_pcu_socket_noconnect_nosi3gprs Fixed	0	11 sec
TC_pcu_socket_noconnect_nosi4gprs Fixed	0	11 sec
TC_pcu_socket_nsvc_ipv4	1	2 sec
TC_pcu_socket_nsvc_ipv6	1	2 sec
TC_pcu_socket_reconnect	0	12 sec
TC_pcu_socket_verify_info_ind	1	14 sec
TC_pcu_time_ind	0	18 sec
TC_pcu_ver_si13	0	10 sec
TC_rach_content	0	1 min 8 sec
TC_rach_content_emerg	0	1 min 8 sec
TC_rach_count	0	1 min 4 sec
TC_rach_load_count	32	2 sec
TC_rach_load_idle_below_thresh	32	2 sec
TC_rach_load_idle_thresh0	32	2 sec
TC_rach_max_ta	32	11 sec
TC_rll_est_ind Fixed	0	41 sec
TC_rll_est_req_ACCH_3	32	15 sec
TC_rll_est_req_DCCH_3 Fixed	0	13 sec
TC_rll_rel_ind_ACCH_0	32	16 sec
TC_rll_rel_ind_ACCH_3	32	18 sec
TC_rll_rel_ind_DCCH_0 Fixed	0	14 sec
TC_rll_rel_ind_DCCH_3	1	19 sec
TC_rll_rel_req	32	22 sec
TC_rll_unit_data_ind_ACCH Fixed	0	17 sec
TC_rll_unit_data_ind_DCCH Fixed	0	16 sec
TC_rll_unit_data_req_ACCH	32	17 sec
TC_rll_unit_data_req_DCCH Fixed	0	16 sec
TC_rsl_bs_pwr_static_ass Fixed	0	14 sec
TC_rsl_bs_pwr_static_power_control Fixed	0	15 sec
TC_rsl_chan_initial_ms_pwr	32	14 sec
TC_rsl_chan_initial_ta	32	10 sec
TC_rsl_ie_content_error	0	10 sec
TC_rsl_mand_ie_error	0	11 sec
TC_rsl_modify_encr	32	11 sec
TC_rsl_ms_pwr_ctrl Fixed	0	1 min 15 sec
TC_rsl_ms_pwr_dyn_active	32	11 sec
TC_rsl_ms_pwr_dyn_active2	32	10 sec
TC_rsl_ms_pwr_dyn_ass_updown	32	10 sec
TC_rsl_ms_pwr_dyn_down	32	10 sec
TC_rsl_ms_pwr_dyn_max	32	10 sec
TC_rsl_ms_pwr_dyn_up	32	10 sec
TC_rsl_protocol_error	0	11 sec
TC_sacch_chan_act	32	26 sec
TC_sacch_chan_act_ho_async	32	11 sec
TC_sacch_chan_act_ho_sync	32	10 sec
TC_sacch_filling	32	21 sec
TC_sacch_info_mod	32	27 sec
TC_sacch_multi	32	42 sec
TC_sacch_multi_chg	32	50 sec
TC_si_sched_1 Fixed	0	18 sec
TC_si_sched_13 Fixed	0	18 sec
TC_si_sched_13_2bis_2ter_2quater	32	26 sec
TC_si_sched_2bis Fixed	0	19 sec
TC_si_sched_2quater Fixed	0	26 sec
TC_si_sched_2ter Fixed	0	18 sec
TC_si_sched_2ter_2bis Fixed	0	18 sec
TC_si_sched_default Fixed	0	19 sec
TC_speech_no_rtp_tchf Fixed	0	21 sec
TC_speech_no_rtp_tchh Fixed	0	21 sec
TC_tch_sign_l2_fill_frame	32	16 sec
TC_tch_sign_l2_fill_frame_dtxd	32	12 sec
TC_tx_power_ramp_adm_state_change	32	12 sec
TC_tx_power_start_ramp_down_bcch	32	12 sec
TC_tx_power_start_ramp_up_bcch	32	10 sec