ttcn3_bts_tests 101

Took 49 min

All Tests

Name	Age	Duration
TC_chan_act_a51 Fixed	0	27 sec
TC_chan_act_a52	1	23 sec
TC_chan_act_a53	34	23 sec
TC_chan_act_react	0	25 sec
TC_chan_act_stress	1	24 sec
TC_chan_act_wrong_nr	0	17 sec
TC_chan_deact_not_active	0	15 sec
TC_chopped_ipa_payload	0	43 sec
TC_chopped_ipa_ping	0	39 sec
TC_conn_fail_crit	0	42 sec
TC_deact_sacch	34	34 sec
TC_dyn_ipa_pdch_tchf_act	0	16 sec
TC_dyn_ipa_pdch_tchf_act_pdch_act_nack	0	17 sec
TC_dyn_osmo_pdch_tchf_act	0	15 sec
TC_dyn_osmo_pdch_tchh_act	0	15 sec
TC_dyn_osmo_pdch_unsol_deact	0	16 sec
TC_encr_cmd_a51 Regression	1	26 sec
TC_encr_cmd_a52	1	27 sec
TC_encr_cmd_a53	34	24 sec
TC_err_rep_wrong_mdisc	0	19 sec
TC_err_rep_wrong_msg_type	0	15 sec
TC_err_rep_wrong_sequence	0	16 sec
TC_ho_rach	34	34 sec
TC_ipa_crcx_mdcx_dlcx_not_active	0	15 sec
TC_ipa_crcx_mdcx_mdcx_dlcx_not_active	0	15 sec
TC_ipa_crcx_sdcch_not_active	0	15 sec
TC_ipa_crcx_twice_not_active	0	15 sec
TC_ipa_dlcx_not_active	0	24 sec
TC_lapdm_selftest	0	21 ms
TC_meas_res_sign_sdcch4	34	39 sec
TC_meas_res_sign_sdcch8	34	40 sec
TC_meas_res_sign_tchf	34	39 sec
TC_meas_res_sign_tchh	34	45 sec
TC_meas_res_sign_tchh_toa256	34	40 sec
TC_meas_res_speech_tchf	8	27 sec
TC_meas_res_speech_tchf_facch	5	40 sec
TC_meas_res_speech_tchh	8	40 sec
TC_meas_res_speech_tchh_facch	5	39 sec
TC_meas_res_speech_tchh_toa256	7	40 sec
TC_ms_pwr_ctrl_constant	9	26 sec
TC_ms_pwr_ctrl_pf_ewma	8	17 sec
TC_paging_imsi_200percent Regression	2	58 sec
TC_paging_imsi_80percent Regression	2	47 sec
TC_paging_tmsi_200percent	2	1 min 3 sec
TC_paging_tmsi_80percent	2	46 sec
TC_rach_content	0	1 min 11 sec
TC_rach_content_emerg Regression	1	31 sec
TC_rach_count Regression	1	1 min 18 sec
TC_rach_load_count	34	2 sec
TC_rach_load_idle_below_thresh	34	2 sec
TC_rach_load_idle_thresh0	34	2 sec
TC_rach_max_ta	34	25 sec
TC_rll_est_ind	2	32 sec
TC_rll_est_req_ACCH_3	34	24 sec
TC_rll_est_req_DCCH_3	0	27 sec
TC_rll_rel_ind_ACCH_0	34	24 sec
TC_rll_rel_ind_ACCH_3	34	27 sec
TC_rll_rel_ind_DCCH_0	0	24 sec
TC_rll_rel_ind_DCCH_3	0	23 sec
TC_rll_rel_req	34	35 sec
TC_rll_unit_data_ind_ACCH Regression	1	38 sec
TC_rll_unit_data_ind_DCCH Regression	1	39 sec
TC_rll_unit_data_req_ACCH	34	35 sec
TC_rll_unit_data_req_DCCH	2	31 sec
TC_rsl_bs_pwr_static_ass Regression	2	32 sec
TC_rsl_bs_pwr_static_power_control Regression	2	45 sec
TC_rsl_chan_initial_ms_pwr	34	28 sec
TC_rsl_chan_initial_ta	34	25 sec
TC_rsl_ie_content_error	0	15 sec
TC_rsl_mand_ie_error	0	15 sec
TC_rsl_modify_encr	34	31 sec
TC_rsl_ms_pwr_ctrl	2	39 sec
TC_rsl_ms_pwr_dyn_active	34	25 sec
TC_rsl_ms_pwr_dyn_active2	34	15 sec
TC_rsl_ms_pwr_dyn_ass_updown	34	15 sec
TC_rsl_ms_pwr_dyn_down	34	15 sec
TC_rsl_ms_pwr_dyn_max	34	15 sec
TC_rsl_ms_pwr_dyn_up	34	15 sec
TC_rsl_protocol_error	0	24 sec
TC_sacch_chan_act	34	37 sec
TC_sacch_chan_act_ho_async	34	33 sec
TC_sacch_chan_act_ho_sync	34	25 sec
TC_sacch_filling	34	36 sec
TC_sacch_info_mod	34	33 sec
TC_sacch_multi	34	27 sec
TC_sacch_multi_chg	34	57 sec
TC_si_sched_1	0	31 sec
TC_si_sched_13	2	33 sec
TC_si_sched_13_2bis_2ter_2quater	34	40 sec
TC_si_sched_2bis	0	31 sec
TC_si_sched_2quater	0	39 sec
TC_si_sched_2ter	0	31 sec
TC_si_sched_2ter_2bis Regression	2	32 sec
TC_si_sched_default	0	24 sec
TC_speech_no_rtp_tchf Regression	1	27 sec
TC_speech_no_rtp_tchh	0	36 sec
TC_tch_sign_l2_fill_frame	34	26 sec
TC_tch_sign_l2_fill_frame_dtxd	34	27 sec
TC_tx_power_ramp_adm_state_change	34	19 sec
TC_tx_power_start_ramp_down_bcch	34	26 sec
TC_tx_power_start_ramp_up_bcch	34	39 sec