trial-ttcn3_bts_tests:oc2g 101

Took 55 min

All Failed Tests

Name	Age	Duration
TC_chan_act_a51	1	39 sec
TC_chan_act_a52	1	39 sec
TC_chan_act_a53	35	40 sec
TC_conn_fail_crit	1	40 sec
TC_deact_sacch	35	31 sec
TC_encr_cmd_a51	1	39 sec
TC_encr_cmd_a52	1	40 sec
TC_encr_cmd_a53	35	39 sec
TC_ho_rach	35	40 sec
TC_meas_res_sign_sdcch4	35	39 sec
TC_meas_res_sign_sdcch8	35	39 sec
TC_meas_res_sign_tchf	35	39 sec
TC_meas_res_sign_tchh	35	40 sec
TC_meas_res_sign_tchh_toa256	35	40 sec
TC_meas_res_speech_tchf	9	27 sec
TC_meas_res_speech_tchf_facch	6	39 sec
TC_meas_res_speech_tchh	9	40 sec
TC_meas_res_speech_tchh_facch	6	40 sec
TC_meas_res_speech_tchh_toa256	8	40 sec
TC_ms_pwr_ctrl_constant	10	39 sec
TC_ms_pwr_ctrl_pf_ewma	9	39 sec
TC_paging_imsi_200percent	1	40 sec
TC_paging_imsi_80percent	1	39 sec
TC_paging_tmsi_200percent	1	39 sec
TC_paging_tmsi_80percent	1	39 sec
TC_rach_content	1	39 sec
TC_rach_content_emerg	1	39 sec
TC_rach_count	1	40 sec
TC_rach_load_count	35	2 sec
TC_rach_load_idle_below_thresh	35	2 sec
TC_rach_load_idle_thresh0	35	2 sec
TC_rach_max_ta	35	39 sec
TC_rll_est_ind	1	29 sec
TC_rll_est_req_ACCH_3	35	40 sec
TC_rll_est_req_DCCH_3	1	39 sec
TC_rll_rel_ind_ACCH_0	35	40 sec
TC_rll_rel_ind_ACCH_3	35	39 sec
TC_rll_rel_ind_DCCH_0	1	39 sec
TC_rll_rel_ind_DCCH_3	1	39 sec
TC_rll_rel_req	35	40 sec
TC_rll_unit_data_ind_ACCH	1	39 sec
TC_rll_unit_data_ind_DCCH	2	40 sec
TC_rll_unit_data_req_ACCH	35	39 sec
TC_rll_unit_data_req_DCCH	1	40 sec
TC_rsl_bs_pwr_static_ass	1	31 sec
TC_rsl_bs_pwr_static_power_control	1	39 sec
TC_rsl_chan_initial_ms_pwr	35	29 sec
TC_rsl_chan_initial_ta	35	40 sec
TC_rsl_modify_encr	35	39 sec
TC_rsl_ms_pwr_ctrl	3	39 sec
TC_rsl_ms_pwr_dyn_active	35	29 sec
TC_rsl_ms_pwr_dyn_active2	35	17 sec
TC_rsl_ms_pwr_dyn_ass_updown	35	17 sec
TC_rsl_ms_pwr_dyn_down	35	17 sec
TC_rsl_ms_pwr_dyn_max	35	17 sec
TC_rsl_ms_pwr_dyn_up	35	17 sec
TC_sacch_chan_act	35	39 sec
TC_sacch_chan_act_ho_async	35	40 sec
TC_sacch_chan_act_ho_sync	35	39 sec
TC_sacch_filling	35	39 sec
TC_sacch_info_mod	35	40 sec
TC_sacch_multi	35	39 sec
TC_sacch_multi_chg	35	40 sec
TC_si_sched_1	1	39 sec
TC_si_sched_13	1	39 sec
TC_si_sched_13_2bis_2ter_2quater	1	39 sec
TC_si_sched_2bis	1	39 sec
TC_si_sched_2quater	1	40 sec
TC_si_sched_2ter	1	40 sec
TC_si_sched_2ter_2bis	1	39 sec
TC_si_sched_default	1	29 sec
TC_speech_no_rtp_tchf	1	40 sec
TC_speech_no_rtp_tchh	2	39 sec
TC_tch_sign_l2_fill_frame	35	27 sec
TC_tch_sign_l2_fill_frame_dtxd	35	39 sec
TC_tx_power_ramp_adm_state_change	35	21 sec
TC_tx_power_start_ramp_down_bcch	35	31 sec
TC_tx_power_start_ramp_up_bcch	35	39 sec

All Tests

Class	Failed	Skipped	Passed	Total	Duration
ttcn3_bts_tests	78-1	0	23+1	101	55 min