trial-ttcn3_bts_tests:sysmo 101

Took 46 min

All Failed Tests

Name	Age	Duration
TC_chan_act_a52	1	28 sec
TC_chan_act_a53	37	23 sec
TC_chan_act_stress	1	23 sec
TC_deact_sacch	37	35 sec
TC_encr_cmd_a51	1	25 sec
TC_encr_cmd_a52	1	26 sec
TC_encr_cmd_a53	37	23 sec
TC_ho_rach	37	30 sec
TC_meas_res_sign_sdcch4	37	32 sec
TC_meas_res_sign_sdcch8	37	27 sec
TC_meas_res_sign_tchf	37	20 sec
TC_meas_res_sign_tchh	37	19 sec
TC_meas_res_sign_tchh_toa256	37	19 sec
TC_meas_res_speech_tchf	11	12 sec
TC_meas_res_speech_tchf_facch	8	28 sec
TC_meas_res_speech_tchh	11	26 sec
TC_meas_res_speech_tchh_facch	8	19 sec
TC_meas_res_speech_tchh_toa256	10	19 sec
TC_ms_pwr_ctrl_constant	12	26 sec
TC_ms_pwr_ctrl_pf_ewma	11	17 sec
TC_paging_imsi_200percent	1	58 sec
TC_paging_imsi_80percent	1	47 sec
TC_paging_tmsi_200percent	1	52 sec
TC_paging_tmsi_80percent	1	46 sec
TC_rach_load_count	37	2 sec
TC_rach_load_idle_below_thresh	37	2 sec
TC_rach_load_idle_thresh0	37	2 sec
TC_rach_max_ta	37	35 sec
TC_rll_est_ind	1	28 sec
TC_rll_est_req_ACCH_3	37	30 sec
TC_rll_rel_ind_ACCH_0	37	29 sec
TC_rll_rel_ind_ACCH_3	37	38 sec
TC_rll_rel_ind_DCCH_0	1	32 sec
TC_rll_rel_ind_DCCH_3	1	37 sec
TC_rll_rel_req	37	30 sec
TC_rll_unit_data_ind_ACCH	1	38 sec
TC_rll_unit_data_ind_DCCH	1	37 sec
TC_rll_unit_data_req_ACCH	37	34 sec
TC_rll_unit_data_req_DCCH	1	27 sec
TC_rsl_bs_pwr_static_ass	1	30 sec
TC_rsl_bs_pwr_static_power_control	1	37 sec
TC_rsl_chan_initial_ms_pwr	37	29 sec
TC_rsl_chan_initial_ta	37	25 sec
TC_rsl_modify_encr	37	32 sec
TC_rsl_ms_pwr_ctrl	1	45 sec
TC_rsl_ms_pwr_dyn_active	37	24 sec
TC_rsl_ms_pwr_dyn_active2	37	15 sec
TC_rsl_ms_pwr_dyn_ass_updown	37	15 sec
TC_rsl_ms_pwr_dyn_down	37	15 sec
TC_rsl_ms_pwr_dyn_max	37	15 sec
TC_rsl_ms_pwr_dyn_up	37	15 sec
TC_sacch_chan_act	37	26 sec
TC_sacch_chan_act_ho_async	37	20 sec
TC_sacch_chan_act_ho_sync	37	17 sec
TC_sacch_filling	37	29 sec
TC_sacch_info_mod	37	33 sec
TC_sacch_multi	37	30 sec
TC_sacch_multi_chg	37	27 sec
TC_si_sched_13	1	33 sec
TC_si_sched_13_2bis_2ter_2quater	1	40 sec
TC_si_sched_2ter_2bis	1	34 sec
TC_si_sched_default Regression	1	24 sec
TC_speech_no_rtp_tchf	1	22 sec
TC_speech_no_rtp_tchh	1	25 sec
TC_tch_sign_l2_fill_frame	37	15 sec
TC_tch_sign_l2_fill_frame_dtxd	37	21 sec
TC_tx_power_ramp_adm_state_change	37	19 sec
TC_tx_power_start_ramp_down_bcch	37	19 sec
TC_tx_power_start_ramp_up_bcch	37	19 sec

All Tests

Class	Failed	Skipped	Passed	Total	Duration
ttcn3_bts_tests	69-2	0	32+2	101	46 min