trial-ttcn3_bts_tests:sysmo 101

Took 1 hr 0 min

All Failed Tests

Name	Age	Duration
TC_chan_act_a51	1	45 sec
TC_chan_act_a52	2	45 sec
TC_chan_act_a53	41	45 sec
TC_chan_act_stress	1	24 sec
TC_conn_fail_crit	2	46 sec
TC_deact_sacch	41	35 sec
TC_encr_cmd_a51	1	45 sec
TC_encr_cmd_a52	1	45 sec
TC_encr_cmd_a53	41	46 sec
TC_ho_rach	41	37 sec
TC_meas_res_sign_sdcch4	41	45 sec
TC_meas_res_sign_sdcch8	41	45 sec
TC_meas_res_sign_tchf	41	45 sec
TC_meas_res_sign_tchh	41	45 sec
TC_meas_res_sign_tchh_toa256	41	45 sec
TC_meas_res_speech_tchf	15	32 sec
TC_meas_res_speech_tchf_facch	12	46 sec
TC_meas_res_speech_tchh	15	45 sec
TC_meas_res_speech_tchh_facch	12	45 sec
TC_meas_res_speech_tchh_toa256	14	45 sec
TC_ms_pwr_ctrl_constant	16	45 sec
TC_ms_pwr_ctrl_pf_ewma	15	45 sec
TC_paging_imsi_200percent	2	47 sec
TC_paging_imsi_80percent	2	48 sec
TC_paging_tmsi_200percent	2	46 sec
TC_paging_tmsi_80percent	2	46 sec
TC_rach_content Regression	1	58 sec
TC_rach_content_emerg Regression	1	1 min 10 sec
TC_rach_count Regression	1	2 min 29 sec
TC_rach_load_count	41	2 sec
TC_rach_load_idle_below_thresh	41	2 sec
TC_rach_load_idle_thresh0	41	2 sec
TC_rach_max_ta	41	26 sec
TC_rll_est_ind	2	37 sec
TC_rll_est_req_ACCH_3	41	45 sec
TC_rll_est_req_DCCH_3	2	45 sec
TC_rll_rel_ind_ACCH_0	41	45 sec
TC_rll_rel_ind_ACCH_3	41	45 sec
TC_rll_rel_ind_DCCH_0	2	45 sec
TC_rll_rel_ind_DCCH_3	2	46 sec
TC_rll_rel_req	41	45 sec
TC_rll_unit_data_ind_ACCH	1	40 sec
TC_rll_unit_data_ind_DCCH	1	45 sec
TC_rll_unit_data_req_ACCH	41	46 sec
TC_rll_unit_data_req_DCCH	1	46 sec
TC_rsl_bs_pwr_static_ass	2	38 sec
TC_rsl_bs_pwr_static_power_control	2	45 sec
TC_rsl_chan_initial_ms_pwr	41	36 sec
TC_rsl_chan_initial_ta	41	45 sec
TC_rsl_modify_encr	41	45 sec
TC_rsl_ms_pwr_ctrl	2	45 sec
TC_rsl_ms_pwr_dyn_active	41	25 sec
TC_rsl_ms_pwr_dyn_active2	41	16 sec
TC_rsl_ms_pwr_dyn_ass_updown	41	16 sec
TC_rsl_ms_pwr_dyn_down	41	16 sec
TC_rsl_ms_pwr_dyn_max	41	16 sec
TC_rsl_ms_pwr_dyn_up	41	16 sec
TC_sacch_chan_act	41	28 sec
TC_sacch_chan_act_ho_async	41	20 sec
TC_sacch_chan_act_ho_sync	41	17 sec
TC_sacch_filling	41	36 sec
TC_sacch_info_mod	41	32 sec
TC_sacch_multi	41	56 sec
TC_sacch_multi_chg	41	41 sec
TC_si_sched_1 Regression	2	46 sec
TC_si_sched_13	2	46 sec
TC_si_sched_13_2bis_2ter_2quater	3	47 sec
TC_si_sched_2bis Regression	2	46 sec
TC_si_sched_2quater Regression	2	46 sec
TC_si_sched_2ter	2	47 sec
TC_si_sched_2ter_2bis	2	46 sec
TC_si_sched_default Regression	2	38 sec
TC_speech_no_rtp_tchf	1	45 sec
TC_speech_no_rtp_tchh	1	45 sec
TC_tch_sign_l2_fill_frame	41	33 sec
TC_tch_sign_l2_fill_frame_dtxd	41	45 sec
TC_tx_power_ramp_adm_state_change	41	21 sec
TC_tx_power_start_ramp_down_bcch	41	27 sec
TC_tx_power_start_ramp_up_bcch	41	45 sec

All Tests

Class	Failed	Skipped	Passed	Total	Duration
ttcn3_bts_tests	79+7	0	22-7	101	1 hr 0 min