trial-ttcn3_bts_tests:trx 136

Took 43 min

All Failed Tests

Name	Age	Duration
TC_chan_act_a52	2	21 sec
TC_chan_act_a53	41	13 sec
TC_conn_fail_crit	2	25 sec
TC_deact_sacch	41	46 sec
TC_encr_cmd_a53	41	15 sec
TC_ho_rach	41	26 sec
TC_ipa_crcx_sdcch_not_active	2	10 sec
TC_meas_res_sign_sdcch4	41	26 sec
TC_meas_res_sign_sdcch8	41	26 sec
TC_meas_res_sign_tchf	41	25 sec
TC_meas_res_sign_tchh	41	26 sec
TC_meas_res_sign_tchh_toa256	41	25 sec
TC_meas_res_speech_tchf	15	21 sec
TC_meas_res_speech_tchf_facch	12	25 sec
TC_meas_res_speech_tchh	15	25 sec
TC_meas_res_speech_tchh_facch	12	25 sec
TC_meas_res_speech_tchh_toa256	14	25 sec
TC_ms_pwr_ctrl_constant	16	11 sec
TC_ms_pwr_ctrl_pf_ewma	15	11 sec
TC_paging_imsi_200percent	2	25 sec
TC_paging_imsi_80percent	2	26 sec
TC_paging_tmsi_200percent	2	25 sec
TC_paging_tmsi_80percent	2	25 sec
TC_pcu_data_ind_lqual_cb	10	13 sec
TC_pcu_ext_rach_content	10	12 sec
TC_pcu_oml_alert	10	13 sec
TC_pcu_ptcch	10	19 sec
TC_pcu_socket_disconnect_nosi4gprs	2	19 sec
TC_pcu_socket_nsvc_ipv4	10	2 sec
TC_pcu_socket_nsvc_ipv6	10	2 sec
TC_pcu_socket_verify_info_ind	4	12 sec
TC_rach_load_count	41	2 sec
TC_rach_load_idle_below_thresh	41	2 sec
TC_rach_load_idle_thresh0	41	2 sec
TC_rach_max_ta	41	11 sec
TC_rll_est_req_ACCH_3	41	16 sec
TC_rll_rel_ind_ACCH_0	41	17 sec
TC_rll_rel_ind_ACCH_3	41	17 sec
TC_rll_rel_req	41	22 sec
TC_rll_unit_data_req_ACCH	41	17 sec
TC_rsl_bs_pwr_static_ass	2	25 sec
TC_rsl_bs_pwr_static_power_control	2	25 sec
TC_rsl_chan_initial_ms_pwr	41	22 sec
TC_rsl_chan_initial_ta	41	26 sec
TC_rsl_modify_encr	41	26 sec
TC_rsl_ms_pwr_ctrl	2	26 sec
TC_rsl_ms_pwr_dyn_active	41	10 sec
TC_rsl_ms_pwr_dyn_active2	41	10 sec
TC_rsl_ms_pwr_dyn_ass_updown	41	4.8 sec
TC_rsl_ms_pwr_dyn_down	41	10 sec
TC_rsl_ms_pwr_dyn_max	41	4.9 sec
TC_rsl_ms_pwr_dyn_up	41	10 sec
TC_sacch_chan_act	41	27 sec
TC_sacch_chan_act_ho_async	41	10 sec
TC_sacch_chan_act_ho_sync	41	10 sec
TC_sacch_filling	41	22 sec
TC_sacch_info_mod	41	28 sec
TC_sacch_multi	41	39 sec
TC_sacch_multi_chg	41	48 sec
TC_si_sched_1	2	25 sec
TC_si_sched_2bis	2	25 sec
TC_si_sched_2ter	2	25 sec
TC_si_sched_2ter_2bis	2	25 sec
TC_si_sched_default	2	25 sec
TC_tch_sign_l2_fill_frame_dtxd	41	16 sec
TC_tx_power_ramp_adm_state_change	41	12 sec
TC_tx_power_start_ramp_down_bcch	41	12 sec
TC_tx_power_start_ramp_up_bcch	41	25 sec

All Tests

Class	Failed	Skipped	Passed	Total	Duration
ttcn3_bts_tests	68-18	0	68+18	136	43 min