trial-ttcn3_bts_tests:oc2g 101

Took 55 min

All Failed Tests

Name	Age	Duration
TC_chan_act_a51	1	40 sec
TC_chan_act_a52	3	39 sec
TC_chan_act_a53	42	40 sec
TC_conn_fail_crit	3	39 sec
TC_deact_sacch	42	31 sec
TC_encr_cmd_a51	1	39 sec
TC_encr_cmd_a52	1	40 sec
TC_encr_cmd_a53	42	39 sec
TC_ho_rach	42	40 sec
TC_meas_res_sign_sdcch4	42	39 sec
TC_meas_res_sign_sdcch8	42	40 sec
TC_meas_res_sign_tchf	42	39 sec
TC_meas_res_sign_tchh	42	40 sec
TC_meas_res_sign_tchh_toa256	42	39 sec
TC_meas_res_speech_tchf	16	28 sec
TC_meas_res_speech_tchf_facch	13	39 sec
TC_meas_res_speech_tchh	16	39 sec
TC_meas_res_speech_tchh_facch	13	39 sec
TC_meas_res_speech_tchh_toa256	15	40 sec
TC_ms_pwr_ctrl_constant	17	39 sec
TC_ms_pwr_ctrl_pf_ewma	16	39 sec
TC_paging_imsi_200percent	3	39 sec
TC_paging_imsi_80percent	3	40 sec
TC_paging_tmsi_200percent	3	40 sec
TC_paging_tmsi_80percent	3	39 sec
TC_rach_content	1	39 sec
TC_rach_content_emerg	1	39 sec
TC_rach_count	1	41 sec
TC_rach_load_count	42	2 sec
TC_rach_load_idle_below_thresh	42	2 sec
TC_rach_load_idle_thresh0	42	2 sec
TC_rach_max_ta	42	39 sec
TC_rll_est_ind	1	30 sec
TC_rll_est_req_ACCH_3	42	40 sec
TC_rll_est_req_DCCH_3	1	39 sec
TC_rll_rel_ind_ACCH_0	42	40 sec
TC_rll_rel_ind_ACCH_3	42	39 sec
TC_rll_rel_ind_DCCH_0	1	40 sec
TC_rll_rel_ind_DCCH_3	1	39 sec
TC_rll_rel_req	42	40 sec
TC_rll_unit_data_ind_ACCH	1	40 sec
TC_rll_unit_data_ind_DCCH	1	39 sec
TC_rll_unit_data_req_ACCH	42	39 sec
TC_rll_unit_data_req_DCCH	1	39 sec
TC_rsl_bs_pwr_static_ass	3	31 sec
TC_rsl_bs_pwr_static_power_control	3	39 sec
TC_rsl_chan_initial_ms_pwr	42	29 sec
TC_rsl_chan_initial_ta	42	40 sec
TC_rsl_modify_encr	42	40 sec
TC_rsl_ms_pwr_ctrl	3	40 sec
TC_rsl_ms_pwr_dyn_active	42	28 sec
TC_rsl_ms_pwr_dyn_active2	42	17 sec
TC_rsl_ms_pwr_dyn_ass_updown	42	17 sec
TC_rsl_ms_pwr_dyn_down	42	17 sec
TC_rsl_ms_pwr_dyn_max	42	17 sec
TC_rsl_ms_pwr_dyn_up	42	17 sec
TC_sacch_chan_act	42	39 sec
TC_sacch_chan_act_ho_async	42	40 sec
TC_sacch_chan_act_ho_sync	42	39 sec
TC_sacch_filling	42	39 sec
TC_sacch_info_mod	42	39 sec
TC_sacch_multi	42	39 sec
TC_sacch_multi_chg	42	40 sec
TC_si_sched_1	3	39 sec
TC_si_sched_13	1	40 sec
TC_si_sched_13_2bis_2ter_2quater	1	40 sec
TC_si_sched_2bis	3	40 sec
TC_si_sched_2quater	1	39 sec
TC_si_sched_2ter	3	39 sec
TC_si_sched_2ter_2bis	3	40 sec
TC_si_sched_default	3	29 sec
TC_speech_no_rtp_tchf	1	40 sec
TC_speech_no_rtp_tchh	1	39 sec
TC_tch_sign_l2_fill_frame	1	27 sec
TC_tch_sign_l2_fill_frame_dtxd	42	39 sec
TC_tx_power_ramp_adm_state_change	42	21 sec
TC_tx_power_start_ramp_down_bcch	42	31 sec
TC_tx_power_start_ramp_up_bcch	42	40 sec

All Tests

Class	Failed	Skipped	Passed	Total	Duration
ttcn3_bts_tests	78	0	23	101	55 min