trial-ttcn3_bts_tests:trx 136

Took 43 min

All Failed Tests

Name	Age	Duration
TC_chan_act_a53	42	13 sec
TC_conn_fail_crit	3	25 sec
TC_deact_sacch	42	46 sec
TC_encr_cmd_a53	42	15 sec
TC_ho_rach	42	27 sec
TC_ipa_crcx_sdcch_not_active	3	10 sec
TC_meas_res_sign_sdcch4	42	25 sec
TC_meas_res_sign_sdcch8	42	25 sec
TC_meas_res_sign_tchf	42	25 sec
TC_meas_res_sign_tchh	42	25 sec
TC_meas_res_sign_tchh_toa256	42	26 sec
TC_meas_res_speech_tchf	16	21 sec
TC_meas_res_speech_tchf_facch	13	26 sec
TC_meas_res_speech_tchh	16	25 sec
TC_meas_res_speech_tchh_facch	13	25 sec
TC_meas_res_speech_tchh_toa256	15	26 sec
TC_ms_pwr_ctrl_constant	17	11 sec
TC_ms_pwr_ctrl_pf_ewma	16	11 sec
TC_paging_imsi_200percent	3	25 sec
TC_paging_imsi_80percent	3	25 sec
TC_paging_tmsi_200percent	3	25 sec
TC_paging_tmsi_80percent	3	25 sec
TC_pcu_data_ind_lqual_cb	11	14 sec
TC_pcu_ext_rach_content	11	13 sec
TC_pcu_oml_alert	11	13 sec
TC_pcu_ptcch	11	19 sec
TC_pcu_socket_noconnect_nosi3gprs Regression	1	15 sec
TC_pcu_socket_nsvc_ipv4	11	2 sec
TC_pcu_socket_nsvc_ipv6	11	2 sec
TC_pcu_socket_verify_info_ind	5	14 sec
TC_rach_count Regression	1	1 min 3 sec
TC_rach_load_count	42	2 sec
TC_rach_load_idle_below_thresh	42	2 sec
TC_rach_load_idle_thresh0	42	2 sec
TC_rach_max_ta	42	11 sec
TC_rll_est_req_ACCH_3	42	15 sec
TC_rll_rel_ind_ACCH_0	42	18 sec
TC_rll_rel_ind_ACCH_3	42	16 sec
TC_rll_rel_ind_DCCH_0 Regression	1	19 sec
TC_rll_rel_req	42	22 sec
TC_rll_unit_data_req_ACCH	42	16 sec
TC_rsl_bs_pwr_static_ass	3	25 sec
TC_rsl_bs_pwr_static_power_control	3	25 sec
TC_rsl_chan_initial_ms_pwr	42	25 sec
TC_rsl_chan_initial_ta	42	25 sec
TC_rsl_modify_encr	42	25 sec
TC_rsl_ms_pwr_ctrl	3	26 sec
TC_rsl_ms_pwr_dyn_active	42	10 sec
TC_rsl_ms_pwr_dyn_active2	42	10 sec
TC_rsl_ms_pwr_dyn_ass_updown	42	10 sec
TC_rsl_ms_pwr_dyn_down	42	10 sec
TC_rsl_ms_pwr_dyn_max	42	10 sec
TC_rsl_ms_pwr_dyn_up	42	10 sec
TC_sacch_chan_act	42	25 sec
TC_sacch_chan_act_ho_async	42	11 sec
TC_sacch_chan_act_ho_sync	42	10 sec
TC_sacch_filling	42	21 sec
TC_sacch_info_mod	42	28 sec
TC_sacch_multi	42	40 sec
TC_sacch_multi_chg	42	49 sec
TC_si_sched_1	3	25 sec
TC_si_sched_13 Regression	1	25 sec
TC_si_sched_13_2bis_2ter_2quater Regression	1	25 sec
TC_si_sched_2bis	3	25 sec
TC_si_sched_2quater Regression	1	25 sec
TC_si_sched_2ter	3	25 sec
TC_si_sched_2ter_2bis	3	25 sec
TC_si_sched_default	3	25 sec
TC_tch_sign_l2_fill_frame_dtxd	42	16 sec
TC_tx_power_ramp_adm_state_change	42	12 sec
TC_tx_power_start_ramp_down_bcch	42	12 sec
TC_tx_power_start_ramp_up_bcch	42	13 sec

All Tests

Class	Failed	Skipped	Passed	Total	Duration
ttcn3_bts_tests	72+4	0	64-4	136	43 min