trial-ttcn3_bts_tests:sysmo 101

Took 49 min

All Failed Tests

Name	Age	Duration
TC_chan_act_a51	1	34 sec
TC_chan_act_a52	1	33 sec
TC_chan_act_a53	43	42 sec
TC_chan_act_stress	1	24 sec
TC_deact_sacch	43	1 min 2 sec
TC_encr_cmd_a51	1	34 sec
TC_encr_cmd_a52	1	33 sec
TC_encr_cmd_a53	43	34 sec
TC_ho_rach	43	31 sec
TC_meas_res_sign_sdcch4	43	26 sec
TC_meas_res_sign_sdcch8	43	28 sec
TC_meas_res_sign_tchf	43	20 sec
TC_meas_res_sign_tchh	43	28 sec
TC_meas_res_sign_tchh_toa256	43	35 sec
TC_meas_res_speech_tchf	17	15 sec
TC_meas_res_speech_tchf_facch	14	19 sec
TC_meas_res_speech_tchh	17	19 sec
TC_meas_res_speech_tchh_facch	14	19 sec
TC_meas_res_speech_tchh_toa256	16	19 sec
TC_ms_pwr_ctrl_constant	18	26 sec
TC_ms_pwr_ctrl_pf_ewma	17	17 sec
TC_paging_imsi_200percent	4	59 sec
TC_paging_imsi_80percent	4	47 sec
TC_paging_tmsi_200percent	4	53 sec
TC_paging_tmsi_80percent	4	47 sec
TC_rach_load_count	43	2 sec
TC_rach_load_idle_below_thresh	43	2 sec
TC_rach_load_idle_thresh0	43	2 sec
TC_rach_max_ta	43	26 sec
TC_rll_est_ind	1	32 sec
TC_rll_est_req_ACCH_3	43	34 sec
TC_rll_est_req_DCCH_3	1	29 sec
TC_rll_rel_ind_ACCH_0	43	33 sec
TC_rll_rel_ind_ACCH_3	43	33 sec
TC_rll_rel_ind_DCCH_0	2	33 sec
TC_rll_rel_ind_DCCH_3	1	33 sec
TC_rll_rel_req	43	33 sec
TC_rll_unit_data_ind_ACCH	1	33 sec
TC_rll_unit_data_ind_DCCH	1	33 sec
TC_rll_unit_data_req_ACCH	43	33 sec
TC_rll_unit_data_req_DCCH	1	33 sec
TC_rsl_bs_pwr_static_ass	4	30 sec
TC_rsl_bs_pwr_static_power_control Regression	4	37 sec
TC_rsl_chan_initial_ms_pwr	43	29 sec
TC_rsl_chan_initial_ta	43	25 sec
TC_rsl_modify_encr	43	31 sec
TC_rsl_ms_pwr_ctrl	4	46 sec
TC_rsl_ms_pwr_dyn_active	43	25 sec
TC_rsl_ms_pwr_dyn_active2	43	16 sec
TC_rsl_ms_pwr_dyn_ass_updown	43	16 sec
TC_rsl_ms_pwr_dyn_down	43	16 sec
TC_rsl_ms_pwr_dyn_max	43	16 sec
TC_rsl_ms_pwr_dyn_up	43	16 sec
TC_sacch_chan_act	43	28 sec
TC_sacch_chan_act_ho_async	43	20 sec
TC_sacch_chan_act_ho_sync	43	25 sec
TC_sacch_filling	43	30 sec
TC_sacch_info_mod	43	33 sec
TC_sacch_multi	43	28 sec
TC_sacch_multi_chg	43	1 min 4 sec
TC_si_sched_13	2	33 sec
TC_si_sched_13_2bis_2ter_2quater	2	40 sec
TC_si_sched_2quater Regression	2	40 sec
TC_si_sched_2ter_2bis	4	32 sec
TC_speech_no_rtp_tchf	1	25 sec
TC_speech_no_rtp_tchh	1	33 sec
TC_tch_sign_l2_fill_frame	1	23 sec
TC_tch_sign_l2_fill_frame_dtxd	43	33 sec
TC_tx_power_ramp_adm_state_change	43	20 sec
TC_tx_power_start_ramp_down_bcch	43	19 sec
TC_tx_power_start_ramp_up_bcch	43	26 sec

All Tests

Class	Failed	Skipped	Passed	Total	Duration
ttcn3_bts_tests	71+1	0	30-1	101	49 min