trial-ttcn3_bts_tests:trx 136

Took 43 min

All Failed Tests

Name	Age	Duration
TC_chan_act_a53	43	13 sec
TC_conn_fail_crit	4	25 sec
TC_deact_sacch	43	46 sec
TC_encr_cmd_a53	43	15 sec
TC_ho_rach	43	26 sec
TC_ipa_crcx_sdcch_not_active	4	10 sec
TC_meas_res_sign_sdcch4	43	25 sec
TC_meas_res_sign_sdcch8	43	26 sec
TC_meas_res_sign_tchf	43	25 sec
TC_meas_res_sign_tchh	43	25 sec
TC_meas_res_sign_tchh_toa256	43	26 sec
TC_meas_res_speech_tchf	17	21 sec
TC_meas_res_speech_tchf_facch	14	25 sec
TC_meas_res_speech_tchh	17	26 sec
TC_meas_res_speech_tchh_facch	14	25 sec
TC_meas_res_speech_tchh_toa256	16	25 sec
TC_ms_pwr_ctrl_constant	18	11 sec
TC_ms_pwr_ctrl_pf_ewma	17	11 sec
TC_paging_imsi_200percent	4	25 sec
TC_paging_imsi_80percent	4	25 sec
TC_paging_tmsi_200percent	4	25 sec
TC_paging_tmsi_80percent	4	25 sec
TC_pcu_data_ind_lqual_cb	12	14 sec
TC_pcu_ext_rach_content	12	13 sec
TC_pcu_oml_alert	12	13 sec
TC_pcu_ptcch	12	19 sec
TC_pcu_socket_noconnect_nosi3gprs	2	16 sec
TC_pcu_socket_nsvc_ipv4	12	2 sec
TC_pcu_socket_nsvc_ipv6	12	2 sec
TC_rach_load_count	43	2 sec
TC_rach_load_idle_below_thresh	43	2 sec
TC_rach_load_idle_thresh0	43	2 sec
TC_rach_max_ta	43	11 sec
TC_rll_est_req_ACCH_3	43	15 sec
TC_rll_rel_ind_ACCH_0	43	17 sec
TC_rll_rel_ind_ACCH_3	43	16 sec
TC_rll_rel_req	43	22 sec
TC_rll_unit_data_req_ACCH	43	15 sec
TC_rsl_bs_pwr_static_ass	4	25 sec
TC_rsl_bs_pwr_static_power_control	4	25 sec
TC_rsl_chan_initial_ms_pwr	43	25 sec
TC_rsl_chan_initial_ta	43	25 sec
TC_rsl_modify_encr	43	25 sec
TC_rsl_ms_pwr_ctrl	4	25 sec
TC_rsl_ms_pwr_dyn_active	43	10 sec
TC_rsl_ms_pwr_dyn_active2	43	10 sec
TC_rsl_ms_pwr_dyn_ass_updown	43	10 sec
TC_rsl_ms_pwr_dyn_down	43	10 sec
TC_rsl_ms_pwr_dyn_max	43	10 sec
TC_rsl_ms_pwr_dyn_up	43	10 sec
TC_sacch_chan_act	43	27 sec
TC_sacch_chan_act_ho_async	43	10 sec
TC_sacch_chan_act_ho_sync	43	10 sec
TC_sacch_filling	43	21 sec
TC_sacch_info_mod	43	27 sec
TC_sacch_multi	43	39 sec
TC_sacch_multi_chg	43	49 sec
TC_si_sched_1	4	25 sec
TC_si_sched_2bis	4	25 sec
TC_si_sched_2ter	4	25 sec
TC_si_sched_default	4	25 sec
TC_tch_sign_l2_fill_frame_dtxd	43	16 sec
TC_tx_power_ramp_adm_state_change	43	12 sec
TC_tx_power_start_ramp_down_bcch	43	12 sec
TC_tx_power_start_ramp_up_bcch	43	25 sec

All Tests

Class	Failed	Skipped	Passed	Total	Duration
ttcn3_bts_tests	65-7	0	71+7	136	43 min