trial-ttcn3_bts_tests:trx 136

Took 48 min

All Failed Tests

Name	Age	Duration
TC_chan_act_a51 Regression	1	25 sec
TC_chan_act_a52 Regression	1	25 sec
TC_chan_act_a53	6	25 sec
TC_conn_fail_crit	2	25 sec
TC_deact_sacch	6	46 sec
TC_encr_cmd_a51 Regression	1	26 sec
TC_encr_cmd_a52 Regression	1	26 sec
TC_encr_cmd_a53	6	25 sec
TC_ho_rach	6	26 sec
TC_ipa_crcx_sdcch_not_active Regression	1	10 sec
TC_meas_res_sign_sdcch4	6	25 sec
TC_meas_res_sign_sdcch8	6	25 sec
TC_meas_res_sign_tchf	6	25 sec
TC_meas_res_sign_tchh	6	25 sec
TC_meas_res_sign_tchh_toa256	6	25 sec
TC_meas_res_speech_tchf	6	21 sec
TC_meas_res_speech_tchf_facch	6	26 sec
TC_meas_res_speech_tchh	6	25 sec
TC_meas_res_speech_tchh_facch	6	25 sec
TC_meas_res_speech_tchh_toa256	6	25 sec
TC_ms_pwr_ctrl_constant	6	25 sec
TC_ms_pwr_ctrl_pf_ewma	6	25 sec
TC_paging_imsi_200percent Regression	1	25 sec
TC_paging_imsi_80percent Regression	1	25 sec
TC_paging_tmsi_200percent Regression	1	25 sec
TC_paging_tmsi_80percent Regression	1	26 sec
TC_pcu_data_ind_lqual_cb	6	25 sec
TC_pcu_data_req_agch Regression	1	25 sec
TC_pcu_data_req_imm_ass_pch Regression	1	25 sec
TC_pcu_data_req_pch Regression	1	25 sec
TC_pcu_ext_rach_content	6	25 sec
TC_pcu_oml_alert	6	13 sec
TC_pcu_ptcch	6	25 sec
TC_pcu_rach_content Regression	1	25 sec
TC_pcu_rr_suspend Regression	1	25 sec
TC_pcu_socket_connect_si3gprs Regression	1	25 sec
TC_pcu_socket_connect_si4gprs Regression	1	26 sec
TC_pcu_socket_disconnect_nosi3gprs Regression	1	25 sec
TC_pcu_socket_disconnect_nosi4gprs Regression	1	25 sec
TC_pcu_socket_noconnect_nosi3gprs Regression	1	22 sec
TC_pcu_socket_noconnect_nosi4gprs Regression	1	21 sec
TC_pcu_socket_nsvc_ipv4	6	2 sec
TC_pcu_socket_nsvc_ipv6	6	2 sec
TC_pcu_time_ind Regression	1	18 sec
TC_rach_load_count	6	2 sec
TC_rach_load_idle_below_thresh	6	2 sec
TC_rach_load_idle_thresh0	6	2 sec
TC_rach_max_ta	6	12 sec
TC_rll_est_ind Regression	1	25 sec
TC_rll_est_req_ACCH_3	6	26 sec
TC_rll_est_req_DCCH_3 Regression	1	25 sec
TC_rll_rel_ind_ACCH_0	6	25 sec
TC_rll_rel_ind_ACCH_3	6	25 sec
TC_rll_rel_ind_DCCH_0 Regression	1	25 sec
TC_rll_rel_ind_DCCH_3 Regression	1	25 sec
TC_rll_rel_req	6	25 sec
TC_rll_unit_data_ind_ACCH Regression	1	25 sec
TC_rll_unit_data_ind_DCCH Regression	1	25 sec
TC_rll_unit_data_req_ACCH	6	25 sec
TC_rll_unit_data_req_DCCH Regression	1	26 sec
TC_rsl_bs_pwr_static_ass Regression	1	26 sec
TC_rsl_bs_pwr_static_power_control Regression	1	25 sec
TC_rsl_chan_initial_ms_pwr	6	25 sec
TC_rsl_chan_initial_ta	6	26 sec
TC_rsl_modify_encr	6	25 sec
TC_rsl_ms_pwr_ctrl Regression	1	25 sec
TC_rsl_ms_pwr_dyn_active	6	10 sec
TC_rsl_ms_pwr_dyn_active2	6	10 sec
TC_rsl_ms_pwr_dyn_ass_updown	6	10 sec
TC_rsl_ms_pwr_dyn_down	6	10 sec
TC_rsl_ms_pwr_dyn_max	6	10 sec
TC_rsl_ms_pwr_dyn_up	6	10 sec
TC_sacch_chan_act	6	26 sec
TC_sacch_chan_act_ho_async	6	11 sec
TC_sacch_chan_act_ho_sync	6	11 sec
TC_sacch_filling	6	21 sec
TC_sacch_info_mod	6	27 sec
TC_sacch_multi	6	42 sec
TC_sacch_multi_chg	6	48 sec
TC_si_sched_1 Regression	1	25 sec
TC_si_sched_13 Regression	1	25 sec
TC_si_sched_13_2bis_2ter_2quater Regression	1	25 sec
TC_si_sched_2bis Regression	1	25 sec
TC_si_sched_2quater Regression	1	25 sec
TC_si_sched_2ter Regression	1	25 sec
TC_si_sched_2ter_2bis Regression	1	25 sec
TC_si_sched_default Regression	1	25 sec
TC_speech_no_rtp_tchf Regression	1	25 sec
TC_speech_no_rtp_tchh Regression	1	26 sec
TC_tch_sign_l2_fill_frame Regression	1	23 sec
TC_tch_sign_l2_fill_frame_dtxd	6	25 sec
TC_tx_power_ramp_adm_state_change	6	12 sec
TC_tx_power_start_ramp_down_bcch	6	12 sec
TC_tx_power_start_ramp_up_bcch	6	25 sec

All Tests

Class	Failed	Skipped	Passed	Total	Duration
ttcn3_bts_tests	94+42	0	42-42	136	48 min