trial-ttcn3_bts_tests:sysmo 101

Took 55 min

All Failed Tests

Name	Age	Duration
TC_chan_act_a51	1	29 sec
TC_chan_act_a52	1	25 sec
TC_chan_act_a53	8	23 sec
TC_chan_act_stress	1	25 sec
TC_conn_fail_crit	4	44 sec
TC_deact_sacch	8	33 sec
TC_encr_cmd_a51	1	24 sec
TC_encr_cmd_a52	1	24 sec
TC_encr_cmd_a53	8	32 sec
TC_ho_rach	8	36 sec
TC_meas_res_sign_sdcch4	8	44 sec
TC_meas_res_sign_sdcch8	8	44 sec
TC_meas_res_sign_tchf	8	45 sec
TC_meas_res_sign_tchh	8	44 sec
TC_meas_res_sign_tchh_toa256	8	44 sec
TC_meas_res_speech_tchf	8	32 sec
TC_meas_res_speech_tchf_facch	8	44 sec
TC_meas_res_speech_tchh	8	44 sec
TC_meas_res_speech_tchh_facch	8	44 sec
TC_meas_res_speech_tchh_toa256	8	44 sec
TC_ms_pwr_ctrl_constant	8	26 sec
TC_ms_pwr_ctrl_pf_ewma	8	18 sec
TC_paging_imsi_200percent	1	44 sec
TC_paging_imsi_80percent	1	44 sec
TC_paging_tmsi_200percent	1	44 sec
TC_paging_tmsi_80percent	1	44 sec
TC_rach_load_count	8	2 sec
TC_rach_load_idle_below_thresh	8	2 sec
TC_rach_load_idle_thresh0	8	2 sec
TC_rach_max_ta	8	26 sec
TC_rll_est_ind	1	37 sec
TC_rll_est_req_ACCH_3	8	44 sec
TC_rll_est_req_DCCH_3	1	44 sec
TC_rll_rel_ind_ACCH_0	8	44 sec
TC_rll_rel_ind_ACCH_3	8	44 sec
TC_rll_rel_ind_DCCH_0	1	45 sec
TC_rll_rel_ind_DCCH_3	1	44 sec
TC_rll_rel_req	8	44 sec
TC_rll_unit_data_ind_ACCH	1	36 sec
TC_rll_unit_data_ind_DCCH	1	38 sec
TC_rll_unit_data_req_ACCH	8	36 sec
TC_rll_unit_data_req_DCCH	1	38 sec
TC_rsl_bs_pwr_static_ass	1	37 sec
TC_rsl_bs_pwr_static_power_control	1	45 sec
TC_rsl_chan_initial_ms_pwr	8	35 sec
TC_rsl_chan_initial_ta	8	45 sec
TC_rsl_modify_encr	8	44 sec
TC_rsl_ms_pwr_ctrl	1	44 sec
TC_rsl_ms_pwr_dyn_active	8	25 sec
TC_rsl_ms_pwr_dyn_active2	8	16 sec
TC_rsl_ms_pwr_dyn_ass_updown	8	16 sec
TC_rsl_ms_pwr_dyn_down	8	16 sec
TC_rsl_ms_pwr_dyn_max	8	16 sec
TC_rsl_ms_pwr_dyn_up	8	16 sec
TC_sacch_chan_act	8	32 sec
TC_sacch_chan_act_ho_async	8	31 sec
TC_sacch_chan_act_ho_sync	8	38 sec
TC_sacch_filling	8	30 sec
TC_sacch_info_mod	8	26 sec
TC_sacch_multi	8	26 sec
TC_sacch_multi_chg	8	23 sec
TC_si_sched_1	1	45 sec
TC_si_sched_13	1	44 sec
TC_si_sched_13_2bis_2ter_2quater	1	48 sec
TC_si_sched_2bis	1	44 sec
TC_si_sched_2quater	1	44 sec
TC_si_sched_2ter	1	44 sec
TC_si_sched_2ter_2bis	1	44 sec
TC_si_sched_default	1	35 sec
TC_speech_no_rtp_tchf	3	20 sec
TC_speech_no_rtp_tchh	1	23 sec
TC_tch_sign_l2_fill_frame	1	25 sec
TC_tch_sign_l2_fill_frame_dtxd	8	35 sec
TC_tx_power_ramp_adm_state_change	8	20 sec
TC_tx_power_start_ramp_down_bcch	8	27 sec
TC_tx_power_start_ramp_up_bcch	8	44 sec

All Tests

Class	Failed	Skipped	Passed	Total	Duration
ttcn3_bts_tests	76	0	25	101	55 min