trial-ttcn3_bts_tests:oc2g 101

Took 55 min

All Failed Tests

Name	Age	Duration
TC_chan_act_a51	3	39 sec
TC_chan_act_a52	3	40 sec
TC_chan_act_a53	10	39 sec
TC_chan_act_stress Regression	1	30 sec
TC_conn_fail_crit	6	39 sec
TC_deact_sacch	10	31 sec
TC_encr_cmd_a51	3	40 sec
TC_encr_cmd_a52	3	39 sec
TC_encr_cmd_a53	10	39 sec
TC_ho_rach	10	40 sec
TC_meas_res_sign_sdcch4	10	40 sec
TC_meas_res_sign_sdcch8	10	40 sec
TC_meas_res_sign_tchf	10	39 sec
TC_meas_res_sign_tchh	10	39 sec
TC_meas_res_sign_tchh_toa256	10	39 sec
TC_meas_res_speech_tchf	10	27 sec
TC_meas_res_speech_tchf_facch	10	39 sec
TC_meas_res_speech_tchh	10	39 sec
TC_meas_res_speech_tchh_facch	10	39 sec
TC_meas_res_speech_tchh_toa256	10	40 sec
TC_ms_pwr_ctrl_constant	10	39 sec
TC_ms_pwr_ctrl_pf_ewma	10	39 sec
TC_paging_imsi_200percent	3	39 sec
TC_paging_imsi_80percent	3	40 sec
TC_paging_tmsi_200percent	3	40 sec
TC_paging_tmsi_80percent	3	39 sec
TC_rach_content	2	40 sec
TC_rach_content_emerg	2	39 sec
TC_rach_count	2	40 sec
TC_rach_load_count	10	2 sec
TC_rach_load_idle_below_thresh	10	2 sec
TC_rach_load_idle_thresh0	10	2 sec
TC_rach_max_ta	10	39 sec
TC_rll_est_ind	3	29 sec
TC_rll_est_req_ACCH_3	10	40 sec
TC_rll_est_req_DCCH_3	3	39 sec
TC_rll_rel_ind_ACCH_0	10	39 sec
TC_rll_rel_ind_ACCH_3	10	40 sec
TC_rll_rel_ind_DCCH_0	3	39 sec
TC_rll_rel_ind_DCCH_3	3	40 sec
TC_rll_rel_req	10	39 sec
TC_rll_unit_data_ind_ACCH	3	40 sec
TC_rll_unit_data_ind_DCCH	3	39 sec
TC_rll_unit_data_req_ACCH	10	39 sec
TC_rll_unit_data_req_DCCH	3	40 sec
TC_rsl_bs_pwr_static_ass	3	31 sec
TC_rsl_bs_pwr_static_power_control	3	39 sec
TC_rsl_chan_initial_ms_pwr	10	29 sec
TC_rsl_chan_initial_ta	10	39 sec
TC_rsl_modify_encr	10	40 sec
TC_rsl_ms_pwr_ctrl	3	40 sec
TC_rsl_ms_pwr_dyn_active	10	29 sec
TC_rsl_ms_pwr_dyn_active2	10	17 sec
TC_rsl_ms_pwr_dyn_ass_updown	10	17 sec
TC_rsl_ms_pwr_dyn_down	10	17 sec
TC_rsl_ms_pwr_dyn_max	10	17 sec
TC_rsl_ms_pwr_dyn_up	10	17 sec
TC_sacch_chan_act	10	39 sec
TC_sacch_chan_act_ho_async	10	40 sec
TC_sacch_chan_act_ho_sync	10	39 sec
TC_sacch_filling	10	39 sec
TC_sacch_info_mod	10	40 sec
TC_sacch_multi	10	39 sec
TC_sacch_multi_chg	10	40 sec
TC_si_sched_1	3	39 sec
TC_si_sched_13	3	39 sec
TC_si_sched_13_2bis_2ter_2quater	3	40 sec
TC_si_sched_2bis	3	39 sec
TC_si_sched_2quater	3	39 sec
TC_si_sched_2ter	3	39 sec
TC_si_sched_2ter_2bis	3	40 sec
TC_si_sched_default	3	29 sec
TC_speech_no_rtp_tchf	5	40 sec
TC_speech_no_rtp_tchh	3	40 sec
TC_tch_sign_l2_fill_frame	3	27 sec
TC_tch_sign_l2_fill_frame_dtxd	10	39 sec
TC_tx_power_ramp_adm_state_change	10	21 sec
TC_tx_power_start_ramp_down_bcch	10	30 sec
TC_tx_power_start_ramp_up_bcch	10	40 sec

All Tests

Class	Failed	Skipped	Passed	Total	Duration
ttcn3_bts_tests	79+1	0	22-1	101	55 min