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osmo-gsm-tester_ttcn3
#2753
Tests
trial-ttcn3_bts_tests:trx
ttcn3_bts_tests
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ttcn3_bts_tests
136
117
19
22
Took 28 min
All Tests
Name
Age
Duration
TC_chan_act_a51
3
12 sec
TC_chan_act_a52
3
6.8 sec
TC_chan_act_a53
10
13 sec
TC_chan_act_react
Regression
1
13 sec
TC_chan_act_stress
Regression
1
6.7 sec
TC_chan_act_wrong_nr
Regression
1
12 sec
TC_chan_deact_not_active
Regression
1
12 sec
TC_chopped_ipa_payload
0
43 sec
TC_chopped_ipa_ping
0
30 sec
TC_conn_fail_crit
6
12 sec
TC_deact_sacch
10
12 sec
TC_dyn_ipa_pdch_act_deact
Regression
1
12 sec
TC_dyn_ipa_pdch_act_tchf_act_nack
Regression
1
12 sec
TC_dyn_ipa_pdch_tchf_act
Regression
1
12 sec
TC_dyn_ipa_pdch_tchf_act_pdch_act_nack
Regression
1
12 sec
TC_dyn_osmo_pdch_act_deact
Regression
1
12 sec
TC_dyn_osmo_pdch_double_act
Regression
1
12 sec
TC_dyn_osmo_pdch_tchf_act
2
12 sec
TC_dyn_osmo_pdch_tchh_act
2
12 sec
TC_dyn_osmo_pdch_unsol_deact
Regression
1
8.6 sec
TC_encr_cmd_a51
3
12 sec
TC_encr_cmd_a52
3
12 sec
TC_encr_cmd_a53
10
12 sec
TC_err_rep_wrong_mdisc
Regression
1
12 sec
TC_err_rep_wrong_msg_type
Regression
1
12 sec
TC_err_rep_wrong_sequence
Regression
1
12 sec
TC_ho_rach
10
12 sec
TC_ipa_crcx_mdcx_dlcx_not_active
Regression
1
12 sec
TC_ipa_crcx_mdcx_mdcx_dlcx_not_active
Regression
1
12 sec
TC_ipa_crcx_sdcch_not_active
2
12 sec
TC_ipa_crcx_twice_not_active
Regression
1
12 sec
TC_ipa_dlcx_not_active
Regression
1
12 sec
TC_lapdm_selftest
0
23 ms
TC_meas_res_sign_sdcch4
10
12 sec
TC_meas_res_sign_sdcch8
10
12 sec
TC_meas_res_sign_tchf
10
12 sec
TC_meas_res_sign_tchh
10
12 sec
TC_meas_res_sign_tchh_toa256
10
12 sec
TC_meas_res_speech_tchf
10
8.5 sec
TC_meas_res_speech_tchf_facch
10
12 sec
TC_meas_res_speech_tchh
10
12 sec
TC_meas_res_speech_tchh_facch
10
12 sec
TC_meas_res_speech_tchh_toa256
10
12 sec
TC_ms_pwr_ctrl_constant
10
12 sec
TC_ms_pwr_ctrl_pf_ewma
10
12 sec
TC_paging_imsi_200percent
3
12 sec
TC_paging_imsi_80percent
3
12 sec
TC_paging_tmsi_200percent
3
12 sec
TC_paging_tmsi_80percent
3
12 sec
TC_pcu_act_req
0
13 sec
TC_pcu_act_req_wrong_bts
0
16 sec
TC_pcu_act_req_wrong_trx
0
16 sec
TC_pcu_act_req_wrong_ts
0
16 sec
TC_pcu_data_ind_lqual_cb
2
12 sec
TC_pcu_data_req_agch
2
12 sec
TC_pcu_data_req_imm_ass_pch
2
12 sec
TC_pcu_data_req_pch
2
12 sec
TC_pcu_deact_req
0
18 sec
TC_pcu_deact_req_wrong_ts
0
14 sec
TC_pcu_ext_rach_content
2
12 sec
TC_pcu_info_ind_fh_params
0
10 sec
TC_pcu_oml_alert
2
13 sec
TC_pcu_paging_from_rsl
0
12 sec
TC_pcu_ptcch
2
12 sec
TC_pcu_rach_content
2
12 sec
TC_pcu_rr_suspend
2
12 sec
TC_pcu_rts_req
0
18 sec
TC_pcu_socket_connect_multi
0
15 sec
TC_pcu_socket_connect_si3gprs
2
12 sec
TC_pcu_socket_connect_si4gprs
2
12 sec
TC_pcu_socket_disconnect_nosi3gprs
2
12 sec
TC_pcu_socket_disconnect_nosi4gprs
2
12 sec
TC_pcu_socket_noconnect_nosi3gprs
2
9.1 sec
TC_pcu_socket_noconnect_nosi4gprs
2
9.8 sec
TC_pcu_socket_nsvc_ipv4
2
2 sec
TC_pcu_socket_nsvc_ipv6
2
2 sec
TC_pcu_socket_reconnect
0
12 sec
TC_pcu_socket_verify_info_ind
Regression
1
12 sec
TC_pcu_time_ind
0
18 sec
TC_pcu_ver_si13
0
10 sec
TC_rach_content
Regression
1
12 sec
TC_rach_content_emerg
Regression
1
12 sec
TC_rach_count
Regression
1
12 sec
TC_rach_load_count
10
2 sec
TC_rach_load_idle_below_thresh
10
2 sec
TC_rach_load_idle_thresh0
10
2 sec
TC_rach_max_ta
10
12 sec
TC_rll_est_ind
3
12 sec
TC_rll_est_req_ACCH_3
10
12 sec
TC_rll_est_req_DCCH_3
3
12 sec
TC_rll_rel_ind_ACCH_0
10
12 sec
TC_rll_rel_ind_ACCH_3
10
12 sec
TC_rll_rel_ind_DCCH_0
3
12 sec
TC_rll_rel_ind_DCCH_3
3
12 sec
TC_rll_rel_req
10
12 sec
TC_rll_unit_data_ind_ACCH
3
12 sec
TC_rll_unit_data_ind_DCCH
3
12 sec
TC_rll_unit_data_req_ACCH
10
12 sec
TC_rll_unit_data_req_DCCH
3
12 sec
TC_rsl_bs_pwr_static_ass
3
12 sec
TC_rsl_bs_pwr_static_power_control
3
12 sec
TC_rsl_chan_initial_ms_pwr
10
12 sec
TC_rsl_chan_initial_ta
10
12 sec
TC_rsl_ie_content_error
0
10 sec
TC_rsl_mand_ie_error
0
10 sec
TC_rsl_modify_encr
10
12 sec
TC_rsl_ms_pwr_ctrl
3
12 sec
TC_rsl_ms_pwr_dyn_active
10
12 sec
TC_rsl_ms_pwr_dyn_active2
10
12 sec
TC_rsl_ms_pwr_dyn_ass_updown
10
12 sec
TC_rsl_ms_pwr_dyn_down
10
12 sec
TC_rsl_ms_pwr_dyn_max
10
12 sec
TC_rsl_ms_pwr_dyn_up
10
12 sec
TC_rsl_protocol_error
0
10 sec
TC_sacch_chan_act
10
12 sec
TC_sacch_chan_act_ho_async
10
12 sec
TC_sacch_chan_act_ho_sync
10
12 sec
TC_sacch_filling
10
12 sec
TC_sacch_info_mod
10
12 sec
TC_sacch_multi
10
12 sec
TC_sacch_multi_chg
10
12 sec
TC_si_sched_1
3
12 sec
TC_si_sched_13
3
12 sec
TC_si_sched_13_2bis_2ter_2quater
3
12 sec
TC_si_sched_2bis
3
12 sec
TC_si_sched_2quater
3
12 sec
TC_si_sched_2ter
3
12 sec
TC_si_sched_2ter_2bis
3
12 sec
TC_si_sched_default
3
12 sec
TC_speech_no_rtp_tchf
5
12 sec
TC_speech_no_rtp_tchh
3
12 sec
TC_tch_sign_l2_fill_frame
3
10 sec
TC_tch_sign_l2_fill_frame_dtxd
10
12 sec
TC_tx_power_ramp_adm_state_change
10
12 sec
TC_tx_power_start_ramp_down_bcch
10
12 sec
TC_tx_power_start_ramp_up_bcch
10
12 sec
