trial-ttcn3_bts_tests:sysmo 101

Took 48 min

All Failed Tests

Name	Age	Duration
TC_chan_act_a51	4	36 sec
TC_chan_act_a52	4	29 sec
TC_chan_act_a53	11	23 sec
TC_chan_act_stress	4	25 sec
TC_deact_sacch	11	33 sec
TC_encr_cmd_a51	4	25 sec
TC_encr_cmd_a52	4	25 sec
TC_encr_cmd_a53	11	24 sec
TC_ho_rach	11	36 sec
TC_meas_res_sign_sdcch4	11	19 sec
TC_meas_res_sign_sdcch8	11	20 sec
TC_meas_res_sign_tchf	11	27 sec
TC_meas_res_sign_tchh	11	19 sec
TC_meas_res_sign_tchh_toa256	11	28 sec
TC_meas_res_speech_tchf	11	33 sec
TC_meas_res_speech_tchf_facch	11	45 sec
TC_meas_res_speech_tchh	11	26 sec
TC_meas_res_speech_tchh_facch	11	19 sec
TC_meas_res_speech_tchh_toa256	11	28 sec
TC_ms_pwr_ctrl_constant	11	26 sec
TC_ms_pwr_ctrl_pf_ewma	11	18 sec
TC_paging_imsi_200percent	4	1 min 0 sec
TC_paging_imsi_80percent	4	47 sec
TC_paging_tmsi_200percent	4	53 sec
TC_paging_tmsi_80percent	4	47 sec
TC_rach_load_count	11	2 sec
TC_rach_load_idle_below_thresh	11	2 sec
TC_rach_load_idle_thresh0	11	2 sec
TC_rach_max_ta	11	26 sec
TC_rll_est_ind	4	28 sec
TC_rll_est_req_ACCH_3	11	30 sec
TC_rll_est_req_DCCH_3	4	29 sec
TC_rll_rel_ind_ACCH_0	11	29 sec
TC_rll_rel_ind_ACCH_3	11	25 sec
TC_rll_rel_ind_DCCH_0	4	37 sec
TC_rll_rel_ind_DCCH_3	4	36 sec
TC_rll_rel_req	11	25 sec
TC_rll_unit_data_ind_ACCH	4	37 sec
TC_rll_unit_data_ind_DCCH	4	37 sec
TC_rll_unit_data_req_ACCH	11	33 sec
TC_rll_unit_data_req_DCCH	4	24 sec
TC_rsl_bs_pwr_static_ass Regression	1	30 sec
TC_rsl_bs_pwr_static_power_control	4	36 sec
TC_rsl_chan_initial_ms_pwr	11	28 sec
TC_rsl_chan_initial_ta	11	25 sec
TC_rsl_modify_encr	11	31 sec
TC_rsl_ms_pwr_ctrl	4	27 sec
TC_rsl_ms_pwr_dyn_active	11	18 sec
TC_rsl_ms_pwr_dyn_active2	11	16 sec
TC_rsl_ms_pwr_dyn_ass_updown	11	16 sec
TC_rsl_ms_pwr_dyn_down	11	16 sec
TC_rsl_ms_pwr_dyn_max	11	16 sec
TC_rsl_ms_pwr_dyn_up	11	16 sec
TC_sacch_chan_act	11	29 sec
TC_sacch_chan_act_ho_async	11	26 sec
TC_sacch_chan_act_ho_sync	11	30 sec
TC_sacch_filling	11	36 sec
TC_sacch_info_mod	11	50 sec
TC_sacch_multi	11	28 sec
TC_sacch_multi_chg	11	1 min 6 sec
TC_si_sched_13	4	33 sec
TC_si_sched_13_2bis_2ter_2quater	4	49 sec
TC_si_sched_2ter Regression	1	32 sec
TC_si_sched_2ter_2bis	4	32 sec
TC_speech_no_rtp_tchf	6	20 sec
TC_speech_no_rtp_tchh	4	31 sec
TC_tch_sign_l2_fill_frame	4	24 sec
TC_tch_sign_l2_fill_frame_dtxd	11	30 sec
TC_tx_power_ramp_adm_state_change	11	20 sec
TC_tx_power_start_ramp_down_bcch	11	19 sec
TC_tx_power_start_ramp_up_bcch	11	26 sec

All Tests

Class	Failed	Skipped	Passed	Total	Duration
ttcn3_bts_tests	71+1	0	30-1	101	48 min