trial-ttcn3_bts_tests:sysmo 101

Took 50 min

All Failed Tests

Name	Age	Duration
TC_chan_act_a51	6	37 sec
TC_chan_act_a52	6	37 sec
TC_chan_act_a53	13	37 sec
TC_chan_act_stress	6	24 sec
TC_conn_fail_crit Regression	1	37 sec
TC_deact_sacch	13	33 sec
TC_encr_cmd_a51	6	37 sec
TC_encr_cmd_a52	6	37 sec
TC_encr_cmd_a53	13	37 sec
TC_ho_rach	13	36 sec
TC_meas_res_sign_sdcch4	13	37 sec
TC_meas_res_sign_sdcch8	13	37 sec
TC_meas_res_sign_tchf	13	37 sec
TC_meas_res_sign_tchh	13	37 sec
TC_meas_res_sign_tchh_toa256	13	37 sec
TC_meas_res_speech_tchf	13	24 sec
TC_meas_res_speech_tchf_facch	13	37 sec
TC_meas_res_speech_tchh	13	37 sec
TC_meas_res_speech_tchh_facch	13	37 sec
TC_meas_res_speech_tchh_toa256	13	37 sec
TC_ms_pwr_ctrl_constant	13	37 sec
TC_ms_pwr_ctrl_pf_ewma	13	37 sec
TC_paging_imsi_200percent	6	37 sec
TC_paging_imsi_80percent	6	36 sec
TC_paging_tmsi_200percent	6	37 sec
TC_paging_tmsi_80percent	6	37 sec
TC_rach_content Regression	1	36 sec
TC_rach_content_emerg Regression	1	37 sec
TC_rach_count Regression	1	38 sec
TC_rach_load_count	13	2 sec
TC_rach_load_idle_below_thresh	13	2 sec
TC_rach_load_idle_thresh0	13	2 sec
TC_rach_max_ta	13	37 sec
TC_rll_est_ind	6	29 sec
TC_rll_est_req_ACCH_3	13	37 sec
TC_rll_est_req_DCCH_3	6	37 sec
TC_rll_rel_ind_ACCH_0	13	37 sec
TC_rll_rel_ind_ACCH_3	13	37 sec
TC_rll_rel_ind_DCCH_0	6	37 sec
TC_rll_rel_ind_DCCH_3	6	37 sec
TC_rll_rel_req	13	37 sec
TC_rll_unit_data_ind_ACCH	6	37 sec
TC_rll_unit_data_ind_DCCH	6	37 sec
TC_rll_unit_data_req_ACCH	13	37 sec
TC_rll_unit_data_req_DCCH	6	37 sec
TC_rsl_bs_pwr_static_ass	3	30 sec
TC_rsl_bs_pwr_static_power_control	6	37 sec
TC_rsl_chan_initial_ms_pwr	13	28 sec
TC_rsl_chan_initial_ta	13	37 sec
TC_rsl_modify_encr	13	37 sec
TC_rsl_ms_pwr_ctrl	6	37 sec
TC_rsl_ms_pwr_dyn_active	13	25 sec
TC_rsl_ms_pwr_dyn_active2	13	16 sec
TC_rsl_ms_pwr_dyn_ass_updown	13	16 sec
TC_rsl_ms_pwr_dyn_down	13	16 sec
TC_rsl_ms_pwr_dyn_max	13	16 sec
TC_rsl_ms_pwr_dyn_up	13	16 sec
TC_sacch_chan_act	13	28 sec
TC_sacch_chan_act_ho_async	13	26 sec
TC_sacch_chan_act_ho_sync	13	36 sec
TC_sacch_filling	13	38 sec
TC_sacch_info_mod	13	32 sec
TC_sacch_multi	13	26 sec
TC_sacch_multi_chg	13	57 sec
TC_si_sched_1 Regression	1	37 sec
TC_si_sched_13	6	36 sec
TC_si_sched_13_2bis_2ter_2quater	6	37 sec
TC_si_sched_2bis Regression	1	37 sec
TC_si_sched_2quater Regression	1	37 sec
TC_si_sched_2ter Regression	1	37 sec
TC_si_sched_2ter_2bis	6	37 sec
TC_si_sched_default Regression	1	28 sec
TC_speech_no_rtp_tchf	8	37 sec
TC_speech_no_rtp_tchh	6	37 sec
TC_tch_sign_l2_fill_frame	6	25 sec
TC_tch_sign_l2_fill_frame_dtxd	13	37 sec
TC_tx_power_ramp_adm_state_change	13	20 sec
TC_tx_power_start_ramp_down_bcch	13	27 sec
TC_tx_power_start_ramp_up_bcch	13	37 sec

All Tests

Class	Failed	Skipped	Passed	Total	Duration
ttcn3_bts_tests	79+9	0	22-9	101	50 min