ttcn3_bts_tests 136

Took 38 min

All Tests

Name	Age	Duration
TC_chan_act_a51 Fixed	0	13 sec
TC_chan_act_a52 Fixed	0	13 sec
TC_chan_act_a53	2	13 sec
TC_chan_act_react	0	10 sec
TC_chan_act_stress	0	18 sec
TC_chan_act_wrong_nr	0	12 sec
TC_chan_deact_not_active	0	10 sec
TC_chopped_ipa_payload	0	43 sec
TC_chopped_ipa_ping	0	31 sec
TC_conn_fail_crit Regression	1	29 sec
TC_deact_sacch	2	19 sec
TC_dyn_ipa_pdch_act_deact Fixed	0	13 sec
TC_dyn_ipa_pdch_act_tchf_act_nack Fixed	0	10 sec
TC_dyn_ipa_pdch_tchf_act	0	10 sec
TC_dyn_ipa_pdch_tchf_act_pdch_act_nack	0	10 sec
TC_dyn_osmo_pdch_act_deact Fixed	0	14 sec
TC_dyn_osmo_pdch_double_act Fixed	0	10 sec
TC_dyn_osmo_pdch_tchf_act Fixed	0	5.5 sec
TC_dyn_osmo_pdch_tchh_act Fixed	0	10 sec
TC_dyn_osmo_pdch_unsol_deact	0	6.5 sec
TC_encr_cmd_a51 Fixed	0	14 sec
TC_encr_cmd_a52 Fixed	0	15 sec
TC_encr_cmd_a53	2	15 sec
TC_err_rep_wrong_mdisc	0	11 sec
TC_err_rep_wrong_msg_type	0	10 sec
TC_err_rep_wrong_sequence	0	10 sec
TC_ho_rach	2	16 sec
TC_ipa_crcx_mdcx_dlcx_not_active	0	10 sec
TC_ipa_crcx_mdcx_mdcx_dlcx_not_active	0	10 sec
TC_ipa_crcx_sdcch_not_active	0	10 sec
TC_ipa_crcx_twice_not_active	0	10 sec
TC_ipa_dlcx_not_active	0	10 sec
TC_lapdm_selftest	0	30 ms
TC_meas_res_sign_sdcch4	2	11 sec
TC_meas_res_sign_sdcch8	2	12 sec
TC_meas_res_sign_tchf	2	12 sec
TC_meas_res_sign_tchh	2	12 sec
TC_meas_res_sign_tchh_toa256	2	11 sec
TC_meas_res_speech_tchf	2	9.8 sec
TC_meas_res_speech_tchf_facch	2	12 sec
TC_meas_res_speech_tchh	2	12 sec
TC_meas_res_speech_tchh_facch	2	11 sec
TC_meas_res_speech_tchh_toa256	2	11 sec
TC_ms_pwr_ctrl_constant	2	11 sec
TC_ms_pwr_ctrl_pf_ewma	2	11 sec
TC_paging_imsi_200percent	0	44 sec
TC_paging_imsi_80percent	0	33 sec
TC_paging_tmsi_200percent	0	37 sec
TC_paging_tmsi_80percent	0	32 sec
TC_pcu_act_req	0	13 sec
TC_pcu_act_req_wrong_bts	0	16 sec
TC_pcu_act_req_wrong_trx	0	16 sec
TC_pcu_act_req_wrong_ts	0	16 sec
TC_pcu_data_ind_lqual_cb	2	13 sec
TC_pcu_data_req_agch	0	15 sec
TC_pcu_data_req_imm_ass_pch	0	11 sec
TC_pcu_data_req_pch Fixed	0	15 sec
TC_pcu_deact_req	0	18 sec
TC_pcu_deact_req_wrong_ts	0	14 sec
TC_pcu_ext_rach_content	2	12 sec
TC_pcu_info_ind_fh_params Fixed	0	10 sec
TC_pcu_oml_alert	2	13 sec
TC_pcu_paging_from_rsl	0	11 sec
TC_pcu_ptcch	2	19 sec
TC_pcu_rach_content Regression	1	13 sec
TC_pcu_rr_suspend	0	11 sec
TC_pcu_rts_req	0	18 sec
TC_pcu_socket_connect_multi	0	15 sec
TC_pcu_socket_connect_si3gprs Fixed	0	13 sec
TC_pcu_socket_connect_si4gprs Fixed	0	13 sec
TC_pcu_socket_disconnect_nosi3gprs Fixed	0	15 sec
TC_pcu_socket_disconnect_nosi4gprs Fixed	0	14 sec
TC_pcu_socket_noconnect_nosi3gprs	2	15 sec
TC_pcu_socket_noconnect_nosi4gprs Fixed	0	11 sec
TC_pcu_socket_nsvc_ipv4	2	2 sec
TC_pcu_socket_nsvc_ipv6	2	2 sec
TC_pcu_socket_reconnect	0	12 sec
TC_pcu_socket_verify_info_ind Regression	1	14 sec
TC_pcu_time_ind	0	18 sec
TC_pcu_ver_si13	0	10 sec
TC_rach_content	0	1 min 9 sec
TC_rach_content_emerg	0	1 min 9 sec
TC_rach_count	0	1 min 4 sec
TC_rach_load_count	2	2 sec
TC_rach_load_idle_below_thresh	2	2 sec
TC_rach_load_idle_thresh0	2	2 sec
TC_rach_max_ta	2	12 sec
TC_rll_est_ind Fixed	0	41 sec
TC_rll_est_req_ACCH_3	2	16 sec
TC_rll_est_req_DCCH_3 Fixed	0	13 sec
TC_rll_rel_ind_ACCH_0	2	16 sec
TC_rll_rel_ind_ACCH_3	2	19 sec
TC_rll_rel_ind_DCCH_0 Fixed	0	14 sec
TC_rll_rel_ind_DCCH_3 Fixed	0	14 sec
TC_rll_rel_req	2	21 sec
TC_rll_unit_data_ind_ACCH Fixed	0	16 sec
TC_rll_unit_data_ind_DCCH	2	20 sec
TC_rll_unit_data_req_ACCH	2	16 sec
TC_rll_unit_data_req_DCCH Fixed	0	15 sec
TC_rsl_bs_pwr_static_ass	0	14 sec
TC_rsl_bs_pwr_static_power_control	0	14 sec
TC_rsl_chan_initial_ms_pwr	2	15 sec
TC_rsl_chan_initial_ta	2	10 sec
TC_rsl_ie_content_error	0	10 sec
TC_rsl_mand_ie_error	0	11 sec
TC_rsl_modify_encr	2	11 sec
TC_rsl_ms_pwr_ctrl Fixed	0	1 min 15 sec
TC_rsl_ms_pwr_dyn_active	2	11 sec
TC_rsl_ms_pwr_dyn_active2	2	10 sec
TC_rsl_ms_pwr_dyn_ass_updown	2	10 sec
TC_rsl_ms_pwr_dyn_down	2	10 sec
TC_rsl_ms_pwr_dyn_max	2	10 sec
TC_rsl_ms_pwr_dyn_up	2	10 sec
TC_rsl_protocol_error	0	11 sec
TC_sacch_chan_act	2	25 sec
TC_sacch_chan_act_ho_async	2	12 sec
TC_sacch_chan_act_ho_sync	2	11 sec
TC_sacch_filling	2	21 sec
TC_sacch_info_mod	2	26 sec
TC_sacch_multi	2	21 sec
TC_sacch_multi_chg	2	48 sec
TC_si_sched_1	0	18 sec
TC_si_sched_13 Regression	1	18 sec
TC_si_sched_13_2bis_2ter_2quater	0	27 sec
TC_si_sched_2bis	0	18 sec
TC_si_sched_2quater	0	26 sec
TC_si_sched_2ter	0	18 sec
TC_si_sched_2ter_2bis	0	18 sec
TC_si_sched_default	0	19 sec
TC_speech_no_rtp_tchf	0	21 sec
TC_speech_no_rtp_tchh	0	21 sec
TC_tch_sign_l2_fill_frame Fixed	0	32 sec
TC_tch_sign_l2_fill_frame_dtxd	2	16 sec
TC_tx_power_ramp_adm_state_change	2	12 sec
TC_tx_power_start_ramp_down_bcch	2	12 sec
TC_tx_power_start_ramp_up_bcch	2	10 sec