trial-ttcn3_bts_tests:oc2g 101

Took 55 min

All Failed Tests

Name	Age	Duration
TC_chan_act_a51	10	39 sec
TC_chan_act_a52	10	39 sec
TC_chan_act_a53	17	40 sec
TC_chan_act_stress Regression	1	29 sec
TC_conn_fail_crit	13	40 sec
TC_deact_sacch	17	31 sec
TC_encr_cmd_a51	10	39 sec
TC_encr_cmd_a52	10	39 sec
TC_encr_cmd_a53	17	40 sec
TC_ho_rach	17	41 sec
TC_meas_res_sign_sdcch4	17	40 sec
TC_meas_res_sign_sdcch8	17	39 sec
TC_meas_res_sign_tchf	17	40 sec
TC_meas_res_sign_tchh	17	39 sec
TC_meas_res_sign_tchh_toa256	17	39 sec
TC_meas_res_speech_tchf	17	27 sec
TC_meas_res_speech_tchf_facch	17	39 sec
TC_meas_res_speech_tchh	17	39 sec
TC_meas_res_speech_tchh_facch	17	40 sec
TC_meas_res_speech_tchh_toa256	17	40 sec
TC_ms_pwr_ctrl_constant	17	39 sec
TC_ms_pwr_ctrl_pf_ewma	17	39 sec
TC_paging_imsi_200percent	10	40 sec
TC_paging_imsi_80percent	10	39 sec
TC_paging_tmsi_200percent	10	40 sec
TC_paging_tmsi_80percent	10	39 sec
TC_rach_content	9	39 sec
TC_rach_content_emerg	9	39 sec
TC_rach_count	9	41 sec
TC_rach_load_count	17	2 sec
TC_rach_load_idle_below_thresh	17	2 sec
TC_rach_load_idle_thresh0	17	2 sec
TC_rach_max_ta	17	39 sec
TC_rll_est_ind	10	29 sec
TC_rll_est_req_ACCH_3	17	40 sec
TC_rll_est_req_DCCH_3	10	39 sec
TC_rll_rel_ind_ACCH_0	17	39 sec
TC_rll_rel_ind_ACCH_3	17	40 sec
TC_rll_rel_ind_DCCH_0	10	40 sec
TC_rll_rel_ind_DCCH_3	10	39 sec
TC_rll_rel_req	17	39 sec
TC_rll_unit_data_ind_ACCH	10	40 sec
TC_rll_unit_data_ind_DCCH	10	39 sec
TC_rll_unit_data_req_ACCH	17	39 sec
TC_rll_unit_data_req_DCCH	10	40 sec
TC_rsl_bs_pwr_static_ass	10	31 sec
TC_rsl_bs_pwr_static_power_control	10	39 sec
TC_rsl_chan_initial_ms_pwr	17	29 sec
TC_rsl_chan_initial_ta	17	39 sec
TC_rsl_modify_encr	17	40 sec
TC_rsl_ms_pwr_ctrl	10	39 sec
TC_rsl_ms_pwr_dyn_active	17	28 sec
TC_rsl_ms_pwr_dyn_active2	17	17 sec
TC_rsl_ms_pwr_dyn_ass_updown	17	17 sec
TC_rsl_ms_pwr_dyn_down	17	17 sec
TC_rsl_ms_pwr_dyn_max	17	17 sec
TC_rsl_ms_pwr_dyn_up	17	17 sec
TC_sacch_chan_act	17	40 sec
TC_sacch_chan_act_ho_async	17	39 sec
TC_sacch_chan_act_ho_sync	17	40 sec
TC_sacch_filling	17	39 sec
TC_sacch_info_mod	17	39 sec
TC_sacch_multi	17	40 sec
TC_sacch_multi_chg	17	39 sec
TC_si_sched_1	10	39 sec
TC_si_sched_13	10	40 sec
TC_si_sched_13_2bis_2ter_2quater	10	39 sec
TC_si_sched_2bis	10	39 sec
TC_si_sched_2quater	10	40 sec
TC_si_sched_2ter	10	40 sec
TC_si_sched_2ter_2bis	10	39 sec
TC_si_sched_default	10	29 sec
TC_speech_no_rtp_tchf	12	40 sec
TC_speech_no_rtp_tchh	10	39 sec
TC_tch_sign_l2_fill_frame	10	27 sec
TC_tch_sign_l2_fill_frame_dtxd	17	39 sec
TC_tx_power_ramp_adm_state_change	17	21 sec
TC_tx_power_start_ramp_down_bcch	17	30 sec
TC_tx_power_start_ramp_up_bcch	17	40 sec

All Tests

Class	Failed	Skipped	Passed	Total	Duration
ttcn3_bts_tests	79+1	0	22-1	101	55 min