1 ;-------------------------------------------------------- 2 ; File Created by SDCC : free open source ANSI-C Compiler 3 ; Version 4.2.0 #13081 (Linux) 4 ;-------------------------------------------------------- 5 .module fpga_rev2 6 .optsdcc -mmcs51 --model-small 7 8 ;-------------------------------------------------------- 9 ; Public variables in this module 10 ;-------------------------------------------------------- 11 .globl _fpga_write_reg 12 .globl _spi_write 13 .globl _bitALTERA_DCLK 14 .globl _bitALTERA_DATA0 15 .globl _bitS_IN 16 .globl _bitS_OUT 17 .globl _bitS_CLK 18 .globl _EIPX6 19 .globl _EIPX5 20 .globl _EIPX4 21 .globl _PI2C 22 .globl _PUSB 23 .globl _EIEX6 24 .globl _EIEX5 25 .globl _EIEX4 26 .globl _EI2C 27 .globl _EIUSB 28 .globl _SMOD1 29 .globl _ERESI 30 .globl _RESI 31 .globl _INT6 32 .globl _CY 33 .globl _AC 34 .globl _F0 35 .globl _RS1 36 .globl _RS0 37 .globl _OV 38 .globl _FL 39 .globl _P 40 .globl _TF2 41 .globl _EXF2 42 .globl _RCLK 43 .globl _TCLK 44 .globl _EXEN2 45 .globl _TR2 46 .globl _C_T2 47 .globl _CP_RL2 48 .globl _SM01 49 .globl _SM11 50 .globl _SM21 51 .globl _REN1 52 .globl _TB81 53 .globl _RB81 54 .globl _TI1 55 .globl _RI1 56 .globl _PS1 57 .globl _PT2 58 .globl _PS0 59 .globl _PT1 60 .globl _PX1 61 .globl _PT0 62 .globl _PX0 63 .globl _EA 64 .globl _ES1 65 .globl _ET2 66 .globl _ES0 67 .globl _ET1 68 .globl _EX1 69 .globl _ET0 70 .globl _EX0 71 .globl _SM0 72 .globl _SM1 73 .globl _SM2 74 .globl _REN 75 .globl _TB8 76 .globl _RB8 77 .globl _TI 78 .globl _RI 79 .globl _TF1 80 .globl _TR1 81 .globl _TF0 82 .globl _TR0 83 .globl _IE1 84 .globl _IT1 85 .globl _IE0 86 .globl _IT0 87 .globl _SEL 88 .globl _EIP 89 .globl _B 90 .globl _EIE 91 .globl _ACC 92 .globl _EICON 93 .globl _PSW 94 .globl _TH2 95 .globl _TL2 96 .globl _RCAP2H 97 .globl _RCAP2L 98 .globl _T2CON 99 .globl _SBUF1 100 .globl _SCON1 101 .globl _GPIFSGLDATLNOX 102 .globl _GPIFSGLDATLX 103 .globl _GPIFSGLDATH 104 .globl _GPIFTRIG 105 .globl _EP01STAT 106 .globl _IP 107 .globl _OEE 108 .globl _OED 109 .globl _OEC 110 .globl _OEB 111 .globl _OEA 112 .globl _IOE 113 .globl _IOD 114 .globl _AUTOPTRSETUP 115 .globl _EP68FIFOFLGS 116 .globl _EP24FIFOFLGS 117 .globl _EP2468STAT 118 .globl _IE 119 .globl _INT4CLR 120 .globl _INT2CLR 121 .globl _IOC 122 .globl _AUTODAT2 123 .globl _AUTOPTRL2 124 .globl _AUTOPTRH2 125 .globl _AUTODAT1 126 .globl _APTR1L 127 .globl _APTR1H 128 .globl _SBUF0 129 .globl _SCON0 130 .globl _MPAGE 131 .globl _EXIF 132 .globl _IOB 133 .globl _CKCON 134 .globl _TH1 135 .globl _TH0 136 .globl _TL1 137 .globl _TL0 138 .globl _TMOD 139 .globl _TCON 140 .globl _PCON 141 .globl _DPS 142 .globl _DPH1 143 .globl _DPL1 144 .globl _DPH 145 .globl _DPL 146 .globl _SP 147 .globl _IOA 148 .globl _EP8FIFOBUF 149 .globl _EP6FIFOBUF 150 .globl _EP4FIFOBUF 151 .globl _EP2FIFOBUF 152 .globl _EP1INBUF 153 .globl _EP1OUTBUF 154 .globl _EP0BUF 155 .globl _CT4 156 .globl _CT3 157 .globl _CT2 158 .globl _CT1 159 .globl _USBTEST 160 .globl _TESTCFG 161 .globl _DBUG 162 .globl _UDMACRCQUAL 163 .globl _UDMACRCL 164 .globl _UDMACRCH 165 .globl _GPIFHOLDAMOUNT 166 .globl _FLOWSTBHPERIOD 167 .globl _FLOWSTBEDGE 168 .globl _FLOWSTB 169 .globl _FLOWHOLDOFF 170 .globl _FLOWEQ1CTL 171 .globl _FLOWEQ0CTL 172 .globl _FLOWLOGIC 173 .globl _FLOWSTATE 174 .globl _GPIFABORT 175 .globl _GPIFREADYSTAT 176 .globl _GPIFREADYCFG 177 .globl _XGPIFSGLDATLNOX 178 .globl _XGPIFSGLDATLX 179 .globl _XGPIFSGLDATH 180 .globl _EP8GPIFTRIG 181 .globl _EP8GPIFPFSTOP 182 .globl _EP8GPIFFLGSEL 183 .globl _EP6GPIFTRIG 184 .globl _EP6GPIFPFSTOP 185 .globl _EP6GPIFFLGSEL 186 .globl _EP4GPIFTRIG 187 .globl _EP4GPIFPFSTOP 188 .globl _EP4GPIFFLGSEL 189 .globl _EP2GPIFTRIG 190 .globl _EP2GPIFPFSTOP 191 .globl _EP2GPIFFLGSEL 192 .globl _GPIFTCB0 193 .globl _GPIFTCB1 194 .globl _GPIFTCB2 195 .globl _GPIFTCB3 196 .globl _GPIFADRL 197 .globl _GPIFADRH 198 .globl _GPIFCTLCFG 199 .globl _GPIFIDLECTL 200 .globl _GPIFIDLECS 201 .globl _GPIFWFSELECT 202 .globl _SETUPDAT 203 .globl _SUDPTRCTL 204 .globl _SUDPTRL 205 .globl _SUDPTRH 206 .globl _EP8FIFOBCL 207 .globl _EP8FIFOBCH 208 .globl _EP6FIFOBCL 209 .globl _EP6FIFOBCH 210 .globl _EP4FIFOBCL 211 .globl _EP4FIFOBCH 212 .globl _EP2FIFOBCL 213 .globl _EP2FIFOBCH 214 .globl _EP8FIFOFLGS 215 .globl _EP6FIFOFLGS 216 .globl _EP4FIFOFLGS 217 .globl _EP2FIFOFLGS 218 .globl _EP8CS 219 .globl _EP6CS 220 .globl _EP4CS 221 .globl _EP2CS 222 .globl _EP1INCS 223 .globl _EP1OUTCS 224 .globl _EP0CS 225 .globl _EP8BCL 226 .globl _EP8BCH 227 .globl _EP6BCL 228 .globl _EP6BCH 229 .globl _EP4BCL 230 .globl _EP4BCH 231 .globl _EP2BCL 232 .globl _EP2BCH 233 .globl _EP1INBC 234 .globl _EP1OUTBC 235 .globl _EP0BCL 236 .globl _EP0BCH 237 .globl _FNADDR 238 .globl _MICROFRAME 239 .globl _USBFRAMEL 240 .globl _USBFRAMEH 241 .globl _TOGCTL 242 .globl _WAKEUPCS 243 .globl _SUSPEND 244 .globl _USBCS 245 .globl _XAUTODAT2 246 .globl _XAUTODAT1 247 .globl _I2CTL 248 .globl _I2DAT 249 .globl _I2CS 250 .globl _PORTECFG 251 .globl _PORTCCFG 252 .globl _PORTACFG 253 .globl _INTSETUP 254 .globl _INT4IVEC 255 .globl _INT2IVEC 256 .globl _CLRERRCNT 257 .globl _ERRCNTLIM 258 .globl _USBERRIRQ 259 .globl _USBERRIE 260 .globl _GPIFIRQ 261 .globl _GPIFIE 262 .globl _EPIRQ 263 .globl _EPIE 264 .globl _USBIRQ 265 .globl _USBIE 266 .globl _NAKIRQ 267 .globl _NAKIE 268 .globl _IBNIRQ 269 .globl _IBNIE 270 .globl _EP8FIFOIRQ 271 .globl _EP8FIFOIE 272 .globl _EP6FIFOIRQ 273 .globl _EP6FIFOIE 274 .globl _EP4FIFOIRQ 275 .globl _EP4FIFOIE 276 .globl _EP2FIFOIRQ 277 .globl _EP2FIFOIE 278 .globl _OUTPKTEND 279 .globl _INPKTEND 280 .globl _EP8ISOINPKTS 281 .globl _EP6ISOINPKTS 282 .globl _EP4ISOINPKTS 283 .globl _EP2ISOINPKTS 284 .globl _EP8FIFOPFL 285 .globl _EP8FIFOPFH 286 .globl _EP6FIFOPFL 287 .globl _EP6FIFOPFH 288 .globl _EP4FIFOPFL 289 .globl _EP4FIFOPFH 290 .globl _EP2FIFOPFL 291 .globl _EP2FIFOPFH 292 .globl _EP8AUTOINLENL 293 .globl _EP8AUTOINLENH 294 .globl _EP6AUTOINLENL 295 .globl _EP6AUTOINLENH 296 .globl _EP4AUTOINLENL 297 .globl _EP4AUTOINLENH 298 .globl _EP2AUTOINLENL 299 .globl _EP2AUTOINLENH 300 .globl _EP8FIFOCFG 301 .globl _EP6FIFOCFG 302 .globl _EP4FIFOCFG 303 .globl _EP2FIFOCFG 304 .globl _EP8CFG 305 .globl _EP6CFG 306 .globl _EP4CFG 307 .globl _EP2CFG 308 .globl _EP1INCFG 309 .globl _EP1OUTCFG 310 .globl _REVCTL 311 .globl _REVID 312 .globl _FIFOPINPOLAR 313 .globl _UART230 314 .globl _BPADDRL 315 .globl _BPADDRH 316 .globl _BREAKPT 317 .globl _FIFORESET 318 .globl _PINFLAGSCD 319 .globl _PINFLAGSAB 320 .globl _IFCONFIG 321 .globl _CPUCS 322 .globl _RES_WAVEDATA_END 323 .globl _GPIF_WAVE_DATA 324 .globl _fpga_write_reg_PARM_2 325 .globl _g_rx_reset 326 .globl _g_tx_reset 327 .globl _fpga_set_reset 328 .globl _fpga_set_tx_enable 329 .globl _fpga_set_rx_enable 330 .globl _fpga_set_tx_reset 331 .globl _fpga_set_rx_reset 332 ;-------------------------------------------------------- 333 ; special function registers 334 ;-------------------------------------------------------- 335 .area RSEG (ABS,DATA) 000000 336 .org 0x0000 000080 337 _IOA = 0x0080 000081 338 _SP = 0x0081 000082 339 _DPL = 0x0082 000083 340 _DPH = 0x0083 000084 341 _DPL1 = 0x0084 000085 342 _DPH1 = 0x0085 000086 343 _DPS = 0x0086 000087 344 _PCON = 0x0087 000088 345 _TCON = 0x0088 000089 346 _TMOD = 0x0089 00008A 347 _TL0 = 0x008a 00008B 348 _TL1 = 0x008b 00008C 349 _TH0 = 0x008c 00008D 350 _TH1 = 0x008d 00008E 351 _CKCON = 0x008e 000090 352 _IOB = 0x0090 000091 353 _EXIF = 0x0091 000092 354 _MPAGE = 0x0092 000098 355 _SCON0 = 0x0098 000099 356 _SBUF0 = 0x0099 00009A 357 _APTR1H = 0x009a 00009B 358 _APTR1L = 0x009b 00009C 359 _AUTODAT1 = 0x009c 00009D 360 _AUTOPTRH2 = 0x009d 00009E 361 _AUTOPTRL2 = 0x009e 00009F 362 _AUTODAT2 = 0x009f 0000A0 363 _IOC = 0x00a0 0000A1 364 _INT2CLR = 0x00a1 0000A2 365 _INT4CLR = 0x00a2 0000A8 366 _IE = 0x00a8 0000AA 367 _EP2468STAT = 0x00aa 0000AB 368 _EP24FIFOFLGS = 0x00ab 0000AC 369 _EP68FIFOFLGS = 0x00ac 0000AF 370 _AUTOPTRSETUP = 0x00af 0000B0 371 _IOD = 0x00b0 0000B1 372 _IOE = 0x00b1 0000B2 373 _OEA = 0x00b2 0000B3 374 _OEB = 0x00b3 0000B4 375 _OEC = 0x00b4 0000B5 376 _OED = 0x00b5 0000B6 377 _OEE = 0x00b6 0000B8 378 _IP = 0x00b8 0000BA 379 _EP01STAT = 0x00ba 0000BB 380 _GPIFTRIG = 0x00bb 0000BD 381 _GPIFSGLDATH = 0x00bd 0000BE 382 _GPIFSGLDATLX = 0x00be 0000BF 383 _GPIFSGLDATLNOX = 0x00bf 0000C0 384 _SCON1 = 0x00c0 0000C1 385 _SBUF1 = 0x00c1 0000C8 386 _T2CON = 0x00c8 0000CA 387 _RCAP2L = 0x00ca 0000CB 388 _RCAP2H = 0x00cb 0000CC 389 _TL2 = 0x00cc 0000CD 390 _TH2 = 0x00cd 0000D0 391 _PSW = 0x00d0 0000D8 392 _EICON = 0x00d8 0000E0 393 _ACC = 0x00e0 0000E8 394 _EIE = 0x00e8 0000F0 395 _B = 0x00f0 0000F8 396 _EIP = 0x00f8 397 ;-------------------------------------------------------- 398 ; special function bits 399 ;-------------------------------------------------------- 400 .area RSEG (ABS,DATA) 000000 401 .org 0x0000 000086 402 _SEL = 0x0086 000088 403 _IT0 = 0x0088 000089 404 _IE0 = 0x0089 00008A 405 _IT1 = 0x008a 00008B 406 _IE1 = 0x008b 00008C 407 _TR0 = 0x008c 00008D 408 _TF0 = 0x008d 00008E 409 _TR1 = 0x008e 00008F 410 _TF1 = 0x008f 000098 411 _RI = 0x0098 000099 412 _TI = 0x0099 00009A 413 _RB8 = 0x009a 00009B 414 _TB8 = 0x009b 00009C 415 _REN = 0x009c 00009D 416 _SM2 = 0x009d 00009E 417 _SM1 = 0x009e 00009F 418 _SM0 = 0x009f 0000A8 419 _EX0 = 0x00a8 0000A9 420 _ET0 = 0x00a9 0000AA 421 _EX1 = 0x00aa 0000AB 422 _ET1 = 0x00ab 0000AC 423 _ES0 = 0x00ac 0000AD 424 _ET2 = 0x00ad 0000AE 425 _ES1 = 0x00ae 0000AF 426 _EA = 0x00af 0000B8 427 _PX0 = 0x00b8 0000B9 428 _PT0 = 0x00b9 0000BA 429 _PX1 = 0x00ba 0000BB 430 _PT1 = 0x00bb 0000BC 431 _PS0 = 0x00bc 0000BD 432 _PT2 = 0x00bd 0000BE 433 _PS1 = 0x00be 0000C0 434 _RI1 = 0x00c0 0000C1 435 _TI1 = 0x00c1 0000C2 436 _RB81 = 0x00c2 0000C3 437 _TB81 = 0x00c3 0000C4 438 _REN1 = 0x00c4 0000C5 439 _SM21 = 0x00c5 0000C6 440 _SM11 = 0x00c6 0000C7 441 _SM01 = 0x00c7 0000C8 442 _CP_RL2 = 0x00c8 0000C9 443 _C_T2 = 0x00c9 0000CA 444 _TR2 = 0x00ca 0000CB 445 _EXEN2 = 0x00cb 0000CC 446 _TCLK = 0x00cc 0000CD 447 _RCLK = 0x00cd 0000CE 448 _EXF2 = 0x00ce 0000CF 449 _TF2 = 0x00cf 0000D0 450 _P = 0x00d0 0000D1 451 _FL = 0x00d1 0000D2 452 _OV = 0x00d2 0000D3 453 _RS0 = 0x00d3 0000D4 454 _RS1 = 0x00d4 0000D5 455 _F0 = 0x00d5 0000D6 456 _AC = 0x00d6 0000D7 457 _CY = 0x00d7 0000DB 458 _INT6 = 0x00db 0000DC 459 _RESI = 0x00dc 0000DD 460 _ERESI = 0x00dd 0000DF 461 _SMOD1 = 0x00df 0000E8 462 _EIUSB = 0x00e8 0000E9 463 _EI2C = 0x00e9 0000EA 464 _EIEX4 = 0x00ea 0000EB 465 _EIEX5 = 0x00eb 0000EC 466 _EIEX6 = 0x00ec 0000F8 467 _PUSB = 0x00f8 0000F9 468 _PI2C = 0x00f9 0000FA 469 _EIPX4 = 0x00fa 0000FB 470 _EIPX5 = 0x00fb 0000FC 471 _EIPX6 = 0x00fc 000080 472 _bitS_CLK = 0x0080 000081 473 _bitS_OUT = 0x0081 000082 474 _bitS_IN = 0x0082 0000A1 475 _bitALTERA_DATA0 = 0x00a1 0000A3 476 _bitALTERA_DCLK = 0x00a3 477 ;-------------------------------------------------------- 478 ; overlayable register banks 479 ;-------------------------------------------------------- 480 .area REG_BANK_0 (REL,OVR,DATA) 000000 481 .ds 8 482 ;-------------------------------------------------------- 483 ; internal ram data 484 ;-------------------------------------------------------- 485 .area DSEG (DATA) 000000 486 _g_tx_reset:: 000000 487 .ds 1 000001 488 _g_rx_reset:: 000001 489 .ds 1 000002 490 _fpga_write_reg_PARM_2: 000002 491 .ds 2 492 ;-------------------------------------------------------- 493 ; overlayable items in internal ram 494 ;-------------------------------------------------------- 495 .area OSEG (OVR,DATA) 496 ;-------------------------------------------------------- 497 ; indirectly addressable internal ram data 498 ;-------------------------------------------------------- 499 .area ISEG (DATA) 500 ;-------------------------------------------------------- 501 ; absolute internal ram data 502 ;-------------------------------------------------------- 503 .area IABS (ABS,DATA) 504 .area IABS (ABS,DATA) 505 ;-------------------------------------------------------- 506 ; bit data 507 ;-------------------------------------------------------- 508 .area BSEG (BIT) 509 ;-------------------------------------------------------- 510 ; paged external ram data 511 ;-------------------------------------------------------- 512 .area PSEG (PAG,XDATA) 513 ;-------------------------------------------------------- 514 ; external ram data 515 ;-------------------------------------------------------- 516 .area XSEG (XDATA) 00E400 517 _GPIF_WAVE_DATA = 0xe400 00E480 518 _RES_WAVEDATA_END = 0xe480 00E600 519 _CPUCS = 0xe600 00E601 520 _IFCONFIG = 0xe601 00E602 521 _PINFLAGSAB = 0xe602 00E603 522 _PINFLAGSCD = 0xe603 00E604 523 _FIFORESET = 0xe604 00E605 524 _BREAKPT = 0xe605 00E606 525 _BPADDRH = 0xe606 00E607 526 _BPADDRL = 0xe607 00E608 527 _UART230 = 0xe608 00E609 528 _FIFOPINPOLAR = 0xe609 00E60A 529 _REVID = 0xe60a 00E60B 530 _REVCTL = 0xe60b 00E610 531 _EP1OUTCFG = 0xe610 00E611 532 _EP1INCFG = 0xe611 00E612 533 _EP2CFG = 0xe612 00E613 534 _EP4CFG = 0xe613 00E614 535 _EP6CFG = 0xe614 00E615 536 _EP8CFG = 0xe615 00E618 537 _EP2FIFOCFG = 0xe618 00E619 538 _EP4FIFOCFG = 0xe619 00E61A 539 _EP6FIFOCFG = 0xe61a 00E61B 540 _EP8FIFOCFG = 0xe61b 00E620 541 _EP2AUTOINLENH = 0xe620 00E621 542 _EP2AUTOINLENL = 0xe621 00E622 543 _EP4AUTOINLENH = 0xe622 00E623 544 _EP4AUTOINLENL = 0xe623 00E624 545 _EP6AUTOINLENH = 0xe624 00E625 546 _EP6AUTOINLENL = 0xe625 00E626 547 _EP8AUTOINLENH = 0xe626 00E627 548 _EP8AUTOINLENL = 0xe627 00E630 549 _EP2FIFOPFH = 0xe630 00E631 550 _EP2FIFOPFL = 0xe631 00E632 551 _EP4FIFOPFH = 0xe632 00E633 552 _EP4FIFOPFL = 0xe633 00E634 553 _EP6FIFOPFH = 0xe634 00E635 554 _EP6FIFOPFL = 0xe635 00E636 555 _EP8FIFOPFH = 0xe636 00E637 556 _EP8FIFOPFL = 0xe637 00E640 557 _EP2ISOINPKTS = 0xe640 00E641 558 _EP4ISOINPKTS = 0xe641 00E642 559 _EP6ISOINPKTS = 0xe642 00E643 560 _EP8ISOINPKTS = 0xe643 00E648 561 _INPKTEND = 0xe648 00E649 562 _OUTPKTEND = 0xe649 00E650 563 _EP2FIFOIE = 0xe650 00E651 564 _EP2FIFOIRQ = 0xe651 00E652 565 _EP4FIFOIE = 0xe652 00E653 566 _EP4FIFOIRQ = 0xe653 00E654 567 _EP6FIFOIE = 0xe654 00E655 568 _EP6FIFOIRQ = 0xe655 00E656 569 _EP8FIFOIE = 0xe656 00E657 570 _EP8FIFOIRQ = 0xe657 00E658 571 _IBNIE = 0xe658 00E659 572 _IBNIRQ = 0xe659 00E65A 573 _NAKIE = 0xe65a 00E65B 574 _NAKIRQ = 0xe65b 00E65C 575 _USBIE = 0xe65c 00E65D 576 _USBIRQ = 0xe65d 00E65E 577 _EPIE = 0xe65e 00E65F 578 _EPIRQ = 0xe65f 00E660 579 _GPIFIE = 0xe660 00E661 580 _GPIFIRQ = 0xe661 00E662 581 _USBERRIE = 0xe662 00E663 582 _USBERRIRQ = 0xe663 00E664 583 _ERRCNTLIM = 0xe664 00E665 584 _CLRERRCNT = 0xe665 00E666 585 _INT2IVEC = 0xe666 00E667 586 _INT4IVEC = 0xe667 00E668 587 _INTSETUP = 0xe668 00E670 588 _PORTACFG = 0xe670 00E671 589 _PORTCCFG = 0xe671 00E672 590 _PORTECFG = 0xe672 00E678 591 _I2CS = 0xe678 00E679 592 _I2DAT = 0xe679 00E67A 593 _I2CTL = 0xe67a 00E67B 594 _XAUTODAT1 = 0xe67b 00E67C 595 _XAUTODAT2 = 0xe67c 00E680 596 _USBCS = 0xe680 00E681 597 _SUSPEND = 0xe681 00E682 598 _WAKEUPCS = 0xe682 00E683 599 _TOGCTL = 0xe683 00E684 600 _USBFRAMEH = 0xe684 00E685 601 _USBFRAMEL = 0xe685 00E686 602 _MICROFRAME = 0xe686 00E687 603 _FNADDR = 0xe687 00E68A 604 _EP0BCH = 0xe68a 00E68B 605 _EP0BCL = 0xe68b 00E68D 606 _EP1OUTBC = 0xe68d 00E68F 607 _EP1INBC = 0xe68f 00E690 608 _EP2BCH = 0xe690 00E691 609 _EP2BCL = 0xe691 00E694 610 _EP4BCH = 0xe694 00E695 611 _EP4BCL = 0xe695 00E698 612 _EP6BCH = 0xe698 00E699 613 _EP6BCL = 0xe699 00E69C 614 _EP8BCH = 0xe69c 00E69D 615 _EP8BCL = 0xe69d 00E6A0 616 _EP0CS = 0xe6a0 00E6A1 617 _EP1OUTCS = 0xe6a1 00E6A2 618 _EP1INCS = 0xe6a2 00E6A3 619 _EP2CS = 0xe6a3 00E6A4 620 _EP4CS = 0xe6a4 00E6A5 621 _EP6CS = 0xe6a5 00E6A6 622 _EP8CS = 0xe6a6 00E6A7 623 _EP2FIFOFLGS = 0xe6a7 00E6A8 624 _EP4FIFOFLGS = 0xe6a8 00E6A9 625 _EP6FIFOFLGS = 0xe6a9 00E6AA 626 _EP8FIFOFLGS = 0xe6aa 00E6AB 627 _EP2FIFOBCH = 0xe6ab 00E6AC 628 _EP2FIFOBCL = 0xe6ac 00E6AD 629 _EP4FIFOBCH = 0xe6ad 00E6AE 630 _EP4FIFOBCL = 0xe6ae 00E6AF 631 _EP6FIFOBCH = 0xe6af 00E6B0 632 _EP6FIFOBCL = 0xe6b0 00E6B1 633 _EP8FIFOBCH = 0xe6b1 00E6B2 634 _EP8FIFOBCL = 0xe6b2 00E6B3 635 _SUDPTRH = 0xe6b3 00E6B4 636 _SUDPTRL = 0xe6b4 00E6B5 637 _SUDPTRCTL = 0xe6b5 00E6B8 638 _SETUPDAT = 0xe6b8 00E6C0 639 _GPIFWFSELECT = 0xe6c0 00E6C1 640 _GPIFIDLECS = 0xe6c1 00E6C2 641 _GPIFIDLECTL = 0xe6c2 00E6C3 642 _GPIFCTLCFG = 0xe6c3 00E6C4 643 _GPIFADRH = 0xe6c4 00E6C5 644 _GPIFADRL = 0xe6c5 00E6CE 645 _GPIFTCB3 = 0xe6ce 00E6CF 646 _GPIFTCB2 = 0xe6cf 00E6D0 647 _GPIFTCB1 = 0xe6d0 00E6D1 648 _GPIFTCB0 = 0xe6d1 00E6D2 649 _EP2GPIFFLGSEL = 0xe6d2 00E6D3 650 _EP2GPIFPFSTOP = 0xe6d3 00E6D4 651 _EP2GPIFTRIG = 0xe6d4 00E6DA 652 _EP4GPIFFLGSEL = 0xe6da 00E6DB 653 _EP4GPIFPFSTOP = 0xe6db 00E6DC 654 _EP4GPIFTRIG = 0xe6dc 00E6E2 655 _EP6GPIFFLGSEL = 0xe6e2 00E6E3 656 _EP6GPIFPFSTOP = 0xe6e3 00E6E4 657 _EP6GPIFTRIG = 0xe6e4 00E6EA 658 _EP8GPIFFLGSEL = 0xe6ea 00E6EB 659 _EP8GPIFPFSTOP = 0xe6eb 00E6EC 660 _EP8GPIFTRIG = 0xe6ec 00E6F0 661 _XGPIFSGLDATH = 0xe6f0 00E6F1 662 _XGPIFSGLDATLX = 0xe6f1 00E6F2 663 _XGPIFSGLDATLNOX = 0xe6f2 00E6F3 664 _GPIFREADYCFG = 0xe6f3 00E6F4 665 _GPIFREADYSTAT = 0xe6f4 00E6F5 666 _GPIFABORT = 0xe6f5 00E6C6 667 _FLOWSTATE = 0xe6c6 00E6C7 668 _FLOWLOGIC = 0xe6c7 00E6C8 669 _FLOWEQ0CTL = 0xe6c8 00E6C9 670 _FLOWEQ1CTL = 0xe6c9 00E6CA 671 _FLOWHOLDOFF = 0xe6ca 00E6CB 672 _FLOWSTB = 0xe6cb 00E6CC 673 _FLOWSTBEDGE = 0xe6cc 00E6CD 674 _FLOWSTBHPERIOD = 0xe6cd 00E60C 675 _GPIFHOLDAMOUNT = 0xe60c 00E67D 676 _UDMACRCH = 0xe67d 00E67E 677 _UDMACRCL = 0xe67e 00E67F 678 _UDMACRCQUAL = 0xe67f 00E6F8 679 _DBUG = 0xe6f8 00E6F9 680 _TESTCFG = 0xe6f9 00E6FA 681 _USBTEST = 0xe6fa 00E6FB 682 _CT1 = 0xe6fb 00E6FC 683 _CT2 = 0xe6fc 00E6FD 684 _CT3 = 0xe6fd 00E6FE 685 _CT4 = 0xe6fe 00E740 686 _EP0BUF = 0xe740 00E780 687 _EP1OUTBUF = 0xe780 00E7C0 688 _EP1INBUF = 0xe7c0 00F000 689 _EP2FIFOBUF = 0xf000 00F400 690 _EP4FIFOBUF = 0xf400 00F800 691 _EP6FIFOBUF = 0xf800 00FC00 692 _EP8FIFOBUF = 0xfc00 000000 693 _regval: 000000 694 .ds 4 695 ;-------------------------------------------------------- 696 ; absolute external ram data 697 ;-------------------------------------------------------- 698 .area XABS (ABS,XDATA) 699 ;-------------------------------------------------------- 700 ; external initialized ram data 701 ;-------------------------------------------------------- 702 .area HOME (CODE) 703 .area GSINIT0 (CODE) 704 .area GSINIT1 (CODE) 705 .area GSINIT2 (CODE) 706 .area GSINIT3 (CODE) 707 .area GSINIT4 (CODE) 708 .area GSINIT5 (CODE) 709 .area GSINIT (CODE) 710 .area GSFINAL (CODE) 711 .area CSEG (CODE) 712 ;-------------------------------------------------------- 713 ; global & static initialisations 714 ;-------------------------------------------------------- 715 .area HOME (CODE) 716 .area GSINIT (CODE) 717 .area GSFINAL (CODE) 718 .area GSINIT (CODE) 719 ; fpga_rev2.c:29: unsigned char g_tx_reset = 0; 000000 75*00 00 [24] 720 mov _g_tx_reset,#0x00 721 ; fpga_rev2.c:30: unsigned char g_rx_reset = 0; 000003 75*01 00 [24] 722 mov _g_rx_reset,#0x00 723 ; fpga_rev2.c:42: static __xdata unsigned char regval[4] = {0, 0, 0, 0}; 000006 90r00r00 [24] 724 mov dptr,#_regval 000009 E4 [12] 725 clr a 00000A F0 [24] 726 movx @dptr,a 00000B 90r00r01 [24] 727 mov dptr,#(_regval + 0x0001) 00000E F0 [24] 728 movx @dptr,a 00000F 90r00r02 [24] 729 mov dptr,#(_regval + 0x0002) 000012 F0 [24] 730 movx @dptr,a 000013 90r00r03 [24] 731 mov dptr,#(_regval + 0x0003) 000016 F0 [24] 732 movx @dptr,a 733 ;-------------------------------------------------------- 734 ; Home 735 ;-------------------------------------------------------- 736 .area HOME (CODE) 737 .area HOME (CODE) 738 ;-------------------------------------------------------- 739 ; code 740 ;-------------------------------------------------------- 741 .area CSEG (CODE) 742 ;------------------------------------------------------------ 743 ;Allocation info for local variables in function 'fpga_write_reg' 744 ;------------------------------------------------------------ 745 ;regval Allocated with name '_fpga_write_reg_PARM_2' 746 ;regno Allocated to registers r7 747 ;------------------------------------------------------------ 748 ; fpga_rev2.c:33: fpga_write_reg (unsigned char regno, const __xdata unsigned char *regval) 749 ; ----------------------------------------- 750 ; function fpga_write_reg 751 ; ----------------------------------------- 000000 752 _fpga_write_reg: 000007 753 ar7 = 0x07 000006 754 ar6 = 0x06 000005 755 ar5 = 0x05 000004 756 ar4 = 0x04 000003 757 ar3 = 0x03 000002 758 ar2 = 0x02 000001 759 ar1 = 0x01 000000 760 ar0 = 0x00 000000 AF 82 [24] 761 mov r7,dpl 762 ; fpga_rev2.c:35: spi_write (0, 0x00 | (regno & 0x7f), 000002 74 7F [12] 763 mov a,#0x7f 000004 5F [12] 764 anl a,r7 000005 F5*00 [12] 765 mov _spi_write_PARM_2,a 766 ; fpga_rev2.c:38: regval, 4); 000007 75*00 01 [24] 767 mov _spi_write_PARM_3,#0x01 00000A 75*00 20 [24] 768 mov _spi_write_PARM_4,#0x20 00000D 85*02*00 [24] 769 mov _spi_write_PARM_5,_fpga_write_reg_PARM_2 000010 85*03*01 [24] 770 mov (_spi_write_PARM_5 + 1),(_fpga_write_reg_PARM_2 + 1) 000013 75*00 04 [24] 771 mov _spi_write_PARM_6,#0x04 000016 75 82 00 [24] 772 mov dpl,#0x00 773 ; fpga_rev2.c:39: } 000019 02r00r00 [24] 774 ljmp _spi_write 775 ;------------------------------------------------------------ 776 ;Allocation info for local variables in function 'write_fpga_master_ctrl' 777 ;------------------------------------------------------------ 778 ;v Allocated to registers r7 779 ;------------------------------------------------------------ 780 ; fpga_rev2.c:45: write_fpga_master_ctrl (void) 781 ; ----------------------------------------- 782 ; function write_fpga_master_ctrl 783 ; ----------------------------------------- 00001C 784 _write_fpga_master_ctrl: 785 ; fpga_rev2.c:47: unsigned char v = 0; 00001C 7F 00 [12] 786 mov r7,#0x00 787 ; fpga_rev2.c:48: if (g_tx_enable) 00001E E5*00 [12] 788 mov a,_g_tx_enable 000020 60 02 [24] 789 jz 00102$ 790 ; fpga_rev2.c:49: v |= bmFR_MC_ENABLE_TX; 000022 7F 01 [12] 791 mov r7,#0x01 000024 792 00102$: 793 ; fpga_rev2.c:50: if (g_rx_enable) 000024 E5*00 [12] 794 mov a,_g_rx_enable 000026 60 03 [24] 795 jz 00104$ 796 ; fpga_rev2.c:51: v |= bmFR_MC_ENABLE_RX; 000028 43 07 02 [24] 797 orl ar7,#0x02 00002B 798 00104$: 799 ; fpga_rev2.c:52: if (g_tx_reset) 00002B E5*00 [12] 800 mov a,_g_tx_reset 00002D 60 03 [24] 801 jz 00106$ 802 ; fpga_rev2.c:53: v |= bmFR_MC_RESET_TX; 00002F 43 07 04 [24] 803 orl ar7,#0x04 000032 804 00106$: 805 ; fpga_rev2.c:54: if (g_rx_reset) 000032 E5*01 [12] 806 mov a,_g_rx_reset 000034 60 03 [24] 807 jz 00108$ 808 ; fpga_rev2.c:55: v |= bmFR_MC_RESET_RX; 000036 43 07 08 [24] 809 orl ar7,#0x08 000039 810 00108$: 811 ; fpga_rev2.c:56: regval[3] = v; 000039 90r00r03 [24] 812 mov dptr,#(_regval + 0x0003) 00003C EF [12] 813 mov a,r7 00003D F0 [24] 814 movx @dptr,a 815 ; fpga_rev2.c:58: fpga_write_reg (FR_MASTER_CTRL, regval); 00003E 75*02r00 [24] 816 mov _fpga_write_reg_PARM_2,#_regval 000041 75*03s00 [24] 817 mov (_fpga_write_reg_PARM_2 + 1),#(_regval >> 8) 000044 75 82 04 [24] 818 mov dpl,#0x04 819 ; fpga_rev2.c:59: } 000047 02r00r00 [24] 820 ljmp _fpga_write_reg 821 ;------------------------------------------------------------ 822 ;Allocation info for local variables in function 'fpga_set_reset' 823 ;------------------------------------------------------------ 824 ;on Allocated to registers r7 825 ;------------------------------------------------------------ 826 ; fpga_rev2.c:64: fpga_set_reset (unsigned char on) 827 ; ----------------------------------------- 828 ; function fpga_set_reset 829 ; ----------------------------------------- 00004A 830 _fpga_set_reset: 831 ; fpga_rev2.c:66: on &= 0x1; 00004A E5 82 [12] 832 mov a,dpl 00004C 30 E0 10 [24] 833 jnb acc.0,00102$ 834 ; fpga_rev2.c:68: if (on){ 835 ; fpga_rev2.c:69: USRP_PC &= ~bmPC_nRESET; // active low 00004F 53 A0 FE [24] 836 anl _IOC,#0xfe 837 ; fpga_rev2.c:70: g_tx_enable = 0; 000052 75*00 00 [24] 838 mov _g_tx_enable,#0x00 839 ; fpga_rev2.c:71: g_rx_enable = 0; 000055 75*00 00 [24] 840 mov _g_rx_enable,#0x00 841 ; fpga_rev2.c:72: g_tx_reset = 0; 000058 75*00 00 [24] 842 mov _g_tx_reset,#0x00 843 ; fpga_rev2.c:73: g_rx_reset = 0; 00005B 75*01 00 [24] 844 mov _g_rx_reset,#0x00 00005E 22 [24] 845 ret 00005F 846 00102$: 847 ; fpga_rev2.c:76: USRP_PC |= bmPC_nRESET; 00005F 43 A0 01 [24] 848 orl _IOC,#0x01 849 ; fpga_rev2.c:77: } 000062 22 [24] 850 ret 851 ;------------------------------------------------------------ 852 ;Allocation info for local variables in function 'fpga_set_tx_enable' 853 ;------------------------------------------------------------ 854 ;on Allocated to registers r7 855 ;------------------------------------------------------------ 856 ; fpga_rev2.c:80: fpga_set_tx_enable (unsigned char on) 857 ; ----------------------------------------- 858 ; function fpga_set_tx_enable 859 ; ----------------------------------------- 000063 860 _fpga_set_tx_enable: 000063 AF 82 [24] 861 mov r7,dpl 862 ; fpga_rev2.c:82: on &= 0x1; 000065 53 07 01 [24] 863 anl ar7,#0x01 864 ; fpga_rev2.c:83: g_tx_enable = on; 000068 8F*00 [24] 865 mov _g_tx_enable,r7 866 ; fpga_rev2.c:85: write_fpga_master_ctrl (); 00006A C0 07 [24] 867 push ar7 00006C 12r00r1C [24] 868 lcall _write_fpga_master_ctrl 00006F D0 07 [24] 869 pop ar7 870 ; fpga_rev2.c:87: if (on){ 000071 EF [12] 871 mov a,r7 000072 60 09 [24] 872 jz 00106$ 873 ; fpga_rev2.c:88: g_tx_underrun = 0; 000074 75*00 00 [24] 874 mov _g_tx_underrun,#0x00 875 ; fpga_rev2.c:89: fpga_clear_flags (); 000077 43 B1 08 [24] 876 orl _IOE,#0x08 00007A 53 B1 F7 [24] 877 anl _IOE,#0xf7 00007D 878 00106$: 879 ; fpga_rev2.c:91: } 00007D 22 [24] 880 ret 881 ;------------------------------------------------------------ 882 ;Allocation info for local variables in function 'fpga_set_rx_enable' 883 ;------------------------------------------------------------ 884 ;on Allocated to registers r7 885 ;------------------------------------------------------------ 886 ; fpga_rev2.c:94: fpga_set_rx_enable (unsigned char on) 887 ; ----------------------------------------- 888 ; function fpga_set_rx_enable 889 ; ----------------------------------------- 00007E 890 _fpga_set_rx_enable: 00007E AF 82 [24] 891 mov r7,dpl 892 ; fpga_rev2.c:96: on &= 0x1; 000080 53 07 01 [24] 893 anl ar7,#0x01 894 ; fpga_rev2.c:97: g_rx_enable = on; 000083 8F*00 [24] 895 mov _g_rx_enable,r7 896 ; fpga_rev2.c:99: write_fpga_master_ctrl (); 000085 C0 07 [24] 897 push ar7 000087 12r00r1C [24] 898 lcall _write_fpga_master_ctrl 00008A D0 07 [24] 899 pop ar7 900 ; fpga_rev2.c:100: if (on){ 00008C EF [12] 901 mov a,r7 00008D 60 09 [24] 902 jz 00106$ 903 ; fpga_rev2.c:101: g_rx_overrun = 0; 00008F 75*00 00 [24] 904 mov _g_rx_overrun,#0x00 905 ; fpga_rev2.c:102: fpga_clear_flags (); 000092 43 B1 08 [24] 906 orl _IOE,#0x08 000095 53 B1 F7 [24] 907 anl _IOE,#0xf7 000098 908 00106$: 909 ; fpga_rev2.c:104: } 000098 22 [24] 910 ret 911 ;------------------------------------------------------------ 912 ;Allocation info for local variables in function 'fpga_set_tx_reset' 913 ;------------------------------------------------------------ 914 ;on Allocated to registers 915 ;------------------------------------------------------------ 916 ; fpga_rev2.c:107: fpga_set_tx_reset (unsigned char on) 917 ; ----------------------------------------- 918 ; function fpga_set_tx_reset 919 ; ----------------------------------------- 000099 920 _fpga_set_tx_reset: 000099 AF 82 [24] 921 mov r7,dpl 922 ; fpga_rev2.c:109: on &= 0x1; 00009B 74 01 [12] 923 mov a,#0x01 00009D 5F [12] 924 anl a,r7 00009E F5*00 [12] 925 mov _g_tx_reset,a 926 ; fpga_rev2.c:112: write_fpga_master_ctrl (); 927 ; fpga_rev2.c:113: } 0000A0 02r00r1C [24] 928 ljmp _write_fpga_master_ctrl 929 ;------------------------------------------------------------ 930 ;Allocation info for local variables in function 'fpga_set_rx_reset' 931 ;------------------------------------------------------------ 932 ;on Allocated to registers 933 ;------------------------------------------------------------ 934 ; fpga_rev2.c:116: fpga_set_rx_reset (unsigned char on) 935 ; ----------------------------------------- 936 ; function fpga_set_rx_reset 937 ; ----------------------------------------- 0000A3 938 _fpga_set_rx_reset: 0000A3 AF 82 [24] 939 mov r7,dpl 940 ; fpga_rev2.c:118: on &= 0x1; 0000A5 74 01 [12] 941 mov a,#0x01 0000A7 5F [12] 942 anl a,r7 0000A8 F5*01 [12] 943 mov _g_rx_reset,a 944 ; fpga_rev2.c:121: write_fpga_master_ctrl (); 945 ; fpga_rev2.c:122: } 0000AA 02r00r1C [24] 946 ljmp _write_fpga_master_ctrl 947 .area CSEG (CODE) 948 .area CONST (CODE) 949 .area CABS (ABS,CODE)