2024-10-30 05:13:26 [INFO] transceiver.py:125 Init transceiver 'BTS@172.18.83.20:5700'
2024-10-30 05:13:26 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5702 <-> R:172.18.83.20:5802)
2024-10-30 05:13:26 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5701 <-> R:172.18.83.20:5801)
2024-10-30 05:13:26 [INFO] transceiver.py:125 Init transceiver 'MS@172.18.83.22:6700'
2024-10-30 05:13:26 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:6702 <-> R:172.18.83.22:6802)
2024-10-30 05:13:26 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:6701 <-> R:172.18.83.22:6801)
2024-10-30 05:13:26 [INFO] transceiver.py:125 Init transceiver 'TRX1@172.18.83.20:5700/1'
2024-10-30 05:13:26 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5704 <-> R:172.18.83.20:5804)
2024-10-30 05:13:26 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5703 <-> R:172.18.83.20:5803)
2024-10-30 05:13:26 [INFO] transceiver.py:125 Init transceiver 'TRX2@172.18.83.20:5700/2'
2024-10-30 05:13:26 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5706 <-> R:172.18.83.20:5806)
2024-10-30 05:13:26 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5705 <-> R:172.18.83.20:5805)
2024-10-30 05:13:26 [INFO] transceiver.py:125 Init transceiver 'TRX3@172.18.83.20:5700/3'
2024-10-30 05:13:26 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5708 <-> R:172.18.83.20:5808)
2024-10-30 05:13:26 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5707 <-> R:172.18.83.20:5807)
2024-10-30 05:13:26 [INFO] fake_trx.py:423 Init complete
2024-10-30 05:13:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:13:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:13:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:13:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:13:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:13:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:13:30 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:13:30 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 0 -> 1
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:13:30 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:13:30 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 0 -> 1
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:13:30 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:13:30 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 0 -> 1
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:13:30 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:13:30 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 0 -> 1
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:13:30 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:13:30 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:13:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:13:30 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:13:31 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:13:31 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:13:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:31 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:13:31 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:13:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:13:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:13:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:13:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:31 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:13:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:13:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:13:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:13:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:13:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:13:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:13:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:13:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:32 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:13:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:13:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:13:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:13:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:32 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:13:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:13:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:13:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:13:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:13:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:13:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:13:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:13:33 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:13:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:33 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:13:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:13:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:13:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:13:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:13:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:13:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:13:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:13:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:34 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:13:34 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:13:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:13:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:13:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:13:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:13:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:13:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:13:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:13:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:34 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:13:35 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:13:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:13:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:13:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:13:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:35 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:13:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:13:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:13:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:13:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:13:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:36 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:13:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:36 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:13:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:13:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:13:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:13:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:37 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:13:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:37 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:13:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:13:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:13:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:13:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:13:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:38 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:13:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:38 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:13:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:13:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:13:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:13:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:39 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:13:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:39 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:13:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:40 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:13:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:13:40 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:13:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:41 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:13:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:13:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:13:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:13:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:41 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:13:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:13:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:13:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:13:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:42 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:13:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:13:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:42 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:13:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:13:42 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:13:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:13:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:13:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:13:43 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:13:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:13:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:13:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:13:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:13:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:13:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:13:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:13:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:13:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:13:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:13:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:13:43 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:13:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:13:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:13:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:13:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:13:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:13:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:13:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:13:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:13:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:13:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:13:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:13:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:13:48 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:13:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:13:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:13:49 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:13:49 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:13:49 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
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2024-10-30 05:13:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
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2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
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2024-10-30 05:13:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
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2024-10-30 05:13:50 [DEBUG] clck_gen.py:102 IND CLOCK 408
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2024-10-30 05:13:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:13:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:13:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:13:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:13:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
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2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:13:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:13:51 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:13:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:13:51 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=515 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:13:51 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=515 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:13:51 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=515 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:13:51 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=515 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:13:51 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=515 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:13:51 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=515 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:13:51 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=515 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:13:51 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=515 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:13:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:13:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:13:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:13:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:13:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:13:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:13:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:13:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:13:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:13:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:13:56 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:13:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:13:56 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:13:56 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:56 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:13:56 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:13:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:13:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:13:56 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:13:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:14:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:14:01 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:14:01 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:14:01 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:14:01 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:14:01 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:14:01 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:14:01 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:14:01 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:14:01 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:14:01 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:14:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:14:01 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:14:02 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:14:02 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:14:02 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:14:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:14:02 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:14:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:14:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:14:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:14:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:14:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:14:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:14:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:14:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:14:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:14:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:14:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:14:02 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:14:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:14:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:14:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:14:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:14:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:14:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:14:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:14:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:14:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:14:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:14:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:14:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:14:07 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:14:07 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:14:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:14:08 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:14:08 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:14:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:14:08 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:14:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:14:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:14:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:14:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:14:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:14:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:14:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:14:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:14:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:14:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:14:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:14:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:14:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:14:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:14:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:14:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:14:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:14:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:14:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:14:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:14:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:14:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:14:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:14:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:14:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:14:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:14:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:14:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:14:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:14:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:14:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:14:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:14:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:14:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:14:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:14:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:14:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:14:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:14:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:14:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:14:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:14:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:14:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:14:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:14:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:14:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:14:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:14:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:14:08 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:14:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:14:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:14:13 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:14:13 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:14:13 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:14:13 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:14:13 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:14:13 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:14:13 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:14:13 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:14:13 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:14:13 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:14:13 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:14:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:14:13 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:14:13 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:14:13 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:14:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:14:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:14:14 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:14:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:14:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:14:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:14:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:14:14 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:14:15 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:14:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:14:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:14:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:14:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:14:15 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:14:16 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:14:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:14:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:14:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:14:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:14:16 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:14:17 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:14:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:14:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:14:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:14:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:14:17 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:14:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:14:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:14:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:14:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:14:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:14:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:14:18 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:14:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:14:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:14:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:14:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:14:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:14:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:14:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:14:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:14:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:14:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:14:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:14:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:14:18 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:14:18 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:14:19 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:14:19 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:14:20 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:14:20 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:14:21 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:14:21 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:14:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:14:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:14:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:14:22 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:14:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:14:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:14:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:14:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:14:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:14:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:14:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:14:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:14:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:14:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:14:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:14:22 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:14:23 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:14:23 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:14:24 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:14:24 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:14:25 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:14:25 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:14:26 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:14:26 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:14:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:14:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:14:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:14:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:14:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:14:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:14:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:14:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:14:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:14:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:14:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:14:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:14:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:14:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:14:26 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 05:14:27 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 05:14:27 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 05:14:28 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 05:14:28 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 05:14:29 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 05:14:29 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 05:14:30 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 05:14:30 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 05:14:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:14:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:14:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:14:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:14:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:14:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:14:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:14:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:14:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:14:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:14:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:14:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:14:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:14:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:31 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 05:14:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:14:31 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 05:14:32 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 05:14:32 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 05:14:33 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 05:14:33 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 05:14:33 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 05:14:34 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 05:14:34 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 05:14:35 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 05:14:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:14:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:14:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:14:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:14:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:14:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:14:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:14:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:14:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:14:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:14:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:14:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:14:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:14:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:35 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 05:14:36 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 05:14:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:14:36 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 05:14:37 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 05:14:37 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 05:14:38 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 05:14:38 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 05:14:39 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 05:14:39 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 05:14:40 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 05:14:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:14:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:14:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:14:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:14:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:14:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:14:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:14:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:14:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:14:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:14:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:14:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:14:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:14:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:40 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 05:14:41 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 05:14:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:14:41 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 05:14:41 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 05:14:42 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-10-30 05:14:42 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-10-30 05:14:43 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-10-30 05:14:43 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-10-30 05:14:44 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-10-30 05:14:44 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-10-30 05:14:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:14:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:14:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:14:45 [WARNING] transceiver.py:250 (MS@172.18.83.22:6700) RX TRXD message (fn=6928 tn=5 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:14:45 [WARNING] transceiver.py:250 (MS@172.18.83.22:6700) RX TRXD message (fn=6928 tn=6 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:14:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:14:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:14:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:14:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:14:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:14:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:14:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:14:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:14:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:14:45 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-10-30 05:14:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:14:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:14:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:45 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-10-30 05:14:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:14:46 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-10-30 05:14:46 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-10-30 05:14:47 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-10-30 05:14:47 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-10-30 05:14:48 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-10-30 05:14:48 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-10-30 05:14:48 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-10-30 05:14:49 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-10-30 05:14:49 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-10-30 05:14:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:14:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:14:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:14:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:14:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:14:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:14:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:14:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:14:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:14:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:14:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:14:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:14:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:14:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:50 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-10-30 05:14:50 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-10-30 05:14:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:14:51 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-10-30 05:14:51 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-10-30 05:14:52 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-10-30 05:14:52 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-10-30 05:14:53 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-10-30 05:14:53 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-10-30 05:14:54 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-10-30 05:14:54 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-10-30 05:14:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:14:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:14:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:14:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:14:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:14:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:14:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:14:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:14:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:14:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:14:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:14:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:14:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:14:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:14:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:55 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-10-30 05:14:55 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-10-30 05:14:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:14:56 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-10-30 05:14:56 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2024-10-30 05:14:56 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2024-10-30 05:14:57 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2024-10-30 05:14:57 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2024-10-30 05:14:58 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2024-10-30 05:14:58 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2024-10-30 05:14:59 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2024-10-30 05:14:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:14:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:14:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:14:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:14:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:14:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:14:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:14:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:14:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:14:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:14:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:14:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:14:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:14:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:14:59 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2024-10-30 05:15:00 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2024-10-30 05:15:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:00 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2024-10-30 05:15:01 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2024-10-30 05:15:01 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2024-10-30 05:15:02 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2024-10-30 05:15:02 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2024-10-30 05:15:03 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2024-10-30 05:15:03 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2024-10-30 05:15:04 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2024-10-30 05:15:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:15:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:15:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:15:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:04 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2024-10-30 05:15:04 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2024-10-30 05:15:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:05 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2024-10-30 05:15:05 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2024-10-30 05:15:06 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2024-10-30 05:15:06 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2024-10-30 05:15:07 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2024-10-30 05:15:07 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2024-10-30 05:15:08 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2024-10-30 05:15:08 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2024-10-30 05:15:09 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2024-10-30 05:15:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:15:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:15:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:15:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:09 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2024-10-30 05:15:10 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2024-10-30 05:15:10 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2024-10-30 05:15:11 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2024-10-30 05:15:11 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2024-10-30 05:15:11 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2024-10-30 05:15:12 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2024-10-30 05:15:12 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2024-10-30 05:15:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:15:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:15:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:15:13 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2024-10-30 05:15:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:13 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2024-10-30 05:15:14 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2024-10-30 05:15:14 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2024-10-30 05:15:15 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2024-10-30 05:15:15 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2024-10-30 05:15:16 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2024-10-30 05:15:16 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2024-10-30 05:15:17 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2024-10-30 05:15:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:15:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:15:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:15:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:17 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2024-10-30 05:15:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:18 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2024-10-30 05:15:18 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2024-10-30 05:15:19 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2024-10-30 05:15:19 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2024-10-30 05:15:19 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2024-10-30 05:15:20 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2024-10-30 05:15:20 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2024-10-30 05:15:21 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2024-10-30 05:15:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:15:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:15:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:15:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:21 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2024-10-30 05:15:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:22 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2024-10-30 05:15:22 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2024-10-30 05:15:23 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2024-10-30 05:15:23 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2024-10-30 05:15:24 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2024-10-30 05:15:24 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2024-10-30 05:15:25 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2024-10-30 05:15:25 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2024-10-30 05:15:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:26 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2024-10-30 05:15:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:15:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:15:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:15:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:26 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2024-10-30 05:15:26 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2024-10-30 05:15:27 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2024-10-30 05:15:27 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2024-10-30 05:15:28 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2024-10-30 05:15:28 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2024-10-30 05:15:29 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2024-10-30 05:15:29 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2024-10-30 05:15:30 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2024-10-30 05:15:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:15:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:15:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:15:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:30 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2024-10-30 05:15:31 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2024-10-30 05:15:31 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2024-10-30 05:15:32 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2024-10-30 05:15:32 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2024-10-30 05:15:33 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2024-10-30 05:15:33 [DEBUG] clck_gen.py:102 IND CLOCK 17442
2024-10-30 05:15:34 [DEBUG] clck_gen.py:102 IND CLOCK 17544
2024-10-30 05:15:34 [DEBUG] clck_gen.py:102 IND CLOCK 17646
2024-10-30 05:15:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:15:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:15:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:15:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:34 [DEBUG] clck_gen.py:102 IND CLOCK 17748
2024-10-30 05:15:35 [DEBUG] clck_gen.py:102 IND CLOCK 17850
2024-10-30 05:15:35 [DEBUG] clck_gen.py:102 IND CLOCK 17952
2024-10-30 05:15:36 [DEBUG] clck_gen.py:102 IND CLOCK 18054
2024-10-30 05:15:36 [DEBUG] clck_gen.py:102 IND CLOCK 18156
2024-10-30 05:15:37 [DEBUG] clck_gen.py:102 IND CLOCK 18258
2024-10-30 05:15:37 [DEBUG] clck_gen.py:102 IND CLOCK 18360
2024-10-30 05:15:38 [DEBUG] clck_gen.py:102 IND CLOCK 18462
2024-10-30 05:15:38 [DEBUG] clck_gen.py:102 IND CLOCK 18564
2024-10-30 05:15:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:15:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:15:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:15:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:39 [DEBUG] clck_gen.py:102 IND CLOCK 18666
2024-10-30 05:15:39 [DEBUG] clck_gen.py:102 IND CLOCK 18768
2024-10-30 05:15:40 [DEBUG] clck_gen.py:102 IND CLOCK 18870
2024-10-30 05:15:40 [DEBUG] clck_gen.py:102 IND CLOCK 18972
2024-10-30 05:15:41 [DEBUG] clck_gen.py:102 IND CLOCK 19074
2024-10-30 05:15:41 [DEBUG] clck_gen.py:102 IND CLOCK 19176
2024-10-30 05:15:42 [DEBUG] clck_gen.py:102 IND CLOCK 19278
2024-10-30 05:15:42 [DEBUG] clck_gen.py:102 IND CLOCK 19380
2024-10-30 05:15:42 [DEBUG] clck_gen.py:102 IND CLOCK 19482
2024-10-30 05:15:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:15:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:15:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:15:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:15:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:15:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:15:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:15:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:15:43 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:15:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:15:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:15:43 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=19535 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:15:43 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=19535 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:15:43 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=19535 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:15:43 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=19535 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:15:43 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=19535 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:15:43 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=19535 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:15:43 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=19535 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:15:43 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=19535 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:15:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:15:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:15:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:15:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:15:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:15:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:15:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:15:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:15:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:15:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:15:48 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:15:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:15:48 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:15:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:15:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:15:53 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:15:53 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:15:53 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:15:53 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:15:53 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:15:53 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:15:53 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:15:53 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:15:53 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:15:53 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:15:53 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:15:53 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:53 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:15:53 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:15:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:15:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:54 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:15:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:15:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:15:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:15:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:15:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:15:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:15:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:15:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:15:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:15:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:15:54 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:15:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:55 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:15:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:15:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:15:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:15:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:15:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:15:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:15:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:15:55 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:15:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:15:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:15:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:15:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:56 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:15:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:15:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:15:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:15:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:15:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:15:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:15:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:15:56 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:15:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:15:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:15:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:15:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:15:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:57 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:15:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:15:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:15:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:15:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:15:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:15:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:15:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:15:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:57 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:15:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:15:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:15:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:15:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:15:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:57 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:15:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:15:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:15:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:15:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:15:58 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:15:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:15:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:15:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:15:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:58 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:15:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:15:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:15:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:15:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:59 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:15:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:15:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:15:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:15:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:15:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:15:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:59 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:15:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:15:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:15:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:15:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:15:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:16:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:16:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:16:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:00 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:16:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:16:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:16:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:16:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:00 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:16:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:16:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:16:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:16:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:01 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:16:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:16:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:16:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:16:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:16:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:16:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:16:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:01 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:16:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:16:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:16:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:16:02 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:16:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:16:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:16:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:16:02 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:16:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:16:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:16:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:16:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:16:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:16:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:16:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:16:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:16:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:16:03 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:16:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:16:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:16:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:16:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:16:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:16:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:16:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:16:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:16:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:16:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:16:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:16:08 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:16:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:16:08 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:16:08 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:08 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:16:08 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:16:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:09 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:16:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:16:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:16:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:16:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:16:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:09 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:16:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:16:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:16:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:16:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:10 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:16:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:16:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:16:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:16:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:16:10 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:16:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:10 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:16:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:16:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:16:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:16:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:16:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:16:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:16:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:16:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:11 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:16:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:11 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:16:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:16:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:16:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:16:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:16:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:16:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:16:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:16:12 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:16:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:12 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:16:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:16:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:16:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:16:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:16:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:13 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:16:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:16:13 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:16:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:16:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:16:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:14 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:16:14 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:16:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:15 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:16:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:16:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:16:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:16:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:15 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:16:16 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:16:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:16 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:16:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:16:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:16:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:16:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:17 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:16:17 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:16:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:17 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:16:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:16:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:16:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:16:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:16:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:18 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:16:18 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:16:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:19 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:16:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:16:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:16:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:16:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:19 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:16:20 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:16:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:20 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:16:21 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:16:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:16:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:16:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:16:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:16:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:21 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 05:16:22 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 05:16:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:22 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 05:16:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:23 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 05:16:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:16:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:16:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:16:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:23 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 05:16:24 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 05:16:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:24 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 05:16:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:16:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:16:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:16:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:25 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 05:16:25 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 05:16:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:25 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 05:16:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:16:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:16:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:16:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:26 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 05:16:26 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 05:16:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:27 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 05:16:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:16:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:16:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:16:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:27 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 05:16:28 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 05:16:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:28 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 05:16:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:16:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:16:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:16:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:29 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 05:16:29 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 05:16:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:30 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 05:16:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:16:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:16:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:16:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:30 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 05:16:31 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 05:16:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:31 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 05:16:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:16:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:16:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:16:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:32 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 05:16:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:32 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 05:16:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:16:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:16:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:16:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:33 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 05:16:33 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 05:16:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:33 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 05:16:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:16:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:16:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:16:34 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 05:16:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:34 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 05:16:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:35 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 05:16:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:16:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:16:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:16:35 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 05:16:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:36 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 05:16:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:36 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 05:16:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:16:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:16:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:16:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:16:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:16:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:16:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:16:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:16:37 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:16:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:16:37 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6322 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:16:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:16:37 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6322 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:16:37 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6322 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:16:37 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6322 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:16:37 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6322 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:16:37 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6322 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:16:37 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6322 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:16:37 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6322 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:16:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:16:42 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:16:42 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:16:42 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:16:42 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:16:42 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:16:42 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:16:42 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:16:42 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:16:42 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:16:42 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:16:42 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:16:42 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:16:42 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:16:42 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:42 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:16:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:43 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:16:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:16:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:16:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:16:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:16:43 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:16:44 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:16:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:16:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:16:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:16:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:16:44 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:16:45 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:16:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:16:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:16:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:16:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:16:45 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:16:46 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:16:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:16:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:16:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:16:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:16:46 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:16:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:16:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:16:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:16:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:46 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:16:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:16:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:16:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:16:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:16:47 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:16:47 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:16:48 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:16:48 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:16:49 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:16:49 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:16:50 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:16:50 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:16:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:16:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:16:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:16:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:51 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:16:51 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:16:52 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:16:52 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:16:53 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:16:53 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:16:53 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:16:54 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:16:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:16:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:16:54 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:55 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:16:55 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 05:16:56 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 05:16:56 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 05:16:57 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 05:16:57 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 05:16:58 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 05:16:58 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 05:16:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:59 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 05:16:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:16:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:16:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:16:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:16:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:16:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:16:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:16:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:16:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:16:59 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 05:17:00 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 05:17:00 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 05:17:01 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 05:17:01 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 05:17:01 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 05:17:02 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 05:17:02 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 05:17:03 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 05:17:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:17:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:17:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:17:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:17:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:17:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:17:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:17:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:17:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:17:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:17:03 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 05:17:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:17:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:17:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:17:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:04 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 05:17:04 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 05:17:05 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 05:17:05 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 05:17:06 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 05:17:06 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 05:17:07 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 05:17:07 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 05:17:08 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 05:17:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:17:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:17:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:17:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:17:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:17:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:17:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:17:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:17:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:17:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:17:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:17:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:17:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:17:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:08 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 05:17:08 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 05:17:09 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 05:17:09 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 05:17:10 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 05:17:10 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 05:17:11 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-10-30 05:17:11 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-10-30 05:17:12 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-10-30 05:17:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:17:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:17:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:17:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:17:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:17:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:17:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:17:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:17:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:17:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:17:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:17:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:17:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:17:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:17:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:12 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-10-30 05:17:13 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-10-30 05:17:13 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-10-30 05:17:14 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-10-30 05:17:14 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-10-30 05:17:15 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-10-30 05:17:15 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-10-30 05:17:16 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-10-30 05:17:16 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-10-30 05:17:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:17:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:17:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:17:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:17:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:17:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:17:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:17:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:17:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:17:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:17:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:17:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:17:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:17:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:16 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-10-30 05:17:17 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-10-30 05:17:17 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-10-30 05:17:18 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-10-30 05:17:18 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-10-30 05:17:19 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-10-30 05:17:19 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-10-30 05:17:20 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-10-30 05:17:20 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-10-30 05:17:21 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-10-30 05:17:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:17:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:17:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:17:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:17:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:17:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:17:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:17:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:17:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:17:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:17:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:17:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:17:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:17:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:17:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:21 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-10-30 05:17:22 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-10-30 05:17:22 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-10-30 05:17:23 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-10-30 05:17:23 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-10-30 05:17:24 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-10-30 05:17:24 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-10-30 05:17:24 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-10-30 05:17:25 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2024-10-30 05:17:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:17:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:17:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:17:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:17:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:17:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:17:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:17:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:17:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:17:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:17:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:17:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:17:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:17:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:25 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2024-10-30 05:17:26 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2024-10-30 05:17:26 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2024-10-30 05:17:27 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2024-10-30 05:17:27 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2024-10-30 05:17:28 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2024-10-30 05:17:28 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2024-10-30 05:17:29 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2024-10-30 05:17:29 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2024-10-30 05:17:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:17:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:17:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:17:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:17:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:17:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:17:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:17:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:17:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:17:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:17:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:17:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:17:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:17:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:30 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2024-10-30 05:17:30 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2024-10-30 05:17:31 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2024-10-30 05:17:31 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2024-10-30 05:17:31 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2024-10-30 05:17:32 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2024-10-30 05:17:32 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2024-10-30 05:17:33 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2024-10-30 05:17:33 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2024-10-30 05:17:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:17:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:17:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:17:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:17:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:17:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:17:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:17:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:17:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:17:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:17:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:17:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:17:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:17:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:34 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2024-10-30 05:17:34 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2024-10-30 05:17:35 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2024-10-30 05:17:35 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2024-10-30 05:17:36 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2024-10-30 05:17:36 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2024-10-30 05:17:37 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2024-10-30 05:17:37 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2024-10-30 05:17:38 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2024-10-30 05:17:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:17:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:17:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:17:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:17:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:17:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:17:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:17:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:17:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:17:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:17:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:17:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:17:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:17:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:38 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2024-10-30 05:17:39 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2024-10-30 05:17:39 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2024-10-30 05:17:39 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2024-10-30 05:17:40 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2024-10-30 05:17:40 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2024-10-30 05:17:41 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2024-10-30 05:17:41 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2024-10-30 05:17:42 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2024-10-30 05:17:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:17:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:17:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:17:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:17:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:17:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:17:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:17:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:17:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:17:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:17:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:17:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:17:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:17:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:42 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2024-10-30 05:17:43 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2024-10-30 05:17:43 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2024-10-30 05:17:44 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2024-10-30 05:17:44 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2024-10-30 05:17:45 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2024-10-30 05:17:45 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2024-10-30 05:17:46 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2024-10-30 05:17:46 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2024-10-30 05:17:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:17:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:17:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:17:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:17:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:17:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:17:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:17:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:17:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:17:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:17:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:17:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:17:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:17:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:46 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2024-10-30 05:17:47 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2024-10-30 05:17:47 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2024-10-30 05:17:48 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2024-10-30 05:17:48 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2024-10-30 05:17:49 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2024-10-30 05:17:49 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2024-10-30 05:17:50 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2024-10-30 05:17:50 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2024-10-30 05:17:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:17:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:17:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:17:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:17:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:17:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:17:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:17:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:17:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:17:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:17:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:17:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:17:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:17:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:51 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2024-10-30 05:17:51 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2024-10-30 05:17:52 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2024-10-30 05:17:52 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2024-10-30 05:17:53 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2024-10-30 05:17:53 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2024-10-30 05:17:54 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2024-10-30 05:17:54 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2024-10-30 05:17:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:17:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:17:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:17:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:17:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:17:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:17:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:17:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:17:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:17:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:17:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:17:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:17:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:17:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:54 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2024-10-30 05:17:55 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2024-10-30 05:17:55 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2024-10-30 05:17:56 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2024-10-30 05:17:56 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2024-10-30 05:17:57 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2024-10-30 05:17:57 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2024-10-30 05:17:58 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2024-10-30 05:17:58 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2024-10-30 05:17:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:17:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:17:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:17:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:17:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:17:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:17:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:17:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:17:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:17:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:17:59 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2024-10-30 05:17:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:17:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:17:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:17:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:17:59 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2024-10-30 05:18:00 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2024-10-30 05:18:00 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2024-10-30 05:18:01 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2024-10-30 05:18:01 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2024-10-30 05:18:01 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2024-10-30 05:18:02 [DEBUG] clck_gen.py:102 IND CLOCK 17442
2024-10-30 05:18:02 [DEBUG] clck_gen.py:102 IND CLOCK 17544
2024-10-30 05:18:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:18:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:18:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:18:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:18:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:18:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:18:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:18:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:18:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:18:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:18:03 [DEBUG] clck_gen.py:102 IND CLOCK 17646
2024-10-30 05:18:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:18:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:18:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:18:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:03 [DEBUG] clck_gen.py:102 IND CLOCK 17748
2024-10-30 05:18:04 [DEBUG] clck_gen.py:102 IND CLOCK 17850
2024-10-30 05:18:04 [DEBUG] clck_gen.py:102 IND CLOCK 17952
2024-10-30 05:18:05 [DEBUG] clck_gen.py:102 IND CLOCK 18054
2024-10-30 05:18:05 [DEBUG] clck_gen.py:102 IND CLOCK 18156
2024-10-30 05:18:06 [DEBUG] clck_gen.py:102 IND CLOCK 18258
2024-10-30 05:18:06 [DEBUG] clck_gen.py:102 IND CLOCK 18360
2024-10-30 05:18:07 [DEBUG] clck_gen.py:102 IND CLOCK 18462
2024-10-30 05:18:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:18:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:18:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:18:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:18:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:18:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:18:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:18:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:18:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:18:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:18:07 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:18:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=18562 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:18:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:18:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:18:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:18:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=18562 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:18:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=18562 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:18:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:18:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:18:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:18:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:18:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:18:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:18:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:18:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:18:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:18:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:18:12 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:18:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:18:12 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:18:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:18:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:18:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:18:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:18:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:18:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:18:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:18:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:18:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:18:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:18:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:18:17 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:18:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:18:17 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:18:18 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:18:18 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:18:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:18:18 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:18:18 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:18:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:18:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:18:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:18:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:18:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:18:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:18:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:18:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:18:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:18:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:18:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:18 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:18:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:18:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:18:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:18:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:18:19 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:18:19 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:18:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:18:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:18:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:18:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:18:20 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:18:20 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:18:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:18:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:18:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:18:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:18:20 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:18:21 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:18:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:18:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:18:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:18:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:18:21 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:18:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:18:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:18:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:18:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:18:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:18:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:18:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:18:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:18:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:18:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:18:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:18:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:18:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:18:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:22 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:18:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:18:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:18:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:18:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:18:22 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:18:23 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:18:23 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:18:24 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:18:24 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:18:25 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:18:25 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:18:26 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:18:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:18:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:18:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:18:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:18:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:18:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:18:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:18:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:18:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:18:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:18:26 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:18:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:18:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:18:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:18:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:27 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:18:27 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:18:28 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:18:28 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:18:28 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:18:29 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:18:29 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:18:30 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:18:30 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:18:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:18:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:18:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:18:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:18:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:18:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:18:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:18:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:18:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:18:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:18:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:18:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:18:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:18:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:31 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 05:18:31 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 05:18:32 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 05:18:32 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 05:18:33 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 05:18:33 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 05:18:34 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 05:18:34 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 05:18:35 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 05:18:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:18:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:18:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:18:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:18:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:18:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:18:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:18:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:18:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:18:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:18:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:18:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:18:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:18:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:35 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 05:18:35 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 05:18:36 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 05:18:36 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 05:18:37 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 05:18:37 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 05:18:38 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 05:18:38 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 05:18:39 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 05:18:39 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 05:18:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:18:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:18:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:18:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:18:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:18:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:18:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:18:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:18:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:18:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:18:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:18:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:18:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:18:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:40 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 05:18:40 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 05:18:41 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 05:18:41 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 05:18:42 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 05:18:42 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 05:18:43 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 05:18:43 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 05:18:43 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 05:18:44 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 05:18:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:18:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:18:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:18:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:18:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:18:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:18:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:18:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:18:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:18:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:18:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:18:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:18:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:18:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:44 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 05:18:45 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 05:18:45 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 05:18:46 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 05:18:46 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-10-30 05:18:47 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-10-30 05:18:47 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-10-30 05:18:48 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-10-30 05:18:48 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-10-30 05:18:49 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-10-30 05:18:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:18:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:18:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:18:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:18:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:18:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:18:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:18:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:18:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:18:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:18:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:18:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:18:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:18:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:18:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:49 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-10-30 05:18:50 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-10-30 05:18:50 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-10-30 05:18:51 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-10-30 05:18:51 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-10-30 05:18:51 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-10-30 05:18:52 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-10-30 05:18:52 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-10-30 05:18:53 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-10-30 05:18:53 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-10-30 05:18:54 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-10-30 05:18:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:18:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:18:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:18:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:18:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:18:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:18:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:18:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:18:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:18:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:18:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:18:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:18:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:18:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:54 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-10-30 05:18:55 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-10-30 05:18:55 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-10-30 05:18:56 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-10-30 05:18:56 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-10-30 05:18:57 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-10-30 05:18:57 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-10-30 05:18:58 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-10-30 05:18:58 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-10-30 05:18:58 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-10-30 05:18:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:18:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:18:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:18:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:18:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:18:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:18:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:18:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:18:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:18:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:18:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:18:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:18:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:18:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:18:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:18:59 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-10-30 05:18:59 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-10-30 05:19:00 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-10-30 05:19:00 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2024-10-30 05:19:01 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2024-10-30 05:19:01 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2024-10-30 05:19:02 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2024-10-30 05:19:02 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2024-10-30 05:19:03 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2024-10-30 05:19:03 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2024-10-30 05:19:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:19:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:19:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:19:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:19:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:19:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:19:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:19:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:19:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:19:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:19:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:19:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:19:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:19:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:04 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2024-10-30 05:19:04 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2024-10-30 05:19:05 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2024-10-30 05:19:05 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2024-10-30 05:19:06 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2024-10-30 05:19:06 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2024-10-30 05:19:06 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2024-10-30 05:19:07 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2024-10-30 05:19:07 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2024-10-30 05:19:08 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2024-10-30 05:19:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:19:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:19:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:19:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:19:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:19:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:19:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:19:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:19:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:19:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:19:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:19:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:19:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:19:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:08 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2024-10-30 05:19:09 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2024-10-30 05:19:09 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2024-10-30 05:19:10 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2024-10-30 05:19:10 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2024-10-30 05:19:11 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2024-10-30 05:19:11 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2024-10-30 05:19:12 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2024-10-30 05:19:12 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2024-10-30 05:19:13 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2024-10-30 05:19:13 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2024-10-30 05:19:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:19:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:19:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:19:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:19:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:19:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:19:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:19:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:19:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:19:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:19:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:19:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:19:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:19:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:13 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2024-10-30 05:19:14 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2024-10-30 05:19:14 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2024-10-30 05:19:15 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2024-10-30 05:19:15 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2024-10-30 05:19:16 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2024-10-30 05:19:16 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2024-10-30 05:19:17 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2024-10-30 05:19:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:19:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:19:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:19:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:19:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:19:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:19:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:19:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:19:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:19:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:19:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:19:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:19:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:19:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:17 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2024-10-30 05:19:18 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2024-10-30 05:19:18 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2024-10-30 05:19:19 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2024-10-30 05:19:19 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2024-10-30 05:19:20 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2024-10-30 05:19:20 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2024-10-30 05:19:21 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2024-10-30 05:19:21 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2024-10-30 05:19:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:19:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:19:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:19:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:19:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:19:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:19:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:19:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:19:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:19:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:19:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:19:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:19:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:19:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:21 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2024-10-30 05:19:22 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2024-10-30 05:19:22 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2024-10-30 05:19:23 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2024-10-30 05:19:23 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2024-10-30 05:19:24 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2024-10-30 05:19:24 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2024-10-30 05:19:25 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2024-10-30 05:19:25 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2024-10-30 05:19:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:19:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:19:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:19:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:19:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:19:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:19:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:19:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:19:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:19:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:19:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:19:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:19:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:19:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:26 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2024-10-30 05:19:26 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2024-10-30 05:19:27 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2024-10-30 05:19:27 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2024-10-30 05:19:28 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2024-10-30 05:19:28 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2024-10-30 05:19:29 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2024-10-30 05:19:29 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2024-10-30 05:19:29 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2024-10-30 05:19:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:19:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:19:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:19:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:19:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:19:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:19:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:19:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:19:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:19:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:19:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:19:30 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2024-10-30 05:19:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:19:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:19:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:30 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2024-10-30 05:19:31 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2024-10-30 05:19:31 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2024-10-30 05:19:32 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2024-10-30 05:19:32 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2024-10-30 05:19:33 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2024-10-30 05:19:33 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2024-10-30 05:19:34 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2024-10-30 05:19:34 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2024-10-30 05:19:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:19:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:19:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:19:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:19:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:19:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:19:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:19:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:19:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:19:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:19:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:19:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:19:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:19:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:35 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2024-10-30 05:19:35 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2024-10-30 05:19:36 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2024-10-30 05:19:36 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2024-10-30 05:19:36 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2024-10-30 05:19:37 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2024-10-30 05:19:37 [DEBUG] clck_gen.py:102 IND CLOCK 17442
2024-10-30 05:19:38 [DEBUG] clck_gen.py:102 IND CLOCK 17544
2024-10-30 05:19:38 [DEBUG] clck_gen.py:102 IND CLOCK 17646
2024-10-30 05:19:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:19:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:19:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:19:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:19:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:19:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:19:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:19:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:19:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:19:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:19:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:19:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:19:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:19:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:39 [DEBUG] clck_gen.py:102 IND CLOCK 17748
2024-10-30 05:19:39 [DEBUG] clck_gen.py:102 IND CLOCK 17850
2024-10-30 05:19:40 [DEBUG] clck_gen.py:102 IND CLOCK 17952
2024-10-30 05:19:40 [DEBUG] clck_gen.py:102 IND CLOCK 18054
2024-10-30 05:19:41 [DEBUG] clck_gen.py:102 IND CLOCK 18156
2024-10-30 05:19:41 [DEBUG] clck_gen.py:102 IND CLOCK 18258
2024-10-30 05:19:42 [DEBUG] clck_gen.py:102 IND CLOCK 18360
2024-10-30 05:19:42 [DEBUG] clck_gen.py:102 IND CLOCK 18462
2024-10-30 05:19:43 [DEBUG] clck_gen.py:102 IND CLOCK 18564
2024-10-30 05:19:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:19:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:19:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:19:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:19:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:19:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:19:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:19:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:19:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:19:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:19:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:19:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:19:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:19:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:43 [DEBUG] clck_gen.py:102 IND CLOCK 18666
2024-10-30 05:19:44 [DEBUG] clck_gen.py:102 IND CLOCK 18768
2024-10-30 05:19:44 [DEBUG] clck_gen.py:102 IND CLOCK 18870
2024-10-30 05:19:44 [DEBUG] clck_gen.py:102 IND CLOCK 18972
2024-10-30 05:19:45 [DEBUG] clck_gen.py:102 IND CLOCK 19074
2024-10-30 05:19:45 [DEBUG] clck_gen.py:102 IND CLOCK 19176
2024-10-30 05:19:46 [DEBUG] clck_gen.py:102 IND CLOCK 19278
2024-10-30 05:19:46 [DEBUG] clck_gen.py:102 IND CLOCK 19380
2024-10-30 05:19:47 [DEBUG] clck_gen.py:102 IND CLOCK 19482
2024-10-30 05:19:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:19:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:19:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:19:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:19:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:19:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:19:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:19:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:19:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:19:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:19:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:19:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:19:47 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:19:47 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=19520 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:19:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:19:47 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=19520 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:19:47 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=19520 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:19:47 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=19520 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:19:47 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=19520 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:19:47 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=19520 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:19:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:19:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:19:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:19:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:19:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:19:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:19:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:19:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:19:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:19:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:19:52 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:19:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:19:52 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:19:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:19:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:19:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:19:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:19:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:19:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:19:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:19:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:19:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:19:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:19:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:19:57 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:19:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:19:57 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:19:58 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:19:58 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:19:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:19:58 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:19:58 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:19:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:19:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:19:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:19:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:19:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:19:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:19:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:19:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:19:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:19:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:19:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:58 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:19:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:19:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:19:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:19:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:19:58 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:19:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:19:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:19:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:19:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:19:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:19:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:19:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:19:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:19:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:19:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:19:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:19:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:19:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:19:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:19:59 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:19:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:19:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:19:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:19:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:19:59 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:20:00 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:20:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:20:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:20:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:20:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:20:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:20:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:20:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:20:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:00 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:20:01 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:20:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:20:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:20:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:20:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:20:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:20:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:20:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:20:01 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:20:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:02 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:20:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:20:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:20:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:20:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:20:02 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:20:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:03 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:20:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:20:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:20:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:20:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:03 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:20:04 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:20:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:20:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:20:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:20:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:04 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:20:05 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:20:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:20:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:20:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:20:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:05 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:20:06 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:20:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:20:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:20:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:20:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:20:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:06 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:20:06 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:20:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:20:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:20:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:20:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:07 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:20:07 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:20:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:20:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:20:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:20:08 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:20:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:20:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:08 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:20:09 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:20:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:20:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:20:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:20:09 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:20:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:10 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:20:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:20:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:20:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:20:10 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:20:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:11 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 05:20:11 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 05:20:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:20:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:20:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:20:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:12 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 05:20:12 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 05:20:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:20:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:20:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:20:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:13 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 05:20:13 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 05:20:13 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 05:20:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:20:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:20:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:20:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:14 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 05:20:14 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 05:20:15 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 05:20:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:20:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:20:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:20:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:15 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 05:20:16 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 05:20:16 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 05:20:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:20:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:20:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:20:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:17 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 05:20:17 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 05:20:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:20:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:20:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:20:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:18 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 05:20:18 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 05:20:19 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 05:20:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:20:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:20:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:20:19 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 05:20:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:20 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 05:20:20 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 05:20:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:20:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:20:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:20:21 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 05:20:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:21 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 05:20:21 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 05:20:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:20:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:20:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:20:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:20:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:20:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:20:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:20:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:20:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:20:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:20:22 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:20:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5404 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:20:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5404 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:20:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5404 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:20:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5404 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:20:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5404 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:20:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5404 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:20:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:20:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:20:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:20:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:20:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:20:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:20:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:20:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:20:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:20:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:20:27 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:20:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:20:27 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:20:27 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:20:27 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:27 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:20:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:20:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:20:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:28 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:20:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:20:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:20:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:20:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:20:28 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:20:29 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:20:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:20:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:20:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:20:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:20:29 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:20:30 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:20:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:20:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:20:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:20:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:20:30 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:20:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:31 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:20:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:20:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:20:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:20:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:20:31 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:20:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:20:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:20:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:20:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:20:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:32 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:20:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:20:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:20:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:20:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:20:32 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:20:33 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:20:33 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:20:34 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:20:34 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:20:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:34 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:20:35 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:20:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:20:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:20:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:20:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:20:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:35 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:20:36 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:20:36 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:20:37 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:20:37 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:20:38 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:20:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:38 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:20:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:20:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:20:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:20:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:20:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:39 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:20:39 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:20:40 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:20:40 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:20:41 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 05:20:41 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 05:20:42 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 05:20:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:42 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 05:20:42 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 05:20:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:20:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:20:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:20:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:20:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:43 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 05:20:43 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 05:20:44 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 05:20:44 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 05:20:45 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 05:20:45 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 05:20:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:46 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 05:20:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:20:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:20:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:20:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:20:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:46 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 05:20:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:47 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 05:20:47 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 05:20:48 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 05:20:48 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 05:20:49 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 05:20:49 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 05:20:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:20:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:20:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:20:49 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 05:20:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:20:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:50 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 05:20:50 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 05:20:51 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 05:20:51 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 05:20:52 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 05:20:52 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 05:20:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:53 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 05:20:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:20:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:20:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:20:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:20:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:20:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:20:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:53 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 05:20:54 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 05:20:54 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 05:20:55 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 05:20:55 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 05:20:56 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 05:20:56 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-10-30 05:20:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:20:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:20:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:20:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:20:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:20:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:20:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:20:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:20:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:20:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:20:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:20:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:20:56 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:20:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:20:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:21:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:21:01 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:21:01 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:21:01 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:21:01 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:21:01 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:21:01 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:21:01 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:21:01 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:21:01 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:21:01 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:21:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:21:01 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:21:02 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:21:02 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:21:02 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:21:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:21:02 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:21:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:21:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:21:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:21:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:21:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:21:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:21:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:21:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:21:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:21:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:21:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:02 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:21:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:21:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:21:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:21:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:21:03 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:21:03 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:21:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:21:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:21:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:21:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:21:04 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:21:04 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:21:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:21:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:21:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:21:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:21:05 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:21:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:21:05 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:21:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:21:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:21:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:21:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:21:06 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:21:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:21:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:21:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:21:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:21:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:21:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:21:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:21:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:21:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:21:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:21:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:21:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:06 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:21:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:21:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:21:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:21:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:21:07 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:21:07 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:21:08 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:21:08 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:21:09 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:21:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:21:09 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:21:09 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:21:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:21:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:21:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:21:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:21:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:21:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:21:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:21:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:21:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:21:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:21:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:21:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:10 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:21:10 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:21:11 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:21:11 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:21:12 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:21:12 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:21:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:21:13 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:21:13 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:21:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:21:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:21:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:21:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:21:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:21:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:21:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:21:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:21:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:21:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:21:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:21:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:14 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:21:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:21:14 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:21:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:21:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:21:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:21:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:21:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:21:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:21:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:21:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:21:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:21:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:21:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:21:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:21:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:21:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:15 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:21:15 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 05:21:16 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 05:21:16 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 05:21:17 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 05:21:17 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 05:21:17 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 05:21:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:21:18 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 05:21:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:21:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:21:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:21:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:21:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:21:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:21:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:21:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:21:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:21:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:21:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:21:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:18 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 05:21:19 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 05:21:19 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 05:21:20 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 05:21:20 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 05:21:21 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 05:21:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:21:21 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 05:21:22 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 05:21:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:21:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:21:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:21:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:21:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:21:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:21:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:21:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:21:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:21:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:21:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:21:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:22 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 05:21:23 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 05:21:23 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 05:21:24 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 05:21:24 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 05:21:24 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 05:21:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:21:25 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 05:21:25 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 05:21:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:21:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:21:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:21:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:21:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:21:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:21:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:21:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:21:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:21:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:21:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:21:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:26 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 05:21:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:21:26 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 05:21:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:21:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:21:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:21:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:21:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:21:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:21:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:21:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:21:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:21:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:21:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:21:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:21:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:21:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:27 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 05:21:27 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 05:21:28 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 05:21:28 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 05:21:29 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 05:21:29 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 05:21:30 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 05:21:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:21:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:21:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:21:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:21:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:21:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:21:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:21:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:21:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:21:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:21:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:21:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:21:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:30 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 05:21:31 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-10-30 05:21:31 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-10-30 05:21:32 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-10-30 05:21:32 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-10-30 05:21:32 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-10-30 05:21:33 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-10-30 05:21:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:21:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:21:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:21:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:21:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:21:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:21:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:21:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:21:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:21:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:21:33 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-10-30 05:21:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:21:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:21:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:34 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-10-30 05:21:34 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-10-30 05:21:35 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-10-30 05:21:35 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-10-30 05:21:36 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-10-30 05:21:36 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-10-30 05:21:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:21:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:21:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:21:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:21:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:21:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:21:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:21:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:21:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:21:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:21:37 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-10-30 05:21:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:21:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:21:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:21:37 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-10-30 05:21:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:21:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:21:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:21:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:21:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:21:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:21:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:21:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:21:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:21:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:21:38 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-10-30 05:21:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:21:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:21:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:21:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:38 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-10-30 05:21:39 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-10-30 05:21:39 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-10-30 05:21:39 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-10-30 05:21:40 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-10-30 05:21:40 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-10-30 05:21:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:21:41 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-10-30 05:21:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:21:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:21:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:21:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:21:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:21:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:21:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:21:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:21:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:21:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:21:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:21:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:41 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-10-30 05:21:42 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-10-30 05:21:42 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-10-30 05:21:43 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-10-30 05:21:43 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-10-30 05:21:44 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-10-30 05:21:44 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-10-30 05:21:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:21:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:21:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:21:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:21:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:21:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:21:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:21:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:21:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:21:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:21:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:21:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:21:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:45 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2024-10-30 05:21:45 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2024-10-30 05:21:46 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2024-10-30 05:21:46 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2024-10-30 05:21:47 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2024-10-30 05:21:47 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2024-10-30 05:21:47 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2024-10-30 05:21:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:21:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:21:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:21:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:21:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:21:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:21:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:21:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:21:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:21:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:21:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:21:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:21:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:48 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2024-10-30 05:21:48 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2024-10-30 05:21:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:21:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:21:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:21:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:21:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:21:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:21:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:21:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:21:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:21:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:21:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:21:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:21:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:21:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:21:49 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:21:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:21:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:21:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:21:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:21:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:21:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:21:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:21:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:21:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:21:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:21:54 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:21:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:21:54 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:21:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:21:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:21:59 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:21:59 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:21:59 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:21:59 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:21:59 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:21:59 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:21:59 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:21:59 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:21:59 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:21:59 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:21:59 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:21:59 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:21:59 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:21:59 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:21:59 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:21:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:21:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:21:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:22:00 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:22:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:22:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:22:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:22:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:22:00 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:22:01 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:22:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:22:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:22:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:22:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:22:01 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:22:02 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:22:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:22:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:22:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:22:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:22:02 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:22:03 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:22:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:22:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:22:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:22:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:22:03 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:22:04 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:22:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:22:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:22:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:22:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:22:04 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:22:05 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:22:05 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:22:05 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:22:06 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:22:06 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:22:07 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:22:07 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:22:08 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:22:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:22:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:22:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:22:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:22:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:22:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:22:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:22:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:22:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:22:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:22:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:22:08 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:22:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:22:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:22:13 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:22:13 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:22:13 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:22:13 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:22:13 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:22:13 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:22:13 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:22:13 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:22:13 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:22:13 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:22:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:22:13 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:22:14 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:22:14 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:22:14 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:22:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:22:14 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:22:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:22:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:22:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:22:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:22:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:22:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:22:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:22:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:22:14 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:22:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:22:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:22:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:22:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:22:15 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:22:15 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:22:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:22:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:22:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:22:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:22:16 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:22:16 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:22:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:22:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:22:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:22:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:22:16 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:22:17 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:22:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:22:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:22:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:22:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:22:17 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:22:18 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:22:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:22:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:22:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:22:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:22:18 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:22:19 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:22:19 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:22:20 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:22:20 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:22:21 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:22:21 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:22:22 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:22:22 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:22:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:22:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:22:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:22:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:22:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:22:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:22:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:22:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:22:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:22:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:22:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:22:22 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:22:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:22:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:22:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:22:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:22:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:22:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:22:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:22:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:22:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:22:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:22:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:22:27 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:22:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:22:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:22:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:22:28 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:22:28 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:22:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:22:28 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:22:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:22:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:22:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:22:28 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:22:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:22:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:22:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:22:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:22:29 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:22:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:22:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:22:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:22:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:22:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:22:29 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:22:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:22:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:22:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:22:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:22:30 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:22:30 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:22:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:22:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:22:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:22:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:22:31 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:22:31 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:22:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:22:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:22:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:22:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:22:32 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:22:32 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:22:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:22:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:22:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:22:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:22:33 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:22:33 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:22:34 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:22:34 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:22:35 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:22:35 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:22:35 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:22:36 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:22:36 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:22:37 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:22:37 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:22:38 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:22:38 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:22:39 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:22:39 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:22:40 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:22:40 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:22:41 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:22:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:22:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:22:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:22:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:22:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:22:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:22:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:22:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:22:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:22:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:22:41 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:22:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:22:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:22:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:22:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:22:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:22:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:22:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:22:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:22:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:22:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:22:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:22:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:22:46 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:22:46 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:22:46 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:22:46 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:22:46 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:22:46 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:22:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:22:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:22:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:22:47 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:22:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:22:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:22:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:22:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:22:47 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:22:47 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:22:48 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:22:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:22:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:22:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:22:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:22:48 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:22:48 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:22:48 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:22:49 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:22:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:22:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:22:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:22:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:22:49 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:22:50 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:22:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:22:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:22:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:22:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:22:50 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:22:50 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:22:51 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:22:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:22:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:22:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:22:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:22:51 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:22:51 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:22:51 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:22:51 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:22:52 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:22:52 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:22:52 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:22:53 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:22:53 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:22:54 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:22:54 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:22:54 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:22:55 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:22:55 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:22:56 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:22:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:22:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:22:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:22:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:22:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:22:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:22:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:22:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:22:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:22:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:22:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:22:56 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:22:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:23:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:23:01 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:23:01 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:23:01 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:23:01 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:23:01 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:23:01 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:23:01 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:23:01 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:23:01 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:23:01 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:01 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:23:02 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:23:02 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:23:02 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:23:02 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:23:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:23:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:23:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:23:02 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:23:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:23:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:23:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:23:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:23:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:23:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:23:02 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:23:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:23:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:23:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:23:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:23:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:23:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:03 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:23:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:23:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:03 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:23:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:23:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:23:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:23:04 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:23:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:23:04 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:23:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:23:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:23:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:23:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:23:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:23:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:23:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:23:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:23:09 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:23:09 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:23:09 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:23:09 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:09 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:23:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:23:10 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:23:10 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:10 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:23:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:23:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:23:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 05:23:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:10 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:23:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:23:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:23:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:23:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:23:11 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:23:11 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:23:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:23:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:23:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:23:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:23:11 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:23:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:23:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:23:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:23:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:23:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:23:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:23:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:23:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:23:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:23:12 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:23:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:23:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:23:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:23:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:23:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:23:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:23:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:23:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:23:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:23:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:23:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:23:17 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:23:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:23:17 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:23:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:23:22 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:23:22 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:23:22 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:23:22 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:23:22 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:23:22 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:23:22 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:23:22 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:23:22 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:23:22 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:22 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:23:22 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:23:22 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:23:22 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:23:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:22 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:23:23 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:23:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:23:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:23:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:23:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:23:23 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:23:24 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:23:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:23:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:23:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:23:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:23:24 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:23:25 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:23:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:23:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:23:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:23:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:23:25 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:23:26 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:23:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:23:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:23:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:23:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:23:26 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:23:27 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:23:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:23:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:23:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:23:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:23:27 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:23:27 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:23:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:23:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:23:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:23:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:23:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:23:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:23:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:23:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:23:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:23:28 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:23:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1308 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:23:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:23:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1308 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:23:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1308 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:23:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1308 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:23:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1308 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:23:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:23:33 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:23:33 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:23:33 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:23:33 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:23:33 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:23:33 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:23:33 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:23:33 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:23:33 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:23:33 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:33 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:23:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:23:33 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:23:33 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:23:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:33 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:23:34 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:23:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:23:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:23:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:23:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:23:34 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:23:35 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:23:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:23:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:23:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:23:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:23:35 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:23:36 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:23:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:23:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:23:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:23:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:23:36 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:23:37 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:23:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:23:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:23:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:23:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:23:37 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:23:38 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:23:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:23:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:23:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:23:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:23:38 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:23:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:23:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:23:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:23:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:23:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:23:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:23:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:23:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:23:38 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:23:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:23:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:23:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:23:43 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:23:43 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:23:43 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:23:43 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:23:43 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:23:43 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:23:43 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:23:43 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:23:43 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:23:43 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:23:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:23:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:23:43 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:23:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:23:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:23:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:23:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:23:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:23:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:23:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:23:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:23:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:23:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:23:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:23:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:23:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:23:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:23:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:23:49 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:23:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:23:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:23:49 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:23:49 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:23:49 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:23:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:23:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:23:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:23:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:23:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:23:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:23:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:23:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:23:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:23:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:23:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:23:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:23:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:23:50 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:23:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:23:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:23:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:23:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:23:51 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:23:51 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:23:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:23:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:23:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:23:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:23:52 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:23:52 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:23:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:23:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:23:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:23:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:23:53 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:23:53 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:23:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:23:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:23:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:23:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:23:54 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:23:54 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:23:55 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:23:55 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:23:56 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:23:56 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:23:57 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:23:57 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:23:57 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:23:58 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:23:58 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:23:59 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:23:59 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:24:00 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:24:00 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:24:01 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:24:01 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:24:02 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:24:02 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 05:24:03 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 05:24:03 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 05:24:04 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 05:24:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:24:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:24:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:24:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:24:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:24:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:24:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:24:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:24:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:24:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:24:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:24:04 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:24:04 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3314 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:24:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:24:04 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3314 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:24:04 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3314 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:24:04 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3314 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:24:04 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3314 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:24:04 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3314 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:24:04 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3314 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:24:04 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3314 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:24:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:24:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:24:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:24:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:24:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:24:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:24:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:24:09 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:24:09 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:24:09 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:24:09 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:24:09 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:24:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:24:09 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:24:09 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:24:09 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:24:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:24:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:24:09 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:24:09 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:24:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:24:10 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:24:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:24:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:24:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:24:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:24:10 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:24:11 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:24:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:24:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:24:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:24:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:24:11 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:24:12 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:24:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:24:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:24:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:24:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:24:12 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:24:13 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:24:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:24:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:24:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:24:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:24:13 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:24:14 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:24:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:24:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:24:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:24:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:24:14 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:24:14 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:24:15 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:24:15 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:24:16 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:24:16 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:24:17 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:24:17 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:24:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:24:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:24:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:24:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:24:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:24:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:24:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:24:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:24:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:24:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:24:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:24:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:24:17 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:24:17 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1862 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:24:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:24:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:24:17 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1862 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:24:17 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1862 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:24:17 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1862 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:24:17 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1862 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:24:17 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1862 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:24:17 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1862 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:24:17 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1862 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:24:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:24:22 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:24:22 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:24:22 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:24:22 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:24:22 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:24:22 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:24:22 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:24:22 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:24:22 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:24:22 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:24:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:24:22 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:24:23 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:24:23 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:24:23 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:24:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:24:23 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:24:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:24:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:24:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:24:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:24:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:24:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:24:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:24:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:24:23 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:24:23 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:24:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:24:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:24:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:24:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:24:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:24:23 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:24:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:24:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:24:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:24:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:24:24 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:24:24 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:24:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:24:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:24:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:24:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:24:25 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:24:25 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:24:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:24:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:24:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:24:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:24:26 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:24:26 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:24:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:24:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:24:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:24:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:24:27 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:24:27 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:24:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:24:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:24:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:24:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:24:28 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:24:28 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:24:29 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:24:29 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:24:29 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:24:30 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:24:30 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:24:31 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:24:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:24:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:24:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:24:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:24:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:24:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:24:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:24:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:24:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:24:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:24:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:24:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:24:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:24:31 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:24:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:24:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:24:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:24:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:24:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:24:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:24:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:24:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:24:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:24:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:24:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:24:36 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:24:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:24:36 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:24:37 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:24:37 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:24:37 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:24:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:24:37 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:24:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:24:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:24:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:24:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:24:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:24:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:24:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:24:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:24:37 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:24:37 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:24:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:24:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:24:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:24:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:24:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:24:37 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:24:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:24:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:24:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:24:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:24:37 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:24:38 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:24:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:24:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:24:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:24:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:24:38 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:24:39 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:24:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:24:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:24:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:24:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:24:39 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:24:40 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:24:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:24:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:24:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:24:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:24:40 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:24:41 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:24:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:24:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:24:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:24:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:24:41 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:24:42 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:24:42 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:24:43 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:24:43 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:24:44 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:24:44 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:24:45 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:24:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:24:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:24:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:24:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:24:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:24:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:24:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:24:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:24:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:24:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:24:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:24:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:24:45 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:24:45 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:24:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:24:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:24:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:24:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:24:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:24:45 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:24:45 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:24:46 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:24:46 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:24:47 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:24:47 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:24:48 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:24:48 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:24:49 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:24:49 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:24:50 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 05:24:50 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 05:24:51 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 05:24:51 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 05:24:52 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 05:24:52 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 05:24:52 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 05:24:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:24:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:24:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:24:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:24:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:24:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:24:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:24:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:24:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:24:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:24:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:24:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:24:53 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:24:53 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3621 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:24:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:24:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:24:53 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3621 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:24:53 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3621 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:24:53 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3621 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:24:53 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3621 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:24:53 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3621 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:24:53 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3621 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:24:53 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3621 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:24:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:24:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:24:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:24:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:24:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:24:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:24:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:24:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:24:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:24:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:24:58 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:24:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:24:58 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:24:58 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:24:58 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:24:58 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:24:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:24:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:24:58 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:24:58 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:24:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:24:59 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:24:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:24:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:24:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:24:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:24:59 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:25:00 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:25:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:25:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:25:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:25:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:25:00 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:25:01 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:25:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:25:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:25:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:25:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:25:01 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:25:02 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:25:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:25:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:25:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:25:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:25:02 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:25:02 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:25:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:25:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:25:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:25:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:25:03 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:25:03 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:25:04 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:25:04 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:25:05 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:25:05 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:25:06 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:25:06 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:25:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:25:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:25:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:25:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:25:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:25:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:25:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:25:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:25:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:25:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:25:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:25:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:25:06 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:25:06 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:25:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:25:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:25:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:25:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:25:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:25:07 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:25:07 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:25:08 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:25:08 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:25:09 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:25:09 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:25:09 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:25:10 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:25:10 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:25:11 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:25:11 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 05:25:12 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 05:25:12 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 05:25:13 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 05:25:13 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 05:25:14 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 05:25:14 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 05:25:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:25:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:25:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:25:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:25:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:25:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:25:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:25:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:25:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:25:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:25:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:25:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:25:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:25:14 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:25:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:25:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:25:19 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:25:19 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:25:19 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:25:19 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:25:19 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:25:19 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:25:19 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:25:19 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:25:19 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:25:19 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:25:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:25:19 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:25:20 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:25:20 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:25:20 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:25:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:25:20 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:25:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:25:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:25:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:25:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:25:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:25:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:25:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:25:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:25:20 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:25:20 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:25:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:25:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:25:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:25:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:25:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:25:20 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:25:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:25:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:25:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:25:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:25:21 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:25:21 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:25:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:25:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:25:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:25:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:25:22 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:25:22 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:25:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:25:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:25:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:25:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:25:23 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:25:23 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:25:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:25:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:25:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:25:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:25:24 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:25:24 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:25:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:25:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:25:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:25:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:25:25 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:25:25 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:25:26 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:25:26 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:25:26 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:25:27 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:25:27 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:25:28 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:25:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:25:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:25:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:25:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:25:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:25:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:25:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:25:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:25:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:25:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:25:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:25:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:25:28 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:25:28 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:25:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:25:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:25:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:25:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:25:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:25:28 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:25:29 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:25:29 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:25:30 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:25:30 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:25:31 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:25:31 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:25:32 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:25:32 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:25:33 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:25:33 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 05:25:34 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 05:25:34 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 05:25:34 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 05:25:35 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 05:25:35 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 05:25:36 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 05:25:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:25:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:25:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:25:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:25:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:25:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:25:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:25:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:25:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:25:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:25:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:25:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:25:36 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:25:36 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3621 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:25:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:25:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:25:36 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3621 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:25:36 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3621 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:25:36 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3621 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:25:36 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3621 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:25:36 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3621 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:25:36 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3621 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:25:36 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3621 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:25:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:25:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:25:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:25:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:25:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:25:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:25:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:25:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:25:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:25:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:25:41 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:25:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:25:42 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:25:42 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:25:42 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:25:42 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:25:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:25:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:25:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:25:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:25:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:25:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:25:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:25:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:25:42 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:25:42 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:25:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:25:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:25:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:25:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:25:42 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:25:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:25:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:25:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:25:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:25:43 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:25:43 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:25:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:25:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:25:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:25:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:25:43 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:25:44 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:25:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:25:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:25:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:25:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:25:44 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:25:45 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:25:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:25:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:25:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:25:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:25:45 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:25:46 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:25:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:25:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:25:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:25:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:25:46 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:25:47 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:25:47 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:25:48 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:25:48 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:25:49 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:25:49 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:25:50 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:25:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:25:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:25:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:25:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:25:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:25:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:25:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:25:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:25:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:25:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:25:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:25:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:25:50 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:25:50 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:25:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:25:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:25:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:25:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:25:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:25:50 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:25:51 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:25:51 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:25:51 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:25:52 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:25:52 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:25:53 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:25:53 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:25:54 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:25:54 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:25:55 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 05:25:55 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 05:25:56 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 05:25:56 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 05:25:57 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 05:25:57 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 05:25:58 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 05:25:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:25:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:25:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:25:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:25:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:25:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:25:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:25:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:25:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:25:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:25:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:25:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:25:58 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:25:58 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:25:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:25:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:25:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:25:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:25:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:25:58 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 05:25:59 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 05:25:59 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 05:25:59 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 05:26:00 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 05:26:00 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 05:26:01 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 05:26:01 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 05:26:02 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 05:26:02 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 05:26:03 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 05:26:03 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 05:26:04 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 05:26:04 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 05:26:05 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 05:26:05 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 05:26:06 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 05:26:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:26:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:26:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:26:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:26:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:26:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:26:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:26:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:26:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:26:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:26:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:26:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:26:06 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:26:06 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:26:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:26:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:26:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:26:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:26:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:26:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:26:06 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 05:26:06 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 05:26:07 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 05:26:07 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 05:26:08 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 05:26:08 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 05:26:09 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 05:26:09 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 05:26:10 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 05:26:10 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-10-30 05:26:11 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-10-30 05:26:11 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-10-30 05:26:12 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-10-30 05:26:12 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-10-30 05:26:13 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-10-30 05:26:13 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-10-30 05:26:14 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-10-30 05:26:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:26:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:26:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:26:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:26:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:26:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:26:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:26:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:26:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:26:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:26:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:26:14 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:26:14 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=7128 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:26:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:26:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:26:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:26:14 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=7128 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:26:14 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=7128 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:26:14 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=7128 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:26:14 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=7128 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:26:14 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=7128 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:26:14 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=7128 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:26:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:26:19 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:26:19 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:26:19 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:26:19 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:26:19 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:26:19 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:26:19 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:26:19 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:26:19 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:26:19 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:26:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:26:19 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:26:19 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:26:20 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:26:20 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:26:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:26:20 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:26:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:26:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:26:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:26:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:26:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:26:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:26:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:26:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:26:20 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:26:20 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:26:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:26:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:26:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:26:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:26:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:26:20 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:26:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:26:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:26:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:26:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:26:20 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:26:21 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:26:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:26:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:26:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:26:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:26:21 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:26:22 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:26:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:26:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:26:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:26:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:26:22 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:26:23 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:26:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:26:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:26:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:26:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:26:23 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:26:24 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:26:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:26:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:26:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:26:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:26:24 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:26:25 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:26:25 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:26:26 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:26:26 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:26:26 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:26:27 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:26:27 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:26:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:26:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:26:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:26:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:26:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:26:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:26:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:26:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:26:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:26:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:26:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:26:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:26:28 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:26:28 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:26:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:26:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:26:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:26:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:26:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:26:28 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:26:28 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:26:29 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:26:29 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:26:30 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:26:30 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:26:31 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:26:31 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:26:32 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:26:32 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:26:33 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 05:26:33 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 05:26:34 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 05:26:34 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 05:26:34 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 05:26:35 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 05:26:35 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 05:26:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:26:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:26:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:26:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:26:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:26:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:26:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:26:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:26:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:26:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:26:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:26:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:26:36 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:26:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:26:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:26:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:26:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:26:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:26:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:26:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:26:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:26:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:26:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:26:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:26:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:26:41 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:26:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:26:41 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:26:41 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:26:41 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:26:41 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:26:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:26:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:26:41 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:26:41 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:26:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:26:42 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:26:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:26:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:26:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:26:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:26:42 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:26:43 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:26:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:26:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:26:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:26:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:26:43 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:26:43 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:26:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:26:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:26:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:26:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:26:44 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:26:44 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:26:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:26:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:26:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:26:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:26:45 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:26:45 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:26:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:26:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:26:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:26:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:26:46 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:26:46 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:26:47 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:26:47 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:26:48 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:26:48 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:26:49 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:26:49 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:26:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:26:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:26:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:26:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:26:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:26:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:26:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:26:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:26:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:26:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:26:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:26:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:26:49 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:26:49 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:26:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:26:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:26:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:26:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:26:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:26:50 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:26:50 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:26:51 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:26:51 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:26:51 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:26:52 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:26:52 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:26:53 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:26:53 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:26:54 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:26:54 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 05:26:55 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 05:26:55 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 05:26:56 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 05:26:56 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 05:26:57 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 05:26:57 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 05:26:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:26:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:26:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:26:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:26:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:26:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:26:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:26:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:26:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:26:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:26:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:26:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:26:57 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:26:57 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:26:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:26:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:26:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:26:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:26:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:26:58 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 05:26:58 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 05:26:59 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 05:26:59 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 05:26:59 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 05:27:00 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 05:27:00 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 05:27:01 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 05:27:01 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 05:27:02 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 05:27:02 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 05:27:03 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 05:27:03 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 05:27:04 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 05:27:04 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 05:27:05 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 05:27:05 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 05:27:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:27:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:27:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:27:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:27:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:27:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:27:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:27:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:27:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:27:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:27:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:27:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:27:05 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:27:05 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:27:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:27:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:27:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:27:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:27:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:27:06 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 05:27:06 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 05:27:06 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 05:27:07 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 05:27:07 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 05:27:08 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 05:27:08 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 05:27:09 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 05:27:09 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 05:27:10 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-10-30 05:27:10 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-10-30 05:27:11 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-10-30 05:27:11 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-10-30 05:27:12 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-10-30 05:27:12 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-10-30 05:27:13 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-10-30 05:27:13 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-10-30 05:27:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:27:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:27:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:27:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:27:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:27:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:27:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:27:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:27:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:27:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:27:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:27:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:27:13 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:27:13 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=7131 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:27:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:27:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:27:13 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=7131 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:27:13 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=7131 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:27:13 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=7131 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:27:13 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=7131 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:27:13 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=7131 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:27:13 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=7131 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:27:13 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=7131 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:27:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:27:18 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:27:18 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:27:18 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:27:18 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:27:18 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:27:18 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:27:18 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:27:18 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:27:18 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:27:18 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:27:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:27:18 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:27:19 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:27:19 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:27:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:27:19 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:27:19 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:27:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:27:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:27:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:27:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:27:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:27:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:27:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:27:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:27:19 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:27:19 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:27:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:27:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:27:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:27:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:27:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:27:19 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:27:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:27:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:27:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:27:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:27:20 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:27:20 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:27:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:27:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:27:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:27:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:27:21 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:27:21 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:27:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:27:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:27:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:27:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:27:22 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:27:22 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:27:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:27:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:27:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:27:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:27:23 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:27:23 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:27:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:27:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:27:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:27:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:27:24 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:27:24 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:27:25 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:27:25 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:27:26 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:27:26 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:27:26 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:27:27 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:27:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:27:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:27:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:27:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:27:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:27:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:27:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:27:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:27:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:27:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:27:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:27:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:27:27 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:27:27 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:27:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:27:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:27:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:27:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:27:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:27:27 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:27:28 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:27:28 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:27:29 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:27:29 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:27:30 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:27:30 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:27:31 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:27:31 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:27:32 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:27:32 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 05:27:33 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 05:27:33 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 05:27:34 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 05:27:34 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 05:27:34 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 05:27:35 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 05:27:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:27:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:27:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:27:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:27:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:27:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:27:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:27:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:27:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:27:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:27:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:27:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:27:35 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:27:35 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:27:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:27:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:27:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:27:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:27:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:27:35 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 05:27:36 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 05:27:36 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 05:27:37 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 05:27:37 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 05:27:38 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 05:27:38 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 05:27:39 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 05:27:39 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 05:27:40 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 05:27:40 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 05:27:41 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 05:27:41 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 05:27:41 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 05:27:42 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 05:27:42 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 05:27:43 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 05:27:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:27:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:27:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:27:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:27:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:27:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:27:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:27:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:27:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:27:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:27:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:27:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:27:43 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:27:43 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:27:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:27:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:27:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:27:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:27:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:27:43 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 05:27:44 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 05:27:44 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 05:27:45 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 05:27:45 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 05:27:46 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 05:27:46 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 05:27:47 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 05:27:47 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 05:27:48 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-10-30 05:27:48 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-10-30 05:27:49 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-10-30 05:27:49 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-10-30 05:27:49 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-10-30 05:27:50 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-10-30 05:27:50 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-10-30 05:27:51 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-10-30 05:27:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:27:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:27:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:27:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:27:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:27:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:27:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:27:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:27:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:27:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:27:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:27:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:27:51 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:27:51 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:27:51 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-10-30 05:27:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:27:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:27:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:27:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:27:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:27:52 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-10-30 05:27:52 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-10-30 05:27:53 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-10-30 05:27:53 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-10-30 05:27:54 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-10-30 05:27:54 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-10-30 05:27:55 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-10-30 05:27:55 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-10-30 05:27:56 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-10-30 05:27:56 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-10-30 05:27:56 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-10-30 05:27:57 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-10-30 05:27:57 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-10-30 05:27:58 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-10-30 05:27:58 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-10-30 05:27:59 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-10-30 05:27:59 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-10-30 05:27:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:27:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:27:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:27:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:27:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:27:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:27:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:27:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:27:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:27:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:27:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:27:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:27:59 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:27:59 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:27:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:27:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:27:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:27:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:27:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:28:00 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-10-30 05:28:00 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-10-30 05:28:01 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-10-30 05:28:01 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-10-30 05:28:02 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2024-10-30 05:28:02 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2024-10-30 05:28:03 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2024-10-30 05:28:03 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2024-10-30 05:28:04 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2024-10-30 05:28:04 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2024-10-30 05:28:04 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2024-10-30 05:28:05 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2024-10-30 05:28:05 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2024-10-30 05:28:06 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2024-10-30 05:28:06 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2024-10-30 05:28:07 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2024-10-30 05:28:07 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2024-10-30 05:28:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:28:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:28:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:28:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:28:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:28:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:28:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:28:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:28:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:28:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:28:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:28:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:28:07 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:28:07 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:28:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:28:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:28:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:28:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:28:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:28:08 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2024-10-30 05:28:08 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2024-10-30 05:28:09 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2024-10-30 05:28:09 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2024-10-30 05:28:10 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2024-10-30 05:28:10 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2024-10-30 05:28:11 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2024-10-30 05:28:11 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2024-10-30 05:28:12 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2024-10-30 05:28:12 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2024-10-30 05:28:12 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2024-10-30 05:28:13 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2024-10-30 05:28:13 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2024-10-30 05:28:14 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2024-10-30 05:28:14 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2024-10-30 05:28:15 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2024-10-30 05:28:15 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2024-10-30 05:28:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:28:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:28:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:28:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:28:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:28:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:28:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:28:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:28:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:28:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:28:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:28:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:28:16 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:28:16 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:28:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:28:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:28:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:28:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:28:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:28:16 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2024-10-30 05:28:16 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2024-10-30 05:28:17 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2024-10-30 05:28:17 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2024-10-30 05:28:18 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2024-10-30 05:28:18 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2024-10-30 05:28:19 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2024-10-30 05:28:19 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2024-10-30 05:28:19 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2024-10-30 05:28:20 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2024-10-30 05:28:20 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2024-10-30 05:28:21 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2024-10-30 05:28:21 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2024-10-30 05:28:22 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2024-10-30 05:28:22 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2024-10-30 05:28:23 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2024-10-30 05:28:23 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2024-10-30 05:28:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:28:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:28:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:28:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:28:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:28:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:28:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:28:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:28:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:28:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:28:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:28:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:28:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:28:24 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:28:24 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=14150 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:28:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:28:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:28:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:28:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:28:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:28:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:28:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:28:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:28:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:28:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:28:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:28:29 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:28:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:28:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:28:29 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:28:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:28:34 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:28:34 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:28:34 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:28:34 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:28:34 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:28:34 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:28:34 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:28:34 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:28:34 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:28:34 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:28:34 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:28:34 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:28:34 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:28:34 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:28:34 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:28:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:28:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:28:34 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:28:34 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:28:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:28:35 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:28:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:28:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:28:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:28:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:28:35 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:28:36 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:28:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:28:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:28:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:28:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:28:36 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:28:36 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:28:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:28:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:28:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:28:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:28:37 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:28:37 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:28:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:28:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:28:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:28:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:28:38 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:28:38 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:28:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:28:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:28:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:28:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:28:39 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:28:39 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:28:40 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:28:40 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:28:41 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:28:41 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:28:42 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:28:42 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:28:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:28:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:28:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:28:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:28:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:28:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:28:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:28:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:28:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:28:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:28:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:28:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:28:42 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:28:42 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:28:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:28:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:28:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:28:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:28:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:28:43 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:28:43 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:28:43 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:28:44 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:28:44 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:28:45 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:28:45 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:28:46 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:28:46 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:28:47 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:28:47 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 05:28:48 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 05:28:48 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 05:28:49 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 05:28:49 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 05:28:50 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 05:28:50 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 05:28:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:28:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:28:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:28:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:28:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:28:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:28:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:28:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:28:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:28:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:28:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:28:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:28:50 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:28:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:28:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:28:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:28:55 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:28:55 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:28:55 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:28:55 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:28:55 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:28:55 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:28:55 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:28:55 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:28:55 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:28:55 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:28:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:28:55 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:28:56 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:28:56 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:28:56 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:28:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:28:56 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:28:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:28:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:28:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:28:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:28:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:28:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:28:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:28:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:28:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:28:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:28:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:28:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:28:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:28:56 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:28:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:28:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:28:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:28:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:28:57 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:28:57 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:28:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:28:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:28:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:28:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:28:58 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:28:58 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:28:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:28:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:28:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:28:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:28:59 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:28:59 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:28:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:28:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:28:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:28:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:29:00 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:29:00 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:29:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:29:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:29:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:29:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:29:01 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:29:01 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:29:01 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:29:02 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:29:02 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:29:03 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:29:03 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:29:04 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:29:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:29:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:29:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:29:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:29:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:29:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:29:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:29:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:29:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:29:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:29:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:29:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:29:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:29:04 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:29:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:29:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:29:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:29:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:29:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:29:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:29:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:29:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:29:09 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:29:09 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:29:09 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:29:09 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:09 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:29:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:29:09 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:29:09 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:29:09 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:29:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:29:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:29:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:29:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:29:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:29:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:29:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:29:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:29:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:29:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:29:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:29:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:29:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:29:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:29:10 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:29:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:29:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:29:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:29:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:29:10 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:29:11 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:29:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:29:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:29:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:29:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:29:11 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:29:12 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:29:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:29:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:29:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:29:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:29:12 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:29:13 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:29:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:29:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:29:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:29:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:29:13 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:29:14 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:29:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:29:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:29:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:29:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:29:14 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:29:15 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:29:15 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:29:16 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:29:16 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:29:16 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:29:17 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:29:17 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:29:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:29:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:29:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:29:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:29:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:29:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:29:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:29:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:29:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:29:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:29:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:29:18 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:29:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:29:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:29:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:29:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:29:23 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:29:23 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:29:23 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:29:23 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:29:23 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:29:23 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:29:23 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:29:23 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:29:23 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:29:23 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:23 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:29:23 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:29:23 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:29:23 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:29:23 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:29:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:29:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:29:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:29:24 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:29:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:29:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:29:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:29:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:29:24 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:29:24 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:29:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:29:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:29:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:29:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:29:25 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:29:25 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:29:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:29:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:29:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:29:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:29:26 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:29:26 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:29:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:29:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:29:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:29:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:29:27 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:29:27 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:29:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:29:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:29:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:29:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:29:28 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:29:28 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:29:29 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:29:29 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:29:30 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:29:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:29:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:29:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:29:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:29:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:29:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:29:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:29:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:29:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:29:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:29:30 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:29:30 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1563 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:29:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:29:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:29:30 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1563 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:29:30 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1563 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:29:30 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1563 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:29:30 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1563 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:29:30 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1563 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:29:30 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1563 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:29:30 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1563 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:29:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:29:35 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:29:35 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:29:35 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:29:35 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:29:35 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:29:35 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:29:35 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:29:35 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:29:35 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:29:35 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:35 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:29:35 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:29:35 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:29:35 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:29:35 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:29:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:29:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:29:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:29:36 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:29:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:29:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:29:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:29:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:29:36 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:29:37 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:29:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:29:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:29:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:29:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:29:37 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:29:38 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:29:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:29:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:29:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:29:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:29:38 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:29:39 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:29:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:29:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:29:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:29:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:29:39 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:29:40 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:29:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:29:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:29:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:29:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:29:40 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:29:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:29:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:29:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:29:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:29:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:29:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:29:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:29:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:29:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:29:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:29:40 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1130 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:29:40 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1130 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:29:40 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:29:41 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:29:41 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:29:42 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:29:42 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:29:43 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:29:43 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:29:44 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:29:44 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:29:45 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:29:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:29:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:29:45 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:29:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:29:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:29:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:29:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:29:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:29:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:29:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:29:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:29:45 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:29:45 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:29:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:29:45 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:29:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:29:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:29:50 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:29:50 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:29:50 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:29:50 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:29:50 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:29:50 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:29:50 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:29:50 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:29:50 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:29:50 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:29:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:29:50 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:29:51 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:29:51 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:29:51 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:29:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:29:51 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:29:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:29:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:29:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:29:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:29:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:29:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:29:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:29:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:29:51 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:29:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:29:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:29:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:29:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:29:52 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:29:52 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:29:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:29:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:29:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:29:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:29:52 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:29:53 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:29:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:29:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:29:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:29:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:29:53 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:29:54 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:29:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:29:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:29:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:29:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:29:54 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:29:55 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:29:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:29:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:29:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:29:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:29:55 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:29:56 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:29:56 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:29:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:29:57 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:29:57 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:29:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:29:58 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:29:58 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:29:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:29:59 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:29:59 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:29:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:29:59 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:30:00 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:30:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:30:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:30:00 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:30:01 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:30:01 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:30:02 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:30:02 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:30:03 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:30:03 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:30:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:30:04 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 05:30:04 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 05:30:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:30:05 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 05:30:05 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 05:30:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:30:06 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 05:30:06 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 05:30:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:30:07 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 05:30:07 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 05:30:07 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 05:30:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:30:08 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 05:30:08 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 05:30:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:30:09 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 05:30:09 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 05:30:10 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 05:30:10 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 05:30:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:30:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:30:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:30:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:30:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:30:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:30:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:30:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:30:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:30:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:30:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:30:11 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:30:11 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4470 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:30:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:30:11 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4470 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:30:11 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4470 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:30:11 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4470 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:30:11 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4470 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:30:11 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4470 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:30:11 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4470 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:30:11 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4470 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:30:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:30:16 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:30:16 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:30:16 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:30:16 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:30:16 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:30:16 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:30:16 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:30:16 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:30:16 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:30:16 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:30:16 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:30:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:30:16 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:30:16 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:30:16 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:30:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:30:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:30:16 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:30:16 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD NOHANDOVER
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:30:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=130 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=131 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=132 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=133 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=134 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=135 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=136 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=137 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=138 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=139 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=140 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=141 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=143 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=144 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=145 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=146 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=147 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=148 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=149 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=150 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=151 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=152 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=153 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=154 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=156 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=157 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=158 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=159 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=160 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=161 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=162 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=163 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=164 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=165 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=166 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=167 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=169 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=170 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=171 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=172 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=173 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=174 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=175 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=176 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=177 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=178 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=179 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=180 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=182 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=183 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=184 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=185 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=186 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=187 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=188 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=189 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=190 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=191 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=192 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=193 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=195 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=196 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=197 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=198 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=199 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=200 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=201 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=202 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=203 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=204 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=205 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=206 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:30:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=208 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=209 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=210 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=211 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=212 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=213 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=214 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=215 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=216 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=217 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:30:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:30:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:30:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:30:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD NOHANDOVER
2024-10-30 05:30:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:30:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:30:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:30:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:30:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:30:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:30:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:30:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:30:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:30:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:30:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:30:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:30:17 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:30:17 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=301 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:30:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:30:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:30:22 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:30:22 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:30:22 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:30:22 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:30:22 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:30:22 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:30:22 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:30:22 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:30:22 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:30:22 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:30:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:30:22 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:30:23 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:30:23 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:30:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:30:23 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:30:23 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:30:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:30:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:30:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:30:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:30:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:30:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:30:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:30:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:30:23 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:30:23 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:30:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD NOHANDOVER
2024-10-30 05:30:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:30:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:30:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:30:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=130 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=131 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=132 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=133 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=134 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=135 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=136 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=137 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=138 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=139 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=140 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=141 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=143 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=144 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=145 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=146 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=147 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=148 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=149 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=150 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=151 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=152 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=153 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=154 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=156 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=157 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=158 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=159 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=160 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=161 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=162 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=163 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=164 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=165 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=166 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=167 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=169 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=170 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=171 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=172 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=173 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=174 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=175 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=176 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=177 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=178 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=179 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=180 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=182 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=183 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=184 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=185 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=186 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=187 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=188 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=189 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=190 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=191 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=192 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=193 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=195 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=196 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=197 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=198 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=199 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=200 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=201 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=202 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=203 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=204 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=205 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=206 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=208 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=209 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=210 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=211 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=212 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=213 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=214 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=215 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=216 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=217 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=218 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=219 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 05:30:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:30:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:30:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:30:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:30:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD NOHANDOVER
2024-10-30 05:30:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:30:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:30:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:30:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:30:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:30:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:30:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:30:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:30:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:30:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:30:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:30:23 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:30:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=301 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:30:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:30:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:30:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=301 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:30:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=301 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:30:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=301 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:30:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=301 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:30:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=301 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:30:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=301 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:30:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=301 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:30:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:30:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:30:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:30:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:30:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:30:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:30:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:30:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:30:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:30:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:30:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:30:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:30:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:30:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:30:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:30:29 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:30:29 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:30:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:30:29 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:30:29 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:30:29 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:30:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:30:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:30:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:30:29 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:30:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:30:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:30:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:30:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:30:30 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:30:30 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:30:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:30:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:30:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:30:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:30:31 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:30:31 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:30:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:30:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:30:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:30:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:30:32 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:30:32 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:30:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:30:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:30:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:30:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:30:33 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:30:33 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:30:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:30:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:30:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:30:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:30:34 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:30:34 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:30:35 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:30:35 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:30:36 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:30:36 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:30:37 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:30:37 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:30:37 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:30:38 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:30:38 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:30:39 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:30:39 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:30:40 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:30:40 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:30:41 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:30:41 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:30:42 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:30:42 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 05:30:43 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 05:30:43 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 05:30:44 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 05:30:44 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 05:30:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:30:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:30:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:30:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:30:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:30:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:30:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:30:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:30:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:30:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:30:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:30:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:30:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:30:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:30:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:30:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:30:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:30:44 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 05:30:45 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 05:30:45 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 05:30:46 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 05:30:46 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 05:30:47 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 05:30:47 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 05:30:48 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 05:30:48 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 05:30:49 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 05:30:49 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 05:30:50 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 05:30:50 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 05:30:51 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 05:30:51 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 05:30:52 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 05:30:52 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 05:30:52 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 05:30:53 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 05:30:53 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 05:30:54 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 05:30:54 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 05:30:55 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 05:30:55 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 05:30:56 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 05:30:56 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 05:30:57 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 05:30:57 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 05:30:58 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-10-30 05:30:58 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-10-30 05:30:59 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-10-30 05:30:59 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-10-30 05:31:00 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-10-30 05:31:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:31:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:31:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:31:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:31:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:31:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:31:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:31:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:31:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:31:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:31:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:31:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:31:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:31:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:31:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:31:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:31:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:31:00 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-10-30 05:31:00 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-10-30 05:31:01 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-10-30 05:31:01 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-10-30 05:31:02 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-10-30 05:31:02 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-10-30 05:31:03 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-10-30 05:31:03 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-10-30 05:31:04 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-10-30 05:31:04 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-10-30 05:31:05 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-10-30 05:31:05 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-10-30 05:31:06 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-10-30 05:31:06 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-10-30 05:31:07 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-10-30 05:31:07 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-10-30 05:31:07 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-10-30 05:31:08 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-10-30 05:31:08 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-10-30 05:31:09 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-10-30 05:31:09 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-10-30 05:31:10 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-10-30 05:31:10 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-10-30 05:31:11 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-10-30 05:31:11 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-10-30 05:31:12 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2024-10-30 05:31:12 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2024-10-30 05:31:13 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2024-10-30 05:31:13 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2024-10-30 05:31:14 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2024-10-30 05:31:14 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2024-10-30 05:31:15 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2024-10-30 05:31:15 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2024-10-30 05:31:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:31:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:31:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:31:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:31:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:31:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:31:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:31:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:31:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:31:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:31:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:31:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:31:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:31:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:31:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:31:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:31:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:31:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:31:15 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2024-10-30 05:31:16 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2024-10-30 05:31:16 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2024-10-30 05:31:17 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2024-10-30 05:31:17 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2024-10-30 05:31:18 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2024-10-30 05:31:18 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2024-10-30 05:31:19 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2024-10-30 05:31:19 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2024-10-30 05:31:20 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2024-10-30 05:31:20 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2024-10-30 05:31:21 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2024-10-30 05:31:21 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2024-10-30 05:31:22 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2024-10-30 05:31:22 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2024-10-30 05:31:22 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2024-10-30 05:31:23 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2024-10-30 05:31:23 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2024-10-30 05:31:24 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2024-10-30 05:31:24 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2024-10-30 05:31:25 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2024-10-30 05:31:25 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2024-10-30 05:31:26 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2024-10-30 05:31:26 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2024-10-30 05:31:27 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2024-10-30 05:31:27 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2024-10-30 05:31:28 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2024-10-30 05:31:28 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2024-10-30 05:31:29 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2024-10-30 05:31:29 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2024-10-30 05:31:30 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2024-10-30 05:31:30 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2024-10-30 05:31:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:31:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:31:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:31:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:31:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:31:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:31:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:31:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:31:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:31:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:31:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:31:30 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:31:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:31:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:31:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:31:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:31:35 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:31:35 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:31:35 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:31:35 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:31:35 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:31:35 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:31:35 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:31:35 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:31:35 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:31:35 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:31:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:31:35 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:31:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:31:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:31:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:31:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:31:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:31:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:31:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:31:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:31:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:31:40 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:31:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:31:40 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:31:40 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:31:40 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:31:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:31:40 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:31:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:31:40 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:31:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:31:40 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:31:40 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:31:40 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:31:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:31:40 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:31:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:31:40 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:31:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:31:40 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:31:40 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:31:40 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:31:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:31:40 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:31:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:31:40 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:31:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:31:40 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:31:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:31:41 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:31:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:31:41 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:31:41 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:31:41 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:31:41 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:31:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:31:41 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:31:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:31:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:31:41 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:31:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:31:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:31:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:31:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:31:42 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:31:42 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:31:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:31:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:31:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:31:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:31:43 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:31:43 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:31:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:31:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:31:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:31:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:31:44 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:31:44 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:31:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:31:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:31:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:31:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:31:45 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:31:45 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:31:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:31:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:31:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:31:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:31:46 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:31:46 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:31:47 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:31:47 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:31:48 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:31:48 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:31:48 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:31:49 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:31:49 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:31:50 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:31:50 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:31:51 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:31:51 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:31:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:31:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:31:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:31:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:31:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:31:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:31:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:31:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:31:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:31:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:31:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:31:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:31:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:31:51 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:31:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:31:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:31:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:31:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:31:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:31:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:31:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:31:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:31:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:31:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:31:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:31:56 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:31:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:31:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:31:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:31:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:31:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:31:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:31:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:31:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:31:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:31:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:31:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:31:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:31:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:31:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:31:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:31:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:31:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:31:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:31:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:31:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:31:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:31:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:31:57 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:31:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:31:57 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:31:57 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:31:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:31:57 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:31:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:31:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:31:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:31:57 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:31:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:31:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:31:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:31:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:31:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:31:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:31:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:31:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:31:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:31:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:31:57 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:31:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:31:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:31:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:31:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:31:58 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:31:58 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:31:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:31:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:31:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:31:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:31:59 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:31:59 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:32:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:32:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:32:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:32:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:32:00 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:32:00 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:32:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:32:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:32:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:32:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:32:01 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:32:01 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:32:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:32:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:32:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:32:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:32:02 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:32:02 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:32:03 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:32:03 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:32:04 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:32:04 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:32:04 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:32:05 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:32:05 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:32:06 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:32:06 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:32:07 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:32:07 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:32:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:32:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:32:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:32:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:32:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:32:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:32:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:32:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:32:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:32:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:32:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:32:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:32:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:32:07 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:32:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2382 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:32:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:32:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2382 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:32:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2382 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:32:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2382 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:32:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2382 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:32:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2382 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:32:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2382 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:32:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2382 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:32:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:32:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:32:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:32:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:32:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:32:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:32:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:32:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:32:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:32:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:32:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:32:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:32:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:32:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:32:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:32:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:32:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:32:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:32:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:32:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:32:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:32:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:32:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:32:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:32:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:32:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:32:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:32:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:32:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:32:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:32:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:32:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:32:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:32:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:32:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:32:13 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:32:13 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:32:13 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:32:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:32:13 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:32:13 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:32:13 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:32:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:32:13 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:32:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:32:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:32:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:32:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:32:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:32:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:32:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:32:14 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:32:14 [DEBUG] fake_trx.py:263 (MS@172.18.83.22:6700) Recv SETTA cmd
2024-10-30 05:32:14 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:32:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:32:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:32:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:32:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:32:15 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:32:15 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:32:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:32:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:32:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:32:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:32:16 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:32:16 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:32:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:32:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:32:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:32:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:32:17 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:32:17 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:32:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:32:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:32:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:32:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:32:18 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:32:18 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:32:19 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:32:19 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:32:20 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:32:20 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:32:21 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:32:21 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:32:21 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:32:22 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:32:22 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:32:23 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:32:23 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:32:24 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:32:24 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:32:25 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:32:25 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:32:26 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:32:26 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 05:32:27 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 05:32:27 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 05:32:28 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 05:32:28 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 05:32:28 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 05:32:29 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 05:32:29 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 05:32:30 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 05:32:30 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 05:32:31 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 05:32:31 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 05:32:32 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 05:32:32 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 05:32:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:32:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:32:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:32:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:32:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:32:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:32:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:32:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:32:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:32:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:32:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:32:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:32:33 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:32:33 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4382 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:32:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:32:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:32:33 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4382 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:32:33 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4382 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:32:33 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4382 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:32:33 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4382 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:32:33 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4382 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:32:33 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4382 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:32:33 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4382 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:32:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:32:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:32:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:32:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:32:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:32:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:32:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:32:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:32:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:32:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:32:38 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:32:38 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:32:38 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:32:38 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:32:38 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:32:38 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:32:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:32:38 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:32:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:32:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:32:39 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:32:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:32:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:32:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:32:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:32:39 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:32:40 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:32:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:32:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:32:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:32:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:32:40 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:32:41 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:32:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:32:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:32:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:32:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:32:41 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:32:41 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:32:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:32:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:32:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:32:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:32:42 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:32:42 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:32:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:32:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:32:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:32:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:32:43 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:32:43 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:32:44 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:32:44 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:32:45 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:32:45 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:32:46 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:32:46 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:32:47 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:32:47 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:32:48 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:32:48 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:32:49 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:32:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:32:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:32:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:32:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:32:49 [WARNING] transceiver.py:250 (MS@172.18.83.22:6700) RX TRXD message (fn=2381 tn=4 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:32:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:32:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:32:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:32:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:32:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:32:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:32:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:32:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:32:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:32:49 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:32:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:32:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:32:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:32:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:32:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:32:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:32:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:32:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:32:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:32:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:32:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:32:54 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:32:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:32:54 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:32:54 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:32:54 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:32:54 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:32:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:32:54 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:32:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:32:54 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:32:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:32:55 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:32:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:32:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:32:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:32:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:32:55 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:32:55 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:32:56 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:32:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:32:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:32:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:32:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:32:56 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:32:57 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:32:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:32:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:32:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:32:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:32:57 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:32:57 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:32:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:32:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:32:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:32:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:32:58 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:32:58 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:32:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:32:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:32:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:32:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:32:59 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:32:59 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:33:00 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:33:00 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:33:01 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:33:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:33:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:33:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:33:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:33:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:33:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:33:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:33:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:33:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:33:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:33:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:33:01 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:33:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:33:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:33:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:33:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:33:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:33:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:33:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:33:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:33:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:33:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:33:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:33:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:33:06 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:33:06 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:33:06 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:33:06 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:33:06 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:33:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:33:06 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:33:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:33:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:33:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:33:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:33:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:33:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:07 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:33:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:33:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:33:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:33:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:33:07 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:33:08 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:33:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:33:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:33:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:33:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:33:08 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:33:09 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:33:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:33:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:33:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:33:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:33:09 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:33:10 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:33:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:33:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:33:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:33:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:33:10 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:33:11 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:33:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:33:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:33:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:33:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:33:11 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:33:12 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:33:12 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:33:13 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:33:13 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:33:13 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:33:14 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:33:14 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:33:15 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:33:15 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:33:16 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:33:16 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:33:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:33:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:33:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:33:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:33:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:33:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:33:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:33:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:33:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:33:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:33:17 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:33:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:33:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:33:17 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2301 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:33:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:33:17 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2301 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:33:17 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2301 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:33:17 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2301 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:33:17 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2301 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:33:17 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2301 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:33:17 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2301 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:33:17 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2301 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:33:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:33:22 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:33:22 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:33:22 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:33:22 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:33:22 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:33:22 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:33:22 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:33:22 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:33:22 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:33:22 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:22 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:33:22 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:33:22 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:33:22 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:33:22 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:33:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:33:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:23 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:33:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:33:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:33:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:33:23 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:33:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:33:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:33:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:33:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:33:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:33:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:33:23 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:33:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:33:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:33:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:33:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:33:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:33:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:33:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:33:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:33:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:33:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:33:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:33:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:33:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:33:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:33:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:33:24 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:33:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:33:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:33:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:33:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:33:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:33:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:33:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:33:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:33:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:33:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:33:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:33:29 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:29 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:33:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:33:29 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:33:29 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:33:29 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:33:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:33:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:33:29 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:30 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:33:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:33:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:33:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:33:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:33:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:33:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:33:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:33:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:33:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:33:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:33:30 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:33:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:33:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:33:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:33:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:33:35 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:33:35 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:33:35 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:33:35 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:33:35 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:33:35 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:33:35 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:33:35 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:33:35 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:33:35 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:35 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:33:35 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:33:35 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:33:35 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:33:35 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:33:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:33:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:33:36 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:33:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:33:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:33:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:33:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:33:36 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:33:37 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:33:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:33:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:33:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:33:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:33:37 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:33:38 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:33:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:33:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:33:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:33:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:33:38 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:33:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:33:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:33:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:33:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:33:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:33:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:33:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:33:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:33:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:33:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:33:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:33:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:33:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:33:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:39 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:33:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:33:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:33:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:33:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:33:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:33:39 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:33:40 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:33:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:33:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:33:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:33:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:33:40 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:33:41 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:33:41 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:33:41 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:33:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:33:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:33:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:33:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:33:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:33:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:33:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:33:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:33:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:33:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:33:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:33:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:33:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:33:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:33:42 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:33:42 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:33:43 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:33:43 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:33:44 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:33:44 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:33:45 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:33:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:33:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:33:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:33:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:33:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:33:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:33:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:33:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:33:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:33:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:33:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:33:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:33:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:33:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:33:45 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:33:46 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:33:46 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:33:47 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:33:47 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:33:48 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:33:48 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:33:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:33:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:33:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:33:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:33:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:33:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:33:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:33:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:33:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:33:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:33:48 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:33:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:33:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:33:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:33:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:33:53 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:33:53 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:33:53 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:33:53 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:33:53 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:33:53 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:33:53 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:33:53 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:33:53 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:33:53 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:33:53 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:33:54 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:33:54 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:33:54 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:33:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:33:54 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:33:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:33:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:33:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:33:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:33:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:33:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:33:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:33:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:33:54 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:33:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:33:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:33:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:33:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:33:55 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:33:55 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:33:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:33:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:33:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:33:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:33:56 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:33:56 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:33:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:33:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:33:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:33:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:33:56 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:33:57 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:33:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:33:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:33:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:33:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:33:57 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:33:58 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:33:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:33:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:33:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:33:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:33:58 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:33:59 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:33:59 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:34:00 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:34:00 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:34:01 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:34:01 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:34:02 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:34:02 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:34:03 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:34:03 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:34:04 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:34:04 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:34:04 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:34:05 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:34:05 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:34:06 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:34:06 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:34:07 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 05:34:07 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 05:34:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:34:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:34:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:34:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:34:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:34:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:34:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:34:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:34:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:34:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:34:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:34:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:34:08 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:34:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:34:13 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:34:13 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:34:13 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:34:13 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:34:13 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:34:13 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:34:13 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:34:13 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:34:13 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:34:13 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:34:13 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:34:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:34:13 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:34:13 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:34:13 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:34:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:34:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:34:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:34:14 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:34:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:34:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:34:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:34:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:34:14 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:34:14 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:34:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:34:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:34:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:34:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:34:15 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:34:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:34:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:34:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:34:15 [WARNING] transceiver.py:250 (MS@172.18.83.22:6700) RX TRXD message (fn=560 tn=0 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:34:15 [WARNING] transceiver.py:250 (MS@172.18.83.22:6700) RX TRXD message (fn=560 tn=1 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:34:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:34:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:34:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:34:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:34:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:34:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:34:15 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:34:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:34:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:34:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:34:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:34:16 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:34:16 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:34:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:34:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:34:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:34:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:34:17 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:34:17 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:34:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:34:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:34:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:34:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:34:18 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:34:18 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:34:19 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:34:19 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:34:20 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:34:20 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:34:21 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:34:21 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:34:22 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:34:22 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:34:22 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:34:23 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:34:23 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:34:24 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:34:24 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:34:25 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:34:25 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:34:26 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:34:26 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 05:34:27 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 05:34:27 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 05:34:28 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 05:34:28 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 05:34:29 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 05:34:29 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 05:34:29 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 05:34:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:34:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:34:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:34:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:34:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:34:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:34:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:34:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:34:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:34:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:34:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:34:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:34:30 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:34:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:34:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:34:35 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:34:35 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:34:35 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:34:35 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:34:35 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:34:35 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:34:35 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:34:35 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:34:35 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:34:35 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:34:35 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:34:35 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:34:35 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:34:35 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:34:35 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:34:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:34:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:34:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:34:36 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:34:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:34:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:34:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:34:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:34:36 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:34:37 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:34:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:34:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:34:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:34:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:34:37 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:34:38 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:34:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:34:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:34:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:34:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:34:38 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:34:39 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:34:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:34:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:34:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:34:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:34:39 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:34:40 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:34:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:34:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:34:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:34:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:34:40 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:34:40 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:34:41 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:34:41 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:34:42 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:34:42 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:34:43 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:34:43 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:34:44 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:34:44 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:34:45 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:34:45 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:34:46 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:34:46 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:34:47 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:34:47 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:34:47 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:34:48 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:34:48 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 05:34:49 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 05:34:49 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 05:34:50 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 05:34:50 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 05:34:51 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 05:34:51 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 05:34:52 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 05:34:52 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 05:34:53 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 05:34:53 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 05:34:54 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 05:34:54 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 05:34:55 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 05:34:55 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 05:34:55 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 05:34:56 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 05:34:56 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 05:34:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:34:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:34:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:34:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:34:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:34:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:34:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:34:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:34:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:34:57 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:34:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:34:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:34:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:35:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:35:02 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:35:02 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:35:02 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:35:02 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:35:02 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:35:02 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:35:02 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:35:02 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:35:02 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:35:02 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:35:02 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:35:02 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:35:02 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:35:02 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:35:02 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:35:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:35:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:35:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:35:03 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:35:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:35:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:35:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:35:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:35:03 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:35:04 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:35:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:35:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:35:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:35:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:35:04 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:35:05 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:35:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:35:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:35:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:35:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:35:05 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:35:06 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:35:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:35:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:35:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:35:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:35:06 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:35:07 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:35:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:35:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:35:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:35:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:35:07 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:35:08 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:35:08 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:35:08 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:35:09 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:35:09 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:35:10 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:35:10 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:35:11 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:35:11 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:35:12 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:35:12 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:35:13 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:35:13 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:35:14 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:35:14 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:35:15 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:35:15 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:35:15 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 05:35:16 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 05:35:16 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 05:35:17 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 05:35:17 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 05:35:18 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 05:35:18 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 05:35:19 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 05:35:19 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 05:35:20 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 05:35:20 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 05:35:21 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 05:35:21 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 05:35:22 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 05:35:22 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 05:35:23 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 05:35:23 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 05:35:23 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 05:35:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:35:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:35:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:35:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:35:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:35:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:35:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:35:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:35:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:35:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:35:24 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:35:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:35:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:35:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:35:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:35:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:35:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:35:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:35:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:35:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:35:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:35:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:35:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:35:29 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:35:29 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:35:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:35:29 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:35:29 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:35:29 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:35:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:35:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:35:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:35:30 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:35:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:35:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:35:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:35:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:35:30 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:35:31 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:35:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:35:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:35:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:35:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:35:31 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:35:32 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:35:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:35:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:35:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:35:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:35:32 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:35:33 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:35:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:35:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:35:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:35:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:35:33 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:35:34 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:35:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:35:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:35:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:35:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:35:34 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:35:35 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:35:35 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:35:36 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:35:36 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:35:36 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:35:37 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:35:37 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:35:38 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:35:38 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:35:39 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:35:39 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:35:40 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:35:40 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:35:41 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:35:41 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:35:42 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:35:42 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:35:43 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 05:35:43 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 05:35:43 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 05:35:44 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 05:35:44 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 05:35:45 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 05:35:45 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 05:35:46 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 05:35:46 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 05:35:47 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 05:35:47 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 05:35:48 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 05:35:48 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 05:35:49 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 05:35:49 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 05:35:50 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 05:35:50 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 05:35:51 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 05:35:51 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 05:35:51 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 05:35:52 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 05:35:52 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 05:35:53 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 05:35:53 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 05:35:54 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 05:35:54 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 05:35:55 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 05:35:55 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 05:35:56 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 05:35:56 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 05:35:57 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 05:35:57 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 05:35:58 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 05:35:58 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-10-30 05:35:58 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-10-30 05:35:59 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-10-30 05:35:59 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-10-30 05:36:00 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-10-30 05:36:00 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-10-30 05:36:01 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-10-30 05:36:01 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-10-30 05:36:02 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-10-30 05:36:02 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-10-30 05:36:03 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-10-30 05:36:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:36:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:36:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:36:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:36:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:36:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:36:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:36:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:36:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:36:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:36:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:36:03 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:36:03 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=7399 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:36:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:36:03 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=7399 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:36:03 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=7399 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:36:03 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=7399 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:36:03 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=7399 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:36:03 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=7399 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:36:03 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=7399 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:36:03 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=7399 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:36:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:36:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:36:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:36:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:36:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:36:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:36:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:36:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:36:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:36:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:36:08 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:36:08 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:36:09 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:36:09 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:36:09 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:36:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:36:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:36:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:36:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:36:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:36:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:36:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:36:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:36:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:36:09 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:36:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:36:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:36:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:36:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:36:09 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:36:10 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:36:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:36:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:36:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:36:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:36:10 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:36:11 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:36:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:36:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:36:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:36:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:36:11 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:36:12 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:36:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:36:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:36:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:36:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:36:12 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:36:13 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:36:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:36:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:36:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:36:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:36:13 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:36:14 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:36:14 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:36:15 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:36:15 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:36:16 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:36:16 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:36:16 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:36:17 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:36:17 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:36:18 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:36:18 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:36:19 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:36:19 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:36:20 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:36:20 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:36:21 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:36:21 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:36:22 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 05:36:22 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 05:36:23 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 05:36:23 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 05:36:23 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 05:36:24 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 05:36:24 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 05:36:25 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 05:36:25 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 05:36:26 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 05:36:26 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 05:36:27 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 05:36:27 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 05:36:28 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 05:36:28 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 05:36:29 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 05:36:29 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 05:36:30 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 05:36:30 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 05:36:31 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 05:36:31 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 05:36:31 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 05:36:32 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 05:36:32 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 05:36:33 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 05:36:33 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 05:36:34 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 05:36:34 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 05:36:35 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 05:36:35 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 05:36:36 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 05:36:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:36:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:36:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:36:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:36:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:36:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:36:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:36:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:36:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:36:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:36:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:36:36 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:36:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:36:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:36:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:36:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:36:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:36:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:36:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:36:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:36:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:36:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:36:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:36:41 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:36:42 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:36:42 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:36:42 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:36:42 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:36:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:36:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:36:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:36:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:36:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:36:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:36:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:36:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:36:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:36:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:36:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:36:42 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:36:42 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:36:42 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:36:42 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:36:42 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:36:42 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:36:42 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:36:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:36:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:36:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:36:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:36:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:36:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:36:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:36:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:36:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:36:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:36:47 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:47 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:36:47 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:36:47 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:36:47 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:36:47 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:36:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:36:47 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:36:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:36:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:36:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:36:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:36:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:36:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:36:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:36:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:36:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:36:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:36:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:36:52 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:52 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:36:53 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:36:53 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:36:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:36:53 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:36:53 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:36:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:36:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:36:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:36:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:36:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:36:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:36:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:36:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:36:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:36:53 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:36:53 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:36:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:36:53 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:36:53 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:36:53 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:36:53 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:36:53 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:36:53 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:36:53 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:36:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:36:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:36:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:36:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:36:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:36:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:36:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:36:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:36:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:36:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:36:58 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:36:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:36:58 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:36:58 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:36:58 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:36:58 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:36:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:36:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:36:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:36:59 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:36:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:36:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:36:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:36:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:36:59 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:37:00 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:37:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:37:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:37:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:37:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:37:00 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:37:01 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:37:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:37:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:37:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:37:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:37:01 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:37:02 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:37:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:37:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:37:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:37:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:37:02 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:37:03 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:37:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:37:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:37:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:37:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:37:03 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:37:03 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:37:04 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:37:04 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:37:05 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:37:05 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:37:06 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:37:06 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:37:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:37:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:37:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:37:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:37:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:37:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:37:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:37:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:37:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:37:06 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:37:06 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:37:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:37:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:37:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:37:06 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:37:06 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:37:06 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:37:06 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:37:06 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:37:06 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:37:06 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:37:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:37:11 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:37:11 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:37:11 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:37:11 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:37:11 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:37:11 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:37:11 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:37:11 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:37:11 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:37:11 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:37:11 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:37:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:37:12 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:37:12 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:37:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:37:12 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:37:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:37:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:37:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:37:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:37:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:37:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:37:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:37:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:37:12 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:37:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:37:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:37:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:37:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:37:13 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:37:13 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:37:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:37:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:37:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:37:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:37:14 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:37:14 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:37:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:37:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:37:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:37:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:37:15 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:37:15 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:37:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:37:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:37:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:37:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:37:16 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:37:16 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:37:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:37:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:37:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:37:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:37:17 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:37:17 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:37:18 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:37:18 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:37:18 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:37:19 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:37:19 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:37:20 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:37:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:37:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:37:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:37:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:37:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:37:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:37:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:37:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:37:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:37:20 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:37:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:37:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:37:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:37:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:37:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:37:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:37:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:37:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:37:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:37:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:37:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:37:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:37:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:37:25 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:37:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:37:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:37:26 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:37:26 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:37:26 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:37:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:37:26 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:37:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:37:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:37:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:37:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:37:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:37:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:37:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:37:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:37:26 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:37:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:37:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:37:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:37:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:37:26 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:37:27 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:37:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:37:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:37:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:37:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:37:27 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:37:28 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:37:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:37:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:37:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:37:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:37:28 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:37:29 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:37:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:37:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:37:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:37:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:37:29 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:37:30 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:37:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:37:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:37:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:37:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:37:30 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:37:31 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:37:31 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:37:32 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:37:32 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:37:33 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:37:33 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:37:33 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:37:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:37:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:37:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:37:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:37:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:37:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:37:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:37:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:37:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:37:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:37:34 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:37:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:37:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:37:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:37:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:37:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:37:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:37:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:37:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:37:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:37:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:37:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:37:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:37:39 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:37:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:37:39 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:37:39 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:37:39 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:37:39 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:37:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:37:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:37:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:37:40 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:37:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:37:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:37:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:37:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:37:40 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:37:41 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:37:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:37:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:37:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:37:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:37:41 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:37:41 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:37:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:37:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:37:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:37:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:37:42 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:37:42 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:37:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:37:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:37:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:37:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:37:43 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:37:43 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:37:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:37:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:37:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:37:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:37:44 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:37:44 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:37:45 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:37:45 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:37:46 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:37:46 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:37:47 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:37:47 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:37:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:37:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:37:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:37:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:37:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:37:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:37:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:37:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:37:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:37:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:37:47 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:37:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:37:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:37:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:37:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:37:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:37:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:37:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:37:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:37:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:37:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:37:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:37:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:37:52 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:37:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:37:52 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:37:53 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:37:53 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:37:53 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:37:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:37:53 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:37:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:37:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:37:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:37:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:37:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:37:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:37:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:37:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:37:53 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:37:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:37:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:37:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:37:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:37:54 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:37:54 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:37:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:37:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:37:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:37:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:37:55 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:37:55 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:37:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:37:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:37:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:37:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:37:56 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:37:56 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:37:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:37:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:37:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:37:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:37:56 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:37:57 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:37:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:37:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:37:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:37:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:37:57 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:37:58 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:37:58 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:37:59 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:37:59 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:38:00 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:38:00 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:38:01 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:38:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:38:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:38:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:38:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:38:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:38:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:38:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:38:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:38:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:38:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:38:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:38:01 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:38:01 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:38:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:38:01 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:38:01 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:38:01 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:38:01 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:38:01 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:38:01 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:38:01 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:38:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:38:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:38:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:38:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:38:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:38:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:38:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:38:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:38:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:38:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:38:06 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:38:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:38:06 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:38:06 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:38:06 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:38:06 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:38:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:38:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:38:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:38:07 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:38:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:38:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:38:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:38:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:38:07 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:38:08 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:38:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:38:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:38:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:38:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:38:08 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:38:09 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:38:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:38:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:38:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:38:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:38:09 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:38:10 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:38:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:38:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:38:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:38:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:38:10 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:38:11 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:38:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:38:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:38:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:38:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:38:11 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:38:12 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:38:12 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:38:12 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:38:13 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:38:13 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:38:14 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:38:14 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:38:15 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:38:15 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:38:16 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:38:16 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:38:17 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:38:17 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:38:18 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:38:18 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:38:19 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:38:19 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:38:19 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 05:38:20 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 05:38:20 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 05:38:21 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 05:38:21 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 05:38:22 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 05:38:22 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 05:38:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:38:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:38:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:38:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:38:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:38:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:38:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:38:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:38:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:38:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:38:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:38:22 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:38:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:38:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:38:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:38:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:38:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:38:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:38:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:38:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:38:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:38:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:38:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:38:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:38:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:38:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:38:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:38:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:38:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:38:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:38:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:38:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:38:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:38:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:38:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:38:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:38:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:38:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:38:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:38:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:38:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:38:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:38:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:38:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:38:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:38:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:38:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:38:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:38:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:38:28 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:38:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:38:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:38:28 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:38:28 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:38:28 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:38:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:38:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:38:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:38:28 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:38:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:38:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:38:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:38:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:38:29 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:38:29 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:38:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:38:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:38:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:38:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:38:30 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:38:30 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:38:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:38:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:38:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:38:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:38:31 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:38:31 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:38:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:38:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:38:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:38:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:38:32 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:38:32 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:38:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:38:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:38:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:38:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:38:33 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:38:33 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:38:34 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:38:34 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:38:35 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:38:35 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:38:35 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:38:36 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:38:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:38:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:38:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:38:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:38:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:38:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:38:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:38:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:38:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:38:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:38:36 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:38:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:38:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:38:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:38:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:38:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:38:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:38:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:38:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:38:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:38:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:38:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:38:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:38:41 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:38:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:38:42 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:38:42 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:38:42 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:38:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:38:42 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:38:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:38:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:38:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:38:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:38:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:38:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:38:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:38:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:38:42 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:38:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:38:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:38:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:38:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:38:43 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:38:43 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:38:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:38:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:38:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:38:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:38:43 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:38:44 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:38:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:38:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:38:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:38:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:38:44 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:38:45 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:38:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:38:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:38:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:38:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:38:45 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:38:46 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:38:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:38:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:38:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:38:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:38:46 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:38:47 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:38:47 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:38:48 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:38:48 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:38:49 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:38:49 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:38:50 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:38:50 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:38:51 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:38:51 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:38:51 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:38:52 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:38:52 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:38:53 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:38:53 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:38:54 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:38:54 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:38:55 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 05:38:55 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 05:38:56 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 05:38:56 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 05:38:57 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 05:38:57 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 05:38:58 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 05:38:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:38:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:38:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:38:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:38:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:38:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:38:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:38:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:38:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:38:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:38:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:38:58 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:38:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:39:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:39:03 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:39:03 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:39:03 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:39:03 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:39:03 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:39:03 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:39:03 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:39:03 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:39:03 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:39:03 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:03 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:39:03 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:39:03 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:39:03 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:39:03 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:39:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:39:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:39:03 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:39:03 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=121 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:39:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:39:03 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=121 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:39:03 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=121 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:39:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:39:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:39:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:39:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:39:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:39:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:39:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:39:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:39:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:39:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:39:08 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:39:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:39:09 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:39:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:39:09 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:39:09 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:39:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:39:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:39:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:39:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:39:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:39:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:39:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:39:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:39:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:39:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:39:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:39:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:39:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:39:09 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:39:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:39:14 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:39:14 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:39:14 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:39:14 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:39:14 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:39:14 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:39:14 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:39:14 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:39:14 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:39:14 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:14 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:39:14 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:39:14 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:39:14 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:39:14 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:39:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:39:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:39:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:39:14 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:39:14 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:39:14 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:39:14 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:39:14 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:39:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:39:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:39:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:39:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:39:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:39:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:39:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:39:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:39:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:39:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:39:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:39:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:39:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:39:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:39:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:39:20 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:20 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:39:20 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:39:20 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:39:20 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:39:20 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:39:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:39:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:39:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:39:20 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:39:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:39:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:39:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:39:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:39:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:39:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:39:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:39:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:39:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:39:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:39:25 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:39:26 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:39:26 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:39:26 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:39:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:39:26 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:39:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:39:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:39:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:39:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:39:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:39:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:39:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:39:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:39:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:39:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:39:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:39:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:39:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:39:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:39:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:39:26 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:39:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:39:26 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=125 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:39:26 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:39:26 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:39:26 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:39:26 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:39:26 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:39:26 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:39:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:39:31 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:39:31 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:39:31 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:39:31 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:39:31 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:39:31 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:39:31 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:39:31 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:39:31 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:39:31 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:31 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:39:31 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:39:31 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:39:31 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:39:31 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:39:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:39:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:39:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:39:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:39:31 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:39:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:39:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:39:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:39:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:39:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:39:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:39:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:39:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:39:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:39:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:39:36 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:39:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:39:36 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:39:37 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:39:37 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:39:37 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:39:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:39:37 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:39:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:39:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:39:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:39:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:39:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:39:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:39:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:39:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:39:37 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:39:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:39:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:39:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:39:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:39:38 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:39:38 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:39:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:39:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:39:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:39:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:39:39 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:39:39 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:39:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:39:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:39:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:39:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:39:40 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:39:40 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:39:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:39:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:39:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:39:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:39:41 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:39:41 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:39:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:39:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:39:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:39:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:39:42 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:39:42 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:39:42 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:39:43 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:39:43 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:39:44 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:39:44 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:39:45 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:39:45 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:39:46 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:39:46 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:39:47 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:39:47 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:39:48 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:39:48 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:39:49 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:39:49 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:39:50 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:39:50 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 05:39:50 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 05:39:51 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 05:39:51 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 05:39:52 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 05:39:52 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 05:39:53 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 05:39:53 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 05:39:54 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 05:39:54 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 05:39:55 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 05:39:55 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 05:39:56 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 05:39:56 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 05:39:57 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 05:39:57 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 05:39:57 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 05:39:58 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 05:39:58 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 05:39:59 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 05:39:59 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 05:40:00 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 05:40:00 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 05:40:01 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 05:40:01 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 05:40:02 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 05:40:02 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 05:40:03 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 05:40:03 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 05:40:04 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 05:40:04 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 05:40:05 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 05:40:05 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 05:40:05 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-10-30 05:40:06 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-10-30 05:40:06 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-10-30 05:40:07 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-10-30 05:40:07 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-10-30 05:40:08 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-10-30 05:40:08 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-10-30 05:40:09 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-10-30 05:40:09 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-10-30 05:40:10 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-10-30 05:40:10 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-10-30 05:40:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:40:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:40:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:40:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:40:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:40:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:40:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:40:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:40:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:40:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:40:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:40:10 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:40:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:40:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:40:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:40:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:40:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:40:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:40:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:40:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:40:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:40:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:40:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:40:15 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:15 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:40:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:40:16 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:40:16 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:40:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:40:16 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:40:16 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:40:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:40:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:40:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:40:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:40:17 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:40:17 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:40:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:40:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:40:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:40:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:40:18 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:40:18 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:40:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:40:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:40:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:40:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:40:19 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:40:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:40:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:40:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:40:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:40:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:40:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:40:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:40:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:40:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:40:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:40:19 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:40:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:40:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:40:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:40:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:40:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:40:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:40:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:40:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:40:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:40:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:40:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:40:24 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:24 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:40:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:40:25 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:40:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:40:25 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:40:25 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:40:25 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:40:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:40:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:40:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:40:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:40:25 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:40:26 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:40:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:40:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:40:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:40:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:40:26 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:40:27 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:40:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:40:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:40:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:40:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:40:27 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:40:28 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:40:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:40:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:40:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:40:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:40:28 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:40:29 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:40:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:40:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:40:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:40:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:40:29 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:40:30 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:40:30 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:40:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:40:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:40:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:40:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:40:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:40:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:40:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:40:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:40:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:40:31 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:40:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:40:31 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1416 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:40:31 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1416 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:40:31 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1416 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:40:31 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1416 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:40:31 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1416 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:40:31 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1416 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:40:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:40:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:40:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:40:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:40:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:40:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:40:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:40:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:40:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:40:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:40:36 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:36 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:40:36 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:40:36 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:40:36 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:40:36 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:40:37 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:40:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:40:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:40:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:40:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:40:37 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:40:37 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:40:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:40:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:40:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:40:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:40:38 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:40:38 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:40:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:40:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:40:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:40:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:40:39 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:40:39 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:40:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:40:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:40:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:40:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:40:40 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:40:40 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:40:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:40:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:40:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:40:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:40:41 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:40:41 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:40:42 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:40:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:40:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:40:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:40:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:40:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:40:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:40:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:40:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:40:42 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:40:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:40:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:40:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:40:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:40:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:40:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:40:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:40:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:40:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:40:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:40:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:40:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:40:47 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:47 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:40:48 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:40:48 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:40:48 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:40:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:40:48 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:40:48 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:40:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:40:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:40:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:40:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:40:49 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:40:49 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:40:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:40:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:40:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:40:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:40:50 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:40:50 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:40:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:40:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:40:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:40:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:40:50 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:40:51 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:40:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:40:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:40:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:40:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:40:51 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:40:52 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:40:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:40:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:40:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:40:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:40:52 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:40:53 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:40:53 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:40:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:40:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:40:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:40:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:40:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:40:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:40:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:40:54 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:40:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:40:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:40:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:40:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:40:59 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:40:59 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:40:59 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:40:59 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:40:59 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:40:59 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:40:59 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:40:59 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:40:59 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:40:59 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:40:59 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:40:59 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:40:59 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:40:59 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:40:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:40:59 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:41:00 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:41:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:41:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:41:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:41:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:41:00 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:41:01 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:41:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:41:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:41:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:41:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:41:01 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:41:02 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:41:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:41:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:41:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:41:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:41:02 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:41:03 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:41:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:41:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:41:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:41:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:41:03 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:41:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:41:03 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:41:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:41:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:41:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:41:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:41:04 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:41:04 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:41:05 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:41:05 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:41:06 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:41:06 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:41:07 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:41:07 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:41:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:41:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:41:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:41:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:41:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:41:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:41:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:41:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:41:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:41:07 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:41:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:41:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:41:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:41:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:41:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:41:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:41:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:41:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:41:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:41:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:41:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:41:12 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:41:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:41:13 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:41:13 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:41:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:41:13 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:41:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:41:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:41:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:41:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:41:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:41:14 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:41:14 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:41:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:41:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:41:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:41:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:41:15 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:41:15 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:41:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:41:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:41:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:41:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:41:16 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:41:16 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:41:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:41:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:41:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:41:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:41:17 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:41:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:41:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:41:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:41:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:41:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:41:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:41:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:41:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:41:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:41:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:41:17 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:41:17 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=987 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:17 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=987 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:17 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=987 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:17 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=987 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:17 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=987 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:17 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=987 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:41:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:41:22 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:41:22 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:41:22 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:41:22 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:41:22 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:41:22 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:41:22 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:41:22 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:41:22 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:41:22 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:22 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:41:22 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:41:22 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:41:22 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:41:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:41:22 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:41:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:41:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:41:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:41:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:41:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:41:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:41:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:41:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:41:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:41:23 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:41:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:41:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:41:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:41:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:41:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:41:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:41:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:41:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:41:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:41:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:41:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:41:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:41:28 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:41:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:41:28 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:41:28 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:41:28 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:41:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:41:28 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:41:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:41:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=120 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=120 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=120 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=120 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=120 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=120 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=120 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=120 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:41:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:41:33 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:41:33 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:41:33 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:41:33 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:41:33 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:41:33 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:41:33 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:41:33 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:41:33 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:41:33 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:33 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:41:34 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:41:34 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:41:34 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:41:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:41:34 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:41:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:41:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:41:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:41:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:41:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:41:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:41:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:41:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:41:34 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:41:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:41:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:41:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=119 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=119 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=119 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=119 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=119 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=119 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=119 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=119 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:41:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:41:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:41:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:41:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:41:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:41:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:41:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:41:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:41:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:41:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:41:39 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:41:39 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:41:39 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:41:39 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:41:39 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:41:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:41:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:41:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:41:40 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:41:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:41:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:41:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:41:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:41:40 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:41:41 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:41:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:41:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:41:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:41:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:41:41 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:41:42 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:41:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:41:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:41:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:41:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:41:42 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:41:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:41:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:41:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:41:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:41:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:41:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:41:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:41:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:41:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:41:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:41:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:41:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:41:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:41:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:41:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:41:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:41:42 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:41:42 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=789 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:41:42 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=789 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:42 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=789 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:42 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=789 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:42 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=789 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:42 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=789 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:41:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:41:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:41:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:41:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:41:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:41:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:41:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:41:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:41:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:41:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:41:47 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:47 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:41:48 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:41:48 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:41:48 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:41:48 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:41:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:41:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:41:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:41:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:41:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:41:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:41:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:41:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:41:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:41:48 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:41:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:41:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:41:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:41:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:41:49 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:41:49 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:41:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:41:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:41:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:41:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:41:50 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:41:50 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:41:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:41:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:41:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:41:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:41:51 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:41:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:41:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:41:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:41:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:41:51 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:41:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:41:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:41:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:41:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:41:52 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:41:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:41:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:41:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:41:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:41:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:41:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:41:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:41:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:41:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:41:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:41:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:41:52 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:41:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:41:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:41:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:41:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:41:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:41:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:41:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:41:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:41:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:41:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:41:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:41:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:41:57 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:41:57 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:41:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:41:57 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:41:57 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:41:57 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:41:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:41:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:41:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:41:58 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:41:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:41:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:41:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:41:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:41:58 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:41:59 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:41:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:41:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:41:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:41:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:41:59 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:41:59 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:42:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:42:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:42:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:42:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:42:00 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:42:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:42:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:42:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:42:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:42:00 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:42:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:42:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:42:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:42:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:42:01 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:42:01 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:42:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:42:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:42:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:42:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:42:02 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:42:02 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:42:03 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:42:03 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:42:04 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:42:04 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:42:05 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:42:05 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:42:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:42:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:42:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:42:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:42:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:42:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:42:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:42:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:42:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:42:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:42:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:42:05 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:42:05 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1867 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:42:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:42:05 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1867 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:42:05 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1867 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:42:05 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1867 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:42:05 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1867 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:42:05 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1868 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:42:05 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1868 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:42:05 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1868 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:42:05 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1868 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:42:05 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1868 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:42:05 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1868 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:42:05 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1868 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:42:05 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1868 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:42:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:42:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:42:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:42:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:42:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:42:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:42:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:42:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:42:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:42:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:42:10 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:42:11 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:42:11 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:42:11 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:42:11 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:42:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:42:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:42:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:42:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:42:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:42:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:42:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:42:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:42:11 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:42:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:42:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:42:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:42:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:42:12 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:42:12 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:42:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:42:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:42:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:42:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:42:13 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:42:13 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:42:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:42:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:42:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:42:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:42:14 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:42:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:42:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:42:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:42:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:42:14 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:42:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:42:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:42:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:42:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:42:15 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:42:15 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:42:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:42:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:42:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:42:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:42:15 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:42:16 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:42:16 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:42:17 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:42:17 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:42:18 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:42:18 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:42:19 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:42:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:42:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:42:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:42:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:42:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:42:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:42:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:42:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:42:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:42:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:42:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:42:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:42:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:42:19 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:42:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1869 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:42:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1869 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:42:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1869 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:42:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1869 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:42:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1869 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:42:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1869 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:42:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:42:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:42:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:42:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:42:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:42:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:42:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:42:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:42:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:42:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:42:24 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:24 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:42:24 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:42:24 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:42:24 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:42:24 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:42:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:42:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:42:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:42:25 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:42:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:42:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:42:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:42:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:42:25 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:42:26 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:42:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:42:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:42:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:42:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:42:26 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:42:27 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:42:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:42:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:42:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:42:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:42:27 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:42:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:42:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:42:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:42:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:42:28 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:42:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:42:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:42:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:42:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:42:28 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:42:29 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:42:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:42:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:42:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:42:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:42:29 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:42:30 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:42:30 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:42:31 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:42:31 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:42:31 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:42:32 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:42:32 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:42:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:42:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:42:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:42:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:42:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:42:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:42:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:42:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:42:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:42:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:42:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:42:33 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:42:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:42:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:42:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:42:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:42:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:42:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:42:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:42:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:42:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:42:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:42:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:42:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:42:38 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:38 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:42:38 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:42:38 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:42:38 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:42:38 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:42:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:42:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:42:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:42:39 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:42:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:42:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:42:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:42:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:42:39 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:42:39 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:42:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:42:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:42:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:42:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:42:40 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:42:40 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:42:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:42:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:42:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:42:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:42:41 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:42:41 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:42:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:42:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:42:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:42:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:42:42 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:42:42 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:42:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:42:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:42:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:42:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:42:43 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:42:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:42:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:42:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:42:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:42:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:42:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:42:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:42:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:42:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:42:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:42:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:42:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:42:43 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:42:43 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1213 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:42:43 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1213 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:42:43 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1213 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:42:43 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1213 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:42:43 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1213 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:42:43 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1213 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:42:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:42:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:42:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:42:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:42:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:42:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:42:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:42:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:42:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:42:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:42:48 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:42:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:42:49 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:42:49 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:42:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:42:49 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:42:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:42:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:42:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:42:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:42:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:42:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:42:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:42:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:42:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:42:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:42:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:42:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:42:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:42:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:42:50 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:42:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:42:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:42:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:42:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:42:51 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:42:51 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:42:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:42:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:42:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:42:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:42:51 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:42:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:42:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:42:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:42:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:42:52 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:42:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:42:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:42:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:42:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:42:52 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:42:53 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:42:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:42:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:42:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:42:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:42:53 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:42:54 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:42:54 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:42:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:42:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:42:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:42:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:42:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:42:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:42:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:42:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:42:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:42:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:42:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:42:54 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:42:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:42:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:42:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:42:59 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:42:59 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:42:59 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:42:59 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:42:59 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:42:59 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:42:59 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:42:59 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:42:59 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:42:59 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:42:59 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:43:00 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:43:00 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:43:00 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:43:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:43:00 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:43:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:43:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:43:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:43:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:43:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:43:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:43:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:43:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:43:00 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:43:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:43:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:43:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:43:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:43:01 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:43:01 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:43:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:43:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:43:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:43:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:43:02 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:43:02 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:43:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:43:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:43:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:43:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:43:03 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:43:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:43:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:43:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:43:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:43:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:43:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:43:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:43:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:43:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:43:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:43:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:43:03 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:43:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:43:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:43:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:43:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:43:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:43:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:43:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:43:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:43:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:43:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:43:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:43:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:43:08 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:43:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:43:09 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:43:09 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:43:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:43:09 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:43:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:43:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:43:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:43:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:43:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:43:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:43:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:43:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:43:09 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:43:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:43:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:43:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:43:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:43:09 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:43:10 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:43:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:43:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:43:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:43:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:43:10 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:43:11 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:43:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:43:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:43:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:43:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:43:11 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:43:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:43:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:43:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:43:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:43:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:43:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:43:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:43:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:43:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:43:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:43:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:43:12 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:43:12 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=785 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:43:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:43:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:43:12 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=785 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:43:12 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=785 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:43:12 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=785 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:43:12 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=785 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:43:12 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=785 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:43:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:43:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:43:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:43:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:43:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:43:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:43:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:43:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:43:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:43:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:43:17 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:17 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:43:17 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:43:17 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:43:17 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:43:17 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:43:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:43:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:43:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:43:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:43:17 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:43:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:43:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:43:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:43:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:43:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:43:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:43:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:43:23 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:43:23 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:43:23 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:43:23 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:43:23 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:43:23 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:43:23 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:43:23 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:43:23 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:43:23 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:23 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:43:23 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:43:23 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:43:23 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:43:23 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:43:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:43:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:43:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:43:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:43:23 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:43:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=163 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:43:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:43:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=163 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:43:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=163 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:43:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=163 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:43:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=164 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:43:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=164 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:43:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=164 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:43:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=164 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:43:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=164 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:43:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=164 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:43:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=164 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:43:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=164 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:43:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:43:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:43:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:43:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:43:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:43:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:43:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:43:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:43:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:43:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:43:28 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:43:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:43:29 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:43:29 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:43:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:43:29 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:43:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:43:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:43:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:43:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:43:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:43:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:43:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:43:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:43:29 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:43:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:43:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:43:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:43:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:43:30 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:43:30 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:43:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:43:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:43:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:43:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:43:31 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:43:31 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:43:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:43:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:43:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:43:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:43:32 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:43:32 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:43:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:43:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:43:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:43:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:43:33 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:43:33 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:43:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:43:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:43:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:43:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:43:33 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:43:34 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:43:34 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:43:35 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:43:35 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:43:36 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:43:36 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:43:37 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:43:37 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:43:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:43:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:43:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:43:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:43:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:43:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:43:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:43:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:43:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:43:38 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:43:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:43:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:43:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:43:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:43:43 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:43:43 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:43:43 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:43:43 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:43:43 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:43:43 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:43:43 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:43:43 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:43:43 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:43:43 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:43 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:43:43 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:43:43 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:43:43 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:43:43 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:43:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:43:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:43:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:43:44 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:43:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:43:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:43:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:43:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:43:44 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:43:45 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:43:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:43:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:43:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:43:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:43:45 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:43:45 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:43:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:43:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:43:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:43:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:43:46 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:43:46 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:43:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:43:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:43:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:43:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:43:47 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:43:47 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:43:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:43:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:43:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:43:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:43:48 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:43:48 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:43:49 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:43:49 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:43:50 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:43:50 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:43:51 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:43:51 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:43:52 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:43:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:43:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:43:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:43:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:43:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:43:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:43:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:43:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:43:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:43:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:43:52 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:43:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:43:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:43:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:43:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:43:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:43:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:43:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:43:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:43:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:43:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:43:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:43:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:43:57 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:43:57 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:43:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:43:57 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:43:57 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:43:57 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:43:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:43:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:43:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:43:58 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:43:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:43:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:43:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:43:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:43:58 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:43:59 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:43:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:43:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:43:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:43:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:43:59 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:44:00 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:44:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:44:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:44:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:44:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:44:00 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:44:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:44:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:44:01 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:44:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:44:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:44:01 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:44:01 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:44:01 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:44:01 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:44:01 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:44:01 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:44:01 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:44:01 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:44:01 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:44:01 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:44:01 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:44:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:44:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:44:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:44:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:44:01 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:44:01 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:44:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:44:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:44:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:44:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:44:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:44:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:44:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:44:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:44:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:44:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:44:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:44:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:44:01 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:44:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:44:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:44:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:44:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:44:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:44:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:44:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:44:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:44:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:44:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:44:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:44:06 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:44:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:44:07 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:44:07 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:44:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:44:07 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:44:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:44:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:44:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:44:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:44:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:44:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:44:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:44:07 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:44:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:44:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:44:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:44:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=142 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=142 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=142 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=142 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=142 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=142 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=142 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=142 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:44:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:44:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:44:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:44:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:44:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:44:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:44:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:44:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:44:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:44:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:44:12 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:44:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:44:12 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:44:12 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:44:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:44:12 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:44:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:44:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:44:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:44:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:44:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:44:13 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:44:14 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:44:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:44:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:44:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:44:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:44:14 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:44:15 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:44:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:44:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:44:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:44:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:44:15 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:44:16 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:44:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:44:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:44:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:44:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:44:16 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:44:16 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:44:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:44:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:44:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:44:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:44:17 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:44:17 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:44:18 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:44:18 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:44:19 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:44:19 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:44:20 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:44:20 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:44:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:44:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:44:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:44:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:44:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:44:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:44:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:44:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:44:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:44:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:44:20 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:44:20 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1859 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:44:20 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1859 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:20 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1859 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:20 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1859 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:20 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1859 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:20 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1859 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:44:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:44:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:44:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:44:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:44:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:44:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:44:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:44:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:44:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:44:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:44:25 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:44:26 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:44:26 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:44:26 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:44:26 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:44:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:44:26 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:44:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:44:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:44:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:44:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:44:27 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:44:27 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:44:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:44:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:44:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:44:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:44:28 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:44:28 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:44:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:44:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:44:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:44:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:44:29 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:44:29 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:44:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:44:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:44:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:44:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:44:30 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:44:30 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:44:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:44:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:44:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:44:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:44:31 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:44:31 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:44:31 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:44:32 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:44:32 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:44:33 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:44:33 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:44:34 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:44:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:44:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:44:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:44:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:44:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:44:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:44:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:44:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:44:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:44:34 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:44:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:44:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1857 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:44:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1857 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1857 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1857 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1857 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1857 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1857 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1857 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:44:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:44:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:44:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:44:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:44:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:44:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:44:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:44:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:44:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:44:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:44:39 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:44:39 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:44:39 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:44:39 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:44:39 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:44:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:44:40 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:44:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:44:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:44:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:44:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:44:40 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:44:41 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:44:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:44:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:44:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:44:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:44:41 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:44:42 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:44:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:44:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:44:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:44:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:44:42 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:44:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:44:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:44:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:44:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:44:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:44:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:44:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:44:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:44:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:44:43 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:44:43 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=778 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:44:43 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=778 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:43 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=778 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:43 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=778 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:43 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=778 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:43 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=778 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:43 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=778 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:43 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=778 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:44:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:44:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:44:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:44:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:44:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:44:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:44:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:44:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:44:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:44:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:44:48 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:44:48 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:44:48 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:44:48 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:44:48 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:44:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:44:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:44:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:44:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:44:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:44:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:44:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:44:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:44:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:44:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:44:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:44:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:44:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:44:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:44:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:44:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:44:49 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:44:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=210 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:44:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:44:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=210 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=210 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=210 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=210 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=210 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=210 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=210 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:44:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:44:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:44:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:44:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:44:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:44:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:44:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:44:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:44:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:44:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:44:54 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:44:54 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:44:54 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:44:54 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:44:54 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:44:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:44:54 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:44:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:44:54 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=117 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:54 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=117 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:54 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:54 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:54 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:54 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:54 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:54 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:44:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:44:59 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:44:59 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:44:59 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:44:59 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:44:59 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:44:59 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:44:59 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:44:59 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:44:59 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:44:59 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:44:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:44:59 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:45:00 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:45:00 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:45:00 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:45:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:45:00 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:45:00 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:45:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:45:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:45:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:45:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:45:01 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:45:01 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:45:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:45:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:45:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:45:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:45:01 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:45:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:45:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:45:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:45:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:45:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:45:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:45:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:45:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:45:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:45:02 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:45:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:45:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:45:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:45:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:45:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:45:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:45:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:45:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:45:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:45:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:45:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:45:07 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:07 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:45:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:45:07 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:45:07 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:45:07 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:45:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:45:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:45:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:45:08 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:45:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:45:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:45:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:45:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:45:08 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:45:09 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:45:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:45:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:45:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:45:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:45:09 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:45:10 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:45:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:45:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:45:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:45:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:45:10 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:45:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:45:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:45:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:45:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:45:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:45:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:45:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:45:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:45:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:45:10 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:45:10 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=720 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:45:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:45:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:45:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:45:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:45:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:45:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:45:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:45:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:45:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:45:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:45:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:45:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:45:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:45:15 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:15 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:45:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:45:16 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:45:16 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:45:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:45:16 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:45:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:45:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:45:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:45:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:45:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:45:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:45:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:45:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:45:16 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:45:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:45:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:45:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:45:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:45:16 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:45:17 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:45:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:45:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:45:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:45:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:45:17 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:45:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:45:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:45:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:45:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:45:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:45:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:45:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:45:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:45:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:45:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:45:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:45:18 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:45:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:45:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:45:23 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:45:23 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:45:23 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:45:23 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:45:23 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:45:23 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:45:23 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:45:23 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:45:23 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:45:23 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:23 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:45:23 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:45:23 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:45:23 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:45:23 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:45:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:45:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:45:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:45:24 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:45:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:45:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:45:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:45:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:45:24 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:45:25 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:45:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:45:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:45:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:45:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:45:25 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:45:26 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:45:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:45:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:45:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:45:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:45:26 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:45:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:45:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:45:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:45:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:45:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:45:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:45:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:45:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:45:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:45:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:45:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:45:26 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:45:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:45:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:45:31 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:45:31 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:45:31 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:45:31 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:45:31 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:45:31 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:45:31 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:45:31 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:45:31 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:45:31 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:31 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:45:32 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:45:32 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:45:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:45:32 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:45:32 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:45:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:45:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:45:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:45:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:45:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:45:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:45:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:45:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:45:32 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:45:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:45:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:45:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:45:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:45:32 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:45:33 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:45:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:45:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:45:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:45:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:45:33 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:45:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:45:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:45:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:45:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:45:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:45:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:45:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:45:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:45:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:45:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:45:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:45:34 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:45:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:45:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=567 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:45:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=567 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:45:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=567 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:45:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=567 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:45:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=567 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:45:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=567 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:45:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=567 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:45:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:45:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:45:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:45:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:45:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:45:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:45:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:45:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:45:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:45:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:45:39 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:45:39 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:45:39 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:45:39 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:45:39 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:45:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:45:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:45:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:45:40 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:45:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:45:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:45:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:45:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:45:40 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:45:41 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:45:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:45:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:45:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:45:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:45:41 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:45:42 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:45:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:45:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:45:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:45:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:45:42 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:45:42 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:45:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:45:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:45:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:45:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:45:43 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:45:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:45:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:45:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:45:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:45:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:45:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:45:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:45:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:45:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:45:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:45:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:45:43 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:45:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:45:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:45:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:45:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:45:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:45:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:45:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:45:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:45:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:45:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:45:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:45:48 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:45:48 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:45:49 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:45:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:45:49 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:45:49 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:45:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:45:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:45:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:45:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:45:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:45:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:45:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:45:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:45:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:45:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:45:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:45:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:45:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:45:49 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:45:50 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:45:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:45:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:45:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:45:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:45:50 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:45:51 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:45:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:45:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:45:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:45:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:45:51 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:45:52 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:45:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:45:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:45:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:45:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:45:52 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:45:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:45:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:45:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:45:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:45:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:45:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:45:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:45:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:45:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:45:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:45:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:45:53 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:45:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:45:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:45:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:45:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:45:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:45:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:45:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:45:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:45:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:45:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:45:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:45:58 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:45:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:45:58 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:45:58 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:45:58 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:45:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:45:58 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:45:58 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:45:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:45:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:45:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:45:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:45:59 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:45:59 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:46:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:46:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:46:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:46:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:46:00 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:46:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:46:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:46:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:46:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:46:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:46:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:46:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:46:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:46:00 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:46:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:46:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:46:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:46:05 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:46:05 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:46:05 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:46:05 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:46:05 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:46:05 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:46:05 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:46:05 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:46:05 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:46:05 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:05 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:46:06 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:46:06 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:46:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:46:06 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:46:06 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:46:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:46:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:46:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:46:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:46:06 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:46:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:46:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:46:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:46:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:46:07 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:46:07 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:46:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:46:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:46:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:46:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:46:07 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:46:08 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:46:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:46:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:46:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:46:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:46:08 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:46:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:46:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:46:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:46:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:46:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:46:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:46:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:46:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:46:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:46:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:46:09 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:46:09 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=776 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:46:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:46:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:46:14 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:46:14 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:46:14 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:46:14 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:46:14 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:46:14 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:46:14 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:46:14 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:46:14 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:46:14 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:14 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:46:14 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:46:14 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:46:14 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:46:14 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:46:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:46:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:46:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:46:14 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:46:14 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=121 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:46:14 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=121 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:46:14 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=121 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:46:14 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=121 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:46:14 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=121 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:46:14 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=121 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:46:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:46:19 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:46:19 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:46:19 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:46:19 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:46:19 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:46:19 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:46:19 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:46:19 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:46:19 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:46:19 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:19 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:46:20 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:46:20 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:46:20 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:46:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:46:20 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:46:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:46:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:46:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:46:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:46:20 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:46:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:46:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:46:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:46:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:46:21 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:46:21 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:46:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:46:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:46:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:46:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:46:22 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:46:22 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:46:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:46:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:46:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:46:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:46:23 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:46:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:46:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:46:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:46:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:46:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:46:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:46:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:46:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:46:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:46:23 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:46:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:46:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:46:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:46:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:46:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:46:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:46:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:46:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:46:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:46:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:46:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:46:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:46:28 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:46:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:46:28 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:46:28 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:46:28 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:46:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:46:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:46:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:46:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:46:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:46:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:46:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:46:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:46:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:46:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:46:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:46:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:46:29 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:46:29 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=125 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:46:29 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:46:29 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:46:29 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:46:29 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:46:29 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:46:29 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:46:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:46:34 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:46:34 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:46:34 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:46:34 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:46:34 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:46:34 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:46:34 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:46:34 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:46:34 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:46:34 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:34 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:46:34 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:46:34 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:46:34 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:46:34 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:46:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:46:34 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:46:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:46:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:46:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:46:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:46:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:46:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:46:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:46:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:46:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:46:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:46:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:46:39 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:46:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:46:40 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:46:40 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:46:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:46:40 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:46:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:46:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:46:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:46:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:46:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:46:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:46:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:46:40 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:46:40 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:46:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:46:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:46:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:46:40 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:46:40 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:46:40 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:46:40 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:46:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:46:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:46:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:46:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:46:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:46:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:46:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:46:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:46:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:46:45 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:46:45 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:45 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:46:45 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:46:45 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:46:45 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:46:45 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:46:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:46:45 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:46:45 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:46:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:46:45 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:46:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:46:50 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:46:50 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:46:50 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:46:50 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:46:50 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:46:50 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:46:50 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:46:50 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:46:50 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:46:50 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:50 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:46:51 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:46:51 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:46:51 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:46:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:46:51 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:46:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:46:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:46:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:46:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:46:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:46:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:46:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:46:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:46:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:46:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:46:51 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:46:51 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:46:51 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:46:51 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:46:51 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:46:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:46:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:46:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:46:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:46:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:46:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:46:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:46:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:46:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:46:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:46:56 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:46:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:46:56 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:46:56 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:46:56 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:46:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:46:56 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:46:57 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:46:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:46:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:46:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:46:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:46:57 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:46:58 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:46:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:46:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:46:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:46:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:46:58 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:46:59 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:46:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:46:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:46:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:46:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:46:59 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:46:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:46:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:46:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:46:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:46:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:46:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:46:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:46:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:47:00 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:47:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:47:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:47:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:47:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:47:00 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:47:01 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:47:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:47:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:47:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:47:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:47:01 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:47:02 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:47:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:47:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:47:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:47:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:47:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:47:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:47:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:47:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:47:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:47:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:47:02 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:47:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:47:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:47:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:47:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:47:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:47:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:47:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:47:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:47:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:47:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:47:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:47:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:47:07 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:07 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:47:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:47:07 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:47:07 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:47:07 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:47:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:47:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:47:07 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:47:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:47:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:47:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:47:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:47:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:47:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:47:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:47:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:47:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:47:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:47:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:47:12 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:47:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:47:13 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:47:13 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:47:13 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:47:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:47:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:47:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:47:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:47:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:47:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:47:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:47:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:47:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:47:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:47:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:47:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:47:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:47:13 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:47:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:47:18 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:47:18 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:47:18 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:47:18 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:47:18 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:47:18 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:47:18 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:47:18 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:47:18 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:47:18 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:18 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:47:18 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:47:18 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:47:18 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:47:18 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:47:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:47:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:47:18 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:47:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:47:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:47:23 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:47:23 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:47:23 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:47:23 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:47:23 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:47:23 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:47:23 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:47:23 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:47:23 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:47:23 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:23 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:47:24 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:47:24 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:47:24 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:47:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:24 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:47:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:47:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:47:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:47:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:47:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:47:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:47:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:47:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:47:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:47:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:47:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:47:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:47:24 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:47:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:47:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:47:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:47:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:47:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:47:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:47:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:47:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:47:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:47:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:47:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:47:29 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:29 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:47:30 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:47:30 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:47:30 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:30 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:47:30 [DEBUG] fake_trx.py:376 (BTS@172.18.83.20:5700) Recv FAKE_TRXC_DELAY cmd
2024-10-30 05:47:30 [INFO] fake_trx.py:379 (BTS@172.18.83.20:5700) Artificial TRXC delay set to 200
2024-10-30 05:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD FAKE_TRXC_DELAY
2024-10-30 05:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:30 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:47:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:47:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:47:31 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:47:31 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:47:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:31 [DEBUG] fake_trx.py:376 (BTS@172.18.83.20:5700) Recv FAKE_TRXC_DELAY cmd
2024-10-30 05:47:31 [INFO] fake_trx.py:379 (BTS@172.18.83.20:5700) Artificial TRXC delay set to 0
2024-10-30 05:47:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD FAKE_TRXC_DELAY
2024-10-30 05:47:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:47:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:47:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:47:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:47:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:47:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:47:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:47:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:47:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:47:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:47:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:47:31 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:47:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:47:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:47:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:47:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:47:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:47:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:47:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:47:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:47:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:47:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:47:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:47:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:47:36 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:36 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:47:37 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:47:37 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:47:37 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:47:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:37 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:47:37 [DEBUG] fake_trx.py:376 (BTS@172.18.83.20:5700) Recv FAKE_TRXC_DELAY cmd
2024-10-30 05:47:37 [INFO] fake_trx.py:379 (BTS@172.18.83.20:5700) Artificial TRXC delay set to 200
2024-10-30 05:47:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD FAKE_TRXC_DELAY
2024-10-30 05:47:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:37 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:47:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:47:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:47:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:47:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:38 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:47:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:38 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:47:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:38 [DEBUG] fake_trx.py:376 (BTS@172.18.83.20:5700) Recv FAKE_TRXC_DELAY cmd
2024-10-30 05:47:38 [INFO] fake_trx.py:379 (BTS@172.18.83.20:5700) Artificial TRXC delay set to 0
2024-10-30 05:47:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD FAKE_TRXC_DELAY
2024-10-30 05:47:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:47:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:47:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:47:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:47:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:47:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:47:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:47:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:47:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:47:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:47:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:47:38 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:47:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:47:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:47:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:47:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:47:43 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:47:43 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:47:43 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:47:43 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:47:43 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:47:43 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:47:43 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:47:43 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:47:43 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:47:43 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:43 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:47:44 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:47:44 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:47:44 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:47:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:44 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:47:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:47:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:47:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:47:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:47:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:47:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:47:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:47:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:47:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:47:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:47:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:47:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:47:44 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:47:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:47:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:47:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:47:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:47:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:47:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:47:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:47:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:47:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:47:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:47:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:47:49 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:47:50 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:47:50 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:50 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:47:50 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:47:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:47:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:47:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:47:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:47:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:47:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:47:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:47:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:47:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:47:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:47:50 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:47:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:47:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:47:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:47:55 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:47:55 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:47:55 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:47:55 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:47:55 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:47:55 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:47:55 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:47:55 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:47:55 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:47:55 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:47:55 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:47:55 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:47:55 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:55 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:47:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:47:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:47:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:47:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:47:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:47:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:47:56 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:47:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:47:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:47:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:47:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:47:56 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:47:57 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:47:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:47:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:47:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:47:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:47:57 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:47:58 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:47:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:47:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:47:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:47:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:47:58 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:47:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:47:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:47:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:47:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:47:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:47:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:47:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:47:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:47:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:47:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:47:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:47:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:47:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:47:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:47:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:47:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:58 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:47:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:47:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:47:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:47:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:47:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:47:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:47:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:47:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:47:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:47:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:47:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:47:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:47:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:47:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:47:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:47:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:47:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:47:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:47:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:47:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:47:59 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:47:59 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:48:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:48:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:48:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:48:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:48:00 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:48:00 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:48:01 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:48:01 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:48:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:48:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:48:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:48:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:02 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:48:02 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:48:03 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:48:03 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:48:04 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:48:04 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:48:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:05 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:48:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:48:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:48:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:48:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:48:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:05 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:48:06 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:48:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:48:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:48:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:48:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:48:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:48:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:48:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:06 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:48:06 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:48:07 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:48:07 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:48:08 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:48:08 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 05:48:09 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 05:48:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:48:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:48:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:48:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:48:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:48:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:48:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:09 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 05:48:10 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 05:48:10 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 05:48:11 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 05:48:11 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 05:48:12 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 05:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:48:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:48:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:12 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 05:48:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:13 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 05:48:13 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 05:48:13 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 05:48:14 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 05:48:14 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 05:48:15 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 05:48:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:48:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:48:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:48:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:48:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:48:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:48:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:15 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 05:48:16 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 05:48:16 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 05:48:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:48:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:48:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:48:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:17 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 05:48:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:48:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:48:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:48:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:17 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 05:48:18 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 05:48:18 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 05:48:19 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 05:48:19 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 05:48:20 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 05:48:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:48:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:48:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:48:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:20 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 05:48:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:48:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:48:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:48:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:21 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 05:48:21 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 05:48:21 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 05:48:22 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 05:48:22 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 05:48:23 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 05:48:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:48:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:48:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:48:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:23 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 05:48:24 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-10-30 05:48:24 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-10-30 05:48:25 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-10-30 05:48:25 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-10-30 05:48:26 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-10-30 05:48:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:26 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-10-30 05:48:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:26 [WARNING] transceiver.py:250 (MS@172.18.83.22:6700) RX TRXD message (fn=6837 tn=5 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:48:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:48:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:48:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:48:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:48:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:48:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:48:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:27 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-10-30 05:48:27 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-10-30 05:48:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:48:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:48:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:48:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:48:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:48:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:48:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:28 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-10-30 05:48:28 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-10-30 05:48:28 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-10-30 05:48:29 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-10-30 05:48:29 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-10-30 05:48:30 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-10-30 05:48:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:48:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:48:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:48:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:30 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-10-30 05:48:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:48:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:48:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:48:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:31 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-10-30 05:48:31 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-10-30 05:48:32 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-10-30 05:48:32 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-10-30 05:48:33 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-10-30 05:48:33 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-10-30 05:48:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:48:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:48:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:48:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:34 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-10-30 05:48:34 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-10-30 05:48:35 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-10-30 05:48:35 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-10-30 05:48:36 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-10-30 05:48:36 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-10-30 05:48:36 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:48:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:48:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:37 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:48:37 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:48:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:48:37 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:48:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:48:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:48:42 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:48:42 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:48:42 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:48:42 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:48:42 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:48:42 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:48:42 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:48:42 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:48:42 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:48:42 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:48:42 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:48:43 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:48:43 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:48:43 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:43 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:48:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:48:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:48:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:48:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:43 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:48:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:48:43 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:48:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:48:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:48:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:48:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:48:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:48:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:48:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:48:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:48:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:48:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:48:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:48:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:48:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:48:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:48:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:48:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:48:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:48:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:48:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:48:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:48:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:48:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:48:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:48:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:48:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:48:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:48:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:48:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:48:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:48:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:48:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:48:49 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:48:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:48:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:48:49 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:48:49 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:49 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:48:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:48:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:48:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:48:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:48:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:48:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:48:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:48:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:48:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:48:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:48:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:48:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:48:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:48:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:50 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:48:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:48:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:48:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:48:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:48:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:48:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:48:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:48:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:48:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:48:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:48:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:48:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:48:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:48:51 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:48:51 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=496 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:48:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:48:51 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=496 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:48:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:48:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:48:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:48:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:48:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:48:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:48:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:48:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:48:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:48:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:48:56 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:48:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:48:56 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:48:56 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:48:56 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:48:56 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:48:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:48:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:57 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:48:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:57 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:48:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:48:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:48:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:48:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:48:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:48:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:48:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:48:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:48:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:48:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:48:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:48:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:48:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:48:58 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:48:58 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=394 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:48:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:48:58 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=394 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:48:58 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=394 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:48:58 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=394 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:48:58 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=394 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:48:58 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=394 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:48:58 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=394 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:48:58 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=394 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:49:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:49:03 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:49:03 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:49:03 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:49:03 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:49:03 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:49:03 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:49:03 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:49:03 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:49:03 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:49:03 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:49:03 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:49:03 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:49:03 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:03 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:49:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:49:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:04 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:49:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:04 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:49:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:49:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:49:04 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:49:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:49:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:49:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:49:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:49:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:49:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:49:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:49:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:49:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:49:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:49:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:49:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:49:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:49:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:49:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:49:10 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:49:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:49:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:49:10 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:49:10 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:10 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:49:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:10 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:49:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:49:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:49:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:49:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:49:11 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:49:11 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:49:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:49:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:49:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:49:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:49:12 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:49:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:49:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:49:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:49:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:12 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:49:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:49:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:49:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:49:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:49:13 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:49:13 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:49:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:49:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:49:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:49:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:49:14 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:49:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:49:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:49:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:49:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:14 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:49:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:49:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:49:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:49:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:49:15 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:49:15 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:49:16 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:49:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:49:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:49:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:49:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:16 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:49:17 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:49:17 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:49:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:49:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:49:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:49:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:49:18 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:49:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:49:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:49:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:49:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:49:18 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:49:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:49:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:49:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:49:23 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:49:23 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:49:23 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:49:23 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:49:23 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:49:23 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:49:23 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:49:23 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:49:23 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:49:23 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:49:23 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:49:23 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:49:23 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:23 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:49:23 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:49:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:23 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:49:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:49:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:49:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:49:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:49:24 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:49:24 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:49:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:49:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:49:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:49:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:49:25 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:49:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:49:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:49:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:49:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:25 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:49:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:49:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:49:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:49:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:49:26 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:49:26 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:49:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:49:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:49:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:49:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:49:27 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:49:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:49:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:49:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:49:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:27 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:49:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:49:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:49:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:49:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:49:28 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:49:28 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:49:29 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:49:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:49:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:49:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:49:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:29 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:49:30 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:49:30 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:49:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:49:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:49:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:49:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:49:31 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:49:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:49:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:49:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:49:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:49:31 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:49:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:49:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:49:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:49:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:49:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:49:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:49:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:49:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:49:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:49:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:49:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:49:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:49:36 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:49:36 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:49:36 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:49:36 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:49:36 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:49:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:49:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:37 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:49:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:49:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:49:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:49:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:49:37 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:49:37 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:49:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:49:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:49:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:49:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:49:38 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:49:38 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:49:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:49:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:49:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:49:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:49:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:49:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:49:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:49:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:49:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:49:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:49:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:39 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:49:39 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:49:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:49:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:49:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:49:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:49:40 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:49:40 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:49:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:49:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:49:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:49:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:49:41 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:49:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:49:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:49:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:49:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:49:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:49:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:49:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:41 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:49:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:42 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:49:42 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:49:43 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:49:43 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:49:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:49:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:49:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:49:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:44 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:49:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:49:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:49:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:49:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:44 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:49:44 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:49:45 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:49:45 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:49:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:49:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:49:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:49:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:46 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:49:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:46 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:49:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:49:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:49:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:49:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:47 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:49:47 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:49:48 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:49:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:49:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:49:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:49:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:48 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:49:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:49 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:49:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:49:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:49:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:49:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:49 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 05:49:50 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 05:49:50 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 05:49:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:49:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:49:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:49:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:51 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 05:49:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:51 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 05:49:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:49:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:49:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:49:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:52 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 05:49:52 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 05:49:52 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 05:49:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:49:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:49:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:49:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:53 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 05:49:53 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 05:49:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:49:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:49:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:49:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:49:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:49:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:54 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 05:49:54 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 05:49:55 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 05:49:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:49:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:49:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:49:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:49:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:49:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:49:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:49:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:49:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:49:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:49:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:49:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:49:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:49:55 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:49:55 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4270 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:49:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:49:55 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4270 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:49:55 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4270 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:49:55 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4270 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:49:55 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4270 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:49:55 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4270 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:49:55 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4271 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:49:55 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4271 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:49:55 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4271 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:49:55 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4271 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:49:55 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4271 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:49:55 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4271 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:49:55 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4271 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:49:55 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4271 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:50:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:50:00 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:50:00 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:50:00 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:50:00 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:50:00 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:50:00 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:50:00 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:50:00 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:50:00 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:50:00 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:00 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:50:01 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:50:01 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:01 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:50:01 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:01 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:02 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:50:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:50:02 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:50:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:50:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:50:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:50:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:50:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:50:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:50:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:50:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:50:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:50:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:50:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:50:07 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:07 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:50:08 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:50:08 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:50:08 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:08 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:08 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:50:08 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:09 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:50:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:50:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:50:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:50:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:50:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:09 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:10 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:10 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:11 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:50:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:50:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:50:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:50:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:50:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:50:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:50:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:50:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:50:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:50:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:50:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:50:11 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:50:11 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=905 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:50:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:50:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:50:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:50:11 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=905 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:50:11 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=905 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:50:11 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=905 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:50:11 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=905 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:50:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:50:16 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:50:16 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:50:16 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:50:16 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:50:16 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:50:16 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:50:16 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:50:16 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:50:16 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:50:16 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:16 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:50:17 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:50:17 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:50:17 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:17 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:17 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:18 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:50:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:50:18 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:50:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:50:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:50:23 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:50:23 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:50:23 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:50:23 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:50:23 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:50:23 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:50:23 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:50:23 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:50:23 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:50:23 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:23 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:50:24 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:50:24 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:50:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:24 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:50:24 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:50:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:24 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:50:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:50:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:50:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:50:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:50:24 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:50:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:25 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:50:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:50:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:50:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:50:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:50:25 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:50:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:26 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:50:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:50:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:50:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:50:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:50:26 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:50:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:27 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:50:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:50:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:50:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:50:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:50:27 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:50:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:28 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:50:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:50:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:50:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:50:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:50:28 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:50:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:29 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:50:29 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:50:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:30 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:50:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:30 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:50:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:31 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:50:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:31 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:50:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:50:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:50:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:50:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:50:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:50:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:50:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:50:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:50:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:50:31 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:50:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:50:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:50:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:50:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:50:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:50:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:50:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:50:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:50:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:50:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:50:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:50:36 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:36 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:50:37 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:50:37 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:50:37 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:50:37 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:37 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:50:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:50:37 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:50:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:50:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:50:42 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:50:42 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:50:42 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:50:42 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:50:42 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:50:42 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:50:42 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:50:42 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:50:42 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:50:42 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:42 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:50:43 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:50:43 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:50:43 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:43 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:43 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:50:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:50:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:50:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:50:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:50:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:50:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:50:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:50:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:50:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:50:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:50:44 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:50:44 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=291 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:50:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:50:44 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=291 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:50:44 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=291 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:50:44 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=291 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:50:44 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=291 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:50:44 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=291 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:50:44 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=292 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:50:44 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=292 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:50:44 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=292 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:50:44 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=292 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:50:44 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=292 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:50:44 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=292 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:50:44 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=292 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:50:44 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=292 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:50:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:50:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:50:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:50:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:50:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:50:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:50:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:50:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:50:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:50:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:50:49 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:50:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:50:49 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:50:49 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:49 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:50 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:50:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:50:50 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:50:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:50:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:50:55 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:50:55 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:50:55 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:50:55 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:50:55 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:50:55 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:50:55 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:50:55 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:50:55 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:50:55 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:50:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:50:55 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:50:56 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:50:56 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:50:56 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:56 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:56 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:50:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:50:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:50:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:50:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:50:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:50:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:50:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:50:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:50:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:50:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:50:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:50:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:50:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:50:57 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:50:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:51:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:51:02 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:51:02 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:51:02 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:51:02 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:51:02 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:51:02 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:51:02 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:51:02 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:51:02 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:51:02 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:02 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:51:02 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:51:02 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:51:02 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:02 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:51:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:51:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:51:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:51:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:51:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:51:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:51:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:51:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:51:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:51:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:51:03 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:51:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:51:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:51:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:51:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:51:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:51:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:51:03 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:51:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:51:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:51:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:51:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:51:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:51:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:51:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:51:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:51:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:51:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:51:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:51:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:04 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:51:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:51:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:51:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:51:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:51:04 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:51:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:51:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:51:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:51:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:51:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:51:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:51:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:51:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:51:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:51:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:51:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:51:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:04 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:51:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:51:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:51:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:51:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:51:05 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:51:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:51:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:51:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:51:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:51:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:51:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:51:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:51:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:51:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:51:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:51:05 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:51:05 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=787 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:51:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:51:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:51:05 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=787 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:51:05 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=787 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:51:05 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=787 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:51:05 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=787 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:51:05 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=787 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:51:05 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=787 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:51:05 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=787 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:51:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:51:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:51:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:51:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:51:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:51:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:51:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:51:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:51:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:51:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:51:10 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:51:11 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:51:11 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:51:11 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:51:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:11 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:51:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:51:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:51:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:51:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:51:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:51:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:51:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:51:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:51:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:51:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:51:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:51:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:51:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:51:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:51:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:51:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:51:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:51:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:51:11 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:51:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:51:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:51:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:51:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:51:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:51:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:51:12 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:51:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:51:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:51:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:51:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:51:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:51:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:51:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:51:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:51:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:51:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:51:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:51:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:12 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:51:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:51:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:51:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:51:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:51:13 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:51:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:51:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:51:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:51:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:51:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:51:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:51:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:51:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:51:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:51:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:51:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:51:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:13 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:51:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:51:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:51:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:51:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:51:14 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:51:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:51:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:51:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:51:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:51:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:51:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:51:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:51:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:51:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:51:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:51:14 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:51:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:51:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:51:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:51:19 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:51:19 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:51:19 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:51:19 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:51:19 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:51:19 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:51:19 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:51:19 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:51:19 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:51:19 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:19 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:51:19 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:51:19 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:51:19 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:19 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:51:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:51:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:51:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:51:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:51:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:51:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:51:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:51:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:51:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:51:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:51:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:51:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:51:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:51:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:51:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:51:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:20 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:51:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:51:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:51:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:51:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:51:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:51:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:51:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:51:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:51:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:51:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:51:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:51:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:51:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:51:20 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:51:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:51:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:51:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:21 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:51:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:51:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:51:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:51:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:51:21 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:51:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:51:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:51:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:51:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:51:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:51:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:51:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:51:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:51:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:51:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:51:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:51:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:22 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:51:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:51:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:51:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:51:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:51:22 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:51:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:51:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:51:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:51:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:51:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:51:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:51:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:51:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:51:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:51:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:51:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:51:23 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:51:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=786 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:51:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:51:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=786 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:51:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=786 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:51:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=786 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:51:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=786 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:51:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=786 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:51:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=786 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:51:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=786 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:51:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:51:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:51:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:51:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:51:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:51:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:51:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:51:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:51:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:51:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:51:28 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:51:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:51:28 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:51:28 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:28 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:51:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:51:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:51:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:51:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:51:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:51:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:51:29 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:51:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:51:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:51:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:51:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:51:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:51:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:51:29 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:51:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:51:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:51:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:51:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:51:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:51:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:51:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:51:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:51:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:51:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:51:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:51:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:29 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:51:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:51:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:51:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:51:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:51:30 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:51:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:51:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:51:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:51:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:51:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:51:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:51:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:51:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:51:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:51:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:51:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:51:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:30 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:51:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:51:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:51:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:51:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:51:31 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:51:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:51:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:51:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:51:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:51:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:51:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:51:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:51:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:51:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:51:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:51:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:51:31 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:51:31 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=786 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:51:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:51:31 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=786 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:51:31 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=786 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:51:31 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=786 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:51:31 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=786 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:51:31 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=786 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:51:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:51:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:51:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:51:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:51:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:51:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:51:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:51:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:51:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:51:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:51:36 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:36 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:51:37 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:51:37 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:51:37 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:51:37 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:51:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:51:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:51:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:51:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:51:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:51:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:51:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:51:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:51:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:51:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:51:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:51:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:51:37 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:51:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:51:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:51:42 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:51:42 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:51:42 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:51:42 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:51:42 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:51:42 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:51:42 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:51:42 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:51:42 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:51:42 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:42 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:51:42 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:51:42 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:42 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:51:42 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:51:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:51:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:51:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:51:42 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:51:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:51:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:51:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:51:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:51:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:51:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:51:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:51:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:51:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:51:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:51:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:51:47 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:47 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:51:48 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:51:48 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:51:48 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:51:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:48 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:51:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:51:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:51:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:51:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:51:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:51:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:51:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:51:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:51:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:51:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:51:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:51:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:51:48 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:51:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:51:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:51:53 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:51:53 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:51:53 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:51:53 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:51:53 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:51:53 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:51:53 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:51:53 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:51:53 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:51:53 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:51:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:51:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:51:53 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:51:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:51:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:51:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:51:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:51:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:51:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:51:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:51:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:51:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:51:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:51:58 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:51:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:51:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:51:59 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:51:59 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:51:59 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:51:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:59 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:51:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:51:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:51:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:51:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:51:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:51:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:51:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:51:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:51:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:51:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:51:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:51:59 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:51:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:51:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:51:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:51:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:52:00 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:52:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:52:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:52:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:52:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:00 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:52:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:52:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:52:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:52:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:52:00 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:52:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:52:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:52:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:52:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:01 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:52:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:52:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:52:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:52:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:52:01 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:52:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:52:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:52:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:52:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:02 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:52:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:52:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:52:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:52:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:52:02 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:52:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:52:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:52:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:52:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:03 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:52:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:52:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:52:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:52:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:52:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:52:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:52:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:52:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:03 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:52:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:52:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:52:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:52:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:04 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:52:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:04 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:52:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:52:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:52:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:52:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:52:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:05 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:52:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:52:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:52:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:52:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:05 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:52:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:52:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:52:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:52:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:52:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:06 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:52:06 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:52:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:52:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:52:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:52:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:07 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:52:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:52:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:52:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:52:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:07 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:52:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:52:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:52:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:52:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:07 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:52:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:08 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:52:08 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:52:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:52:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:52:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:52:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:09 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:52:09 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:52:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:52:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:52:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:52:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:10 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:52:10 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:52:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:52:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:52:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:52:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:11 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:52:11 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:52:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:52:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:52:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:52:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:12 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 05:52:12 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 05:52:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:52:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:52:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:52:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:13 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 05:52:13 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 05:52:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:52:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:52:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:52:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:14 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 05:52:14 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 05:52:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:52:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:52:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:52:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:15 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 05:52:15 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 05:52:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:52:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:52:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:52:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:52:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:52:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:52:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:52:15 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:52:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:52:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:52:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:52:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:52:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:52:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:52:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:52:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:52:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:52:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:52:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:52:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:52:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:52:20 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:52:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:52:20 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:52:21 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:52:21 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:52:21 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:21 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:52:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:52:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:21 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:52:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:52:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:52:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:52:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:52:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:52:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:22 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:52:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:52:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:52:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:52:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:52:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:52:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:52:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:52:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:52:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:52:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:52:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:52:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:52:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:52:22 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:52:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=347 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:52:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:52:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=347 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:52:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=347 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:52:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=347 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:52:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=347 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:52:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=347 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:52:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=347 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:52:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=347 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:52:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:52:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:52:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:52:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:52:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:52:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:52:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:52:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:52:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:52:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:52:27 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:52:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:52:27 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:52:28 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:52:28 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:52:29 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:52:29 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:52:30 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:52:30 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:52:31 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:52:31 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:52:32 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:52:32 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:52:32 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:52:33 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:52:33 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:52:34 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:52:34 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:52:35 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:52:35 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:52:36 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:52:36 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:52:37 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:52:37 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:52:38 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:52:38 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:52:39 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:52:39 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:52:40 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:52:40 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:52:40 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 05:52:41 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 05:52:41 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 05:52:42 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 05:52:42 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 05:52:43 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 05:52:43 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 05:52:44 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 05:52:44 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 05:52:45 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 05:52:45 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 05:52:46 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 05:52:46 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 05:52:47 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 05:52:47 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 05:52:47 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 05:52:48 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 05:52:48 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 05:52:49 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 05:52:49 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 05:52:50 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 05:52:50 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 05:52:51 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 05:52:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:52:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:52:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:52:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:52:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:52:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:52:51 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:52:51 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5215 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:52:51 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5215 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:52:51 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5215 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:52:51 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5215 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:52:51 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5215 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:52:51 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5215 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:52:51 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5215 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:52:51 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5215 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:52:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:52:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:52:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:52:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:52:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:52:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:52:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:52:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:52:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:52:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:52:56 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:52:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:52:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:52:56 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:52:57 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:52:57 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:52:58 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:52:58 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:52:59 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:52:59 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:53:00 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:53:00 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:53:01 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:53:01 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:53:02 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:53:02 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:53:02 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:53:03 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:53:03 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:53:04 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:53:04 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:53:05 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:53:05 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:53:06 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:53:06 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:53:07 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:53:07 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:53:08 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:53:08 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:53:09 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:53:09 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:53:09 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 05:53:10 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 05:53:10 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 05:53:11 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 05:53:11 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 05:53:12 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 05:53:12 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 05:53:13 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 05:53:13 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 05:53:14 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 05:53:14 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 05:53:15 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 05:53:15 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 05:53:16 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 05:53:16 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 05:53:17 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 05:53:17 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 05:53:17 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 05:53:18 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 05:53:18 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 05:53:19 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 05:53:19 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 05:53:20 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 05:53:20 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 05:53:21 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 05:53:21 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 05:53:22 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 05:53:22 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 05:53:23 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 05:53:23 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 05:53:24 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 05:53:24 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 05:53:24 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 05:53:25 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-10-30 05:53:25 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-10-30 05:53:26 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-10-30 05:53:26 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-10-30 05:53:27 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-10-30 05:53:27 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-10-30 05:53:28 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-10-30 05:53:28 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-10-30 05:53:29 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-10-30 05:53:29 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-10-30 05:53:30 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-10-30 05:53:30 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-10-30 05:53:31 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-10-30 05:53:31 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-10-30 05:53:32 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-10-30 05:53:32 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-10-30 05:53:32 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-10-30 05:53:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:53:33 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-10-30 05:53:33 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-10-30 05:53:34 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-10-30 05:53:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:53:34 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-10-30 05:53:35 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-10-30 05:53:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:53:35 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-10-30 05:53:36 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-10-30 05:53:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:53:36 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-10-30 05:53:37 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-10-30 05:53:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:53:37 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-10-30 05:53:38 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-10-30 05:53:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:53:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:53:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:53:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:53:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:53:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:53:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:53:38 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:53:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:53:43 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:53:43 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:53:43 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:53:43 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:53:43 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:53:43 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:53:43 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:53:43 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:53:43 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:53:43 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:53:43 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:53:43 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:53:43 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:53:43 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:53:43 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:53:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:53:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:53:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:53:43 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:53:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:53:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:53:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:53:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:53:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:53:44 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:53:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:53:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:53:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:53:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:53:44 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:53:45 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:53:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:53:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:53:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:53:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:53:45 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:53:46 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:53:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:53:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:53:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:53:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:53:46 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:53:47 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:53:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:53:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:53:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:53:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:53:47 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:53:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:53:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:53:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:53:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:53:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:53:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:53:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:53:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:53:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:53:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:53:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:53:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:53:47 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:53:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:53:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:53:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:53:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:53:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:53:48 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:53:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:53:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:53:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:53:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:53:48 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:53:49 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:53:49 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:53:50 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:53:50 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:53:50 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:53:51 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:53:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:53:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:53:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:53:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:53:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:53:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:53:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:53:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:53:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:53:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:53:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:53:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:53:51 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:53:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:53:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:53:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:53:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:53:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:53:51 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:53:52 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:53:52 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:53:53 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:53:53 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:53:54 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:53:54 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:53:55 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:53:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:53:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:53:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:53:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:53:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:53:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:53:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:53:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:53:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:53:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:53:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:53:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:53:55 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:53:55 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:53:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:53:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:53:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:53:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:53:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:53:56 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:53:56 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:53:57 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 05:53:57 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 05:53:57 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 05:53:58 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 05:53:58 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 05:53:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:53:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:53:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:53:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:53:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:53:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:53:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:53:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:53:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:53:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:53:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:53:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:53:59 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:53:59 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3455 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:53:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:53:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:53:59 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3455 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:53:59 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3455 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:53:59 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3455 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:53:59 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3455 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:53:59 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3455 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:53:59 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3455 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:53:59 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3455 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:54:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:54:04 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:54:04 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:54:04 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:54:04 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:54:04 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:54:04 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:54:04 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:54:04 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:54:04 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:54:04 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:54:04 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:54:04 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:54:04 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:54:04 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:54:04 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:54:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:54:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:54:04 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:54:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:54:05 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:54:05 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:54:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:54:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:54:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:54:05 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:54:05 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:06 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:54:06 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:54:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:54:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:54:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:54:06 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:54:06 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:07 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:54:07 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:54:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:54:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:54:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:54:07 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:54:07 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:08 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:54:08 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:54:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:54:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:54:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:54:08 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:54:08 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:09 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:54:09 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:54:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:54:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:54:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:54:09 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:54:09 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:09 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:54:10 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:10 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:54:10 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:10 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:54:11 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:11 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:54:11 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:11 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:54:12 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:12 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:54:12 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:54:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:54:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:54:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:54:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:54:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:54:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:54:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:54:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:54:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:54:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:54:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:54:12 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:54:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:54:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:54:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:54:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:54:12 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:54:13 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:13 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:54:13 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:13 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:54:14 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:14 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:54:14 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:14 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:54:15 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:15 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:54:15 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:15 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:54:16 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:16 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:54:16 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:16 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:54:17 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:17 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:54:17 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:54:17 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:17 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 05:54:17 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:18 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 05:54:18 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:18 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 05:54:18 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:19 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 05:54:19 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:19 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 05:54:19 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:20 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 05:54:20 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:54:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:54:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:54:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:54:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:54:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:54:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:54:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:54:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:54:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:54:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:54:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:54:20 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:54:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:54:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:54:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:54:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:54:20 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:20 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 05:54:21 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:21 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 05:54:21 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:21 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 05:54:22 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:22 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 05:54:22 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:22 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 05:54:23 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:23 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 05:54:23 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:23 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 05:54:24 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:24 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 05:54:24 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:24 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 05:54:24 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:24 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 05:54:25 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:25 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 05:54:25 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:25 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 05:54:26 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:26 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 05:54:26 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:26 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 05:54:27 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:27 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 05:54:27 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:54:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:54:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:54:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:54:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:54:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:54:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:54:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:54:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:54:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:54:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:54:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:54:27 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:27 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 05:54:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:54:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:54:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:54:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:54:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:54:28 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:28 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 05:54:28 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:28 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 05:54:29 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:29 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 05:54:29 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:29 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 05:54:30 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:30 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 05:54:30 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:30 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 05:54:31 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:31 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 05:54:31 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:31 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 05:54:31 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:32 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 05:54:32 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:32 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 05:54:32 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:32 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 05:54:33 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:33 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-10-30 05:54:33 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:33 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-10-30 05:54:34 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:34 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-10-30 05:54:34 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:34 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-10-30 05:54:35 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:54:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:54:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:54:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:54:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:54:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:54:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:54:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:54:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:54:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:54:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:54:35 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:54:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:54:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:54:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:54:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:54:40 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:54:40 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:54:40 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:54:40 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:54:40 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:54:40 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:54:40 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:54:40 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:54:40 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:54:40 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:54:40 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:54:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:54:40 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:54:40 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:40 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:54:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:54:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:54:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:54:41 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:54:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:54:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:54:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:54:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:54:41 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:54:42 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:54:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:54:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:54:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:54:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:54:42 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:54:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:54:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:54:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:54:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:54:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:54:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:54:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:54:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:54:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:54:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:54:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:54:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:54:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:54:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:54:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:54:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:54:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:54:43 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:54:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:54:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:54:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:54:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:54:43 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:54:44 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:54:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:54:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:54:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:54:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:54:44 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:54:44 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:54:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:54:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:54:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:54:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:54:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:54:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:54:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:54:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:54:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:54:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:54:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:54:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:54:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:54:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:54:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:54:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:54:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:54:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:54:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:54:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:54:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:54:45 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:54:45 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:54:46 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:54:46 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:54:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:54:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:54:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:54:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:54:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:54:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:54:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:54:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:54:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:54:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:54:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:54:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:54:47 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:54:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:54:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:54:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:54:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:54:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:54:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:54:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:54:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:54:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:54:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:54:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:54:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:54:52 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:54:52 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:54:52 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:54:52 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:54:52 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:54:52 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:54:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:54:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:54:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:54:53 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:54:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:54:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:54:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:54:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:54:53 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:54:54 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:54:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:54:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:54:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:54:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:54:54 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:54:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:54:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:54:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:54:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:54:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:54:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:54:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:54:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:54:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:54:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:54:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:54:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:54:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:54:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:54:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:54:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:54:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:54:55 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:54:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:54:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:54:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:54:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:54:55 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:54:56 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:54:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:54:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:54:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:54:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:54:56 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:54:56 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:54:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:54:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:54:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:54:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:54:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:54:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:54:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:54:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:54:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:54:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:54:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:54:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:54:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:54:57 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:54:57 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1053 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:54:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:54:57 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1053 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:54:57 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1053 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:54:57 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1053 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:54:57 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1053 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:54:57 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1053 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:54:57 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1053 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:54:57 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1053 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:55:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:55:02 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:55:02 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:55:02 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:55:02 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:55:02 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:55:02 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:55:02 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:55:02 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:55:02 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:55:02 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:02 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:55:02 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:55:02 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:55:02 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:55:02 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:55:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:55:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:03 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:55:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:55:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:55:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:55:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:55:03 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:55:04 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:55:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:55:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:55:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:55:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:55:04 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:55:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:55:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:55:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:55:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:55:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:55:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:55:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:55:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:55:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:55:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:55:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:55:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:55:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:55:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:04 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:55:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:55:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:55:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:55:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:55:05 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:55:05 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:55:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:55:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:55:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:55:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:55:06 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:55:06 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:55:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:55:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:55:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:55:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:55:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:55:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:55:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:55:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:55:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:55:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:55:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:55:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:55:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:55:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:55:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:55:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:55:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:55:07 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:55:07 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:55:08 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:55:08 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:55:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:55:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:55:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:55:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:55:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:55:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:55:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:55:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:55:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:55:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:55:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:55:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:55:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:55:09 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:55:09 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1505 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:09 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1505 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:09 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1506 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:09 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1506 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:09 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1506 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:09 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1506 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:09 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1506 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:09 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1506 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:09 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1506 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:09 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1506 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:55:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:55:14 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:55:14 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:55:14 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:55:14 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:55:14 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:55:14 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:55:14 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:55:14 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:55:14 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:55:14 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:14 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:55:14 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:55:14 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:55:14 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:55:14 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:55:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:55:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:15 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:55:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:55:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:55:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:55:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:55:15 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:55:16 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:55:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:55:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:55:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:55:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:55:16 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:55:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:55:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:55:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:55:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:55:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:55:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:55:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:55:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:55:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:55:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:55:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:55:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:55:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:55:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:16 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:55:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:55:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:55:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:55:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:55:17 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:55:17 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:55:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:55:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:55:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:55:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:55:18 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:55:18 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:55:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:55:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:55:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:55:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:55:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:55:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:55:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:55:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:55:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:55:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:55:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:55:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:55:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:55:18 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:55:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:55:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:55:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:55:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:55:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:55:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:55:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:55:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:55:23 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:55:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:55:23 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:55:23 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:55:23 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:55:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:55:23 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:55:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:55:23 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:55:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:55:23 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:55:23 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:55:23 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:55:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:55:23 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:55:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:55:23 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:55:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:55:23 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:55:23 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:55:23 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:55:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:55:23 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:55:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:55:23 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:55:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:55:23 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:55:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:55:24 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:24 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:55:24 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:55:24 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:55:24 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:55:24 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:55:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:55:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:24 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:55:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:55:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:55:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:55:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:55:25 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:55:25 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:55:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:55:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:55:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:55:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:55:26 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:55:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:55:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:55:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:55:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:55:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:55:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:55:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:55:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:55:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:55:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:55:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:55:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:55:26 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:55:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:55:26 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=595 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:26 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=595 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:26 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=595 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:26 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=595 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:26 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=595 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:26 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=595 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:26 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=595 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:26 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=595 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:55:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:55:31 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:55:31 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:55:31 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:55:31 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:55:31 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:55:31 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:55:31 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:55:31 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:55:31 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:55:31 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:31 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:55:32 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:55:32 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:55:32 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:55:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:55:32 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:55:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:55:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:55:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:55:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:55:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:55:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:55:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:55:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:55:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:55:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:55:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:32 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:55:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:55:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:55:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:55:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:55:33 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:55:33 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:55:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:55:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:55:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:55:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:55:34 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:55:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:55:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:55:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:55:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:55:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:55:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:55:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:55:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:55:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:55:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:55:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:55:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:55:34 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:55:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:55:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:55:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:55:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:55:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:55:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:55:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:55:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:55:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:55:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:55:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:55:39 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:55:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:55:40 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:55:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:55:40 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:55:40 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:55:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:55:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:55:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:55:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:55:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:55:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:55:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:55:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:55:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:55:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:55:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:55:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:55:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:55:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:55:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:55:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:55:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:55:40 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:55:40 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=135 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:55:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:55:40 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=135 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:40 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=135 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:40 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=135 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:40 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=136 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:40 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=136 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:40 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=136 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:40 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=136 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:40 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=136 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:40 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=136 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:40 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=136 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:40 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=136 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:55:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:55:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:55:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:55:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:55:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:55:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:55:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:55:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:55:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:55:45 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:55:45 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:45 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:55:45 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:55:45 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:55:45 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:55:45 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:55:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:55:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:46 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:55:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:55:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:55:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:55:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:55:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:55:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:55:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:55:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:55:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:55:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:55:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:55:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:55:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:55:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:55:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:55:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:55:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:55:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:46 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:55:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:55:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:55:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:55:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:55:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:55:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:55:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:55:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:55:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:55:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:55:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:55:46 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:55:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:55:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:55:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:55:51 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:55:51 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:55:51 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:55:51 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:55:51 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:55:51 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:55:51 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:55:51 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:55:51 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:55:51 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:51 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:55:52 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:55:52 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:55:52 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:55:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:55:52 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:55:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:55:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:55:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:55:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:55:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:55:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:55:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:55:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:55:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:55:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:55:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:52 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:55:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:55:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:55:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:55:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:55:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:55:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:55:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:55:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:55:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:55:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:55:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:55:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:55:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:55:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:55:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:55:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:55:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:55:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:53 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:55:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:55:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:55:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:55:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:55:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:55:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:55:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:55:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:55:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:55:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:55:53 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:55:53 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=318 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:55:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:55:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:55:53 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=318 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:53 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=318 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:53 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=318 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:53 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=318 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:53 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=318 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:53 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=318 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:53 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=318 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:55:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:55:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:55:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:55:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:55:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:55:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:55:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:55:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:55:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:55:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:55:58 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:55:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:55:58 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:55:58 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:55:58 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:55:58 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:55:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:55:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:59 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:55:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:55:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:55:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:55:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:55:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:55:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:55:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:55:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:55:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:55:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:55:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:55:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:55:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:55:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:55:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:55:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:55:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:55:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:59 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:55:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:55:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:55:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:55:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:55:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:55:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:55:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:55:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:55:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:55:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:55:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:55:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:55:59 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:55:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:55:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:56:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:56:04 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:56:04 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:56:04 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:56:04 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:56:04 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:56:04 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:56:04 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:56:04 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:56:04 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:56:04 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:04 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:56:05 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:56:05 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:56:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:56:05 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:56:05 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:56:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:56:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:56:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:56:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:56:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:56:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:56:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:56:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:56:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:56:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:56:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:56:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:56:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:56:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:56:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:56:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:56:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:56:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:56:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:56:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:56:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:56:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:56:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:56:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:56:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:56:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:56:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:56:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:56:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:56:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:56:05 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:56:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:56:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:56:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:56:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:56:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:56:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:56:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:56:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:56:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:56:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:56:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:56:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:56:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:56:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:56:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:56:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:56:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:56:06 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:56:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:56:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:56:11 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:56:11 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:56:11 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:56:11 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:56:11 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:56:11 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:56:11 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:56:11 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:56:11 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:56:11 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:11 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:56:11 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:56:11 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:56:11 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:56:11 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:56:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:56:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:56:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:56:12 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:56:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:56:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:56:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:56:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:56:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:56:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:56:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:56:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:56:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:56:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:56:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:56:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:56:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:56:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:56:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:56:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:56:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:56:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:56:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:56:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:56:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:56:12 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:56:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:56:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:56:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:56:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:56:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:56:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:56:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:56:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:56:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:56:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:56:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:56:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:56:12 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:56:12 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=368 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:56:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:56:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:56:12 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=368 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:56:12 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=368 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:56:12 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=368 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:56:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:56:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:56:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:56:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:56:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:56:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:56:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:56:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:56:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:56:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:56:17 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:17 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:56:18 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:56:18 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:56:18 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:56:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:56:18 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:56:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:56:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:56:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:56:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:56:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:56:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:56:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:56:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:56:18 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:56:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:56:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:56:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:56:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:56:19 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:56:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:56:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:56:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:56:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:56:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:56:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:56:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:56:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:56:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:56:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:56:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:56:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:56:19 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:56:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:56:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:56:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:56:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:56:20 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:56:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD NOHANDOVER
2024-10-30 05:56:20 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:56:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD NOHANDOVER
2024-10-30 05:56:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:56:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:56:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:56:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:56:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:56:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:56:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:56:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:56:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:56:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:56:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:56:20 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:56:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:56:20 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=623 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:56:20 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=623 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:56:20 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=623 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:56:20 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=623 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:56:20 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=623 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:56:20 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=623 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:56:20 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=623 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:56:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:56:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:56:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:56:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:56:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:56:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:56:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:56:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:56:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:56:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:56:25 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:56:26 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:56:26 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:56:26 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:56:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:56:26 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:56:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:56:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:56:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:56:26 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:56:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:56:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:56:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:56:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:56:27 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:56:27 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:56:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:56:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:56:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:56:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:56:28 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:56:28 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:56:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:56:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:56:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:56:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:56:29 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:56:29 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:56:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:56:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:56:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:56:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:56:29 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:56:30 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:56:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:56:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:56:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:56:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:56:30 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:56:31 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:56:31 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:56:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:56:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:56:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:56:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:56:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:56:32 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:56:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD NOHANDOVER
2024-10-30 05:56:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:56:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:56:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:56:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:56:32 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:56:33 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:56:33 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:56:34 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:56:34 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:56:35 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:56:35 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:56:36 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:56:36 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:56:37 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:56:37 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:56:37 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:56:38 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:56:38 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:56:39 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 05:56:39 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 05:56:40 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 05:56:40 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 05:56:41 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 05:56:41 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 05:56:42 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 05:56:42 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 05:56:43 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 05:56:43 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 05:56:44 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 05:56:44 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 05:56:44 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 05:56:45 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 05:56:45 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 05:56:46 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 05:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD NOHANDOVER
2024-10-30 05:56:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:56:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:56:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:56:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:56:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:56:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:56:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:56:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:56:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:56:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:56:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:56:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:56:46 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:56:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:56:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:56:51 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:56:51 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:56:51 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:56:51 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:56:51 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:56:51 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:56:51 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:56:51 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:56:51 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:56:51 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:56:51 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:56:52 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:56:52 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:56:52 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:56:52 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:56:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:56:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:56:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:56:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:56:52 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:56:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:56:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:56:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:56:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:56:53 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:56:53 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:56:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:56:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:56:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:56:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:56:54 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:56:54 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:56:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:56:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:56:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:56:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:56:55 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:56:55 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:56:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:56:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:56:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:56:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:56:55 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:56:56 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:56:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:56:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:56:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:56:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:56:56 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:56:57 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:56:57 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:56:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:56:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:56:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:56:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:56:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:56:58 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:56:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD NOHANDOVER
2024-10-30 05:56:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:56:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:56:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:56:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:56:58 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:56:59 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:56:59 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:57:00 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:57:00 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:57:01 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:57:01 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:57:02 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:57:02 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:57:03 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:57:03 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:57:03 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:57:04 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:57:04 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:57:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD NOHANDOVER
2024-10-30 05:57:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:57:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:57:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:57:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:57:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:57:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:57:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:57:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:57:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:57:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:57:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:57:05 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:57:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:57:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:57:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:57:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:57:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:57:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:57:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:57:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:57:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:57:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:57:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:57:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:57:10 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:57:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:57:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:57:10 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:57:10 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:57:10 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:57:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:57:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:57:11 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:57:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:57:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:57:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:57:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:57:11 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:57:12 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:57:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:57:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:57:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:57:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:57:12 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:57:12 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:57:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:57:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:57:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:57:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:57:13 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:57:13 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:57:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:57:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:57:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:57:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:57:14 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:57:14 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:57:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:57:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:57:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:57:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:57:15 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:57:15 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:57:16 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:57:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:57:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:57:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:57:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:57:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:57:16 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:57:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD NOHANDOVER
2024-10-30 05:57:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:57:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:57:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:57:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:57:17 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:57:17 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:57:18 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:57:18 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:57:19 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:57:19 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:57:19 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:57:20 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:57:20 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:57:21 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:57:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD NOHANDOVER
2024-10-30 05:57:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:57:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:57:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:57:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:57:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:57:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:57:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:57:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:57:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:57:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:57:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:57:21 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:57:21 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2484 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:57:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:57:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:57:21 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2484 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:57:21 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2484 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:57:21 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2484 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:57:21 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2484 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:57:21 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2484 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:57:21 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2484 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:57:21 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2484 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:57:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:57:26 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:57:26 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:57:26 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:57:26 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:57:26 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:57:26 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:57:26 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:57:26 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:57:26 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:57:26 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:57:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:57:26 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:57:27 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:57:27 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:57:27 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:57:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:57:27 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:57:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:57:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:57:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:57:27 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:57:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:57:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:57:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:57:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:57:28 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:57:28 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:57:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:57:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:57:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:57:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:57:28 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:57:29 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:57:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:57:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:57:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:57:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:57:29 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:57:30 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:57:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:57:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:57:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:57:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:57:30 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:57:31 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:57:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:57:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:57:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:57:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:57:31 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:57:32 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:57:32 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:57:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:57:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:57:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:57:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:57:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:57:33 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:57:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD NOHANDOVER
2024-10-30 05:57:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:57:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:57:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:57:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:57:33 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:57:34 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:57:34 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:57:35 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:57:35 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:57:36 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:57:36 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:57:36 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:57:37 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:57:37 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:57:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD NOHANDOVER
2024-10-30 05:57:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:57:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:57:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:57:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:57:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:57:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:57:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:57:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:57:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:57:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:57:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:57:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:57:38 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:57:38 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2485 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:57:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:57:38 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2485 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:57:38 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2485 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:57:38 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2485 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:57:38 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2485 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:57:38 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2485 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:57:38 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2485 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:57:38 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2485 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:57:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:57:43 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:57:43 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:57:43 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:57:43 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:57:43 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:57:43 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:57:43 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:57:43 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:57:43 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:57:43 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:57:43 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:57:43 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:57:43 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:57:43 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:57:43 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:57:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:57:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:57:44 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:57:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:57:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:57:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:57:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:57:44 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:57:44 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:57:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:57:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:57:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:57:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:57:45 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:57:45 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:57:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:57:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:57:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:57:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:57:46 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:57:46 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:57:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:57:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:57:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:57:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:57:47 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:57:47 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:57:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:57:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:57:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:57:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:57:48 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:57:48 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:57:49 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:57:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:57:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:57:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:57:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:57:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:57:49 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:57:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD NOHANDOVER
2024-10-30 05:57:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:57:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:57:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:57:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:57:50 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:57:50 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:57:51 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:57:51 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:57:52 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:57:52 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:57:52 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:57:53 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:57:53 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:57:54 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:57:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD NOHANDOVER
2024-10-30 05:57:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:57:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:57:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:57:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:57:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:57:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:57:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:57:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:57:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:57:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:57:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:57:54 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:57:54 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2485 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:57:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:57:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:57:54 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2485 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:57:54 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2485 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:57:54 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2485 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:57:54 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2485 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:57:54 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2485 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:57:54 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2485 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:57:54 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2485 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:57:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:57:59 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:57:59 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:57:59 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:57:59 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:57:59 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:57:59 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:57:59 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:57:59 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:57:59 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:57:59 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:57:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:57:59 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:58:00 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:58:00 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:58:00 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:58:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:58:00 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:58:00 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:58:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:58:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:58:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:58:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:58:00 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:58:01 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:58:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:58:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:58:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:58:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:58:01 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:58:02 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:58:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:58:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:58:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:58:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:58:02 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:58:03 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:58:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:58:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:58:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:58:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:58:03 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:58:04 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:58:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:58:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:58:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:58:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:58:04 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:58:05 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:58:05 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:58:06 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:58:06 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:58:07 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:58:07 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:58:08 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:58:08 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:58:08 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:58:09 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:58:09 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:58:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:58:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:58:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:58:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:58:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:58:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:58:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:58:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:58:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:58:10 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:58:10 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2287 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:58:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:58:10 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2287 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:58:10 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2287 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:58:10 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2287 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:58:10 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2287 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:58:10 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2287 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:58:10 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2287 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:58:10 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2287 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:58:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:58:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:58:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:58:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:58:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:58:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:58:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:58:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:58:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:58:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:58:15 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:58:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:58:15 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:58:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:58:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:58:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:58:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:58:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:58:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:58:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:58:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:58:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:58:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:58:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:58:20 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:20 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:58:20 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:58:20 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:58:20 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:58:20 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:58:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:58:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:58:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:58:21 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:58:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:58:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:58:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:58:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:58:21 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:58:22 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:58:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:58:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:58:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:58:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:58:22 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:58:22 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:58:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:58:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:58:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:58:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:58:23 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:58:23 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:58:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:58:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:58:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:58:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:58:24 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:58:24 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:58:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:58:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:58:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:58:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:58:25 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:58:25 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:58:26 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:58:26 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:58:27 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:58:27 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:58:28 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:58:28 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:58:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:58:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:58:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:58:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:58:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:58:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:58:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:58:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:58:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:58:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:58:28 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:58:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:58:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:58:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:58:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:58:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:58:33 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:58:33 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:58:33 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:58:33 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:58:33 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:58:33 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:58:33 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:58:33 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:58:33 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:58:33 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:58:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:58:33 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:58:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:58:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:58:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:58:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:58:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:58:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:58:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:58:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:58:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:58:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:58:38 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:38 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:58:39 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:58:39 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:58:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:58:39 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:58:39 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:58:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:58:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:58:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:58:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:58:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:58:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:58:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:58:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:58:39 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:58:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:58:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:58:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:58:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:58:40 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:58:40 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:58:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:58:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:58:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:58:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:58:41 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:58:41 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:58:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:58:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:58:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:58:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:58:42 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:58:42 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:58:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:58:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:58:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:58:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:58:43 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:58:43 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:58:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:58:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:58:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:58:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:58:43 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:58:44 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:58:44 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:58:45 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:58:45 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:58:46 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:58:46 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:58:47 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:58:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:58:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:58:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:58:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:58:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:58:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:58:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:58:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:58:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:58:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:58:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:58:47 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:58:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:58:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:58:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:58:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:58:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:58:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:58:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:58:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:58:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:58:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:58:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:58:52 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:58:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:58:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:58:52 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:58:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:58:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:58:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:58:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:58:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:58:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:58:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:58:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:58:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:58:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:58:57 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:58:57 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:58:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:58:58 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:58:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:58:58 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:58:58 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:58:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:58:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:58:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:58:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:58:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:58:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:58:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:58:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:58:58 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:58:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:58:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:58:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:58:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:58:58 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:58:59 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:58:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:58:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:58:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:58:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:58:59 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:59:00 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:59:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:59:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:59:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:59:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:59:00 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:59:01 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:59:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:59:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:59:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:59:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:59:01 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:59:02 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:59:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:59:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:59:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:59:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:59:02 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:59:03 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:59:03 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:59:04 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:59:04 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:59:05 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:59:05 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:59:05 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:59:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:59:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:59:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:59:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:59:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:59:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:59:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:59:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:59:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:59:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:59:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:59:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:59:06 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:59:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:59:11 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:59:11 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:59:11 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:59:11 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:59:11 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:59:11 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:59:11 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:59:11 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:59:11 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:59:11 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:59:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:59:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:59:11 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:59:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:59:16 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:59:16 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:59:16 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:59:16 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:59:16 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:59:16 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:59:16 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:59:16 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:59:16 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:59:16 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:16 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:59:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:59:16 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:59:16 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:59:16 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:59:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:59:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:59:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:59:17 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:59:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:59:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:59:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:59:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:59:17 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:59:18 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:59:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:59:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:59:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:59:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:59:18 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:59:18 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:59:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:59:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:59:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:59:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:59:19 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:59:19 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:59:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:59:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:59:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:59:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:59:20 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:59:20 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:59:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:59:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:59:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:59:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:59:21 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:59:21 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:59:22 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:59:22 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:59:23 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:59:23 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:59:24 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:59:24 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:59:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:59:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:59:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:59:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:59:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:59:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:59:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:59:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:59:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:59:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:59:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:59:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:59:24 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:59:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:59:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:59:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:59:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:59:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:59:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:59:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:59:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:59:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:59:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:59:29 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:59:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:59:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:59:29 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:59:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:59:34 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:59:34 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:59:34 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:59:34 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:59:34 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:59:34 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:59:34 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:59:34 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:59:34 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:59:34 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:34 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:59:35 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:59:35 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:59:35 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:59:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:59:35 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:59:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:59:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:59:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:59:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:59:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:59:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:59:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:59:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 05:59:35 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 05:59:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:59:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:59:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:59:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:59:36 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 05:59:36 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 05:59:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:59:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:59:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:59:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:59:37 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 05:59:37 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 05:59:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:59:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:59:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:59:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:59:38 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 05:59:38 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 05:59:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:59:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:59:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:59:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:59:39 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 05:59:39 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 05:59:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:59:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:59:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:59:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:59:39 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 05:59:40 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 05:59:40 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 05:59:41 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 05:59:41 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 05:59:42 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 05:59:42 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 05:59:43 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 05:59:43 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 05:59:44 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 05:59:44 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 05:59:45 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 05:59:45 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 05:59:46 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 05:59:46 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 05:59:47 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 05:59:47 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 05:59:47 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 05:59:48 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 05:59:48 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 05:59:49 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 05:59:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:59:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:59:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 05:59:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 05:59:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 05:59:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 05:59:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:59:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:59:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:59:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:59:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:59:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:59:49 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:59:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3169 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:59:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3170 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:59:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3170 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:59:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3170 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:59:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3170 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:59:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3170 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:59:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3170 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:59:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3170 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:59:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3170 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:59:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:59:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:59:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:59:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:59:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:59:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:59:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:59:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:59:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:59:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:59:54 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:59:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:59:54 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 05:59:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 05:59:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:59:59 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 05:59:59 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:59:59 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 05:59:59 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:59:59 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 05:59:59 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:59:59 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 05:59:59 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 05:59:59 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 05:59:59 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 05:59:59 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 05:59:59 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 05:59:59 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 05:59:59 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 05:59:59 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 05:59:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 05:59:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 05:59:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:00:00 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:00:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:00:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:00:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:00:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:00:00 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:00:01 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:00:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:00:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:00:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:00:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:00:01 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:00:02 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:00:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:00:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:00:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:00:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:00:02 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:00:03 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:00:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:00:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:00:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:00:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:00:03 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:00:04 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:00:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:00:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:00:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:00:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:00:04 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:00:05 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:00:05 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:00:06 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:00:06 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:00:06 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:00:07 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:00:07 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:00:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:00:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:00:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:00:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:00:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:00:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:00:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:00:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:00:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:00:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:00:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:00:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:00:08 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:00:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:00:13 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:00:13 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:00:13 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:00:13 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:00:13 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:00:13 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:00:13 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:00:13 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:00:13 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:00:13 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:00:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:00:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:00:13 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:00:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:00:18 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:00:18 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:00:18 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:00:18 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:00:18 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:00:18 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:00:18 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:00:18 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:00:18 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:00:18 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:18 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:00:18 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:00:18 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:00:18 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:00:18 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:00:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:00:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:00:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:00:19 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:00:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:00:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:00:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:00:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:00:19 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:00:19 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:00:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:00:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:00:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:00:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:00:20 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:00:20 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:00:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:00:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:00:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:00:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:00:21 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:00:21 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:00:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:00:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:00:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:00:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:00:22 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:00:22 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:00:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:00:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:00:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:00:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:00:23 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:00:23 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:00:24 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:00:24 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:00:25 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:00:25 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:00:26 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:00:26 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:00:27 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:00:27 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:00:27 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:00:28 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:00:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:00:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:00:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:00:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:00:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:00:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:00:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:00:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:00:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:00:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:00:28 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:00:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:00:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:00:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2299 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:00:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2299 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:00:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2299 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:00:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2299 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:00:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2299 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:00:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2299 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:00:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2299 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:00:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2299 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:00:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:00:33 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:00:33 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:00:33 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:00:33 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:00:33 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:00:33 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:00:33 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:00:33 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:00:33 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:00:33 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:33 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:00:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:00:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:00:33 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:00:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:00:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:00:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:00:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:00:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:00:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:00:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:00:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:00:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:00:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:00:38 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:38 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:39 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:00:39 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:00:39 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:00:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:00:39 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:00:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:00:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:00:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:00:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:00:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:00:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:00:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:00:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:00:39 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:00:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:00:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:00:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:00:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:00:40 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:00:40 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:00:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:00:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:00:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:00:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:00:41 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:00:41 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:00:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:00:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:00:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:00:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:00:42 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:00:42 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:00:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:00:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:00:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:00:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:00:43 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:00:43 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:00:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:00:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:00:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:00:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:00:44 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:00:44 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:00:45 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:00:45 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:00:45 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:00:46 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:00:46 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:00:47 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:00:47 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:00:48 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:00:48 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:00:49 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:00:49 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:00:50 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:00:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:00:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:00:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:00:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:00:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:00:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:00:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:00:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:00:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:00:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:00:50 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2488 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:00:50 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2488 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:00:50 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2488 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:00:50 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2488 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:00:50 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2488 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:00:50 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2488 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:00:50 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2488 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:00:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:00:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:00:50 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:00:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:00:55 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:00:55 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:00:55 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:00:55 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:00:55 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:00:55 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:00:55 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:00:55 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:00:55 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:00:55 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:55 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:00:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:00:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:00:55 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:01:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:01:00 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:01:00 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:01:00 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:01:00 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:01:00 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:01:00 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:01:00 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:01:00 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:01:00 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:01:00 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:00 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:01 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:01:01 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:01:01 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:01:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:01:01 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:01:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:01:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:01:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:01:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:01:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:01:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:01:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:01:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:01:01 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:01:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:01:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:01:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:01:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:01:02 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:01:02 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:01:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:01:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:01:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:01:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:01:02 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:01:03 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:01:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:01:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:01:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:01:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:01:03 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:01:04 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:01:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:01:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:01:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:01:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:01:04 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:01:05 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:01:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:01:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:01:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:01:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:01:05 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:01:06 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:01:06 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:01:07 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:01:07 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:01:08 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:01:08 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:01:09 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:01:09 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:01:10 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:01:10 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:01:10 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:01:11 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:01:11 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:01:12 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:01:12 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:01:13 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:01:13 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:01:14 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:01:14 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:01:15 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:01:15 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:01:16 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:01:16 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 06:01:17 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 06:01:17 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 06:01:17 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 06:01:18 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 06:01:18 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 06:01:19 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 06:01:19 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 06:01:20 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 06:01:20 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 06:01:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:01:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:01:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:01:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:01:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:01:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:01:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:01:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:01:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:01:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:01:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:01:21 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:01:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:01:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:01:26 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:01:26 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:01:26 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:01:26 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:01:26 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:01:26 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:01:26 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:01:26 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:01:26 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:01:26 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:01:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:01:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:01:26 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:01:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:01:31 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:01:31 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:01:31 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:01:31 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:01:31 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:01:31 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:01:31 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:01:31 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:01:31 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:01:31 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:31 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:01:31 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:01:31 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:01:31 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:01:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:01:31 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:01:32 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:01:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:01:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:01:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:01:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:01:32 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:01:33 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:01:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:01:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:01:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:01:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:01:33 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:01:34 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:01:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:01:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:01:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:01:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:01:34 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:01:35 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:01:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:01:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:01:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:01:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:01:35 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:01:35 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:01:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:01:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:01:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:01:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:01:36 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:01:36 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:01:37 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:01:37 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:01:38 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:01:38 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:01:39 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:01:39 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:01:40 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:01:40 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:01:41 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:01:41 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:01:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:01:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:01:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:01:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:01:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:01:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:01:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:01:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:01:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:01:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:01:41 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:01:41 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2295 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:01:41 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2295 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:01:41 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2295 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:01:41 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2295 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:01:41 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2295 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:01:41 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2295 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:01:41 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2295 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:01:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:01:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:01:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:01:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:01:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:01:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:01:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:01:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:01:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:01:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:01:46 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:01:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:01:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:01:46 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:01:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:01:51 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:01:51 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:01:51 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:01:51 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:01:51 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:01:51 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:01:51 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:01:51 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:01:51 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:01:51 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:01:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:01:51 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:01:52 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:01:52 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:01:52 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:01:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:01:52 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:01:52 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:01:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:01:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:01:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:01:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:01:53 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:01:53 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:01:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:01:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:01:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:01:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:01:54 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:01:54 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:01:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:01:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:01:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:01:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:01:55 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:01:55 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:01:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:01:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:01:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:01:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:01:56 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:01:56 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:01:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:01:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:01:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:01:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:01:57 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:01:57 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:01:57 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:01:58 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:01:58 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:01:59 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:01:59 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:02:00 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:02:00 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:02:01 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:02:01 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:02:02 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:02:02 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:02:03 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:02:03 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:02:04 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:02:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:02:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:02:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:02:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:02:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:02:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:02:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:02:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:02:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:02:04 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:02:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:02:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:02:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:02:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:02:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:02:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:02:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:02:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:02:09 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:02:09 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:02:09 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:02:09 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:02:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:02:09 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:02:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:02:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:02:14 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:02:14 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:02:14 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:02:14 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:02:14 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:02:14 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:02:14 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:02:14 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:02:14 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:02:14 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:14 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:02:14 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:02:15 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:02:15 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:02:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:02:15 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:02:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:02:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:02:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:02:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:02:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:02:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:02:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:02:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:02:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:02:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:02:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:02:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:02:15 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:02:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:02:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:02:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:02:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:02:15 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:02:16 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:02:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:02:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:02:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:02:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:02:16 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:02:17 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:02:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:02:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:02:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:02:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:02:17 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:02:18 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:02:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:02:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:02:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:02:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:02:18 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:02:19 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:02:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:02:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:02:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:02:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:02:19 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:02:20 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:02:20 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:02:21 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:02:21 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:02:22 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:02:22 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:02:22 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:02:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:02:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:02:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:02:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:02:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:02:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:02:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:02:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:02:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:02:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:02:23 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:02:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:02:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:02:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:02:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:02:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:02:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:02:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:02:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:02:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:02:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:02:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:02:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:02:28 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:02:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:02:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:02:28 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:02:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:02:33 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:02:33 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:02:33 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:02:33 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:02:33 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:02:33 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:02:33 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:02:33 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:02:33 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:02:33 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:33 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:02:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:02:33 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:02:33 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:02:33 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:02:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:02:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:02:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:02:34 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:02:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:02:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:02:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:02:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:02:34 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:02:35 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:02:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:02:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:02:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:02:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:02:35 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:02:35 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:02:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:02:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:02:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:02:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:02:36 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:02:36 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:02:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:02:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:02:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:02:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:02:37 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:02:37 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:02:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:02:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:02:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:02:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:02:38 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:02:38 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:02:39 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:02:39 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:02:40 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:02:40 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:02:41 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:02:41 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:02:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:02:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:02:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:02:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:02:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:02:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:02:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:02:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:02:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:02:41 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:02:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:02:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:02:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:02:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:02:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:02:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:02:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:02:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:02:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:02:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:02:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:02:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:02:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:02:46 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:46 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:02:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:02:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:02:46 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:02:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:02:51 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:02:51 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:02:51 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:02:51 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:02:51 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:02:51 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:02:51 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:02:51 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:02:51 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:02:51 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:02:51 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:02:52 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:02:52 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:02:52 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:02:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:02:52 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:02:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:02:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:02:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:02:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:02:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:02:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:02:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:02:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:02:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:02:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:02:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:02:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:02:52 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:02:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:02:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:02:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:02:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:02:53 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:02:53 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:02:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:02:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:02:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:02:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:02:54 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:02:54 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:02:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:02:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:02:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:02:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:02:55 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:02:55 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:02:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:02:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:02:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:02:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:02:56 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:02:56 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:02:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:02:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:02:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:02:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:02:57 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:02:57 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:02:57 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:02:58 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:02:58 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:02:59 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:02:59 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:03:00 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:03:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:03:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:03:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:03:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:03:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:03:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:03:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:03:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:03:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:03:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:03:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:03:00 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:03:00 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1863 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:03:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:03:00 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1863 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:03:00 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1863 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:03:00 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1863 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:03:00 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1864 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:03:00 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1864 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:03:00 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1864 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:03:00 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1864 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:03:00 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1864 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:03:00 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1864 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:03:00 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1864 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:03:00 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1864 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:03:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:03:05 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:03:05 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:03:05 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:03:05 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:03:05 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:03:05 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:03:05 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:03:05 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:03:05 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:03:05 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:03:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:03:05 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:03:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:03:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:03:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:03:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:03:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:03:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:03:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:03:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:03:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:03:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:03:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:03:10 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:03:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:03:11 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:03:11 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:03:11 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:03:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:03:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:03:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:03:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:03:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:03:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:03:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:03:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:03:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:03:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:03:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:03:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:03:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:03:11 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:03:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:03:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:03:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:03:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:03:11 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:03:12 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:03:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:03:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:03:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:03:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:03:12 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:03:13 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:03:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:03:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:03:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:03:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:03:13 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:03:14 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:03:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:03:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:03:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:03:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:03:14 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:03:15 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:03:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:03:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:03:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:03:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:03:15 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:03:16 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:03:16 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:03:17 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:03:17 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:03:17 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:03:18 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:03:18 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:03:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:03:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:03:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:03:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:03:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:03:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:03:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:03:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:03:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:03:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:03:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:03:19 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:03:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1864 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:03:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:03:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1864 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:03:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1864 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:03:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1864 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:03:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1864 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:03:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1864 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:03:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:03:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:03:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:03:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:03:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:03:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:03:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:03:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:03:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:03:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:03:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:03:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:03:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:03:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:03:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:03:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:03:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:03:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:03:24 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:03:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:03:24 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:03:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:03:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:03:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:03:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:03:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:03:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:03:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:03:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:03:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:03:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:03:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:03:29 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:29 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:03:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:03:29 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:03:29 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:03:29 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:03:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:03:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:03:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:03:30 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:03:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:03:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:03:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:03:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:03:30 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:03:31 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:03:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:03:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:03:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:03:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:03:31 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:03:31 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:03:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:03:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:03:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:03:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:03:32 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:03:32 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:03:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:03:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:03:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:03:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:03:33 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:03:33 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:03:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:03:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:03:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:03:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:03:34 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:03:34 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:03:35 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:03:35 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:03:36 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:03:36 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:03:37 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:03:37 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:03:38 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:03:38 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:03:38 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:03:39 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:03:39 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:03:40 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:03:40 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:03:41 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:03:41 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:03:42 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:03:42 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:03:43 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:03:43 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:03:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:03:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:03:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:03:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:03:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:03:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:03:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:03:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:03:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:03:43 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:03:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:03:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:03:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:03:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:03:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:03:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:03:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:03:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:03:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:03:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:03:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:03:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:03:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:03:48 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:03:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:03:48 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:03:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:03:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:03:53 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:03:53 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:03:53 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:03:53 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:03:53 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:03:53 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:03:53 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:03:53 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:03:53 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:03:53 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:03:53 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:03:54 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:03:54 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:03:54 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:03:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:03:54 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:03:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:03:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:03:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:03:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:03:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:03:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:03:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:03:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:03:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:03:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:03:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:03:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:03:54 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:03:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:03:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:03:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:03:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:03:55 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:03:55 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:03:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:03:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:03:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:03:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:03:56 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:03:56 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:03:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:03:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:03:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:03:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:03:57 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:03:57 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:03:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:03:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:03:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:03:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:03:58 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:03:58 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:03:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:03:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:03:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:03:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:03:58 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:03:59 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:03:59 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:04:00 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:04:00 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:04:01 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:04:01 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:04:02 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:04:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:04:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:04:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:04:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:04:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:04:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:04:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:04:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:04:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:04:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:04:02 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:04:02 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:04:02 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:04:02 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:04:02 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:04:02 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:04:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:04:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:04:02 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:04:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:04:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:04:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:04:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:04:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:04:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:04:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:04:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:04:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:04:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:04:07 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:04:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:04:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:04:07 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:04:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:04:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:04:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:04:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:04:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:04:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:04:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:04:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:04:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:04:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:04:12 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:04:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:04:12 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:04:12 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:04:12 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:04:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:04:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:04:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:04:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:04:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:04:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:04:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:04:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:04:13 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:04:14 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:04:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:04:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:04:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:04:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:04:14 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:04:15 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:04:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:04:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:04:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:04:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:04:15 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:04:16 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:04:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:04:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:04:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:04:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:04:16 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:04:17 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:04:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:04:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:04:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:04:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:04:17 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:04:18 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:04:18 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:04:19 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:04:19 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:04:19 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:04:20 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:04:20 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:04:21 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:04:21 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:04:22 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:04:22 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:04:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:04:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:04:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:04:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:04:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:04:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:04:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:04:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:04:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:04:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:04:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:04:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:04:23 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:04:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:04:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:04:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:04:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:04:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:04:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:04:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:04:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:04:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:04:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:04:28 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:04:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:04:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:04:28 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:04:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:04:33 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:04:33 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:04:33 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:04:33 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:04:33 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:04:33 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:04:33 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:04:33 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:04:33 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:04:33 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:33 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:04:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:04:33 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:04:33 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:04:33 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:04:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:04:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:04:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:04:34 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:04:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:04:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:04:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:04:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:04:34 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:04:34 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:04:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:04:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:04:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:04:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:04:35 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:04:35 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:04:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:04:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:04:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:04:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:04:36 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:04:36 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:04:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:04:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:04:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:04:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:04:37 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:04:37 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:04:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:04:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:04:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:04:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:04:38 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:04:38 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:04:39 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:04:39 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:04:40 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:04:40 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:04:41 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:04:41 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:04:42 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:04:42 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:04:42 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:04:43 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:04:43 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:04:44 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:04:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:04:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:04:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:04:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:04:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:04:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:04:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:04:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:04:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:04:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:04:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:04:44 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:04:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:04:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:04:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:04:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:04:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:04:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:04:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:04:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:04:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:04:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:04:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:04:49 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:04:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:04:49 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:04:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:04:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:04:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:04:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:04:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:04:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:04:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:04:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:04:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:04:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:04:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:04:54 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:04:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:04:55 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:04:55 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:04:55 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:04:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:04:55 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:04:55 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:04:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:04:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:04:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:04:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:04:56 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:04:56 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:04:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:04:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:04:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:04:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:04:57 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:04:57 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:04:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:04:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:04:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:04:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:04:58 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:04:58 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:04:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:04:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:04:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:04:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:04:58 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:04:59 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:04:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:04:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:04:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:04:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:04:59 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:05:00 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:05:00 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:05:01 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:05:01 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:05:02 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:05:02 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:05:03 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:05:03 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:05:04 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:05:04 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:05:05 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:05:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:05:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:05:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:05:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:05:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:05:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:05:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:05:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:05:05 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:05:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:05:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:05:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:05:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:05:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:05:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:05:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:05:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:05:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:05:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:05:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:05:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:05:10 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:05:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:05:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:05:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:05:10 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:05:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:05:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:05:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:05:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:05:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:05:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:05:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:05:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:05:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:05:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:05:15 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:05:15 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:05:15 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:05:15 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:05:15 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:05:15 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:05:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:05:16 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:05:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:05:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:05:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:05:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:05:16 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:05:17 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:05:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:05:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:05:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:05:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:05:17 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:05:18 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:05:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:05:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:05:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:05:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:05:18 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:05:19 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:05:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:05:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:05:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:05:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:05:19 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:05:20 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:05:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:05:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:05:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:05:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:05:20 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:05:21 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:05:21 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:05:21 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:05:22 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:05:22 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:05:23 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:05:23 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:05:24 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:05:24 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:05:25 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:05:25 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:05:26 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:05:26 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:05:27 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:05:27 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:05:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:05:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:05:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:05:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:05:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:05:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:05:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:05:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:05:27 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:05:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:05:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:05:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:05:32 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:05:32 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:05:32 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:05:32 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:05:32 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:05:32 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:05:32 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:05:32 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:05:32 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:05:32 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:05:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:05:32 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:05:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:05:33 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:05:33 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:05:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:05:33 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:05:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:05:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:05:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:05:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:05:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:05:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:05:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:05:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:05:33 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:05:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:05:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:05:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:05:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:05:34 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:05:34 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:05:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:05:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:05:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:05:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:05:35 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:05:35 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:05:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:05:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:05:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:05:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:05:36 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:05:36 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:05:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:05:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:05:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:05:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:05:37 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:05:37 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:05:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:05:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:05:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:05:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:05:38 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:05:38 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:05:39 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:05:39 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:05:40 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:05:40 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:05:40 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:05:41 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:05:41 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:05:42 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:05:42 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:05:43 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:05:43 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:05:44 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:05:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:05:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:05:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:05:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:05:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:05:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:05:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:05:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:05:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:05:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:05:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:05:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:05:44 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:05:44 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2518 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:05:44 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2518 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:05:44 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2518 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:05:44 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2518 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:05:44 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2518 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:05:44 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2518 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:05:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:05:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:05:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:05:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:05:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:05:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:05:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:05:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:05:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:05:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:05:49 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:05:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:05:50 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:05:50 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:05:50 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:05:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:05:50 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:05:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:05:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:05:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:05:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:05:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:05:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:05:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:05:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:05:50 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:05:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:05:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:05:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:05:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:05:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:05:51 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:05:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:05:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:05:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:05:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:05:51 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:05:52 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:05:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:05:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:05:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:05:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:05:52 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:05:53 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:05:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:05:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:05:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:05:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:05:53 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:05:54 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:05:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:05:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:05:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:05:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:05:54 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:05:55 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:05:55 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:05:56 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:05:56 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:05:57 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:05:57 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:05:58 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:05:58 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:05:58 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:05:59 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:05:59 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:06:00 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:06:00 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:06:01 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:06:01 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:06:02 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:06:02 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:06:03 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:06:03 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:06:04 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:06:04 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:06:05 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:06:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:06:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:06:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:06:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:06:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:06:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:06:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:06:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:06:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:06:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:06:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:06:05 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:06:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:06:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:06:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:06:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:06:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:06:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:06:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:06:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:06:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:06:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:06:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:06:10 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:06:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:06:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:06:10 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:06:10 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:06:10 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:06:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:06:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:06:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:06:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:06:10 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:06:10 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=126 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:06:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:06:10 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=126 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:06:10 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=126 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:06:10 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=126 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:06:10 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=126 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:06:10 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=126 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:06:10 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=126 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:06:10 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=126 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:06:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:06:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:06:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:06:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:06:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:06:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:06:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:06:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:06:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:06:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:06:15 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:06:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:06:15 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:06:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:06:16 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:06:16 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:06:16 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:06:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:06:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:06:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:06:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:06:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:06:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:06:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:06:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:06:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:06:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:06:16 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:06:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:06:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:06:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:06:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:06:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:06:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:06:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:06:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:06:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:06:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:06:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:06:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:06:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:06:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:06:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:06:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:06:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:06:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:06:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:17 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:06:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:06:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:06:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:06:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:06:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:06:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:06:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:06:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:06:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:06:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:06:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:06:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:06:17 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:06:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:06:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:06:22 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:06:22 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:06:22 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:06:22 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:06:22 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:06:22 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:06:22 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:06:22 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:06:22 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:06:22 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:06:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:06:22 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:06:23 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:06:23 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:06:23 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:06:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:06:23 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:06:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:06:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:06:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:06:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:06:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:06:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:06:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:06:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:06:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:06:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:06:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:06:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:06:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:06:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:23 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:06:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:06:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:06:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:06:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:06:23 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:06:24 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:06:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:06:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:06:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:06:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:06:24 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:06:25 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:06:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:06:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:06:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:06:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:06:25 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:06:26 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:06:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:06:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:06:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:06:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:06:26 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:06:27 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:06:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:06:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:06:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:06:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:06:27 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:06:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:06:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:06:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:06:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:06:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:06:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:06:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:06:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:06:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:06:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:06:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:06:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:28 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:06:28 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:06:29 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:06:29 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:06:30 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:06:30 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:06:31 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:06:31 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:06:31 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:06:32 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:06:32 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:06:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:06:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:06:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:06:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:06:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:06:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:06:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:06:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:06:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:06:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:06:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:06:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:06:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:06:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:06:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:06:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:06:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:33 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:06:33 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:06:34 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:06:34 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:06:35 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:06:35 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:06:36 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:06:36 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:06:37 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:06:37 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:06:38 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:06:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:06:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:06:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:06:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:06:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:06:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:06:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:06:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:06:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:06:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:06:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:06:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:06:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:06:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:06:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:06:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:06:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:38 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 06:06:39 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 06:06:39 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 06:06:39 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 06:06:40 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 06:06:40 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 06:06:41 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 06:06:41 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 06:06:42 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 06:06:42 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 06:06:43 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 06:06:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:06:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:06:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:06:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:06:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:06:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:06:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:06:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:06:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:06:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:06:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:06:43 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:06:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:06:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:06:43 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4520 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:06:43 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4520 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:06:43 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4520 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:06:43 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4520 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:06:43 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4520 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:06:43 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4520 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:06:43 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4520 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:06:43 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4520 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:06:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:06:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:06:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:06:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:06:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:06:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:06:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:06:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:06:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:06:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:06:48 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:06:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:06:48 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:06:48 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:06:48 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:06:48 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:06:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:06:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:06:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:06:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:06:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:06:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:06:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:06:49 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:06:50 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:06:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:06:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:06:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:06:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:06:50 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:06:51 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:06:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:06:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:06:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:06:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:06:51 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:06:52 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:06:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:06:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:06:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:06:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:06:52 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:06:53 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:06:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:06:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:06:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:06:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:06:53 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:06:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:06:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:06:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:06:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:06:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:06:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:06:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:06:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:06:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:06:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:06:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:06:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:06:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:06:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:06:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:06:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:06:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:54 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:06:54 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:06:54 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:06:55 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:06:55 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:06:56 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:06:56 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:06:57 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:06:57 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:06:58 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:06:58 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:06:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:06:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:06:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:06:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:06:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:06:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:06:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:06:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:06:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:06:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:06:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:06:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:06:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:06:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:06:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:06:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:06:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:06:59 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:06:59 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:07:00 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:07:00 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:07:01 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:07:01 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:07:02 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:07:02 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:07:02 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:07:03 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:07:03 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:07:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:07:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:07:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:07:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:07:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:07:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:07:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:07:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:07:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:07:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:07:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:07:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:07:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:07:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:07:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:07:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:07:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:07:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:07:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:07:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:07:04 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 06:07:04 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 06:07:05 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 06:07:05 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 06:07:06 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 06:07:06 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 06:07:07 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 06:07:07 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 06:07:08 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 06:07:08 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 06:07:09 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 06:07:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:07:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:07:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:07:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:07:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:07:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:07:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:07:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:07:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:07:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:07:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:07:09 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:07:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:07:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:07:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:07:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:07:14 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:07:14 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:07:14 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:07:14 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:07:14 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:07:14 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:07:14 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:07:14 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:07:14 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:07:14 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:07:14 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:07:14 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:07:14 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:07:14 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:07:14 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:07:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:07:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:07:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:07:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:07:15 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:07:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:07:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:07:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:07:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:07:15 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:07:16 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:07:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:07:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:07:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:07:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:07:16 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:07:17 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:07:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:07:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:07:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:07:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:07:17 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:07:17 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:07:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:07:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:07:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:07:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:07:18 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:07:18 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:07:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:07:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:07:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:07:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:07:19 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:07:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:07:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:07:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:07:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:07:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:07:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:07:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:07:19 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:07:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:07:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:07:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:07:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:07:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:07:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:07:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:07:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:07:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:07:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:07:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:07:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:07:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:07:20 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:07:20 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:07:21 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:07:21 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:07:22 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:07:22 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:07:23 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:07:23 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:07:24 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:07:24 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:07:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:07:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:07:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:07:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:07:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:07:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:07:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:07:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:07:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:07:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:07:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:07:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:07:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:07:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:07:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:07:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:07:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:07:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:07:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:07:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:07:25 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:07:25 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:07:25 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:07:26 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:07:26 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:07:27 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:07:27 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:07:28 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:07:28 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:07:29 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:07:29 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:07:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:07:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:07:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:07:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:07:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:07:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:07:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:07:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:07:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:07:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:07:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:07:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:07:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:07:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:07:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:07:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:07:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:07:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:07:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:07:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:07:30 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 06:07:30 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 06:07:31 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 06:07:31 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 06:07:32 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 06:07:32 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 06:07:33 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 06:07:33 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 06:07:33 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 06:07:34 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 06:07:34 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 06:07:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:07:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:07:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:07:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:07:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:07:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:07:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:07:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:07:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:07:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:07:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:07:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:07:35 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:07:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:07:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:07:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:07:40 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:07:40 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:07:40 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:07:40 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:07:40 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:07:40 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:07:40 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:07:40 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:07:40 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:07:40 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:07:40 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:07:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:07:40 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:07:40 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:07:40 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:07:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:07:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:07:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:07:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:07:41 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:07:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:07:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:07:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:07:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:07:41 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:07:42 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:07:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:07:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:07:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:07:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:07:42 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:07:42 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:07:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:07:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:07:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:07:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:07:43 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:07:43 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:07:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:07:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:07:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:07:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:07:44 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:07:44 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:07:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:07:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:07:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:07:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:07:45 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:07:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:07:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:07:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:07:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:07:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:07:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:07:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:07:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:07:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:07:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:07:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:07:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:07:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:07:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:07:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:07:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:07:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:07:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:07:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:07:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:07:45 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:07:46 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:07:46 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:07:47 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:07:47 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:07:48 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:07:48 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:07:49 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:07:49 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:07:49 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:07:50 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:07:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:07:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:07:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:07:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:07:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:07:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:07:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:07:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:07:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:07:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:07:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:07:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:07:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:07:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:07:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:07:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:07:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:07:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:07:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:07:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:07:50 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:07:51 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:07:51 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:07:52 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:07:52 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:07:53 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:07:53 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:07:54 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:07:54 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:07:55 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:07:55 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:07:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:07:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:07:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:07:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:07:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:07:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:07:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:07:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:07:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:07:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:07:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:07:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:07:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:07:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:07:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:07:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:07:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:07:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:07:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:07:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:07:56 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 06:07:56 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 06:07:57 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 06:07:57 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 06:07:57 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 06:07:58 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 06:07:58 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 06:07:59 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 06:07:59 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 06:08:00 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 06:08:00 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 06:08:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:08:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:08:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:08:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:08:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:08:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:08:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:08:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:08:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:08:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:08:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:08:00 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:08:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:08:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:08:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:08:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:08:05 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:08:05 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:08:05 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:08:05 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:08:05 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:08:05 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:08:05 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:08:05 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:08:05 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:08:05 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:08:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:08:05 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:08:06 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:08:06 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:08:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:08:06 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:08:06 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:08:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:08:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:08:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:08:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:08:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:08:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:08:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:08:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:08:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:08:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:08:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:08:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:08:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:08:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:08:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:08:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:08:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:08:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:08:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:08:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:08:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:08:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:08:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:08:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:08:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:08:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:08:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:08:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:08:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:08:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:08:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:08:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:08:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:08:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:08:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:08:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:08:06 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:08:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:08:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:08:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:08:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:08:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:08:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:08:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:08:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:08:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:08:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:08:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:08:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:08:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:08:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:08:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:08:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:08:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:08:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:08:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:08:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:08:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:08:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:08:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:08:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:08:07 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:08:07 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:08:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:08:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:08:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:08:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:08:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:08:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:08:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:08:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:08:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:08:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:08:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:08:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:08:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:08:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:08:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:08:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:08:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:08:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:08:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:08:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:08:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:08:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:08:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:08:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:08:08 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:08:08 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:08:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:08:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:08:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:08:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:08:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:08:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:08:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:08:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:08:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:08:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:08:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:08:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:08:08 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:08:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:08:08 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=634 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:08:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:08:08 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=634 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:08:08 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=634 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:08:08 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=634 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:08:08 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=634 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:08:08 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=634 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:08:08 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=634 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:08:08 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=634 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:08:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:08:13 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:08:13 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:08:13 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:08:13 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:08:13 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:08:13 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:08:13 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:08:13 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:08:13 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:08:13 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:08:13 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:08:14 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:08:14 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:08:14 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:08:14 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:08:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:08:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:08:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:08:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:08:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:08:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:08:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:08:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:08:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:08:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:08:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:08:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:08:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:08:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:08:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:08:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:08:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:08:14 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:08:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:08:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:08:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:08:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:08:15 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:08:15 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:08:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:08:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:08:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:08:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:08:16 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:08:16 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:08:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:08:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:08:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:08:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:08:17 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:08:17 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:08:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:08:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:08:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:08:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:08:18 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:08:18 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:08:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:08:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:08:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:08:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:08:19 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:08:19 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:08:20 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:08:20 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:08:20 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:08:21 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:08:21 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:08:22 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:08:22 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:08:23 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:08:23 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:08:24 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:08:24 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:08:25 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:08:25 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:08:26 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:08:26 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:08:27 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:08:27 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:08:27 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:08:28 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:08:28 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:08:29 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:08:29 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 06:08:30 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 06:08:30 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 06:08:31 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 06:08:31 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 06:08:32 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 06:08:32 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 06:08:33 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 06:08:33 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 06:08:34 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 06:08:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:08:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:08:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:08:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:08:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:08:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:08:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:08:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:08:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:08:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:08:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:08:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:08:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:08:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:08:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:08:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:08:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:08:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:08:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:08:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:08:34 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 06:08:35 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 06:08:35 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 06:08:35 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 06:08:36 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 06:08:36 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 06:08:37 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 06:08:37 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 06:08:38 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 06:08:38 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 06:08:39 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 06:08:39 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 06:08:40 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 06:08:40 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 06:08:41 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 06:08:41 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 06:08:42 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 06:08:42 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 06:08:43 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-10-30 06:08:43 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-10-30 06:08:43 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-10-30 06:08:44 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-10-30 06:08:44 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-10-30 06:08:45 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-10-30 06:08:45 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-10-30 06:08:46 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-10-30 06:08:46 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-10-30 06:08:47 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-10-30 06:08:47 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-10-30 06:08:48 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-10-30 06:08:48 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-10-30 06:08:49 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-10-30 06:08:49 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-10-30 06:08:50 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-10-30 06:08:50 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-10-30 06:08:50 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-10-30 06:08:51 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-10-30 06:08:51 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-10-30 06:08:52 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-10-30 06:08:52 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-10-30 06:08:53 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-10-30 06:08:53 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-10-30 06:08:54 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-10-30 06:08:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:08:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:08:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:08:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:08:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:08:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:08:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:08:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:08:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:08:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:08:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:08:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:08:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:08:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:08:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:08:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:08:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:08:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:08:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:08:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:08:54 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-10-30 06:08:55 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-10-30 06:08:55 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-10-30 06:08:56 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-10-30 06:08:56 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-10-30 06:08:57 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2024-10-30 06:08:57 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2024-10-30 06:08:58 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2024-10-30 06:08:58 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2024-10-30 06:08:58 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2024-10-30 06:08:59 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2024-10-30 06:08:59 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2024-10-30 06:09:00 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2024-10-30 06:09:00 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2024-10-30 06:09:01 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2024-10-30 06:09:01 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2024-10-30 06:09:02 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2024-10-30 06:09:02 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2024-10-30 06:09:03 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2024-10-30 06:09:03 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2024-10-30 06:09:04 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2024-10-30 06:09:04 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2024-10-30 06:09:05 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2024-10-30 06:09:05 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2024-10-30 06:09:06 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2024-10-30 06:09:06 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2024-10-30 06:09:06 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2024-10-30 06:09:07 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2024-10-30 06:09:07 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2024-10-30 06:09:08 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2024-10-30 06:09:08 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2024-10-30 06:09:09 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2024-10-30 06:09:09 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2024-10-30 06:09:10 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2024-10-30 06:09:10 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2024-10-30 06:09:11 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2024-10-30 06:09:11 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2024-10-30 06:09:12 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2024-10-30 06:09:12 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2024-10-30 06:09:13 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2024-10-30 06:09:13 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2024-10-30 06:09:13 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2024-10-30 06:09:14 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2024-10-30 06:09:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:09:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:09:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:09:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:09:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:09:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:09:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:09:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:09:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:09:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:09:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:09:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:09:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:09:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:09:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:09:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:09:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:14 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2024-10-30 06:09:15 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2024-10-30 06:09:15 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2024-10-30 06:09:16 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2024-10-30 06:09:16 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2024-10-30 06:09:17 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2024-10-30 06:09:17 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2024-10-30 06:09:18 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2024-10-30 06:09:18 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2024-10-30 06:09:19 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2024-10-30 06:09:19 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2024-10-30 06:09:20 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2024-10-30 06:09:20 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2024-10-30 06:09:21 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2024-10-30 06:09:21 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2024-10-30 06:09:21 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2024-10-30 06:09:22 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2024-10-30 06:09:22 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2024-10-30 06:09:23 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2024-10-30 06:09:23 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2024-10-30 06:09:24 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2024-10-30 06:09:24 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2024-10-30 06:09:25 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2024-10-30 06:09:25 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2024-10-30 06:09:26 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2024-10-30 06:09:26 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2024-10-30 06:09:27 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2024-10-30 06:09:27 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2024-10-30 06:09:28 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2024-10-30 06:09:28 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2024-10-30 06:09:28 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2024-10-30 06:09:29 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2024-10-30 06:09:29 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2024-10-30 06:09:30 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2024-10-30 06:09:30 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2024-10-30 06:09:31 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2024-10-30 06:09:31 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2024-10-30 06:09:32 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2024-10-30 06:09:32 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2024-10-30 06:09:33 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2024-10-30 06:09:33 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2024-10-30 06:09:34 [DEBUG] clck_gen.py:102 IND CLOCK 17442
2024-10-30 06:09:34 [DEBUG] clck_gen.py:102 IND CLOCK 17544
2024-10-30 06:09:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:09:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:09:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:09:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:09:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:09:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:09:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:09:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:09:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:09:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:09:34 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:09:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=17562 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:09:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:09:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:09:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:09:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=17562 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:09:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:09:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:09:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:09:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:09:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:09:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:09:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:09:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:09:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:09:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:09:39 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:09:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:09:39 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:09:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:09:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:09:44 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:09:44 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:09:44 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:09:44 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:09:44 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:09:44 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:09:44 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:09:44 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:09:44 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:09:44 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:09:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:09:44 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:09:45 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:09:45 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:09:45 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:09:45 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:09:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:09:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:09:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:09:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:09:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:09:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:45 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:09:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:09:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:09:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:09:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:09:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:09:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:09:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:46 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:09:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:09:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:09:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:09:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:09:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:09:46 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:09:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:09:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:09:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:09:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:09:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:09:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:09:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:09:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:09:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:09:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:09:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:09:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:09:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:09:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:09:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:09:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:09:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:09:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:09:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:47 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:09:47 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:09:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:09:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:09:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:09:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:09:48 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:09:48 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:09:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:09:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:09:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:09:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:09:49 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:09:49 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:09:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:09:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:09:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:09:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:09:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:09:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:09:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:09:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:09:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:09:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:09:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:09:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:09:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:09:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:09:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:09:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:09:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:09:49 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:09:50 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:09:50 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:09:51 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:09:51 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:09:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:09:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:09:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:09:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:09:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:09:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:09:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:09:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:09:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:09:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:09:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:09:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:09:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:09:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:52 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:09:52 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:09:53 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:09:53 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:09:54 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:09:54 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:09:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:09:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:09:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:09:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:09:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:09:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:09:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:09:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:09:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:09:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:09:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:09:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:09:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:09:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:09:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:09:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:09:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:55 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:09:55 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:09:56 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:09:56 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:09:56 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:09:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:09:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:09:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:09:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:09:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:09:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:09:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:09:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:09:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:09:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:09:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:09:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:09:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:09:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:57 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:09:57 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:09:58 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:09:58 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:09:59 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:09:59 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:09:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:09:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:09:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:09:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:09:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:09:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:09:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:09:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:09:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:09:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:09:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:09:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:09:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:09:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:09:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:00 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:10:00 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 06:10:01 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 06:10:01 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 06:10:02 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 06:10:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:10:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:10:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:10:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:10:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:10:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:10:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:10:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:10:02 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:10:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:10:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:10:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:10:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:10:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:10:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:10:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:10:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:10:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:10:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:10:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:10:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:10:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:10:07 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:10:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:10:07 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:10:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:10:08 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:10:08 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:10:08 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:10:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:10:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:10:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:10:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:10:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:10:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:10:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:10:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:10:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:08 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:10:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:10:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:10:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:10:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:10:08 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:10:09 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:10:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:10:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:10:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:10:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:10:09 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:10:10 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:10:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:10:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:10:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:10:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:10:10 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:10:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:10:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:10:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:10:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:10:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:10:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:10:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:10:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:10:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:10:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:10:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:11 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:10:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:10:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:10:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:10:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:10:11 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:10:12 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:10:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:10:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:10:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:10:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:10:12 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:10:13 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:10:13 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:10:14 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:10:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:10:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:10:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:10:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:10:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:10:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:10:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:10:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:10:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:10:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:10:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:14 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:10:15 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:10:15 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:10:15 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:10:16 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:10:16 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:10:17 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:10:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:10:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:10:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:10:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:10:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:10:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:10:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:10:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:10:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:10:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:10:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:17 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:10:18 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:10:18 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:10:19 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:10:19 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:10:20 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:10:20 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:10:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:10:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:10:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:10:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:10:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:10:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:10:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:10:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:10:20 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:10:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:10:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:10:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:10:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:10:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:10:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:10:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:10:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:10:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:10:26 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:10:26 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:10:26 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:10:26 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:10:26 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:10:26 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:10:26 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:10:26 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:10:26 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:10:26 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:10:26 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:10:26 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:10:26 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:10:26 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:10:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:10:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:10:26 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:10:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:10:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:10:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:10:27 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:10:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:10:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:10:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:10:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:10:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:10:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:10:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:10:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:10:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:10:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:10:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:27 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:10:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:10:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:10:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:10:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:10:28 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:10:28 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:10:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:10:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:10:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:10:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:10:29 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:10:29 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:10:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:10:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:10:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:10:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:10:30 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:10:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:10:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:10:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:10:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:10:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:10:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:10:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:10:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:10:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:10:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:10:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:30 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:10:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:10:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:10:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:10:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:10:31 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:10:31 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:10:32 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:10:32 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:10:33 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:10:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:10:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:10:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:10:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:10:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:10:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:10:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:10:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:10:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:10:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:10:33 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:10:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:10:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:10:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:10:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:10:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:10:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:10:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:10:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:10:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:10:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:10:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:10:38 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:10:38 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:10:38 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:10:38 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:10:38 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:10:38 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:10:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:10:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:10:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:10:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:10:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:10:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:10:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:10:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:39 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:10:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:10:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:10:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:10:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:10:39 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:10:40 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:10:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:10:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:10:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:10:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:10:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:10:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:10:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:10:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:10:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:10:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:10:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:10:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:10:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:10:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:10:40 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:10:41 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:10:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:10:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:10:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:10:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:10:41 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:10:42 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:10:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:10:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:10:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:10:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:10:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:10:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:10:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:10:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:10:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:10:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:10:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:10:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:10:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:10:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:10:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:42 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:10:43 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:10:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:10:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:10:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:10:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:10:43 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:10:44 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:10:44 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:10:45 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:10:45 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:10:45 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:10:46 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:10:46 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:10:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:10:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:10:47 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:10:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:10:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:10:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:10:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:10:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:10:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:10:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:10:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:10:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:47 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:10:48 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:10:48 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:10:49 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:10:49 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:10:50 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:10:50 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:10:51 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:10:51 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:10:52 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:10:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:10:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:10:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:10:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:10:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:10:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:10:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:10:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:10:52 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:10:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:10:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:10:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:10:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:10:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:10:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:10:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:10:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:10:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:10:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:10:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:10:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:10:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:10:57 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:10:57 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:10:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:10:57 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:10:57 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:10:57 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:10:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:58 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:10:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:10:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:10:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:10:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:10:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:10:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:10:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:10:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:10:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:10:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:10:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:10:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:10:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:10:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:10:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:58 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:10:59 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:10:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:10:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:10:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:10:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:10:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:10:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:10:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:10:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:10:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:10:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:10:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:10:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:10:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:10:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:10:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:10:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:10:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:10:59 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:11:00 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:11:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:11:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:11:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:11:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:11:00 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:11:01 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:11:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:11:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:11:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:11:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:11:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:11:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:11:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:11:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:11:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:11:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:11:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:11:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:11:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:11:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:11:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:11:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:11:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:11:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:11:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:11:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:11:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:01 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:11:01 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:11:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:11:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:11:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:11:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:11:02 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:11:02 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:11:03 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:11:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:11:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:11:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:11:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:11:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:11:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:11:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:11:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:11:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:11:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:11:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:11:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:11:03 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:11:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:11:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:11:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:11:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:11:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:11:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:11:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:11:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:11:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:11:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:11:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:11:08 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:11:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:11:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:11:08 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:11:09 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:11:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:11:09 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:11:09 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:11:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:11:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:11:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:11:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:11:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:11:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:11:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:11:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:11:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:11:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:11:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:11:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:11:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:11:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:09 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:11:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:11:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:11:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:11:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:11:09 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:11:10 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:11:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:11:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:11:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:11:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:11:10 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:11:11 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:11:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:11:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:11:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:11:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:11:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:11:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:11:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:11:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:11:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:11:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:11:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:11:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:11:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:11:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:11:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:11:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:11:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:11:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:11:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:11:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:11:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:11 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:11:12 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:11:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:11:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:11:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:11:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:11:12 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:11:13 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:11:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:11:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:11:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:11:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:11:13 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:11:14 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:11:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:11:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:11:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:11:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:11:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:11:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:11:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:11:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:11:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:11:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:11:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:11:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:11:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:11:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:11:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:11:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:11:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:14 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:11:15 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:11:15 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:11:16 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:11:16 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:11:16 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:11:17 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:11:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:11:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:11:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:11:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:11:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:11:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:11:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:11:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:11:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:11:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:11:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:11:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:11:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:11:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:11:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:11:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:11:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:17 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:11:18 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:11:18 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:11:19 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:11:19 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:11:20 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:11:20 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:11:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:11:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:11:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:11:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:11:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:11:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:11:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:11:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:11:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:11:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:11:21 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:11:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:11:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:11:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:11:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:11:26 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:11:26 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:11:26 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:11:26 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:11:26 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:11:26 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:11:26 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:11:26 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:11:26 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:11:26 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:11:26 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:11:26 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:11:26 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:11:26 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:11:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:11:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:11:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:11:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:11:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:11:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:11:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:27 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:11:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:11:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:11:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:11:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:11:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:11:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:11:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:11:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:11:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:11:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:11:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:11:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:11:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:11:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:11:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:11:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:11:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:11:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:11:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:11:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:11:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:27 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:11:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:11:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:11:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:11:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:11:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:11:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:11:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:11:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:11:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:11:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:11:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:11:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:11:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:11:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:11:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:11:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:11:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:27 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:11:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:11:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:11:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:11:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:11:28 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:11:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:11:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:11:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:11:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:11:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:11:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:11:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:11:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:11:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:11:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:11:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:11:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:11:28 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:11:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:11:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:11:33 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:11:33 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:11:33 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:11:33 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:11:33 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:11:33 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:11:33 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:11:33 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:11:33 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:11:33 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:11:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:11:33 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:11:34 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:11:34 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:11:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:11:34 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:11:34 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:11:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:11:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:11:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:11:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:11:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:11:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:11:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:11:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:11:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:11:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:11:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:11:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:11:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:11:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:11:34 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:11:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:11:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:11:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:11:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:11:34 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:11:35 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:11:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:11:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:11:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:11:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:11:35 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:11:36 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:11:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:11:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:11:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:11:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:11:36 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:11:37 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:11:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:11:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:11:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:11:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:11:37 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:11:38 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:11:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:11:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:11:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:11:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:11:38 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:11:39 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:11:39 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:11:40 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:11:40 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:11:41 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:11:41 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:11:42 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:11:42 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:11:42 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:11:43 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:11:43 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:11:44 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:11:44 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:11:45 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:11:45 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:11:46 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:11:46 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:11:47 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:11:47 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:11:48 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:11:48 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:11:49 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:11:49 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 06:11:50 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 06:11:50 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 06:11:50 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 06:11:51 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 06:11:51 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 06:11:52 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 06:11:52 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 06:11:53 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 06:11:53 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 06:11:54 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 06:11:54 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 06:11:55 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 06:11:55 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 06:11:56 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 06:11:56 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 06:11:57 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 06:11:57 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 06:11:57 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 06:11:58 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 06:11:58 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 06:11:59 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 06:11:59 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 06:12:00 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 06:12:00 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 06:12:01 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 06:12:01 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 06:12:02 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 06:12:02 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-10-30 06:12:03 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-10-30 06:12:03 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-10-30 06:12:04 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-10-30 06:12:04 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-10-30 06:12:05 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-10-30 06:12:05 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-10-30 06:12:05 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-10-30 06:12:06 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-10-30 06:12:06 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-10-30 06:12:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:12:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:12:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:12:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:12:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:12:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:12:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:12:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:12:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:12:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:12:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:12:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:12:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:12:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:12:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:12:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:12:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:12:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:12:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:12:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:12:07 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-10-30 06:12:07 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-10-30 06:12:08 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-10-30 06:12:08 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-10-30 06:12:09 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-10-30 06:12:09 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-10-30 06:12:10 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-10-30 06:12:10 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-10-30 06:12:11 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-10-30 06:12:11 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-10-30 06:12:12 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-10-30 06:12:12 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-10-30 06:12:13 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-10-30 06:12:13 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-10-30 06:12:13 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-10-30 06:12:14 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-10-30 06:12:14 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-10-30 06:12:15 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-10-30 06:12:15 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-10-30 06:12:16 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-10-30 06:12:16 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2024-10-30 06:12:17 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2024-10-30 06:12:17 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2024-10-30 06:12:18 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2024-10-30 06:12:18 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2024-10-30 06:12:19 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2024-10-30 06:12:19 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2024-10-30 06:12:20 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2024-10-30 06:12:20 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2024-10-30 06:12:20 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2024-10-30 06:12:21 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2024-10-30 06:12:21 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2024-10-30 06:12:22 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2024-10-30 06:12:22 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2024-10-30 06:12:23 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2024-10-30 06:12:23 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2024-10-30 06:12:24 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2024-10-30 06:12:24 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2024-10-30 06:12:25 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2024-10-30 06:12:25 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2024-10-30 06:12:26 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2024-10-30 06:12:26 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2024-10-30 06:12:27 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2024-10-30 06:12:27 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2024-10-30 06:12:28 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2024-10-30 06:12:28 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2024-10-30 06:12:28 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2024-10-30 06:12:29 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2024-10-30 06:12:29 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2024-10-30 06:12:30 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2024-10-30 06:12:30 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2024-10-30 06:12:31 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2024-10-30 06:12:31 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2024-10-30 06:12:32 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2024-10-30 06:12:32 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2024-10-30 06:12:33 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2024-10-30 06:12:33 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2024-10-30 06:12:34 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2024-10-30 06:12:34 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2024-10-30 06:12:35 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2024-10-30 06:12:35 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2024-10-30 06:12:36 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2024-10-30 06:12:36 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2024-10-30 06:12:36 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2024-10-30 06:12:37 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2024-10-30 06:12:37 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2024-10-30 06:12:38 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2024-10-30 06:12:38 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2024-10-30 06:12:39 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2024-10-30 06:12:39 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2024-10-30 06:12:40 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2024-10-30 06:12:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:12:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:12:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:12:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:12:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:12:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:12:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:12:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:12:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:12:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:12:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:12:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:12:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:12:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:12:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:12:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:12:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:12:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:12:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:12:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:12:40 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2024-10-30 06:12:41 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2024-10-30 06:12:41 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2024-10-30 06:12:42 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2024-10-30 06:12:42 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2024-10-30 06:12:43 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2024-10-30 06:12:43 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2024-10-30 06:12:43 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2024-10-30 06:12:44 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2024-10-30 06:12:44 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2024-10-30 06:12:45 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2024-10-30 06:12:45 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2024-10-30 06:12:46 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2024-10-30 06:12:46 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2024-10-30 06:12:47 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2024-10-30 06:12:47 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2024-10-30 06:12:48 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2024-10-30 06:12:48 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2024-10-30 06:12:49 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2024-10-30 06:12:49 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2024-10-30 06:12:50 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2024-10-30 06:12:50 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2024-10-30 06:12:51 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2024-10-30 06:12:51 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2024-10-30 06:12:51 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2024-10-30 06:12:52 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2024-10-30 06:12:52 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2024-10-30 06:12:53 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2024-10-30 06:12:53 [DEBUG] clck_gen.py:102 IND CLOCK 17442
2024-10-30 06:12:54 [DEBUG] clck_gen.py:102 IND CLOCK 17544
2024-10-30 06:12:54 [DEBUG] clck_gen.py:102 IND CLOCK 17646
2024-10-30 06:12:55 [DEBUG] clck_gen.py:102 IND CLOCK 17748
2024-10-30 06:12:55 [DEBUG] clck_gen.py:102 IND CLOCK 17850
2024-10-30 06:12:56 [DEBUG] clck_gen.py:102 IND CLOCK 17952
2024-10-30 06:12:56 [DEBUG] clck_gen.py:102 IND CLOCK 18054
2024-10-30 06:12:57 [DEBUG] clck_gen.py:102 IND CLOCK 18156
2024-10-30 06:12:57 [DEBUG] clck_gen.py:102 IND CLOCK 18258
2024-10-30 06:12:58 [DEBUG] clck_gen.py:102 IND CLOCK 18360
2024-10-30 06:12:58 [DEBUG] clck_gen.py:102 IND CLOCK 18462
2024-10-30 06:12:59 [DEBUG] clck_gen.py:102 IND CLOCK 18564
2024-10-30 06:12:59 [DEBUG] clck_gen.py:102 IND CLOCK 18666
2024-10-30 06:12:59 [DEBUG] clck_gen.py:102 IND CLOCK 18768
2024-10-30 06:13:00 [DEBUG] clck_gen.py:102 IND CLOCK 18870
2024-10-30 06:13:00 [DEBUG] clck_gen.py:102 IND CLOCK 18972
2024-10-30 06:13:01 [DEBUG] clck_gen.py:102 IND CLOCK 19074
2024-10-30 06:13:01 [DEBUG] clck_gen.py:102 IND CLOCK 19176
2024-10-30 06:13:02 [DEBUG] clck_gen.py:102 IND CLOCK 19278
2024-10-30 06:13:02 [DEBUG] clck_gen.py:102 IND CLOCK 19380
2024-10-30 06:13:03 [DEBUG] clck_gen.py:102 IND CLOCK 19482
2024-10-30 06:13:03 [DEBUG] clck_gen.py:102 IND CLOCK 19584
2024-10-30 06:13:04 [DEBUG] clck_gen.py:102 IND CLOCK 19686
2024-10-30 06:13:04 [DEBUG] clck_gen.py:102 IND CLOCK 19788
2024-10-30 06:13:05 [DEBUG] clck_gen.py:102 IND CLOCK 19890
2024-10-30 06:13:05 [DEBUG] clck_gen.py:102 IND CLOCK 19992
2024-10-30 06:13:06 [DEBUG] clck_gen.py:102 IND CLOCK 20094
2024-10-30 06:13:06 [DEBUG] clck_gen.py:102 IND CLOCK 20196
2024-10-30 06:13:07 [DEBUG] clck_gen.py:102 IND CLOCK 20298
2024-10-30 06:13:07 [DEBUG] clck_gen.py:102 IND CLOCK 20400
2024-10-30 06:13:07 [DEBUG] clck_gen.py:102 IND CLOCK 20502
2024-10-30 06:13:08 [DEBUG] clck_gen.py:102 IND CLOCK 20604
2024-10-30 06:13:08 [DEBUG] clck_gen.py:102 IND CLOCK 20706
2024-10-30 06:13:09 [DEBUG] clck_gen.py:102 IND CLOCK 20808
2024-10-30 06:13:09 [DEBUG] clck_gen.py:102 IND CLOCK 20910
2024-10-30 06:13:10 [DEBUG] clck_gen.py:102 IND CLOCK 21012
2024-10-30 06:13:10 [DEBUG] clck_gen.py:102 IND CLOCK 21114
2024-10-30 06:13:11 [DEBUG] clck_gen.py:102 IND CLOCK 21216
2024-10-30 06:13:11 [DEBUG] clck_gen.py:102 IND CLOCK 21318
2024-10-30 06:13:12 [DEBUG] clck_gen.py:102 IND CLOCK 21420
2024-10-30 06:13:12 [DEBUG] clck_gen.py:102 IND CLOCK 21522
2024-10-30 06:13:13 [DEBUG] clck_gen.py:102 IND CLOCK 21624
2024-10-30 06:13:13 [DEBUG] clck_gen.py:102 IND CLOCK 21726
2024-10-30 06:13:14 [DEBUG] clck_gen.py:102 IND CLOCK 21828
2024-10-30 06:13:14 [DEBUG] clck_gen.py:102 IND CLOCK 21930
2024-10-30 06:13:14 [DEBUG] clck_gen.py:102 IND CLOCK 22032
2024-10-30 06:13:15 [DEBUG] clck_gen.py:102 IND CLOCK 22134
2024-10-30 06:13:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:13:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:13:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:13:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:13:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:13:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:13:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:13:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:13:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:13:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:13:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:13:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:13:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:13:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:13:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:13:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:13:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:13:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:13:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:13:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:13:15 [DEBUG] clck_gen.py:102 IND CLOCK 22236
2024-10-30 06:13:16 [DEBUG] clck_gen.py:102 IND CLOCK 22338
2024-10-30 06:13:16 [DEBUG] clck_gen.py:102 IND CLOCK 22440
2024-10-30 06:13:17 [DEBUG] clck_gen.py:102 IND CLOCK 22542
2024-10-30 06:13:17 [DEBUG] clck_gen.py:102 IND CLOCK 22644
2024-10-30 06:13:18 [DEBUG] clck_gen.py:102 IND CLOCK 22746
2024-10-30 06:13:18 [DEBUG] clck_gen.py:102 IND CLOCK 22848
2024-10-30 06:13:19 [DEBUG] clck_gen.py:102 IND CLOCK 22950
2024-10-30 06:13:19 [DEBUG] clck_gen.py:102 IND CLOCK 23052
2024-10-30 06:13:20 [DEBUG] clck_gen.py:102 IND CLOCK 23154
2024-10-30 06:13:20 [DEBUG] clck_gen.py:102 IND CLOCK 23256
2024-10-30 06:13:21 [DEBUG] clck_gen.py:102 IND CLOCK 23358
2024-10-30 06:13:21 [DEBUG] clck_gen.py:102 IND CLOCK 23460
2024-10-30 06:13:22 [DEBUG] clck_gen.py:102 IND CLOCK 23562
2024-10-30 06:13:22 [DEBUG] clck_gen.py:102 IND CLOCK 23664
2024-10-30 06:13:22 [DEBUG] clck_gen.py:102 IND CLOCK 23766
2024-10-30 06:13:23 [DEBUG] clck_gen.py:102 IND CLOCK 23868
2024-10-30 06:13:23 [DEBUG] clck_gen.py:102 IND CLOCK 23970
2024-10-30 06:13:24 [DEBUG] clck_gen.py:102 IND CLOCK 24072
2024-10-30 06:13:24 [DEBUG] clck_gen.py:102 IND CLOCK 24174
2024-10-30 06:13:25 [DEBUG] clck_gen.py:102 IND CLOCK 24276
2024-10-30 06:13:25 [DEBUG] clck_gen.py:102 IND CLOCK 24378
2024-10-30 06:13:26 [DEBUG] clck_gen.py:102 IND CLOCK 24480
2024-10-30 06:13:26 [DEBUG] clck_gen.py:102 IND CLOCK 24582
2024-10-30 06:13:27 [DEBUG] clck_gen.py:102 IND CLOCK 24684
2024-10-30 06:13:27 [DEBUG] clck_gen.py:102 IND CLOCK 24786
2024-10-30 06:13:28 [DEBUG] clck_gen.py:102 IND CLOCK 24888
2024-10-30 06:13:28 [DEBUG] clck_gen.py:102 IND CLOCK 24990
2024-10-30 06:13:29 [DEBUG] clck_gen.py:102 IND CLOCK 25092
2024-10-30 06:13:29 [DEBUG] clck_gen.py:102 IND CLOCK 25194
2024-10-30 06:13:30 [DEBUG] clck_gen.py:102 IND CLOCK 25296
2024-10-30 06:13:30 [DEBUG] clck_gen.py:102 IND CLOCK 25398
2024-10-30 06:13:30 [DEBUG] clck_gen.py:102 IND CLOCK 25500
2024-10-30 06:13:31 [DEBUG] clck_gen.py:102 IND CLOCK 25602
2024-10-30 06:13:31 [DEBUG] clck_gen.py:102 IND CLOCK 25704
2024-10-30 06:13:32 [DEBUG] clck_gen.py:102 IND CLOCK 25806
2024-10-30 06:13:32 [DEBUG] clck_gen.py:102 IND CLOCK 25908
2024-10-30 06:13:33 [DEBUG] clck_gen.py:102 IND CLOCK 26010
2024-10-30 06:13:33 [DEBUG] clck_gen.py:102 IND CLOCK 26112
2024-10-30 06:13:34 [DEBUG] clck_gen.py:102 IND CLOCK 26214
2024-10-30 06:13:34 [DEBUG] clck_gen.py:102 IND CLOCK 26316
2024-10-30 06:13:35 [DEBUG] clck_gen.py:102 IND CLOCK 26418
2024-10-30 06:13:35 [DEBUG] clck_gen.py:102 IND CLOCK 26520
2024-10-30 06:13:36 [DEBUG] clck_gen.py:102 IND CLOCK 26622
2024-10-30 06:13:36 [DEBUG] clck_gen.py:102 IND CLOCK 26724
2024-10-30 06:13:37 [DEBUG] clck_gen.py:102 IND CLOCK 26826
2024-10-30 06:13:37 [DEBUG] clck_gen.py:102 IND CLOCK 26928
2024-10-30 06:13:37 [DEBUG] clck_gen.py:102 IND CLOCK 27030
2024-10-30 06:13:38 [DEBUG] clck_gen.py:102 IND CLOCK 27132
2024-10-30 06:13:38 [DEBUG] clck_gen.py:102 IND CLOCK 27234
2024-10-30 06:13:39 [DEBUG] clck_gen.py:102 IND CLOCK 27336
2024-10-30 06:13:39 [DEBUG] clck_gen.py:102 IND CLOCK 27438
2024-10-30 06:13:40 [DEBUG] clck_gen.py:102 IND CLOCK 27540
2024-10-30 06:13:40 [DEBUG] clck_gen.py:102 IND CLOCK 27642
2024-10-30 06:13:41 [DEBUG] clck_gen.py:102 IND CLOCK 27744
2024-10-30 06:13:41 [DEBUG] clck_gen.py:102 IND CLOCK 27846
2024-10-30 06:13:42 [DEBUG] clck_gen.py:102 IND CLOCK 27948
2024-10-30 06:13:42 [DEBUG] clck_gen.py:102 IND CLOCK 28050
2024-10-30 06:13:43 [DEBUG] clck_gen.py:102 IND CLOCK 28152
2024-10-30 06:13:43 [DEBUG] clck_gen.py:102 IND CLOCK 28254
2024-10-30 06:13:44 [DEBUG] clck_gen.py:102 IND CLOCK 28356
2024-10-30 06:13:44 [DEBUG] clck_gen.py:102 IND CLOCK 28458
2024-10-30 06:13:45 [DEBUG] clck_gen.py:102 IND CLOCK 28560
2024-10-30 06:13:45 [DEBUG] clck_gen.py:102 IND CLOCK 28662
2024-10-30 06:13:45 [DEBUG] clck_gen.py:102 IND CLOCK 28764
2024-10-30 06:13:46 [DEBUG] clck_gen.py:102 IND CLOCK 28866
2024-10-30 06:13:46 [DEBUG] clck_gen.py:102 IND CLOCK 28968
2024-10-30 06:13:47 [DEBUG] clck_gen.py:102 IND CLOCK 29070
2024-10-30 06:13:47 [DEBUG] clck_gen.py:102 IND CLOCK 29172
2024-10-30 06:13:48 [DEBUG] clck_gen.py:102 IND CLOCK 29274
2024-10-30 06:13:48 [DEBUG] clck_gen.py:102 IND CLOCK 29376
2024-10-30 06:13:49 [DEBUG] clck_gen.py:102 IND CLOCK 29478
2024-10-30 06:13:49 [DEBUG] clck_gen.py:102 IND CLOCK 29580
2024-10-30 06:13:50 [DEBUG] clck_gen.py:102 IND CLOCK 29682
2024-10-30 06:13:50 [DEBUG] clck_gen.py:102 IND CLOCK 29784
2024-10-30 06:13:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:13:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:13:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:13:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:13:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:13:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:13:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:13:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:13:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:13:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:13:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:13:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:13:50 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:13:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:13:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:13:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:13:55 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:13:55 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:13:55 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:13:55 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:13:55 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:13:55 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:13:55 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:13:55 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:13:55 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:13:55 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:13:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:13:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:13:55 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:14:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:14:00 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:14:00 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:14:00 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:14:00 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:14:00 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:14:00 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:14:00 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:14:00 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:14:00 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:14:00 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:14:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:14:00 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:14:01 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:14:01 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:14:01 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:14:01 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:14:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:14:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:14:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:14:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:14:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:14:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:14:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:14:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:14:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:14:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:14:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:14:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:14:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:14:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:14:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:14:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:14:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:14:01 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:14:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:14:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:14:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:14:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:14:02 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:14:02 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:14:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:14:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:14:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:14:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:14:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:14:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:14:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:14:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:14:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:14:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:14:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:14:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:14:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:14:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:14:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:14:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:14:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:14:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:14:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:14:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:14:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:14:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:14:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:14:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:14:03 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:14:03 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:14:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:14:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:14:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:14:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:14:04 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:14:04 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:14:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:14:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:14:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:14:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:14:05 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:14:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:14:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:14:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:14:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:14:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:14:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:14:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:14:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:14:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:14:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:14:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:14:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:14:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:14:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:14:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:14:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:14:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:14:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:14:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:14:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:14:05 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:14:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:14:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:14:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:14:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:14:06 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:14:06 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:14:06 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:14:07 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:14:07 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:14:08 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:14:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:14:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:14:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:14:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:14:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:14:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:14:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:14:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:14:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:14:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:14:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:14:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:14:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:14:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:14:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:14:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:14:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:14:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:14:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:14:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:14:08 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:14:09 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:14:09 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:14:10 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:14:10 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:14:11 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:14:11 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:14:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:14:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:14:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:14:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:14:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:14:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:14:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:14:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:14:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:14:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:14:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:14:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:14:11 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:14:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:14:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:14:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:14:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:14:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:14:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:14:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:14:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:14:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:14:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:14:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:14:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:14:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:14:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:14:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:14:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:14:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:14:17 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:14:17 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:14:17 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:14:17 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:14:17 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:14:17 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:14:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:14:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:14:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:14:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:14:17 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:14:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:14:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:14:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:14:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:14:18 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:14:18 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:14:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:14:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:14:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:14:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:14:19 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:14:19 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:14:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:14:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:14:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:14:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:14:20 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:14:20 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:14:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:14:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:14:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:14:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:14:21 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:14:21 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:14:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:14:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:14:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:14:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:14:22 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:14:22 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:14:23 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:14:23 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:14:24 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:14:24 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:14:25 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:14:25 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:14:25 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:14:26 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:14:26 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:14:27 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:14:27 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:14:28 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:14:28 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:14:29 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:14:29 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:14:30 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:14:30 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:14:31 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:14:31 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:14:32 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:14:32 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:14:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:14:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:14:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:14:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:14:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:14:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:14:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:14:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:14:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:14:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:14:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:14:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:14:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:14:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:14:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:14:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:14:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:14:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:14:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:14:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:14:33 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 06:14:33 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 06:14:33 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 06:14:34 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 06:14:34 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 06:14:35 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 06:14:35 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 06:14:36 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 06:14:36 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 06:14:37 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 06:14:37 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 06:14:38 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 06:14:38 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 06:14:39 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 06:14:39 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 06:14:40 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 06:14:40 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 06:14:40 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 06:14:41 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 06:14:41 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 06:14:42 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 06:14:42 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 06:14:43 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 06:14:43 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 06:14:44 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 06:14:44 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 06:14:45 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 06:14:45 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 06:14:46 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-10-30 06:14:46 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-10-30 06:14:47 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-10-30 06:14:47 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-10-30 06:14:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:14:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:14:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:14:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:14:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:14:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:14:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:14:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:14:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:14:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:14:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:14:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:14:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:14:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:14:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:14:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:14:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:14:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:14:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:14:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:14:48 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-10-30 06:14:48 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-10-30 06:14:48 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-10-30 06:14:49 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-10-30 06:14:49 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-10-30 06:14:50 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-10-30 06:14:50 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-10-30 06:14:51 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-10-30 06:14:51 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-10-30 06:14:52 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-10-30 06:14:52 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-10-30 06:14:53 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-10-30 06:14:53 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-10-30 06:14:54 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-10-30 06:14:54 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-10-30 06:14:55 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-10-30 06:14:55 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-10-30 06:14:56 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-10-30 06:14:56 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-10-30 06:14:56 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-10-30 06:14:57 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-10-30 06:14:57 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-10-30 06:14:58 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-10-30 06:14:58 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-10-30 06:14:59 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-10-30 06:14:59 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-10-30 06:15:00 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2024-10-30 06:15:00 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2024-10-30 06:15:01 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2024-10-30 06:15:01 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2024-10-30 06:15:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:15:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:15:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:15:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:15:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:15:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:15:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:15:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:15:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:15:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:15:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:15:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:15:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:15:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:15:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:15:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:15:02 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2024-10-30 06:15:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:15:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:15:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:15:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:15:02 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2024-10-30 06:15:03 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2024-10-30 06:15:03 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2024-10-30 06:15:03 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2024-10-30 06:15:04 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2024-10-30 06:15:04 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2024-10-30 06:15:05 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2024-10-30 06:15:05 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2024-10-30 06:15:06 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2024-10-30 06:15:06 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2024-10-30 06:15:07 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2024-10-30 06:15:07 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2024-10-30 06:15:08 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2024-10-30 06:15:08 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2024-10-30 06:15:09 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2024-10-30 06:15:09 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2024-10-30 06:15:10 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2024-10-30 06:15:10 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2024-10-30 06:15:11 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2024-10-30 06:15:11 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2024-10-30 06:15:11 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2024-10-30 06:15:12 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2024-10-30 06:15:12 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2024-10-30 06:15:13 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2024-10-30 06:15:13 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2024-10-30 06:15:14 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2024-10-30 06:15:14 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2024-10-30 06:15:15 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2024-10-30 06:15:15 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2024-10-30 06:15:16 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2024-10-30 06:15:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:15:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:15:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:15:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:15:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:15:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:15:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:15:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:15:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:15:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:15:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:15:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:15:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:15:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:15:16 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:15:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:15:21 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:15:21 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:15:21 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:15:21 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:15:21 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:15:21 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:15:21 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:15:21 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:15:21 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:15:21 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:15:21 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:15:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:15:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:15:21 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:15:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:15:26 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:15:26 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:15:26 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:15:26 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:15:26 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:15:26 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:15:26 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:15:26 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:15:26 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:15:26 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:15:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:15:26 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:15:27 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:15:27 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:15:27 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:15:27 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:15:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:15:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:15:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:15:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:15:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:15:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:15:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:15:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:15:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:15:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:15:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:15:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:15:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:15:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:15:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:15:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:15:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:15:27 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:15:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:15:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:15:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:15:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:15:28 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:15:28 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:15:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:15:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:15:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:15:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:15:29 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:15:29 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:15:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:15:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:15:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:15:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:15:30 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:15:30 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:15:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:15:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:15:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:15:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:15:30 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:15:31 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:15:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:15:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:15:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:15:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:15:31 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:15:32 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:15:32 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:15:33 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:15:33 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:15:34 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:15:34 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:15:35 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:15:35 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:15:36 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:15:36 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:15:37 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:15:37 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:15:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:15:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:15:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:15:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:15:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:15:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:15:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:15:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:15:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:15:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:15:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:15:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:15:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:15:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:15:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:15:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:15:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:15:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:15:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:15:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:15:38 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:15:38 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:15:38 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:15:39 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:15:39 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:15:40 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:15:40 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:15:41 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:15:41 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:15:42 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:15:42 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 06:15:43 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 06:15:43 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 06:15:44 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 06:15:44 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 06:15:45 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 06:15:45 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 06:15:45 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 06:15:46 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 06:15:46 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 06:15:47 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 06:15:47 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 06:15:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:15:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:15:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:15:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:15:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:15:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:15:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:15:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:15:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:15:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:15:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:15:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:15:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:15:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:15:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:15:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:15:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:15:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:15:48 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 06:15:48 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 06:15:49 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 06:15:49 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 06:15:50 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 06:15:50 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 06:15:51 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 06:15:51 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 06:15:52 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 06:15:52 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 06:15:53 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 06:15:53 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 06:15:53 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 06:15:54 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 06:15:54 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 06:15:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:15:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:15:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:15:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:15:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:15:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:15:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:15:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:15:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:15:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:15:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:15:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:15:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:15:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:15:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:15:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:15:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:15:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:15:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:15:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:15:55 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 06:15:55 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-10-30 06:15:56 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-10-30 06:15:56 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-10-30 06:15:57 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-10-30 06:15:57 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-10-30 06:15:58 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-10-30 06:15:58 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-10-30 06:15:59 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-10-30 06:15:59 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-10-30 06:16:00 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-10-30 06:16:00 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-10-30 06:16:01 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-10-30 06:16:01 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-10-30 06:16:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:16:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:16:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:16:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:16:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:16:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:16:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:16:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:16:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:16:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:16:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:16:01 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:16:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:16:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:16:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:16:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:16:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:16:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:16:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:16:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:16:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:16:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:16:06 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:16:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:16:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:16:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:16:07 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:16:07 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:16:07 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:16:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:16:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:16:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:16:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:16:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:16:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:16:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:16:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:16:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:16:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:16:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:16:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:16:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:16:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:16:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:16:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:16:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:16:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:16:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:16:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:16:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:07 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:16:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:16:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:16:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:16:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:16:08 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:16:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:16:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:16:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:16:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:16:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:16:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:16:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:16:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:16:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:16:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:16:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:08 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:16:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:16:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:16:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:16:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:16:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:16:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:16:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:16:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:16:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:16:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:16:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:16:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:16:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:16:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:16:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:09 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:16:09 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:16:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:16:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:16:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:16:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:16:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:16:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:16:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:16:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:16:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:16:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:16:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:16:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:16:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:16:10 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:16:10 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=684 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:16:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:16:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:16:10 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=684 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:16:10 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=684 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:16:10 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=684 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:16:10 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=684 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:16:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:16:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:16:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:16:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:16:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:16:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:16:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:16:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:16:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:16:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:16:15 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:16:15 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:16:15 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:16:15 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:16:15 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:16:15 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:16:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:16 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:16:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:16:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:16:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:16:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:16:16 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:16:17 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:16:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:16:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:16:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:16:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:16:17 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:16:17 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:16:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:16:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:16:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:16:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:16:18 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:16:18 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:16:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:16:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:16:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:16:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:16:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:16:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:16:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:16:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:16:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:16:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:16:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:16:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:16:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:16:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:16:19 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:16:19 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:16:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:16:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:16:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:16:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:16:20 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:16:20 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:16:21 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:16:21 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:16:22 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:16:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:16:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:16:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:16:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:16:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:16:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:16:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:16:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:16:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:16:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:16:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:22 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:16:23 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:16:23 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:16:24 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:16:24 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:16:25 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:16:25 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:16:25 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:16:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:16:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:16:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:16:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:16:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:16:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:16:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:16:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:16:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:16:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:16:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:26 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:16:26 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:16:27 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:16:27 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:16:28 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:16:28 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:16:29 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:16:29 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:16:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:16:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:16:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:16:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:16:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:16:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:16:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:16:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:16:29 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:16:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:16:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:16:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:16:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:16:34 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:16:34 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:16:34 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:16:34 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:16:34 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:16:34 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:16:34 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:16:34 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:16:34 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:16:34 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:16:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:16:34 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:16:35 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:16:35 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:16:35 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:16:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:16:35 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:16:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:16:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:16:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:16:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:16:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:16:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:16:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:16:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:16:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:16:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:35 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:16:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:16:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:16:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:16:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:16:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:16:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:16:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:16:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:16:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:16:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:16:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:16:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:16:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:16:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:16:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:36 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:16:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:16:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:16:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:16:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:16:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:16:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:16:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:16:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:16:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:16:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:16:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:36 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:16:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:16:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:16:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:16:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:16:37 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:16:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:16:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:16:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:16:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:16:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:16:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:16:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:16:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:16:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:16:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:16:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:37 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:16:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:16:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:16:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:16:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:16:38 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:16:38 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:16:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:16:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:16:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:16:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:16:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:16:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:16:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:16:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:16:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:16:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:16:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:16:38 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:16:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:16:43 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:16:43 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:16:43 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:16:43 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:16:43 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:16:43 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:16:43 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:16:43 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:16:43 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:16:43 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:16:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:16:43 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:16:44 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:16:44 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:16:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:16:44 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:16:44 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:16:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:16:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:16:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:16:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:16:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:16:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:16:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:16:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:16:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:16:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:44 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:16:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:16:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:16:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:16:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:16:45 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:16:45 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:16:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:16:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:16:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:16:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:16:46 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:16:46 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:16:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:16:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:16:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:16:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:16:47 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:16:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:16:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:16:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:16:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:16:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:16:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:16:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:16:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:16:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:16:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:16:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:47 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:16:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:16:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:16:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:16:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:16:47 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:16:48 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:16:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:16:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:16:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:16:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:16:48 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:16:49 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:16:49 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:16:50 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:16:50 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:16:51 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:16:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:16:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:51 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:16:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:16:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:16:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:16:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:16:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:16:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:16:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:16:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:16:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:16:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:52 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:16:52 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:16:53 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:16:53 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:16:54 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:16:54 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:16:55 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:16:55 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:16:55 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:16:56 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:16:56 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:16:57 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:16:57 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:16:58 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:16:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:16:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:16:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:16:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:16:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:16:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:16:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:16:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:16:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:16:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:16:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:16:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:16:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:16:58 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:16:59 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:16:59 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 06:17:00 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 06:17:00 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 06:17:01 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 06:17:01 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 06:17:02 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 06:17:02 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 06:17:02 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 06:17:03 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 06:17:03 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 06:17:04 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 06:17:04 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 06:17:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:17:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:17:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:17:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:17:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:17:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:17:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:17:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:17:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:17:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:17:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:17:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:17:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:17:05 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:17:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:17:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:17:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:17:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:17:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:17:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:17:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:17:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:17:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:17:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:17:10 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:17:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:17:10 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:17:10 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:10 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:17:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:17:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:17:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:17:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:17:11 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:17:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:17:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:17:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:17:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:17:11 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:17:12 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:17:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:17:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:17:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:17:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:17:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:17:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:17:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:17:12 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:17:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:17:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:17:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:17:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:17:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:17:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:17:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:17:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:17:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:17:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:17:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:17:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:17:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:17:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:17:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:17:13 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:17:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:17:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:17:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:17:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:17:13 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:17:13 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:17:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:17:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:17:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:17:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:17:14 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:17:14 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:17:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:17:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:17:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:17:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:17:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:17:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:17:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:17:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:17:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:17:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:17:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:17:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:17:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:17:15 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:17:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:17:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:17:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:17:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:17:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:17:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:17:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:17:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:17:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:17:15 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:17:16 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:17:16 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:17:17 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:17:17 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:17:18 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:17:18 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:17:19 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:17:19 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:17:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:17:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:17:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:17:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:17:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:17:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:17:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:17:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:17:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:17:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:17:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:17:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:17:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:17:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:17:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:17:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:17:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:17:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:17:20 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:17:20 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:17:21 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:17:21 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:17:21 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:17:22 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:17:22 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:17:23 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:17:23 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:17:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:17:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:17:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:17:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:17:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:17:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:17:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:17:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:17:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:17:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:17:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:17:24 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:17:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:17:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:17:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:17:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:17:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:17:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:17:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:17:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:17:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:17:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:17:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:17:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:17:29 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:29 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:17:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:17:29 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:17:29 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:17:29 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:30 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:17:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:17:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:17:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:17:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:17:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:30 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:17:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:17:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:17:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:17:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:17:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:17:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:17:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:17:31 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:17:31 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=404 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:17:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:17:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:17:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:17:31 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=404 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:17:31 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=404 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:17:31 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=404 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:17:31 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=404 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:17:31 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=404 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:17:31 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=404 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:17:31 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=404 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:17:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:17:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:17:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:17:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:17:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:17:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:17:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:17:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:17:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:17:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:17:36 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:36 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:17:36 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:17:36 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:36 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:17:36 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:37 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:17:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:17:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:17:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:17:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:17:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:37 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:17:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:38 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:17:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:17:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:17:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:17:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:17:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:17:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:17:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:17:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:17:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:17:38 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:17:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:17:38 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=421 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:17:38 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=421 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:17:38 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=421 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:17:38 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=421 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:17:38 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=421 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:17:38 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=421 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:17:38 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=421 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:17:38 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=421 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:17:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:17:43 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:17:43 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:17:43 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:17:43 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:17:43 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:17:43 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:17:43 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:17:43 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:17:43 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:17:43 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:43 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:17:43 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:17:43 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:17:43 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:43 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:44 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:17:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:17:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:17:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:17:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:17:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:44 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:17:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:44 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:17:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:17:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:17:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:17:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:17:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:17:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:17:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:17:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:17:44 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:17:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:17:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:17:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:17:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:17:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:17:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:17:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:17:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:17:50 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:17:50 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:17:50 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:17:50 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:17:50 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:17:50 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:17:50 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:17:50 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:17:50 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:17:50 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:50 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:17:50 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:17:50 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:17:50 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:50 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:50 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:17:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:17:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:17:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:17:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:17:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:51 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:17:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:17:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:17:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:17:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:17:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:17:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:17:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:17:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:17:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:17:51 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:17:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:17:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:17:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:17:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:17:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:17:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:17:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:17:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:17:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:17:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:17:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:17:56 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:17:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:17:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:17:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:17:57 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:17:57 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:17:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:57 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:17:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:17:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:57 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:17:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:17:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:17:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:17:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:17:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:58 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:17:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:17:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:17:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:17:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:17:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:17:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:17:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:17:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:17:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:17:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:17:58 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:17:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:18:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:18:03 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:18:03 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:18:03 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:18:03 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:18:03 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:18:03 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:18:03 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:18:03 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:18:03 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:18:03 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:03 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:18:04 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:18:04 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:18:04 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:18:04 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:18:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:04 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:18:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:18:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:18:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:18:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:18:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:05 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:18:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:05 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:18:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:18:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:18:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:18:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:18:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:18:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:18:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:18:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:18:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:18:05 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:18:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:18:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:18:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:18:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:18:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:18:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:18:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:18:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:18:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:18:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:18:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:18:10 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:18:11 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:18:11 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:18:11 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:18:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:11 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:18:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:11 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:18:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:18:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:18:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:18:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:18:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:12 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:18:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:18:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:18:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:18:12 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:18:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:18:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:18:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:18:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:18:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:18:12 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:18:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:18:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:18:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:18:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:18:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:18:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:18:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:18:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:18:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:18:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:18:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:18:17 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:17 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:18:18 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:18:18 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:18:18 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:18:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:18 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:18:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:18:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:18:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:18:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:18:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:18:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:18:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:18:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:18:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:18:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:18:18 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:18:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:18:23 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:18:23 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:18:23 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:18:23 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:18:23 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:18:23 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:18:23 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:18:23 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:18:23 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:18:23 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:23 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:18:23 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:18:23 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:18:23 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:23 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:18:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:18:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:18:24 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:18:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:18:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:18:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:18:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:18:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:18:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:18:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:18:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:18:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:18:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:18:29 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:29 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:18:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:18:29 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:18:29 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:29 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:18:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:18:29 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:18:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:18:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:18:34 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:18:34 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:18:34 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:18:34 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:18:34 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:18:34 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:18:34 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:18:34 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:18:34 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:18:34 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:34 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:18:35 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:18:35 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:18:35 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:18:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:35 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:18:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:18:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:18:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:18:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:18:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:18:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:18:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:18:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:18:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:18:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:18:35 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:18:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:18:40 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:18:40 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:18:40 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:18:40 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:18:40 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:18:40 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:18:40 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:18:40 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:18:40 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:18:40 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:40 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:18:41 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:18:41 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:18:41 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:18:41 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:18:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:18:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:18:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:18:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:18:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:18:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:18:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:18:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:18:41 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:18:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:18:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:18:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:18:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:18:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:18:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:18:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:18:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:18:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:18:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:18:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:18:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:18:46 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:46 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:18:46 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:18:46 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:18:46 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:46 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:18:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:18:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:18:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:18:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:18:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:18:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:18:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:18:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:18:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:18:47 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:18:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:18:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:18:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:18:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:18:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:18:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:18:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:18:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:18:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:18:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:18:52 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:52 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:18:52 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:18:52 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:18:52 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:52 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:18:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:18:52 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:18:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:18:52 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=152 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:18:52 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=152 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:18:52 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=152 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:18:52 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=152 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:18:52 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=152 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:18:52 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=152 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:18:52 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=152 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:18:52 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=152 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:18:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:18:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:18:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:18:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:18:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:18:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:18:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:18:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:18:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:18:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:18:57 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:18:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:18:57 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:18:58 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:18:58 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:18:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:18:58 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:18:58 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:18:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:18:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:18:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:18:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:18:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:18:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:18:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:18:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:18:58 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:18:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:18:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:18:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:18:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:18:59 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:18:59 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:18:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:18:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:18:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:18:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:19:00 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:19:00 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:19:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:19:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:19:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:19:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:19:01 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:19:01 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:19:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:19:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:19:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:19:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:19:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:19:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:19:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:19:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:19:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:19:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:19:01 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:19:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:19:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:19:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:19:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:19:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:19:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:19:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:19:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:19:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:19:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:19:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:19:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:19:06 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:19:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:19:07 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:19:07 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:19:07 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:19:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:19:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:19:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:19:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:19:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:19:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:19:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:19:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:19:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:19:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:19:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:19:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:19:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:19:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:19:07 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:19:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:19:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:19:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:19:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:19:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:19:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:19:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:19:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:19:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:19:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:19:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:19:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:19:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:19:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:19:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:19:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:19:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:19:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:19:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:19:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:19:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:19:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:19:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:19:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:19:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:19:07 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:19:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=237 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:19:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:19:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=237 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:19:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=237 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:19:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=237 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:19:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=237 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:19:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=237 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:19:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=237 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:19:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=237 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:19:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:19:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:19:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:19:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:19:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:19:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:19:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:19:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:19:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:19:13 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:19:13 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:19:13 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:19:13 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:19:13 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:19:13 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:19:13 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:19:13 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:19:13 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:13 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:19:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:19:13 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:19:13 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:19:13 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:19:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:19:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:19:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:19:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:19:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:19:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:19:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:19:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:19:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:19:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:19:14 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:19:14 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:19:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:19:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:19:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:19:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:19:15 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:19:15 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:19:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:19:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:19:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:19:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:19:16 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:19:16 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:19:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:19:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:19:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:19:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:19:17 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:19:17 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:19:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:19:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:19:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:19:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:19:18 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:19:18 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:19:19 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:19:19 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:19:20 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:19:20 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:19:21 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:19:21 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:19:21 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:19:22 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:19:22 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:19:23 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:19:23 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:19:24 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:19:24 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:19:25 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:19:25 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:19:26 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:19:26 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:19:27 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:19:27 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:19:28 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:19:28 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:19:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:19:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:19:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:19:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:19:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:19:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:19:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:19:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:19:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:19:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:19:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:19:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:19:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:19:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:19:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:19:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:19:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:19:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:19:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:19:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:19:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:19:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:19:28 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:19:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3440 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:19:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3440 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:19:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3440 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:19:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3440 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:19:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3440 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:19:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3440 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:19:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3440 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:19:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3440 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:19:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:19:33 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:19:33 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:19:33 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:19:33 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:19:33 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:19:33 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:19:33 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:19:33 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:19:33 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:19:33 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:33 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:19:34 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:19:34 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:19:34 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:19:34 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:19:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:19:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:19:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:19:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:19:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:19:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:19:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:19:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:19:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:19:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:19:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:19:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:19:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:19:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:19:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:19:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:19:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:19:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:19:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:19:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:19:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:19:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:19:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:19:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:19:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:19:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:19:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:19:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:19:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:19:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:19:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:19:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:19:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:19:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:19:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:19:34 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:19:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:19:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:19:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:19:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=196 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:19:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=196 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:19:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=196 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:19:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=196 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:19:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=196 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:19:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=196 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:19:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=196 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:19:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=196 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:19:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:19:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:19:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:19:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:19:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:19:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:19:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:19:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:19:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:19:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:19:39 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:19:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:19:40 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:19:40 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:19:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:19:40 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:19:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:19:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:19:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:19:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:19:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:19:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:19:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:19:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:19:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:19:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:19:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:19:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:19:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:19:40 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:19:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:19:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:19:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:19:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:19:41 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:19:41 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:19:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:19:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:19:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:19:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:19:42 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:19:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:19:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:19:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:19:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:19:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:19:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:19:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:19:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:19:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:19:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:19:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:19:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:19:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:19:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:19:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:19:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:19:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:19:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:19:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:19:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:19:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:19:42 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:19:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:19:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:19:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:19:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:19:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:19:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:19:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:19:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:19:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:19:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:19:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:19:47 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:19:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:19:47 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:19:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:19:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:19:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:19:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:19:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:19:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:19:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:19:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:19:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:19:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:19:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:19:52 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:19:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:19:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:19:52 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:19:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:19:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:19:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:19:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:19:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:19:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:19:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:19:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:19:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:19:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:19:57 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:19:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:19:57 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:19:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:20:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:20:02 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:20:02 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:20:02 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:20:02 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:20:02 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:20:02 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:20:02 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:20:02 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:20:02 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:20:02 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:20:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:20:02 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:20:03 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:20:03 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:20:04 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:20:07 [INFO] transceiver.py:125 Init transceiver 'BTS@172.18.83.20:5700'
2024-10-30 06:20:07 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5702 <-> R:172.18.83.20:5802)
2024-10-30 06:20:07 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5701 <-> R:172.18.83.20:5801)
2024-10-30 06:20:07 [INFO] transceiver.py:125 Init transceiver 'MS@172.18.83.22:6700'
2024-10-30 06:20:07 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:6702 <-> R:172.18.83.22:6802)
2024-10-30 06:20:07 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:6701 <-> R:172.18.83.22:6801)
2024-10-30 06:20:07 [INFO] transceiver.py:125 Init transceiver 'TRX1@172.18.83.20:5700/1'
2024-10-30 06:20:07 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5704 <-> R:172.18.83.20:5804)
2024-10-30 06:20:07 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5703 <-> R:172.18.83.20:5803)
2024-10-30 06:20:07 [INFO] transceiver.py:125 Init transceiver 'TRX2@172.18.83.20:5700/2'
2024-10-30 06:20:07 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5706 <-> R:172.18.83.20:5806)
2024-10-30 06:20:07 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5705 <-> R:172.18.83.20:5805)
2024-10-30 06:20:07 [INFO] transceiver.py:125 Init transceiver 'TRX3@172.18.83.20:5700/3'
2024-10-30 06:20:07 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5708 <-> R:172.18.83.20:5808)
2024-10-30 06:20:07 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5707 <-> R:172.18.83.20:5807)
2024-10-30 06:20:07 [INFO] fake_trx.py:423 Init complete
2024-10-30 06:20:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:20:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:20:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:20:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:20:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:20:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:20:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:20:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:20:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:20:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:20:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:20:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:20:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:20:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:20:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:20:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:20:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:20:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:20:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:20:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:20:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:20:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:20:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:20:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:20:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:20:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:20:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:20:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:20:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:20:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:20:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:20:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:20:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:20:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:20:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:20:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:20:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:20:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:20:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:20:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:20:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:20:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:20:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:20:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:20:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:20:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:20:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:20:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:20:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:20:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:20:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:20:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:20:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:20:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:20:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:20:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:20:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:20:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:20:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:20:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:20:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:20:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:20:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:20:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:20:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:20:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:20:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:20:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:20:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:20:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:20:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:20:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:20:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:20:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:20:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:20:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:20:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:20:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:20:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:20:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:20:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:20:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:20:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:20:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:20:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:20:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:20:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:20:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:20:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:20:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:21:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:21:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:21:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:21:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:21:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:21:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:21:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:21:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:21:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:21:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:21:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:21:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:21:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:21:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:21:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:21:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:21:09 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:21:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:21:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:21:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:21:09 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:21:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:21:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:21:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:21:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:21:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:21:09 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:21:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:21:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:21:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:21:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 0 -> 1
2024-10-30 06:21:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:21:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 0 -> 1
2024-10-30 06:21:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:21:09 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 0 -> 1
2024-10-30 06:21:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:21:09 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:21:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:21:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 0 -> 1
2024-10-30 06:21:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:21:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:21:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:21:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:21:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:21:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:21:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:21:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:21:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:21:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:21:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:21:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:21:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:21:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:21:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:21:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:21:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:21:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:21:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:21:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:21:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:21:19 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:21:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:21:19 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:21:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:21:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:21:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:21:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:21:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:21:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:21:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:21:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:21:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:21:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:21:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:21:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:21:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:21:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:21:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:21:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:21:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:21:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:21:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:21:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:21:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:21:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:21:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:21:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:21:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:21:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:21:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:21:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:21:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:21:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:21:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:21:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:21:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:21:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:21:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:21:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:21:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:21:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:21:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:21:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:21:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:21:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:21:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:21:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:21:48 [INFO] transceiver.py:125 Init transceiver 'BTS@172.18.83.20:5700'
2024-10-30 06:21:48 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5702 <-> R:172.18.83.20:5802)
2024-10-30 06:21:48 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5701 <-> R:172.18.83.20:5801)
2024-10-30 06:21:48 [INFO] transceiver.py:125 Init transceiver 'MS@172.18.83.22:6700'
2024-10-30 06:21:48 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:6702 <-> R:172.18.83.22:6802)
2024-10-30 06:21:48 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:6701 <-> R:172.18.83.22:6801)
2024-10-30 06:21:48 [INFO] transceiver.py:125 Init transceiver 'TRX1@172.18.83.20:5700/1'
2024-10-30 06:21:48 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5704 <-> R:172.18.83.20:5804)
2024-10-30 06:21:48 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5703 <-> R:172.18.83.20:5803)
2024-10-30 06:21:48 [INFO] transceiver.py:125 Init transceiver 'TRX2@172.18.83.20:5700/2'
2024-10-30 06:21:48 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5706 <-> R:172.18.83.20:5806)
2024-10-30 06:21:48 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5705 <-> R:172.18.83.20:5805)
2024-10-30 06:21:48 [INFO] transceiver.py:125 Init transceiver 'TRX3@172.18.83.20:5700/3'
2024-10-30 06:21:48 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5708 <-> R:172.18.83.20:5808)
2024-10-30 06:21:48 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5707 <-> R:172.18.83.20:5807)
2024-10-30 06:21:48 [INFO] fake_trx.py:423 Init complete
2024-10-30 06:21:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:21:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:21:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:21:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:21:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:21:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:21:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:21:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 0 -> 1
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:21:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:21:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 0 -> 1
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:21:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:21:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 0 -> 1
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:21:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:21:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 0 -> 1
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:21:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:21:52 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:21:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:21:52 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:21:53 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:21:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:21:53 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:21:53 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:21:53 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:21:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:21:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:21:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:21:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:21:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:21:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:21:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:21:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:21:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:21:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:21:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:53 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:21:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:21:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:21:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:21:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:21:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:21:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:21:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:21:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:21:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:21:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:21:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:21:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:21:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:21:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:21:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:21:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:21:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:21:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:54 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:21:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:21:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:21:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:21:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:21:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:21:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:21:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:21:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:21:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:21:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:21:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:21:54 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:21:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:21:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:21:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:21:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:21:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:21:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:21:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:21:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:21:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:21:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:21:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:21:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:21:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:21:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:21:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:21:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:21:54 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:21:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:21:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:21:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:21:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:21:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:21:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:21:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:21:55 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:21:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:21:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:21:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:21:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:21:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:21:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:21:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:21:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:21:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:21:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:21:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:21:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:21:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:21:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:55 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:21:56 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:21:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:21:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:21:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:21:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:21:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:21:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:21:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:21:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:21:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:21:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:21:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:21:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:21:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:21:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:21:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:21:56 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:21:56 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2024-10-30 06:21:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:56 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:21:57 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:21:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:21:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:21:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:21:57 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:21:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:21:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:21:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:21:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:21:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:21:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:21:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:21:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:21:57 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:21:57 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2024-10-30 06:21:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:57 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:21:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:21:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:21:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:21:57 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:21:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:21:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:21:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:21:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:21:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:21:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:21:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:21:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:21:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:21:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:21:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:21:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:58 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:21:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:21:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:21:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:21:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:21:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:21:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:21:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:21:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:21:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:21:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:21:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:21:58 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:21:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:21:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:21:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:59 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:21:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:21:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:21:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:21:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:21:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:21:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:21:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:21:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:21:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:21:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:21:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:21:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:21:59 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:21:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:21:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:21:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:21:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:00 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:22:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:22:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:22:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:22:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:22:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:22:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:00 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:22:00 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:22:00 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:22:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:01 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:22:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:01 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:22:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:22:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:22:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:22:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:22:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:22:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:01 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:22:01 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:22:01 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:22:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:01 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:22:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:22:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:22:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:22:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:22:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:22:02 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:22:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:02 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:22:02 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:22:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:02 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:22:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:22:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:22:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:22:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:22:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:22:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:02 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:22:02 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:22:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:02 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:22:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:02 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:22:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:22:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:22:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:22:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:22:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:22:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:02 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:22:02 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:22:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:02 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:03 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:22:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:22:03 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:03 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:03 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:22:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:22:03 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:03 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:22:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:03 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:22:03 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:04 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:22:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:22:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:22:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:22:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:22:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:22:04 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:22:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:04 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:22:04 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:22:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:04 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:22:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:22:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:22:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:22:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:22:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:22:04 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:22:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:04 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:22:04 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:22:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:05 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:22:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:22:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:22:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:22:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:22:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:22:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:22:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:22:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:22:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:22:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:22:05 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:22:05 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2753 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:22:05 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2753 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:22:05 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2753 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:22:05 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2753 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:22:05 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2753 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:22:05 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2753 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:22:05 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2753 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:22:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:22:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:22:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:22:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:22:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:22:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:22:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:22:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:22:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:22:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:22:10 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:22:10 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:22:10 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:22:10 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
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2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
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2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
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2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
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2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
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2024-10-30 06:22:11 [DEBUG] clck_gen.py:102 IND CLOCK 306
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2024-10-30 06:22:12 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
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2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
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2024-10-30 06:22:12 [DEBUG] clck_gen.py:102 IND CLOCK 510
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2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
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2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:22:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:22:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:22:12 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:22:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:22:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:22:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:22:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:22:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:22:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:22:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:22:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:22:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:22:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:22:17 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:17 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:22:18 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:22:18 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:22:18 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:22:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:18 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:22:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:22:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:22:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:22:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:22:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:22:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:22:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:22:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:22:18 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:22:18 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:22:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:22:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:22:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:22:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:22:23 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:22:23 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:22:23 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:22:23 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:22:23 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:22:23 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:22:23 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:22:23 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:22:23 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:22:23 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:23 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:22:24 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:22:24 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:22:24 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:22:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:24 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:22:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:22:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:22:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:22:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:22:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:22:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:22:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:22:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:22:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:22:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:22:24 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:22:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:22:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:22:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:22:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:22:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:22:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:22:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:22:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:22:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:22:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:22:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:22:29 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:29 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:22:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:22:29 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:22:29 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:22:29 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:22:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:22:29 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:22:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:22:29 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=168 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:22:29 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=168 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:22:29 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=168 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:22:29 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=168 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:22:29 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=168 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:22:29 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=168 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:22:29 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=168 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:22:29 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=168 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:22:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:22:34 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:22:34 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:22:34 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:22:34 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:22:34 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:22:34 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:22:34 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:22:34 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:22:34 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:22:34 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:34 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:22:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:22:35 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:22:35 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:22:35 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:22:35 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:22:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:22:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:22:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:22:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:22:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:22:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:22:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:22:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:35 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:22:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:22:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:22:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:22:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:22:36 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:22:36 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:22:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:22:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:22:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:22:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:22:37 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:22:37 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:22:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:22:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:22:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:22:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:22:38 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:22:38 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:22:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:22:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:22:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:22:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:22:39 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:22:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:22:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:22:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:22:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:22:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:22:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:22:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:22:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:39 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:22:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:22:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:22:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:22:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:22:40 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:22:40 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:22:41 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:22:41 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:22:42 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:22:42 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:22:42 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:22:43 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:22:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:43 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:22:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:22:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:22:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:22:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:22:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:22:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:22:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:22:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:44 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:22:44 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:22:45 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:22:45 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:22:46 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:22:46 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:22:47 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:22:47 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:22:48 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:22:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:22:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:22:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:22:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:22:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:22:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:22:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:22:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:48 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:22:49 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:22:49 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:22:50 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:22:50 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:22:50 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 06:22:51 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 06:22:51 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 06:22:52 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 06:22:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:22:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:22:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:22:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:22:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:22:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:22:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:22:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:52 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 06:22:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:53 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 06:22:53 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 06:22:54 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 06:22:54 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 06:22:55 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 06:22:55 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 06:22:56 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 06:22:56 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 06:22:57 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 06:22:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:22:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:22:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:22:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:22:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:22:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:22:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:22:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:57 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:22:57 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2024-10-30 06:22:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:22:57 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 06:22:58 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 06:22:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:22:58 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 06:22:58 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 06:22:59 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 06:22:59 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 06:23:00 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 06:23:00 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 06:23:01 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 06:23:01 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 06:23:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:23:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:23:02 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:23:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:23:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:23:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:23:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:23:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:23:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:02 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:23:02 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2024-10-30 06:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:02 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 06:23:02 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 06:23:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:03 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 06:23:03 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 06:23:04 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-10-30 06:23:04 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-10-30 06:23:05 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-10-30 06:23:05 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-10-30 06:23:06 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-10-30 06:23:06 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-10-30 06:23:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:23:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:23:06 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:23:06 [WARNING] transceiver.py:250 (MS@172.18.83.22:6700) RX TRXD message (fn=6925 tn=5 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:23:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:23:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:23:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:23:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:23:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:23:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:23:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:23:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:23:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:06 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-10-30 06:23:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:23:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:23:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:07 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-10-30 06:23:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:07 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-10-30 06:23:08 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-10-30 06:23:08 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-10-30 06:23:09 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-10-30 06:23:09 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-10-30 06:23:10 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-10-30 06:23:10 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-10-30 06:23:11 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-10-30 06:23:11 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-10-30 06:23:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:23:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:23:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:23:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:23:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:23:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:23:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:23:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:23:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:23:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:23:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:23:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:12 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-10-30 06:23:12 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-10-30 06:23:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:13 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-10-30 06:23:13 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-10-30 06:23:14 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-10-30 06:23:14 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-10-30 06:23:14 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-10-30 06:23:15 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-10-30 06:23:15 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-10-30 06:23:16 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-10-30 06:23:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:23:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:23:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:23:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:23:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:23:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:23:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:23:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:23:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:23:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:23:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:23:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:23:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:16 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-10-30 06:23:17 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-10-30 06:23:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:17 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-10-30 06:23:18 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2024-10-30 06:23:18 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2024-10-30 06:23:19 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2024-10-30 06:23:19 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2024-10-30 06:23:20 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2024-10-30 06:23:20 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2024-10-30 06:23:21 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2024-10-30 06:23:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:23:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:23:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:23:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:23:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:23:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:23:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:23:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:23:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:23:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:21 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:23:21 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:23:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:21 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2024-10-30 06:23:22 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2024-10-30 06:23:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:22 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2024-10-30 06:23:22 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2024-10-30 06:23:23 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2024-10-30 06:23:23 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2024-10-30 06:23:24 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2024-10-30 06:23:24 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2024-10-30 06:23:25 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2024-10-30 06:23:25 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2024-10-30 06:23:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:23:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:23:26 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:23:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:23:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:23:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:23:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:23:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:23:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:23:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:23:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:26 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:23:26 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:23:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:26 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2024-10-30 06:23:26 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2024-10-30 06:23:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:27 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2024-10-30 06:23:27 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2024-10-30 06:23:28 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2024-10-30 06:23:28 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2024-10-30 06:23:29 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2024-10-30 06:23:29 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2024-10-30 06:23:30 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2024-10-30 06:23:30 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2024-10-30 06:23:30 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2024-10-30 06:23:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:23:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:23:31 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:23:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:23:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:23:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:23:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:23:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:23:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:23:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:23:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:31 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:23:31 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:23:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:31 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2024-10-30 06:23:31 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2024-10-30 06:23:32 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2024-10-30 06:23:32 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2024-10-30 06:23:33 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2024-10-30 06:23:33 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2024-10-30 06:23:34 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2024-10-30 06:23:34 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2024-10-30 06:23:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:23:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:23:35 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:23:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:23:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:23:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:23:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:23:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:23:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:23:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:23:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:35 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2024-10-30 06:23:35 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:23:35 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:23:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:35 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2024-10-30 06:23:36 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2024-10-30 06:23:36 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2024-10-30 06:23:37 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2024-10-30 06:23:37 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2024-10-30 06:23:37 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2024-10-30 06:23:38 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2024-10-30 06:23:38 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2024-10-30 06:23:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:23:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:23:39 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:23:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:23:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:23:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:23:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:23:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:23:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:23:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:23:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:39 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2024-10-30 06:23:39 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:23:39 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:23:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:39 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2024-10-30 06:23:40 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2024-10-30 06:23:40 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2024-10-30 06:23:41 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2024-10-30 06:23:41 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2024-10-30 06:23:42 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2024-10-30 06:23:42 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2024-10-30 06:23:43 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2024-10-30 06:23:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:23:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:23:43 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:23:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:23:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:23:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:23:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:23:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:23:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:23:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:23:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:43 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:23:43 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2024-10-30 06:23:43 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:23:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:44 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2024-10-30 06:23:44 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2024-10-30 06:23:45 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2024-10-30 06:23:45 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2024-10-30 06:23:45 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2024-10-30 06:23:46 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2024-10-30 06:23:46 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2024-10-30 06:23:47 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2024-10-30 06:23:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:23:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:23:47 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:23:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:23:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:23:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:23:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:23:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:23:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:23:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:23:47 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2024-10-30 06:23:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:47 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:23:47 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:23:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:48 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2024-10-30 06:23:48 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2024-10-30 06:23:49 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2024-10-30 06:23:49 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2024-10-30 06:23:50 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2024-10-30 06:23:50 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2024-10-30 06:23:51 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2024-10-30 06:23:51 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2024-10-30 06:23:52 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2024-10-30 06:23:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:23:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:23:52 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:23:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:23:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:23:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:23:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:23:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:23:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:23:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:23:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:52 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:23:52 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:23:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:52 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2024-10-30 06:23:53 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2024-10-30 06:23:53 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2024-10-30 06:23:53 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2024-10-30 06:23:54 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2024-10-30 06:23:54 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2024-10-30 06:23:55 [DEBUG] clck_gen.py:102 IND CLOCK 17442
2024-10-30 06:23:55 [DEBUG] clck_gen.py:102 IND CLOCK 17544
2024-10-30 06:23:56 [DEBUG] clck_gen.py:102 IND CLOCK 17646
2024-10-30 06:23:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:23:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:23:56 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:23:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:23:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:23:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:23:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:23:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:23:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:23:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:23:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:56 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:23:56 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:23:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:23:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:23:56 [DEBUG] clck_gen.py:102 IND CLOCK 17748
2024-10-30 06:23:57 [DEBUG] clck_gen.py:102 IND CLOCK 17850
2024-10-30 06:23:57 [DEBUG] clck_gen.py:102 IND CLOCK 17952
2024-10-30 06:23:58 [DEBUG] clck_gen.py:102 IND CLOCK 18054
2024-10-30 06:23:58 [DEBUG] clck_gen.py:102 IND CLOCK 18156
2024-10-30 06:23:59 [DEBUG] clck_gen.py:102 IND CLOCK 18258
2024-10-30 06:23:59 [DEBUG] clck_gen.py:102 IND CLOCK 18360
2024-10-30 06:24:00 [DEBUG] clck_gen.py:102 IND CLOCK 18462
2024-10-30 06:24:00 [DEBUG] clck_gen.py:102 IND CLOCK 18564
2024-10-30 06:24:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:00 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:24:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:00 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:24:00 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:24:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:00 [DEBUG] clck_gen.py:102 IND CLOCK 18666
2024-10-30 06:24:01 [DEBUG] clck_gen.py:102 IND CLOCK 18768
2024-10-30 06:24:01 [DEBUG] clck_gen.py:102 IND CLOCK 18870
2024-10-30 06:24:02 [DEBUG] clck_gen.py:102 IND CLOCK 18972
2024-10-30 06:24:02 [DEBUG] clck_gen.py:102 IND CLOCK 19074
2024-10-30 06:24:03 [DEBUG] clck_gen.py:102 IND CLOCK 19176
2024-10-30 06:24:03 [DEBUG] clck_gen.py:102 IND CLOCK 19278
2024-10-30 06:24:04 [DEBUG] clck_gen.py:102 IND CLOCK 19380
2024-10-30 06:24:04 [DEBUG] clck_gen.py:102 IND CLOCK 19482
2024-10-30 06:24:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:04 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:24:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:24:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:24:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:24:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:24:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:24:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:24:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:24:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:24:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:24:04 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:24:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:24:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:24:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:24:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:24:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:24:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:24:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:24:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:24:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:24:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:24:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:24:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:24:09 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:24:09 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:24:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:24:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:24:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:24:09 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:24:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:24:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:24:09 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:24:09 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:24:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:24:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:24:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:24:09 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:24:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:24:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:24:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:24:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:24:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:24:10 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:24:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:24:10 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:24:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:24:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:24:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:24:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:24:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:24:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:24:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:24:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:24:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:24:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:24:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:24:15 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:24:15 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:24:15 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:24:15 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:15 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:15 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:16 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:16 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:24:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:24:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:24:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:24:17 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:24:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:17 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:24:17 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2024-10-30 06:24:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:17 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:24:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:17 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:24:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:18 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:24:18 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2024-10-30 06:24:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:24:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:24:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:24:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:24:18 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:24:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:18 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:24:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:24:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:18 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:24:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:24:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:24:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:24:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:24:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:19 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:24:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:24:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:19 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:24:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:24:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:24:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:24:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:24:20 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:24:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:20 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:24:20 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:24:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:20 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:24:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:20 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:24:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:21 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:24:21 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:24:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:21 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:24:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:21 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:24:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:21 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:24:21 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:24:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:21 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:24:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:21 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:24:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:21 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:24:21 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:24:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:22 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:24:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:22 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:24:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:22 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:24:22 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:24:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:22 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:24:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:22 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:24:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:22 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:24:22 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:24:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:23 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:23 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:24:23 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:23 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:24:23 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:23 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:23 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:23 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:24:23 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:24 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:24:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:24 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:24:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:24 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:24:24 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:24:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:24 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:24:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:24:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:24:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:24:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:24:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:24:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:24:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:24:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:24:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:24:24 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:24:24 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2140 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:24:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:24:24 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2140 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:24:24 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2140 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:24:24 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2140 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:24:24 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2140 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:24:24 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2140 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:24:24 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2140 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:24:24 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2140 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:24:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:24:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:24:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:24:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:24:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:24:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:24:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:24:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:24:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:24:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:24:29 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:24:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:24:29 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:24:30 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:24:30 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:24:30 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:24:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:30 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:24:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:30 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:24:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:24:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:24:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:24:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:24:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:31 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:24:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:31 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:24:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:24:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:24:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:24:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:24:32 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:24:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:32 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:24:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:24:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:24:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:24:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:24:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:33 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:24:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:33 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:24:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:24:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:24:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:24:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:24:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:34 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:24:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:34 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:24:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:24:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:24:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:24:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:24:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:35 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:24:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:35 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:24:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:36 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:24:36 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:24:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:36 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:24:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:37 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:24:37 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2024-10-30 06:24:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:37 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:24:37 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:24:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:38 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:24:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:38 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:24:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:38 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:24:38 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2024-10-30 06:24:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:38 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:24:39 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:24:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:39 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:24:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:40 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:24:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:24:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:40 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:24:40 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:24:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:41 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:24:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:41 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:24:42 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:24:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:42 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:24:43 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:24:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:24:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:43 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:24:44 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:24:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:44 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:24:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:44 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:24:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:45 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:24:45 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:24:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:45 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:24:45 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 06:24:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:46 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 06:24:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:46 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:24:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:46 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:24:46 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:24:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:46 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 06:24:47 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 06:24:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:47 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 06:24:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:47 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:24:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:47 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:24:47 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:24:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:48 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 06:24:48 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 06:24:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:49 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 06:24:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:49 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:24:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:49 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:24:49 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:24:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:49 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 06:24:50 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 06:24:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:50 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 06:24:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:50 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:24:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:50 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:24:50 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:24:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:51 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 06:24:51 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 06:24:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:52 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 06:24:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:52 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:24:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:52 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:24:52 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:24:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:52 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 06:24:52 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 06:24:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:53 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 06:24:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:53 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:24:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:53 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:24:53 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:24:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:53 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 06:24:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:54 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 06:24:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:54 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:24:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:54 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:24:54 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:24:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:54 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 06:24:55 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 06:24:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:55 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 06:24:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:56 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:24:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:56 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 06:24:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:56 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:24:56 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:24:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:56 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 06:24:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:57 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 06:24:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:57 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:24:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:24:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:24:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:24:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:24:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:24:57 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 06:24:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:57 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:24:57 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:24:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:58 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 06:24:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:58 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 06:24:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:24:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:24:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:24:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:24:59 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:24:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:24:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:24:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:24:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:24:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:24:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:24:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:24:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:24:59 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:24:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:24:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:25:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:25:04 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:25:04 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:25:04 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:25:04 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:25:04 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:25:04 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:25:04 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:25:04 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:25:04 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:25:04 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:25:04 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:25:04 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:25:04 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:25:04 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:25:04 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:25:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:25:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:05 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:25:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:25:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:25:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:25:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:25:05 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:25:05 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:25:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:25:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:25:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:25:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:25:06 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:25:06 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:25:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:25:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:25:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:25:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:25:07 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:25:07 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:25:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:25:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:25:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:25:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:25:08 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:25:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:25:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:25:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:25:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:25:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:25:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:25:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:25:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:25:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:25:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:25:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:25:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:25:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:25:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:08 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:25:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:25:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:25:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:25:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:25:09 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:25:09 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:25:10 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:25:10 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:25:11 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:25:11 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:25:12 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:25:12 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:25:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:25:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:25:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:25:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:25:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:25:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:25:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:25:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:25:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:25:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:25:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:25:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:25:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:25:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:13 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:25:13 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:25:13 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:25:14 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:25:14 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:25:15 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:25:15 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:25:16 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:25:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:25:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:25:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:25:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:25:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:25:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:25:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:25:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:25:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:25:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:25:16 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:25:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:25:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:25:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:25:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:17 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:25:17 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:25:18 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:25:18 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:25:19 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:25:19 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:25:20 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 06:25:20 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 06:25:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:25:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:25:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:25:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:25:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:25:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:25:21 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 06:25:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:25:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:25:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:25:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:25:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:25:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:25:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:25:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:21 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 06:25:21 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 06:25:22 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 06:25:22 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 06:25:23 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 06:25:23 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 06:25:24 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 06:25:24 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 06:25:25 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 06:25:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:25:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:25:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:25:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:25:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:25:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:25:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:25:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:25:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:25:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:25:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:25:25 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 06:25:25 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:25:25 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2024-10-30 06:25:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:26 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 06:25:26 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 06:25:27 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 06:25:27 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 06:25:28 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 06:25:28 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 06:25:29 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 06:25:29 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 06:25:29 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 06:25:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:25:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:25:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:25:30 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:25:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:25:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:25:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:25:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:25:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:25:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:25:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:25:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:25:30 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:25:30 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2024-10-30 06:25:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:30 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 06:25:30 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 06:25:31 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 06:25:31 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 06:25:32 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 06:25:32 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 06:25:33 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-10-30 06:25:33 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-10-30 06:25:34 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-10-30 06:25:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:25:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:25:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:25:34 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:25:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:25:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:25:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:25:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:25:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:25:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:25:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:25:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:25:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:25:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:25:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:25:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:34 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-10-30 06:25:35 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-10-30 06:25:35 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-10-30 06:25:36 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-10-30 06:25:36 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-10-30 06:25:37 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-10-30 06:25:37 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-10-30 06:25:37 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-10-30 06:25:38 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-10-30 06:25:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:25:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:25:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:25:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:25:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:25:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:25:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:25:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:25:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:25:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:25:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:25:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:25:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:25:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:38 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-10-30 06:25:39 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-10-30 06:25:39 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-10-30 06:25:40 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-10-30 06:25:40 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-10-30 06:25:41 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-10-30 06:25:41 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-10-30 06:25:42 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-10-30 06:25:42 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-10-30 06:25:43 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-10-30 06:25:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:25:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:25:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:25:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:25:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:25:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:25:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:25:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:25:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:25:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:25:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:25:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:25:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:25:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:25:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:43 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-10-30 06:25:44 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-10-30 06:25:44 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-10-30 06:25:44 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-10-30 06:25:45 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-10-30 06:25:45 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-10-30 06:25:46 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-10-30 06:25:46 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-10-30 06:25:47 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2024-10-30 06:25:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:25:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:25:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:25:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:25:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:25:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:25:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:25:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:25:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:25:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:25:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:25:47 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:25:47 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:25:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:47 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2024-10-30 06:25:48 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2024-10-30 06:25:48 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2024-10-30 06:25:49 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2024-10-30 06:25:49 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2024-10-30 06:25:50 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2024-10-30 06:25:50 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2024-10-30 06:25:51 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2024-10-30 06:25:51 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2024-10-30 06:25:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:25:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:25:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:25:51 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:25:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:25:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:25:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:25:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:25:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:25:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:25:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:25:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:25:51 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:25:51 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:25:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:52 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2024-10-30 06:25:52 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2024-10-30 06:25:52 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2024-10-30 06:25:53 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2024-10-30 06:25:53 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2024-10-30 06:25:54 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2024-10-30 06:25:54 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2024-10-30 06:25:55 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2024-10-30 06:25:55 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2024-10-30 06:25:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:25:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:25:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:25:56 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:25:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:25:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:25:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:25:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:25:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:25:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:25:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:25:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:25:56 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:25:56 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:25:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:25:56 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2024-10-30 06:25:56 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2024-10-30 06:25:57 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2024-10-30 06:25:57 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2024-10-30 06:25:58 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2024-10-30 06:25:58 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2024-10-30 06:25:59 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2024-10-30 06:25:59 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2024-10-30 06:25:59 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2024-10-30 06:26:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:26:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:26:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:26:00 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:26:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:26:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:26:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:26:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:26:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:26:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:26:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:26:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:26:00 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:26:00 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:26:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:00 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2024-10-30 06:26:00 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2024-10-30 06:26:01 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2024-10-30 06:26:01 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2024-10-30 06:26:02 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2024-10-30 06:26:02 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2024-10-30 06:26:03 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2024-10-30 06:26:03 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2024-10-30 06:26:04 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2024-10-30 06:26:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:26:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:26:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:26:04 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:26:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:26:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:26:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:26:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:26:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:26:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:26:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:26:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:26:04 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:26:04 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:26:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:04 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2024-10-30 06:26:05 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2024-10-30 06:26:05 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2024-10-30 06:26:06 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2024-10-30 06:26:06 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2024-10-30 06:26:07 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2024-10-30 06:26:07 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2024-10-30 06:26:07 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2024-10-30 06:26:08 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2024-10-30 06:26:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:26:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:26:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:26:08 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:26:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:26:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:26:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:26:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:26:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:26:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:26:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:26:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:26:08 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:26:08 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:26:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:08 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2024-10-30 06:26:09 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2024-10-30 06:26:09 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2024-10-30 06:26:10 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2024-10-30 06:26:10 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2024-10-30 06:26:11 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2024-10-30 06:26:11 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2024-10-30 06:26:12 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2024-10-30 06:26:12 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2024-10-30 06:26:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:26:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:26:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:26:12 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:26:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:26:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:26:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:26:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:26:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:26:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:26:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:26:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:26:12 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:26:12 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:26:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:13 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2024-10-30 06:26:13 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2024-10-30 06:26:14 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2024-10-30 06:26:14 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2024-10-30 06:26:15 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2024-10-30 06:26:15 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2024-10-30 06:26:15 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2024-10-30 06:26:16 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2024-10-30 06:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:26:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:26:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:26:16 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:26:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:26:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:26:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:26:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:26:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:26:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:26:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:26:16 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:26:16 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:26:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:16 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2024-10-30 06:26:17 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2024-10-30 06:26:17 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2024-10-30 06:26:18 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2024-10-30 06:26:18 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2024-10-30 06:26:19 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2024-10-30 06:26:19 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2024-10-30 06:26:20 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2024-10-30 06:26:20 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2024-10-30 06:26:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:26:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:26:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:26:21 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:26:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:26:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:26:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:26:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:26:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:26:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:26:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:26:21 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2024-10-30 06:26:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:26:21 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:26:21 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:26:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:21 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2024-10-30 06:26:22 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2024-10-30 06:26:22 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2024-10-30 06:26:22 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2024-10-30 06:26:23 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2024-10-30 06:26:23 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2024-10-30 06:26:24 [DEBUG] clck_gen.py:102 IND CLOCK 17442
2024-10-30 06:26:24 [DEBUG] clck_gen.py:102 IND CLOCK 17544
2024-10-30 06:26:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:26:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:26:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:26:25 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:26:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:26:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:26:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:26:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:26:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:26:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:26:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:26:25 [DEBUG] clck_gen.py:102 IND CLOCK 17646
2024-10-30 06:26:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:26:25 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:26:25 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:26:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:25 [DEBUG] clck_gen.py:102 IND CLOCK 17748
2024-10-30 06:26:26 [DEBUG] clck_gen.py:102 IND CLOCK 17850
2024-10-30 06:26:26 [DEBUG] clck_gen.py:102 IND CLOCK 17952
2024-10-30 06:26:27 [DEBUG] clck_gen.py:102 IND CLOCK 18054
2024-10-30 06:26:27 [DEBUG] clck_gen.py:102 IND CLOCK 18156
2024-10-30 06:26:28 [DEBUG] clck_gen.py:102 IND CLOCK 18258
2024-10-30 06:26:28 [DEBUG] clck_gen.py:102 IND CLOCK 18360
2024-10-30 06:26:29 [DEBUG] clck_gen.py:102 IND CLOCK 18462
2024-10-30 06:26:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:26:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:26:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:26:29 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:26:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:26:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:26:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:26:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:26:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:26:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:26:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:26:29 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:26:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:26:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:26:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:26:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:26:34 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:26:34 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:26:34 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:26:34 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:26:34 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:26:34 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:26:34 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:26:34 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:26:34 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:26:34 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:26:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:26:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:26:34 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:26:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:26:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:26:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:26:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:26:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:26:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:26:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:26:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:26:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:26:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:26:39 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:26:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:26:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:26:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:26:40 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:26:40 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:26:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:26:40 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:26:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:26:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:26:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:26:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:26:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:26:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:26:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:26:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:26:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:26:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:26:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:40 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:26:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:26:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:26:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:26:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:26:41 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:26:41 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:26:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:26:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:26:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:26:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:26:42 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:26:42 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:26:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:26:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:26:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:26:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:26:42 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:26:43 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:26:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:26:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:26:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:26:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:26:43 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:26:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:26:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:26:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:26:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:26:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:26:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:26:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:26:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:26:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:26:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:26:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:26:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:26:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:26:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:44 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:26:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:26:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:26:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:26:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:26:44 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:26:45 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:26:45 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:26:46 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:26:46 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:26:47 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:26:47 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:26:48 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:26:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:26:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:26:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:26:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:26:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:26:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:26:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:26:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:26:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:26:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:26:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:26:48 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:26:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:26:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:26:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:49 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:26:49 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:26:49 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:26:50 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:26:50 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:26:51 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:26:51 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:26:52 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:26:52 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:26:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:26:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:26:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:26:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:26:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:26:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:26:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:26:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:26:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:26:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:26:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:26:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:26:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:26:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:53 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:26:53 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:26:54 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:26:54 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:26:55 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:26:55 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 06:26:56 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 06:26:56 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 06:26:57 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 06:26:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:26:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:26:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:26:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:26:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:26:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:26:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:26:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:26:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:26:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:26:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:26:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:26:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:26:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:26:57 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 06:26:57 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 06:26:58 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 06:26:58 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 06:26:59 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 06:26:59 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 06:27:00 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 06:27:00 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 06:27:01 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 06:27:01 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 06:27:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:27:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:27:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:27:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:27:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:27:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:27:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:27:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:27:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:27:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:27:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:27:01 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:27:01 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2024-10-30 06:27:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:02 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 06:27:02 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 06:27:03 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 06:27:03 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 06:27:04 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 06:27:04 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 06:27:05 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 06:27:05 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 06:27:06 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 06:27:06 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 06:27:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:27:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:27:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:27:06 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:27:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:27:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:27:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:27:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:27:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:27:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:27:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:27:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:27:06 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:27:06 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2024-10-30 06:27:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:06 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 06:27:07 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 06:27:07 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 06:27:08 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 06:27:08 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-10-30 06:27:09 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-10-30 06:27:09 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-10-30 06:27:10 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-10-30 06:27:10 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-10-30 06:27:11 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-10-30 06:27:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:27:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:27:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:27:11 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:27:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:27:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:27:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:27:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:27:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:27:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:27:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:27:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:27:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:27:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:27:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:27:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:11 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-10-30 06:27:12 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-10-30 06:27:12 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-10-30 06:27:13 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-10-30 06:27:13 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-10-30 06:27:14 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-10-30 06:27:14 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-10-30 06:27:15 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-10-30 06:27:15 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-10-30 06:27:15 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-10-30 06:27:16 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-10-30 06:27:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:27:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:27:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:27:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:27:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:27:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:27:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:27:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:27:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:27:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:27:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:27:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:27:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:27:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:16 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-10-30 06:27:17 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-10-30 06:27:17 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-10-30 06:27:18 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-10-30 06:27:18 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-10-30 06:27:19 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-10-30 06:27:19 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-10-30 06:27:20 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-10-30 06:27:20 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-10-30 06:27:21 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-10-30 06:27:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:27:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:27:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:27:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:27:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:27:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:27:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:27:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:27:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:27:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:27:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:27:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:27:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:27:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:27:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:21 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-10-30 06:27:22 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-10-30 06:27:22 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-10-30 06:27:23 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2024-10-30 06:27:23 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2024-10-30 06:27:23 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2024-10-30 06:27:24 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2024-10-30 06:27:24 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2024-10-30 06:27:25 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2024-10-30 06:27:25 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2024-10-30 06:27:26 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2024-10-30 06:27:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:27:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:27:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:27:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:27:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:27:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:27:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:27:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:27:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:27:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:27:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:27:26 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:27:26 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:27:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:26 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2024-10-30 06:27:27 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2024-10-30 06:27:27 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2024-10-30 06:27:28 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2024-10-30 06:27:28 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2024-10-30 06:27:29 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2024-10-30 06:27:29 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2024-10-30 06:27:30 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2024-10-30 06:27:30 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2024-10-30 06:27:30 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2024-10-30 06:27:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:27:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:27:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:27:31 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:27:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:27:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:27:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:27:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:27:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:27:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:27:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:27:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:27:31 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:27:31 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:27:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:31 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2024-10-30 06:27:31 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2024-10-30 06:27:32 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2024-10-30 06:27:32 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2024-10-30 06:27:33 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2024-10-30 06:27:33 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2024-10-30 06:27:34 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2024-10-30 06:27:34 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2024-10-30 06:27:35 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2024-10-30 06:27:35 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2024-10-30 06:27:36 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2024-10-30 06:27:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:27:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:27:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:27:36 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:27:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:27:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:27:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:27:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:27:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:27:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:27:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:27:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:27:36 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:27:36 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:27:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:36 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2024-10-30 06:27:37 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2024-10-30 06:27:37 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2024-10-30 06:27:38 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2024-10-30 06:27:38 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2024-10-30 06:27:38 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2024-10-30 06:27:39 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2024-10-30 06:27:39 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2024-10-30 06:27:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:27:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:27:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:27:40 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:27:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:27:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:27:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:27:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:27:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:27:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:27:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:27:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:27:40 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:27:40 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:27:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:40 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2024-10-30 06:27:40 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2024-10-30 06:27:41 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2024-10-30 06:27:41 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2024-10-30 06:27:42 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2024-10-30 06:27:42 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2024-10-30 06:27:43 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2024-10-30 06:27:43 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2024-10-30 06:27:44 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2024-10-30 06:27:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:27:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:27:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:27:44 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:27:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:27:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:27:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:27:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:27:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:27:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:27:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:27:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:27:44 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:27:44 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:27:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:44 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2024-10-30 06:27:45 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2024-10-30 06:27:45 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2024-10-30 06:27:45 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2024-10-30 06:27:46 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2024-10-30 06:27:46 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2024-10-30 06:27:47 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2024-10-30 06:27:47 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2024-10-30 06:27:48 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2024-10-30 06:27:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:27:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:27:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:27:48 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:27:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:27:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:27:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:27:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:27:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:27:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:27:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:27:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:27:48 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:27:48 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:27:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:48 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2024-10-30 06:27:49 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2024-10-30 06:27:49 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2024-10-30 06:27:50 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2024-10-30 06:27:50 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2024-10-30 06:27:51 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2024-10-30 06:27:51 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2024-10-30 06:27:52 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2024-10-30 06:27:52 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2024-10-30 06:27:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:27:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:27:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:27:52 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:27:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:27:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:27:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:27:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:27:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:27:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:27:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:27:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:27:53 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2024-10-30 06:27:53 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:27:53 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:27:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:53 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2024-10-30 06:27:53 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2024-10-30 06:27:54 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2024-10-30 06:27:54 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2024-10-30 06:27:55 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2024-10-30 06:27:55 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2024-10-30 06:27:56 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2024-10-30 06:27:56 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2024-10-30 06:27:57 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2024-10-30 06:27:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:27:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:27:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:27:57 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:27:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:27:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:27:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:27:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:27:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:27:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:27:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:27:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:27:57 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:27:57 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:27:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:27:57 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2024-10-30 06:27:58 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2024-10-30 06:27:58 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2024-10-30 06:27:59 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2024-10-30 06:27:59 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2024-10-30 06:28:00 [DEBUG] clck_gen.py:102 IND CLOCK 17442
2024-10-30 06:28:00 [DEBUG] clck_gen.py:102 IND CLOCK 17544
2024-10-30 06:28:00 [DEBUG] clck_gen.py:102 IND CLOCK 17646
2024-10-30 06:28:01 [DEBUG] clck_gen.py:102 IND CLOCK 17748
2024-10-30 06:28:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:01 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:28:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:28:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:28:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:28:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:28:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:28:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:01 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:28:01 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:28:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:01 [DEBUG] clck_gen.py:102 IND CLOCK 17850
2024-10-30 06:28:02 [DEBUG] clck_gen.py:102 IND CLOCK 17952
2024-10-30 06:28:02 [DEBUG] clck_gen.py:102 IND CLOCK 18054
2024-10-30 06:28:03 [DEBUG] clck_gen.py:102 IND CLOCK 18156
2024-10-30 06:28:03 [DEBUG] clck_gen.py:102 IND CLOCK 18258
2024-10-30 06:28:04 [DEBUG] clck_gen.py:102 IND CLOCK 18360
2024-10-30 06:28:04 [DEBUG] clck_gen.py:102 IND CLOCK 18462
2024-10-30 06:28:05 [DEBUG] clck_gen.py:102 IND CLOCK 18564
2024-10-30 06:28:05 [DEBUG] clck_gen.py:102 IND CLOCK 18666
2024-10-30 06:28:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:05 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:28:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:28:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:28:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:28:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:28:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:28:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:05 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:28:05 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:28:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:06 [DEBUG] clck_gen.py:102 IND CLOCK 18768
2024-10-30 06:28:06 [DEBUG] clck_gen.py:102 IND CLOCK 18870
2024-10-30 06:28:07 [DEBUG] clck_gen.py:102 IND CLOCK 18972
2024-10-30 06:28:07 [DEBUG] clck_gen.py:102 IND CLOCK 19074
2024-10-30 06:28:08 [DEBUG] clck_gen.py:102 IND CLOCK 19176
2024-10-30 06:28:08 [DEBUG] clck_gen.py:102 IND CLOCK 19278
2024-10-30 06:28:08 [DEBUG] clck_gen.py:102 IND CLOCK 19380
2024-10-30 06:28:09 [DEBUG] clck_gen.py:102 IND CLOCK 19482
2024-10-30 06:28:09 [DEBUG] clck_gen.py:102 IND CLOCK 19584
2024-10-30 06:28:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:10 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:28:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:28:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:28:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:28:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:28:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:28:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:28:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:28:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:28:10 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:28:10 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=19624 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:28:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:28:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:28:10 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=19624 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:28:10 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=19624 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:28:10 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=19624 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:28:10 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=19624 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:28:10 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=19624 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:28:10 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=19624 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:28:10 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=19624 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:28:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:28:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:28:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:28:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:28:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:28:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:28:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:28:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:28:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:28:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:28:15 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:28:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:28:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:28:15 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:28:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:28:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:28:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:28:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:28:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:28:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:28:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:28:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:28:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:28:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:28:20 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:28:20 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:28:20 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:28:20 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:28:20 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:20 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:28:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:21 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:28:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:28:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:28:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:28:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:28:21 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:28:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:28:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:28:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:28:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:28:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:28:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:28:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:28:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:22 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:28:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:28:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:28:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:28:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:28:22 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:28:22 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:28:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:28:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:28:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:28:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:28:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:28:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:28:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:28:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:28:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:28:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:28:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:28:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:23 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:28:23 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:28:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:28:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:28:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:28:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:28:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:28:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:28:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:28:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:28:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:28:24 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:28:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:28:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:28:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:24 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:28:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:28:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:28:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:28:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:28:25 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:28:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:28:25 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:28:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:28:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:28:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:28:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:28:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:28:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:28:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:26 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:28:26 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:28:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:28:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:28:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:28:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:28:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:28:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:26 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:28:26 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2024-10-30 06:28:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:27 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:28:27 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:28:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:27 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:28:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:28:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:28:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:28:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:28:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:28:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:27 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:28:27 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2024-10-30 06:28:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:28 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:28:28 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:28:29 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:28:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:29 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:28:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:28:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:28:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:28:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:28:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:28:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:28:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:28:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:28:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:29 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:28:29 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:28:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:28:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:28:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:28:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:28:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:28:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:28:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:28:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:30 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:28:30 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:28:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:28:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:28:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:28:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:28:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:28:31 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:28:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:28:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:28:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:28:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:31 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:28:32 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:28:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:28:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:28:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:28:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:28:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:28:32 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:28:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:32 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:28:32 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:28:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:33 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:28:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:33 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:28:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:28:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:28:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:28:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:28:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:28:33 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:28:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:33 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:28:33 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:28:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:34 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:28:34 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:28:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:34 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:28:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:28:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:28:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:28:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:28:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:28:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:34 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:28:34 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:28:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:35 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:28:35 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:28:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:35 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:28:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:28:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:28:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:28:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:28:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:28:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:35 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:28:35 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:28:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:36 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 06:28:36 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 06:28:37 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 06:28:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:37 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:28:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:28:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:28:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:28:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:28:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:28:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:37 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:28:37 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:28:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:37 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 06:28:37 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 06:28:38 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 06:28:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:38 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:28:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:28:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:28:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:28:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:28:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:28:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:38 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:28:38 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:28:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:38 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 06:28:39 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 06:28:39 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 06:28:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:40 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:28:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:28:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:28:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:28:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:28:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:28:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:40 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:28:40 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:28:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:40 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 06:28:40 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 06:28:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:41 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:28:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:28:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:28:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:28:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:28:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:28:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:41 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:28:41 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:28:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:41 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 06:28:41 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 06:28:42 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 06:28:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:42 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:28:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:28:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:28:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:28:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:28:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:28:42 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 06:28:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:42 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:28:42 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:28:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:43 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 06:28:43 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 06:28:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:44 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:28:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:28:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:28:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:28:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:28:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:28:44 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 06:28:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:44 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:28:44 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:28:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:44 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 06:28:44 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 06:28:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:45 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:28:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:28:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:28:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:28:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:28:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:28:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:28:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:28:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:28:45 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:28:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:28:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:28:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:28:50 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:28:50 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:28:50 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:28:50 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:28:50 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:28:50 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:28:50 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:28:50 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:28:50 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:28:50 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:28:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:28:50 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:28:50 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:28:51 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:28:51 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:28:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:51 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:28:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:28:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:28:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:28:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:28:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:28:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:28:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:28:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:28:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:51 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:28:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:28:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:28:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:28:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:28:51 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:28:52 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:28:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:28:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:28:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:28:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:28:52 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:28:53 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:28:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:28:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:28:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:28:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:28:53 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:28:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:54 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:28:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:28:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:28:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:28:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:28:54 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:28:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:28:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:28:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:28:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:28:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:28:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:28:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:28:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:28:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:55 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:28:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:28:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:28:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:28:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:28:55 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:28:56 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:28:56 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:28:57 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:28:57 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:28:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:58 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:28:58 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:28:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:28:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:28:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:28:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:28:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:28:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:28:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:28:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:28:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:28:58 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:28:58 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:28:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:28:58 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:28:59 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:28:59 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:29:00 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:29:00 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:29:01 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:29:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:29:01 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:29:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:29:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:29:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:29:02 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:29:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:29:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:29:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:29:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:29:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:29:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:29:02 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:29:02 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:29:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:02 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:29:02 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:29:03 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:29:03 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:29:04 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:29:04 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:29:05 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:29:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:29:05 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:29:05 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:29:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:29:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:29:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:29:06 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:29:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:29:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:29:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:29:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:29:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:29:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:29:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:29:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:29:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:29:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:29:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:06 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 06:29:06 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 06:29:07 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 06:29:07 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 06:29:08 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 06:29:08 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 06:29:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:29:09 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 06:29:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:29:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:29:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:29:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:29:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:29:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:29:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:29:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:29:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:29:09 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 06:29:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:29:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:29:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:10 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 06:29:10 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 06:29:11 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 06:29:11 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 06:29:12 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 06:29:12 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 06:29:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:29:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:29:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:29:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:29:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:29:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:29:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:29:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:29:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:29:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:29:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:29:13 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 06:29:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:29:13 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:29:13 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:29:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:13 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 06:29:13 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 06:29:14 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 06:29:14 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 06:29:15 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 06:29:15 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 06:29:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:29:16 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 06:29:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:29:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:29:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:29:16 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:29:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:29:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:29:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:29:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:29:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:29:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:29:16 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:29:16 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:29:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:16 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 06:29:17 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 06:29:17 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 06:29:18 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 06:29:18 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 06:29:19 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 06:29:19 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-10-30 06:29:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:29:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:29:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:29:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:29:19 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:29:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:29:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:29:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:29:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:29:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:29:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:29:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:29:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:29:19 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:29:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:29:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:29:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6412 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:29:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6412 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:29:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6412 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:29:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6412 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:29:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6412 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:29:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6412 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:29:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6412 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:29:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6412 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:29:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:29:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:29:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:29:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:29:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:29:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:29:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:29:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:29:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:29:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:29:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:29:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:29:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:29:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:29:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:29:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:29:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:29:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:29:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:29:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:29:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:29:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:29:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:29:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:29:25 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:29:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:29:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:29:25 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:29:25 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:29:25 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:29:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:29:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:25 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:29:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:29:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:29:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:29:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:29:26 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:29:26 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:29:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:29:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:29:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:29:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:29:27 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:29:27 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:29:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:29:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:29:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:29:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:29:28 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:29:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:29:28 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:29:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:29:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:29:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:29:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:29:29 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:29:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:29:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:29:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:29:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:29:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:29:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:29:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:29:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:29:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:29:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:29:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:29:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:29 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:29:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:29:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:29:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:29:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:29:30 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:29:30 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:29:31 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:29:31 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:29:32 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:29:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:29:32 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:29:33 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:29:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:29:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:29:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:29:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:29:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:29:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:29:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:29:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:29:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:29:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:29:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:29:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:33 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:29:33 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:29:34 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:29:34 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:29:35 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:29:35 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:29:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:29:36 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:29:36 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:29:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:29:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:29:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:29:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:29:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:29:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:29:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:29:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:29:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:29:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:29:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:29:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:37 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:29:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:29:37 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:29:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:29:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:29:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:29:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:29:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:29:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:29:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:29:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:29:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:29:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:29:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:29:37 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:29:37 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:29:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:38 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:29:38 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:29:39 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:29:39 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:29:40 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:29:40 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:29:40 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 06:29:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:29:41 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 06:29:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:29:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:29:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:29:41 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:29:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:29:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:29:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:29:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:29:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:29:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:29:41 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:29:41 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:29:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:41 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 06:29:42 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 06:29:42 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 06:29:43 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 06:29:43 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 06:29:44 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 06:29:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:29:44 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 06:29:45 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 06:29:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:29:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:29:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:29:45 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:29:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:29:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:29:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:29:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:29:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:29:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:29:45 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:29:45 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:29:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:45 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 06:29:46 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 06:29:46 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 06:29:47 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 06:29:47 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 06:29:48 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 06:29:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:29:48 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 06:29:48 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 06:29:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:29:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:29:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:29:49 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:29:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:29:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:29:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:29:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:29:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:29:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:29:49 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:29:49 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:29:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:49 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 06:29:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:29:49 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 06:29:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:29:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:29:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:29:50 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:29:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:29:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:29:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:29:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:29:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:29:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:29:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:29:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:29:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:29:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:29:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:50 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 06:29:50 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 06:29:51 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 06:29:51 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 06:29:52 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 06:29:52 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 06:29:53 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 06:29:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:29:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:29:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:29:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:29:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:29:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:29:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:29:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:29:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:29:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:29:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:29:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:29:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:53 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 06:29:54 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-10-30 06:29:54 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-10-30 06:29:55 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-10-30 06:29:55 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-10-30 06:29:55 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-10-30 06:29:56 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-10-30 06:29:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:29:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:29:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:29:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:29:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:29:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:29:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:29:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:29:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:29:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:29:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:29:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:29:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:29:56 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-10-30 06:29:57 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-10-30 06:29:57 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-10-30 06:29:58 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-10-30 06:29:58 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-10-30 06:29:59 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-10-30 06:29:59 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-10-30 06:29:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:30:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:30:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:30:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:30:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:30:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:30:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:30:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:30:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:30:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:30:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:30:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:30:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:30:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:30:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:30:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:30:00 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-10-30 06:30:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:30:00 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-10-30 06:30:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:30:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:30:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:30:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:30:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:30:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:30:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:30:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:30:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:30:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:30:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:30:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:30:01 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-10-30 06:30:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:30:01 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:30:01 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:30:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:30:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:30:01 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-10-30 06:30:02 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-10-30 06:30:02 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-10-30 06:30:03 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-10-30 06:30:03 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-10-30 06:30:03 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-10-30 06:30:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:30:04 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-10-30 06:30:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:30:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:30:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:30:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:30:04 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:30:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:30:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:30:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:30:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:30:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:30:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:30:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:30:04 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:30:04 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:30:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:30:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:30:04 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-10-30 06:30:05 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-10-30 06:30:05 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-10-30 06:30:06 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-10-30 06:30:06 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-10-30 06:30:07 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-10-30 06:30:07 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-10-30 06:30:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:30:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:30:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:30:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:30:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:30:08 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:30:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:30:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:30:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:30:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:30:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:30:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:30:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:30:08 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:30:08 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:30:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:30:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:30:08 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2024-10-30 06:30:08 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2024-10-30 06:30:09 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2024-10-30 06:30:09 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2024-10-30 06:30:10 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2024-10-30 06:30:10 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2024-10-30 06:30:10 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2024-10-30 06:30:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:30:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:30:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:30:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:30:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:30:11 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:30:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:30:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:30:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:30:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:30:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:30:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:30:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:30:11 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:30:11 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:30:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:30:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:30:11 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2024-10-30 06:30:11 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2024-10-30 06:30:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:30:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:30:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:30:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:30:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:30:12 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:30:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:30:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:30:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:30:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:30:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:30:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:30:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:30:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:30:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:30:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:30:12 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:30:12 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=10288 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:30:12 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=10288 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:30:12 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=10288 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:30:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:30:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:30:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:30:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:30:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:30:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:30:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:30:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:30:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:30:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:30:17 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:30:17 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:30:17 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:30:17 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:30:17 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:30:17 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:30:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:30:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:30:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:30:18 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:30:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:30:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:30:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:30:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:30:18 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:30:19 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:30:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:30:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:30:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:30:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:30:19 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:30:20 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:30:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:30:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:30:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:30:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:30:20 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:30:21 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:30:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:30:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:30:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:30:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:30:21 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:30:22 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:30:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:30:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:30:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:30:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:30:22 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:30:23 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:30:23 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:30:23 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:30:24 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:30:24 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:30:25 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:30:25 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:30:26 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:30:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:30:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:30:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:30:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:30:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:30:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:30:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:30:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:30:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:30:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:30:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:30:26 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:30:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:30:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:30:31 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:30:31 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:30:31 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:30:31 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:30:31 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:30:31 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:30:31 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:30:31 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:30:31 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:30:31 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:30:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:30:31 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:30:32 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:30:32 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:30:32 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:30:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:30:32 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:30:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:30:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:30:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:30:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:30:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:30:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:30:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:30:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:30:32 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:30:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:30:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:30:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:30:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:30:33 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:30:33 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:30:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:30:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:30:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:30:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:30:34 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:30:34 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:30:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:30:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:30:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:30:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:30:34 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:30:35 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:30:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:30:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:30:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:30:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:30:35 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:30:36 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:30:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:30:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:30:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:30:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:30:36 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:30:37 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:30:37 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:30:38 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:30:38 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:30:39 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:30:39 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:30:40 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:30:40 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:30:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:30:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:30:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:30:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:30:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:30:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:30:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:30:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:30:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:30:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:30:40 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:30:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:30:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:30:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:30:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:30:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:30:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:30:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:30:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:30:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:30:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:30:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:30:45 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:30:45 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:30:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:30:45 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:30:46 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:30:46 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:30:46 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:30:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:30:46 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:30:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:30:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:30:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:30:46 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:30:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:30:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:30:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:30:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:30:47 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:30:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:30:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:30:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:30:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:30:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:30:47 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:30:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:30:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:30:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:30:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:30:48 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:30:48 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:30:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:30:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:30:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:30:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:30:49 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:30:49 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:30:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:30:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:30:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:30:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:30:50 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:30:50 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:30:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:30:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:30:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:30:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:30:51 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:30:51 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:30:52 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:30:52 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:30:53 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:30:53 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:30:53 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:30:54 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:30:54 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:30:55 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:30:55 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:30:56 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:30:56 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:30:57 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:30:57 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:30:58 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:30:58 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:30:59 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:30:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:30:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:30:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:30:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:30:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:30:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:30:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:30:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:30:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:30:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:30:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:30:59 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:30:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:31:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:31:04 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:31:04 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:31:04 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:31:04 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:31:04 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:31:04 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:31:04 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:31:04 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:31:04 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:31:04 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:04 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:31:04 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:31:04 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:31:04 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:31:04 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:31:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:31:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:31:05 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:31:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:31:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:31:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:31:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:31:05 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:31:05 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:31:06 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:31:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:31:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:31:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:31:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:31:06 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:31:06 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:31:06 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:31:07 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:31:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:31:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:31:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:31:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:31:07 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:31:08 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:31:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:31:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:31:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:31:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:31:08 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:31:08 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:31:09 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:31:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:31:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:31:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:31:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:31:09 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:31:09 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:31:09 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:31:09 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:31:10 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:31:10 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:31:10 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:31:11 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:31:11 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:31:12 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:31:12 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:31:12 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:31:13 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:31:13 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:31:14 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:31:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:31:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:31:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:31:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:31:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:31:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:31:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:31:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:31:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:31:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:31:14 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:31:14 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2218 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:31:14 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2218 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:31:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:31:19 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:31:19 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:31:19 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:31:19 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:31:19 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:31:19 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:31:19 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:31:19 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:31:19 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:31:19 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:19 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:31:20 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:31:20 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:31:20 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:31:20 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:31:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:20 [WARNING] transceiver.py:250 (MS@172.18.83.22:6700) RX TRXD message (fn=140 tn=6 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:31:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:31:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:31:20 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:31:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:31:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:31:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:31:20 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:20 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:31:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:31:20 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:20 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:31:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:31:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:31:20 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:31:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:31:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:31:21 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:21 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:31:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:31:21 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:21 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:31:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:31:21 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:21 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:31:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:31:21 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:21 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:21 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:31:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:31:21 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:21 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:22 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:31:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:31:22 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:22 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:31:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:31:22 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:22 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:22 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:31:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:31:22 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:22 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:31:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:31:22 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:22 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:31:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:23 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:31:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:31:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:31:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:31:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:31:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:31:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:31:23 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:31:23 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:31:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:23 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:31:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:31:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:31:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:31:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:31:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:31:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:31:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:31:23 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:31:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:31:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:31:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:31:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=810 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:31:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=810 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:31:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=810 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:31:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=810 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:31:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=810 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:31:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=810 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:31:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=810 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:31:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=810 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:31:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:31:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:31:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:31:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:31:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:31:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:31:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:31:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:31:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:31:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:31:28 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:31:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:31:28 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:31:28 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:31:28 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:31:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:31:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:29 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:31:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:31:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:31:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:31:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:31:29 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:31:30 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:31:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:31:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:31:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:31:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:31:30 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:31:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:31:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:31:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:31:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:31:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:31:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:31:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:31:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:31:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:31:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:31:30 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:31:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:31:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:31:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:31:35 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:31:35 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:31:35 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:31:35 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:31:35 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:31:35 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:31:35 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:31:35 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:31:35 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:31:35 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:31:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:31:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:31:35 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:31:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:31:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:31:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:31:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:31:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:31:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:31:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:31:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:31:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:31:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:31:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:31:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:31:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:31:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:31:41 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:31:41 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:31:41 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:31:41 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:31:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:41 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:31:41 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:31:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:31:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:31:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:31:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:31:42 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:31:42 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:31:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:31:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:31:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:31:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:31:43 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:31:43 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:31:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:31:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:31:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:31:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:31:44 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:31:44 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:31:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:31:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:31:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:31:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:31:45 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:31:45 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:31:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:31:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:31:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:31:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:31:46 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:31:46 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:31:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:31:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:31:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:31:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:31:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:31:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:31:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:31:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:31:47 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:31:47 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1309 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:31:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:31:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:31:47 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1309 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:31:47 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1309 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:31:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:31:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:31:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:31:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:31:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:31:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:31:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:31:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:31:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:31:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:31:52 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:31:52 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:31:52 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:31:52 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:31:52 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:31:52 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:31:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:31:53 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:31:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:31:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:31:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:31:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:31:53 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:31:53 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:31:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:31:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:31:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:31:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:31:54 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:31:54 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:31:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:31:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:31:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:31:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:31:55 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:31:55 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:31:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:31:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:31:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:31:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:31:56 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:31:56 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:31:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:31:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:31:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:31:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:31:57 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:31:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:31:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:31:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:31:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:31:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:31:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:31:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:31:57 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:31:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:31:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:31:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:32:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:32:02 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:32:02 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:32:02 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:32:02 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:32:02 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:32:02 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:32:02 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:32:02 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:32:02 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:32:02 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:32:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:32:02 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:32:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:32:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:32:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:32:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:32:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:32:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:32:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:32:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:32:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:32:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:32:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:32:07 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:07 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:32:08 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:32:08 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:32:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:32:08 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:32:08 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:32:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:32:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:32:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:32:08 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:32:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:32:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:32:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:32:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:32:09 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:32:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:32:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:32:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:32:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:32:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:32:09 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:32:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:32:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:32:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:32:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:32:10 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:32:10 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:32:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:32:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:32:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:32:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:32:10 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:32:11 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:32:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:32:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:32:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:32:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:32:11 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:32:12 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:32:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:32:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:32:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:32:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:32:12 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:32:13 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:32:13 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:32:14 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:32:14 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:32:15 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:32:15 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:32:16 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:32:16 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:32:17 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:32:17 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:32:18 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:32:18 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:32:18 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:32:19 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:32:19 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:32:20 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:32:20 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:32:21 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:32:21 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:32:22 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:32:22 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:32:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:32:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:32:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:32:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:32:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:32:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:32:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:32:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:32:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:32:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:32:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:32:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:32:22 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:32:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:32:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:32:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:32:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:32:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:32:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:32:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:32:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:32:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:32:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:32:27 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:32:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:32:28 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:32:28 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:32:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:32:28 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:32:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:32:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:32:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:32:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:32:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:32:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:32:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:32:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:32:28 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:32:28 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:32:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:32:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:32:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:32:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:32:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:32:28 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:32:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:32:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:32:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:32:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:32:29 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:32:29 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:32:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:32:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:32:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:32:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:32:30 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:32:30 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:32:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:32:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:32:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:32:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:32:31 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:32:31 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:32:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:32:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:32:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:32:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:32:32 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:32:32 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:32:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:32:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:32:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:32:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:32:33 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:32:33 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:32:34 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:32:34 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:32:35 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:32:35 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:32:35 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:32:36 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:32:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:32:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:32:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:32:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:32:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:32:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:32:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:32:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:32:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:32:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:32:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:32:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:32:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:32:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:32:36 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:32:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:32:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:32:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:32:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:32:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:32:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:32:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:32:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:32:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:32:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:32:41 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:32:42 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:32:42 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:32:42 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:32:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:32:42 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:32:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:32:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:32:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:32:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:32:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:32:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:32:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:32:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:32:42 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:32:42 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:32:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:32:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:32:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:32:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:32:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:32:42 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:32:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:32:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:32:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:32:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:32:43 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:32:43 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:32:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:32:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:32:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:32:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:32:43 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:32:44 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:32:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:32:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:32:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:32:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:32:44 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:32:45 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:32:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:32:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:32:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:32:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:32:45 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:32:46 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:32:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:32:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:32:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:32:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:32:46 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:32:47 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:32:47 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:32:48 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:32:48 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:32:49 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:32:49 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:32:50 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:32:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:32:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:32:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:32:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:32:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:32:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:32:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:32:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:32:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:32:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:32:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:32:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:32:50 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:32:50 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:32:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:32:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:32:50 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:32:50 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:32:50 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:32:50 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:32:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:32:55 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:32:55 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:32:55 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:32:55 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:32:55 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:32:55 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:32:55 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:32:55 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:32:55 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:32:55 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:32:55 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:32:55 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:32:55 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:32:55 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:32:55 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:32:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:32:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:32:55 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:32:55 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:32:55 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:32:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:32:56 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:32:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:32:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:32:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:32:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:32:56 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:32:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:32:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:32:56 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:32:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:32:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:32:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:32:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:32:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:32:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:32:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:32:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:32:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:32:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:32:56 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:33:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:33:01 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:33:01 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:33:01 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:33:01 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:33:01 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:33:01 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:33:01 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:33:01 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:33:01 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:33:01 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:01 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:33:02 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:33:02 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:33:02 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:33:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:33:02 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:33:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:33:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:33:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:33:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:33:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:33:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:33:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:33:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:33:02 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:33:02 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:33:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:33:02 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:33:02 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:33:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:33:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:33:02 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:33:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:33:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:33:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:33:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:33:03 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:33:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:33:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:33:03 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:33:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:33:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:33:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:33:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:33:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:33:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:33:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:33:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:33:03 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:33:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:33:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:33:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:33:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:33:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:33:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:33:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:33:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:33:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:33:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:33:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:33:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:33:08 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:33:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:33:09 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:33:09 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:33:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:33:09 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:33:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:33:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:33:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:33:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:33:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:33:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:33:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:33:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:33:09 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:33:09 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:33:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:33:09 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:33:09 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:33:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:33:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:33:09 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:33:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:33:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:33:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:33:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:33:09 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:33:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:33:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:33:10 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:33:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:33:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:33:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:33:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:33:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:33:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:33:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:33:10 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:33:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:33:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:33:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:33:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:33:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:33:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:33:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:33:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:33:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:33:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:33:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:33:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:33:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:33:15 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:15 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:33:15 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:33:15 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:33:15 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:33:15 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:33:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:33:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:33:15 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:33:15 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:33:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:33:16 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:33:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:33:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:33:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:33:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:33:16 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:33:17 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:33:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:33:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:33:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:33:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:33:17 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:33:18 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:33:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:33:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:33:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:33:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:33:18 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:33:18 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:33:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:33:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:33:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:33:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:33:19 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:33:19 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:33:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:33:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:33:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:33:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:33:20 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:33:20 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:33:21 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:33:21 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:33:22 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:33:22 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:33:23 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:33:23 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:33:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:33:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:33:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:33:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:33:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:33:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:33:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:33:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:33:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:33:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:33:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:33:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:33:23 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:33:23 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:33:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:33:23 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:33:23 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2024-10-30 06:33:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:33:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:33:24 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:33:24 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:33:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:33:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:33:24 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:33:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:33:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:33:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:33:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:33:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:33:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:33:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:33:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:33:24 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:33:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:33:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:33:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:33:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:33:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:33:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:33:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:33:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:33:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:33:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:33:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:33:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:33:29 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:29 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:33:30 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:33:30 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:33:30 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:33:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:33:30 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:33:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:33:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:33:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:33:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:33:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:33:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:33:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:33:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:33:30 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:33:30 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:33:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:33:30 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:33:30 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:33:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:33:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:33:30 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:33:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:33:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:33:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:33:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:33:31 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:33:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:33:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:33:31 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:33:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:33:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:33:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:33:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:33:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:33:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:33:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:33:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:33:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:33:31 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:33:31 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=351 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:33:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:33:31 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=351 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:33:31 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=351 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:33:31 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=352 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:33:31 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=352 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:33:31 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=352 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:33:31 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=352 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:33:31 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=352 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:33:31 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=352 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:33:31 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=352 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:33:31 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=352 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:33:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:33:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:33:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:33:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:33:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:33:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:33:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:33:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:33:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:33:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:33:36 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:33:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:33:36 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:33:37 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:33:37 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:33:37 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:33:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:33:37 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:33:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:33:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:33:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:33:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:33:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:33:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:33:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:33:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:33:37 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:33:37 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:33:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:33:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:33:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:33:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:33:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:33:37 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:33:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:33:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:33:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:33:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:33:37 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:33:38 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:33:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:33:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:33:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:33:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:33:38 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:33:39 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:33:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:33:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:33:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:33:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:33:39 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:33:40 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:33:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:33:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:33:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:33:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:33:40 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:33:41 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:33:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:33:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:33:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:33:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:33:41 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:33:42 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:33:42 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:33:43 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:33:43 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:33:44 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:33:44 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:33:45 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:33:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:33:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:33:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:33:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:33:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:33:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:33:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:33:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:33:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:33:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:33:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:33:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:33:45 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:33:45 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:33:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:33:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:33:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:33:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:33:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:33:45 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:33:45 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:33:46 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:33:46 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:33:47 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:33:47 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:33:48 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:33:48 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:33:49 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:33:49 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:33:50 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:33:50 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:33:51 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:33:51 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:33:52 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:33:52 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 06:33:52 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 06:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:33:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:33:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:33:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:33:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:33:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:33:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:33:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:33:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:33:53 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:33:53 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:33:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:33:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:33:53 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 06:33:53 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 06:33:54 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 06:33:54 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 06:33:55 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 06:33:55 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 06:33:56 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 06:33:56 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 06:33:57 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 06:33:57 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 06:33:58 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 06:33:58 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 06:33:59 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 06:33:59 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 06:34:00 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 06:34:00 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 06:34:00 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 06:34:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:34:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:34:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:34:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:34:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:34:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:34:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:34:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:34:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:34:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:34:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:34:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:34:01 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:34:01 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:34:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:34:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:34:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:34:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:34:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:34:01 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 06:34:01 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 06:34:02 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 06:34:02 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 06:34:03 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 06:34:03 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 06:34:04 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 06:34:04 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 06:34:05 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 06:34:05 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-10-30 06:34:06 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-10-30 06:34:06 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-10-30 06:34:07 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-10-30 06:34:07 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-10-30 06:34:08 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-10-30 06:34:08 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-10-30 06:34:08 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-10-30 06:34:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:34:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:34:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:34:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:34:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:34:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:34:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:34:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:34:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:34:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:34:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:34:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:34:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:34:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:34:09 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:34:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:34:14 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:34:14 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:34:14 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:34:14 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:34:14 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:34:14 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:34:14 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:34:14 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:34:14 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:34:14 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:14 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:34:14 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:34:14 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:34:14 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:34:14 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:34:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:34:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:34:14 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:34:14 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:34:14 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:34:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:34:15 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:34:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:34:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:34:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:34:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:34:15 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:34:16 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:34:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:34:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:34:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:34:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:34:16 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:34:17 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:34:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:34:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:34:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:34:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:34:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:34:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:34:17 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:34:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:34:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:34:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:34:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:34:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:34:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:34:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:34:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:34:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:34:17 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:34:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:34:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:34:22 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:34:22 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:34:22 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:34:22 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:34:22 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:34:22 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:34:22 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:34:22 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:34:22 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:34:22 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:22 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:34:22 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:34:23 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:34:23 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:34:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:34:23 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:34:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:34:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:34:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:34:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:34:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:34:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:34:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:34:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:34:23 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:34:23 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:34:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:34:23 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:34:23 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:34:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:34:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:34:23 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:34:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:34:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:34:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:34:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:34:23 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:34:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:34:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:34:24 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:34:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:34:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:34:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:34:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:34:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:34:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:34:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:34:24 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:34:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:34:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:34:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:34:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:34:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:34:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:34:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:34:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:34:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:34:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:34:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:34:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:34:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:34:29 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:29 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:34:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:34:29 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:34:29 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:34:29 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:34:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:34:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:34:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:34:30 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:34:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:34:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:34:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:34:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:34:30 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:34:31 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:34:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:34:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:34:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:34:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:34:31 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:34:31 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:34:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:34:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:34:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:34:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:34:32 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:34:32 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:34:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:34:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:34:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:34:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:34:33 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:34:33 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:34:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:34:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:34:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:34:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:34:34 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:34:34 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:34:35 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:34:35 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:34:36 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:34:36 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:34:37 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:34:37 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:34:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:34:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:34:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:34:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:34:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:34:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:34:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:34:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:34:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:34:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:34:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:34:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:34:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:34:37 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:34:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:34:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:34:42 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:34:42 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:34:42 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:34:42 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:34:42 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:34:42 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:34:42 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:34:42 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:34:42 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:34:42 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:42 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:34:43 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:34:43 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:34:43 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:34:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:34:43 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:34:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:34:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:34:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:34:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:34:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:34:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:34:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:34:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:34:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:34:43 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:34:43 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:34:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:34:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:34:43 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:34:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:34:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:34:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:34:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:34:44 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:34:44 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:34:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:34:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:34:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:34:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:34:45 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:34:45 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:34:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:34:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:34:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:34:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:34:46 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:34:46 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:34:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:34:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:34:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:34:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:34:46 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:34:47 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:34:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:34:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:34:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:34:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:34:47 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:34:48 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:34:48 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:34:49 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:34:49 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:34:50 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:34:50 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:34:51 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:34:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:34:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:34:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:34:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:34:51 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:34:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:34:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:34:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:34:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:34:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:34:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:34:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:34:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:34:51 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:34:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:34:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:34:51 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1871 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:34:51 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1871 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:34:51 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1871 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:34:51 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1871 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:34:51 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1871 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:34:51 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1871 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:34:51 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1871 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:34:51 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1871 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:34:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:34:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:34:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:34:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:34:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:34:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:34:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:34:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:34:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:34:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:34:56 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:34:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:34:56 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:34:56 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:34:56 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:34:56 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:34:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:34:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:34:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:34:57 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:34:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:34:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:34:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:34:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:34:57 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:34:58 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:34:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:34:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:34:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:34:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:34:58 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:34:59 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:34:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:34:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:34:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:34:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:34:59 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:35:00 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:35:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:35:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:35:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:35:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:35:00 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:35:01 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:35:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:35:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:35:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:35:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:35:01 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:35:02 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:35:02 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:35:02 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:35:03 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:35:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:35:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:35:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:35:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:35:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:35:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:35:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:35:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:35:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:35:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:35:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:35:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:35:03 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:35:03 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1564 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:35:03 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1564 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:35:03 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1564 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:35:03 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1564 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:35:03 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1564 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:35:03 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1564 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:35:03 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1564 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:35:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:35:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:35:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:35:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:35:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:35:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:35:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:35:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:35:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:35:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:35:08 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:35:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:35:09 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:35:09 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:35:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:35:09 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:35:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:35:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:35:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:35:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:35:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:35:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:35:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:35:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:35:09 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:35:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:35:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:35:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:35:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:35:10 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:35:10 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:35:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:35:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:35:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:35:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:35:10 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:35:11 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:35:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:35:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:35:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:35:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:35:11 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:35:12 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:35:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:35:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:35:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:35:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:35:12 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:35:13 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:35:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:35:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:35:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:35:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:35:13 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:35:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:35:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:35:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:35:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:35:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:35:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:35:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:35:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:35:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:35:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:35:14 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:35:14 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:35:15 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:35:15 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:35:16 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:35:16 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:35:17 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:35:17 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:35:18 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:35:18 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:35:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:35:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:35:18 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:35:18 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:35:18 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:35:18 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:35:18 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:35:18 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:35:18 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:35:18 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:35:18 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:35:18 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:35:18 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:35:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:35:18 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:35:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:35:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:35:23 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:35:23 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:35:23 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:35:23 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:35:23 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:35:23 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:35:23 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:35:23 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:35:23 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:35:23 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:23 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:35:24 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:35:24 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:35:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:35:24 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:35:24 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:35:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:35:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:35:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:35:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:35:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:35:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:35:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:35:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:35:24 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:35:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:35:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:35:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:35:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:35:25 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:35:25 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:35:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:35:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:35:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:35:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:35:26 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:35:26 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:35:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:35:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:35:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:35:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:35:27 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:35:27 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:35:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:35:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:35:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:35:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:35:28 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:35:28 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:35:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:35:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:35:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:35:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:35:29 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:35:29 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:35:30 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:35:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:35:30 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:35:30 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:35:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:35:31 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:35:31 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:35:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:35:32 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:35:32 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:35:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:35:33 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:35:33 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:35:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:35:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:35:34 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:35:34 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:35:35 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:35:35 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:35:36 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:35:36 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:35:37 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:35:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:35:37 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:35:38 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:35:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:35:38 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:35:38 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:35:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:35:39 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:35:39 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 06:35:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:35:40 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 06:35:40 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 06:35:41 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 06:35:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:35:41 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 06:35:42 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 06:35:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:35:42 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 06:35:43 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 06:35:43 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 06:35:44 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 06:35:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:35:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:35:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:35:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:35:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:35:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:35:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:35:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:35:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:35:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:35:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:35:44 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:35:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:35:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:35:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:35:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:35:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:35:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:35:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:35:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:35:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:35:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:35:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:35:49 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:35:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:35:50 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:35:50 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:35:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:35:50 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:35:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:35:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:35:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:35:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:35:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:35:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:35:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:35:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:35:50 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:35:50 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:35:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD NOHANDOVER
2024-10-30 06:35:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:35:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:35:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:35:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:35:50 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=126 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:50 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=132 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:50 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=135 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:50 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=138 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:50 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=141 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:50 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=144 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:50 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=147 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:50 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=150 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:50 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=153 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:50 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=156 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:50 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=159 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:50 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=162 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:50 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=165 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:50 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=171 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:50 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=174 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:50 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=177 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:50 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=180 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:50 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=183 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:50 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=186 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:50 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=189 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:50 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=192 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:50 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=195 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:50 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=198 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:50 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=201 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:50 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=204 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:50 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:35:50 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=210 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:50 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=213 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:50 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=216 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:35:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:35:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:35:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:35:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:35:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD NOHANDOVER
2024-10-30 06:35:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:35:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:35:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:35:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:35:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:35:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:35:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:35:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:35:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:35:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:35:51 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:35:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:35:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:35:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:35:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:35:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:35:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:35:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:35:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:35:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:35:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:35:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:35:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:35:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:35:56 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:35:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:35:56 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:35:56 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:35:56 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:35:56 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:35:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:35:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:35:56 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:35:56 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD NOHANDOVER
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:35:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:35:57 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=132 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:57 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=135 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:57 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=138 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:57 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=141 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:57 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=144 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:57 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=147 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:57 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=150 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:57 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=153 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:57 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=156 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:57 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=159 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:57 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=162 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:57 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=165 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:57 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=171 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:57 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=174 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:57 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=177 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:57 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=180 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:57 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=183 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:57 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=186 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:57 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=189 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:57 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=192 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:57 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=195 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:57 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=198 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:57 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=201 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:57 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=204 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:57 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:35:57 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=210 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:57 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=213 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:57 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=216 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-10-30 06:35:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:35:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:35:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:35:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:35:57 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:35:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD NOHANDOVER
2024-10-30 06:35:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:35:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:35:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:35:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:35:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:35:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:35:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:35:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:35:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:35:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:35:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:35:58 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:35:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:35:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:36:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:36:03 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:36:03 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:36:03 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:36:03 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:36:03 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:36:03 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:36:03 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:36:03 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:36:03 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:36:03 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:36:03 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:36:03 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:36:03 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:36:03 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:36:03 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:36:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:36:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:36:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:36:04 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:36:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:36:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:36:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:36:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:36:04 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:36:05 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:36:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:36:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:36:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:36:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:36:05 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:36:06 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:36:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:36:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:36:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:36:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:36:06 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:36:07 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:36:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:36:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:36:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:36:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:36:07 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:36:08 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:36:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:36:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:36:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:36:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:36:08 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:36:08 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:36:09 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:36:09 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:36:10 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:36:10 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:36:11 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:36:11 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:36:12 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:36:12 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:36:13 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:36:13 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:36:14 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:36:14 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:36:15 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:36:15 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:36:15 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:36:16 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:36:16 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:36:17 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:36:17 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:36:18 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:36:18 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:36:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:36:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:36:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:36:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:36:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:36:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:36:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:36:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:36:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:36:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:36:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:36:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:36:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:36:19 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:36:19 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2024-10-30 06:36:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:36:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:36:19 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 06:36:19 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 06:36:20 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 06:36:20 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 06:36:21 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 06:36:21 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 06:36:22 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 06:36:22 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 06:36:23 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 06:36:23 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 06:36:23 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 06:36:24 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 06:36:24 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 06:36:25 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 06:36:25 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 06:36:26 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 06:36:26 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 06:36:27 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 06:36:27 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 06:36:28 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 06:36:28 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 06:36:29 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 06:36:29 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 06:36:30 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 06:36:30 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 06:36:31 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 06:36:31 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 06:36:31 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 06:36:32 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-10-30 06:36:32 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-10-30 06:36:33 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-10-30 06:36:33 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-10-30 06:36:34 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-10-30 06:36:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:36:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:36:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:36:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:36:34 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:36:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:36:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:36:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:36:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:36:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:36:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:36:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:36:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:36:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:36:34 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:36:34 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2024-10-30 06:36:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:36:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:36:34 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-10-30 06:36:35 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-10-30 06:36:35 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-10-30 06:36:36 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-10-30 06:36:36 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-10-30 06:36:37 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-10-30 06:36:37 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-10-30 06:36:38 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-10-30 06:36:38 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-10-30 06:36:38 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-10-30 06:36:39 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-10-30 06:36:39 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-10-30 06:36:40 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-10-30 06:36:40 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-10-30 06:36:41 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-10-30 06:36:41 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-10-30 06:36:42 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-10-30 06:36:42 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-10-30 06:36:43 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-10-30 06:36:43 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-10-30 06:36:44 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-10-30 06:36:44 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-10-30 06:36:45 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-10-30 06:36:45 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-10-30 06:36:46 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-10-30 06:36:46 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2024-10-30 06:36:46 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2024-10-30 06:36:47 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2024-10-30 06:36:47 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2024-10-30 06:36:48 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2024-10-30 06:36:48 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2024-10-30 06:36:49 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2024-10-30 06:36:49 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2024-10-30 06:36:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:36:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:36:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:36:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:36:49 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:36:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:36:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:36:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:36:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:36:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:36:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:36:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:36:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:36:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:36:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:36:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:36:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:36:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:36:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:36:50 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2024-10-30 06:36:50 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2024-10-30 06:36:51 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2024-10-30 06:36:51 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2024-10-30 06:36:52 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2024-10-30 06:36:52 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2024-10-30 06:36:53 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2024-10-30 06:36:53 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2024-10-30 06:36:53 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2024-10-30 06:36:54 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2024-10-30 06:36:54 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2024-10-30 06:36:55 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2024-10-30 06:36:55 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2024-10-30 06:36:56 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2024-10-30 06:36:56 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2024-10-30 06:36:57 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2024-10-30 06:36:57 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2024-10-30 06:36:58 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2024-10-30 06:36:58 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2024-10-30 06:36:59 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2024-10-30 06:36:59 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2024-10-30 06:37:00 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2024-10-30 06:37:00 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2024-10-30 06:37:01 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2024-10-30 06:37:01 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2024-10-30 06:37:01 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2024-10-30 06:37:02 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2024-10-30 06:37:02 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2024-10-30 06:37:03 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2024-10-30 06:37:03 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2024-10-30 06:37:04 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2024-10-30 06:37:04 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2024-10-30 06:37:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:37:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:37:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:37:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:37:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:37:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:37:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:37:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:37:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:37:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:37:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:37:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:37:05 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:37:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:37:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:37:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:37:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:37:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:37:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:37:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:37:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:37:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:37:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:37:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:37:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:37:10 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:37:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:37:10 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:37:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:37:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:37:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:37:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:37:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:37:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:37:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:37:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:37:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:37:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:37:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:37:15 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:37:15 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:37:15 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:37:15 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:37:15 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:37:15 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:37:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:37:15 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:37:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:37:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:37:16 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:37:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:37:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:37:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:37:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:37:16 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:37:17 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:37:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:37:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:37:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:37:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:37:17 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:37:18 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:37:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:37:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:37:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:37:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:37:18 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:37:19 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:37:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:37:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:37:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:37:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:37:19 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:37:19 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:37:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:37:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:37:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:37:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:37:20 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:37:20 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:37:21 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:37:21 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:37:22 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:37:22 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:37:23 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:37:23 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:37:24 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:37:24 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:37:25 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:37:25 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:37:26 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:37:26 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:37:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:37:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:37:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:37:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:37:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:37:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:37:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:37:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:37:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:37:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:37:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:37:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:37:26 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:37:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:37:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:37:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:37:31 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:37:31 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:37:31 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:37:31 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:37:31 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:37:31 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:37:31 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:37:31 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:37:31 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:37:31 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:37:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:37:31 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:37:32 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:37:32 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:37:32 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:37:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:37:32 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:37:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:37:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:37:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:37:32 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:37:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:37:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:37:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:37:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:37:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:37:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:37:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:37:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:37:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:37:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:37:32 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:37:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:37:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:37:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:37:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:37:33 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:37:33 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:37:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:37:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:37:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:37:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:37:34 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:37:34 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:37:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:37:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:37:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:37:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:37:35 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:37:35 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:37:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:37:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:37:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:37:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:37:35 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:37:36 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:37:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:37:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:37:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:37:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:37:36 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:37:37 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:37:37 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:37:38 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:37:38 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:37:39 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:37:39 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:37:40 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:37:40 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:37:41 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:37:41 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:37:42 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:37:42 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:37:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:37:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:37:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:37:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:37:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:37:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:37:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:37:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:37:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:37:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:37:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:37:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:37:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:37:42 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:37:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:37:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:37:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:37:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:37:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:37:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:37:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:37:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:37:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:37:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:37:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:37:47 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:37:47 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:37:48 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:37:48 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:37:48 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:37:48 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:37:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:37:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:37:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:37:48 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:37:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:37:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:37:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:37:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:37:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:37:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:37:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:37:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:37:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:37:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:37:48 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:37:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:37:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:37:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:37:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:37:49 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:37:49 [DEBUG] fake_trx.py:263 (MS@172.18.83.22:6700) Recv SETTA cmd
2024-10-30 06:37:49 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:37:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:37:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:37:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:37:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:37:50 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:37:50 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:37:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:37:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:37:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:37:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:37:51 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:37:51 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:37:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:37:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:37:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:37:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:37:52 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:37:52 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:37:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:37:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:37:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:37:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:37:52 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:37:53 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:37:53 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:37:54 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:37:54 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:37:55 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:37:55 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:37:56 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:37:56 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:37:57 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:37:57 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:37:58 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:37:58 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:37:59 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:37:59 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:37:59 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:38:00 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:38:00 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:38:01 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:38:01 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:38:02 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:38:02 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:38:03 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:38:03 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 06:38:04 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 06:38:04 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 06:38:05 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 06:38:05 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 06:38:06 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 06:38:06 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 06:38:07 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 06:38:07 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 06:38:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:38:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:38:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:38:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:38:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:38:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:38:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:38:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:38:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:38:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:38:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:38:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:38:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:38:07 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:38:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:38:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4383 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:38:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4383 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:38:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4383 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:38:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4383 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:38:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4383 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:38:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4383 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:38:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4383 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:38:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4383 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:38:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:38:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:38:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:38:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:38:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:38:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:38:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:38:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:38:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:38:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:38:12 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:38:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:38:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:38:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:38:13 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:38:13 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:38:13 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:38:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:38:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:38:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:38:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:38:13 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:38:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:38:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:38:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:38:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:38:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:38:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:38:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:38:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:38:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:38:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:38:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:38:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:38:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:38:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:38:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:38:14 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:38:14 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:38:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:38:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:38:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:38:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:38:15 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:38:15 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:38:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:38:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:38:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:38:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:38:16 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:38:16 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:38:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:38:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:38:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:38:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:38:17 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:38:17 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:38:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:38:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:38:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:38:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:38:18 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:38:18 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:38:19 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:38:19 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:38:20 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:38:20 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:38:20 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:38:21 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:38:21 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:38:22 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:38:22 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:38:23 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:38:23 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:38:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:38:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:38:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:38:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:38:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:38:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:38:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:38:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:38:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:38:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:38:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:38:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:38:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:38:23 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:38:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:38:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:38:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:38:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:38:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:38:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:38:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:38:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:38:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:38:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:38:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:38:28 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:38:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:38:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:38:29 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:38:29 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:38:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:38:29 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:38:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:38:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:38:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:38:29 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:38:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:38:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:38:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:38:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:38:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:38:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:38:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:38:29 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:38:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:38:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:38:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:38:29 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:38:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:38:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:38:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:38:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:38:30 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:38:30 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:38:30 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:38:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:38:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:38:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:38:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:38:31 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:38:31 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:38:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:38:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:38:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:38:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:38:32 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:38:32 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:38:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:38:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:38:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:38:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:38:33 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:38:33 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:38:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:38:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:38:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:38:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:38:34 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:38:34 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:38:35 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:38:35 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:38:36 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:38:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:38:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:38:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:38:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:38:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:38:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:38:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:38:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:38:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:38:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:38:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:38:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:38:36 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:38:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:38:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:38:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:38:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:38:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:38:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:38:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:38:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:38:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:38:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:38:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:38:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:38:41 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:38:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:38:41 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:38:41 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:38:41 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:38:41 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:38:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:38:41 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:38:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:38:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:38:42 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:38:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:38:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:38:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:38:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:38:42 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:38:43 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:38:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:38:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:38:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:38:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:38:43 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:38:44 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:38:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:38:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:38:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:38:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:38:44 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:38:44 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:38:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:38:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:38:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:38:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:38:45 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:38:45 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:38:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:38:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:38:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:38:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:38:46 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:38:46 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:38:47 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:38:47 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:38:48 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:38:48 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:38:49 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:38:49 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:38:50 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:38:50 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:38:51 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:38:51 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:38:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:38:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:38:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:38:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:38:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:38:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:38:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:38:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:38:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:38:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:38:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:38:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:38:51 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:38:51 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2300 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:38:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:38:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:38:51 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2300 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:38:51 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2300 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:38:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:38:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:38:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:38:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:38:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:38:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:38:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:38:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:38:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:38:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:38:56 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:38:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:38:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:38:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:38:57 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:38:57 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:38:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:38:57 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:38:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:38:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:38:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:38:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:38:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:38:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:38:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:38:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:38:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:38:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:38:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:38:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:38:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:38:57 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:38:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:38:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:38:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:38:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:38:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:38:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:38:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:38:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:38:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:38:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:38:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:38:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:38:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:38:57 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:38:57 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:38:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:38:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:38:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:38:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:38:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:38:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:38:58 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:38:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:38:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:38:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:38:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:38:58 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:38:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:38:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:38:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:38:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:38:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:38:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:38:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:38:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:38:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:38:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:38:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:38:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:38:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:38:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:38:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:38:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:38:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:38:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:38:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:38:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:38:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:38:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:38:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:38:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:38:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:38:58 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:38:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:38:58 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:38:58 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:38:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:38:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:38:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:38:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:38:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:38:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:38:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:38:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:38:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:38:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:38:59 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:38:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:38:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:38:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:38:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:38:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:38:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:38:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:38:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:38:59 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:38:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:38:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:39:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:39:04 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:39:04 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:39:04 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:39:04 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:39:04 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:39:04 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:39:04 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:39:04 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:39:04 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:39:04 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:39:04 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:39:04 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:39:04 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:39:04 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:39:04 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:39:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:39:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:39:04 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:39:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:39:05 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:39:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:39:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:39:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:39:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:39:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:39:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:39:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:39:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:39:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:39:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:39:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:39:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:39:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:39:05 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:39:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:39:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:39:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:39:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:39:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:39:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:39:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:39:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:39:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:39:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:39:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:39:10 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:39:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:39:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:39:10 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:39:10 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:39:10 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:39:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:39:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:39:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:39:11 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:39:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:39:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:39:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:39:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:39:11 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:39:12 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:39:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:39:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:39:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:39:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:39:12 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:39:12 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:39:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:39:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:39:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:39:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:39:13 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:39:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:39:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:39:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:39:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:39:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:39:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:39:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:39:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:39:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:39:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:39:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:39:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:39:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:39:13 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:39:13 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:39:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:39:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:39:13 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:39:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:39:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:39:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:39:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:39:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:39:14 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:39:14 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:39:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:39:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:39:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:39:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:39:15 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:39:15 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:39:16 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:39:16 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:39:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:39:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:39:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:39:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:39:17 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:39:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:39:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:39:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:39:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:39:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:39:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:39:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:39:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:39:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:39:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:39:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:39:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:39:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:39:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:39:17 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:39:17 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:39:18 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:39:18 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:39:19 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:39:19 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:39:20 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:39:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:39:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:39:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:39:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:39:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:39:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:39:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:39:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:39:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:39:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:39:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:39:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:39:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:39:20 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:39:20 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:39:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:39:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:39:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:39:20 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:39:20 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:39:21 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:39:21 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:39:22 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:39:22 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:39:23 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:39:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:39:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:39:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:39:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:39:23 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:39:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:39:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:39:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:39:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:39:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:39:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:39:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:39:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:39:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:39:23 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:39:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:39:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:39:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:39:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:39:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:39:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:39:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:39:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:39:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:39:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:39:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:39:28 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:39:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:39:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:39:28 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:39:28 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:39:28 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:39:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:39:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:39:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:39:29 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:39:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:39:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:39:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:39:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:39:29 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:39:30 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:39:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:39:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:39:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:39:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:39:30 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:39:31 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:39:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:39:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:39:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:39:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:39:31 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:39:32 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:39:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:39:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:39:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:39:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:39:32 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:39:33 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:39:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:39:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:39:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:39:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:39:33 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:39:34 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:39:34 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:39:35 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:39:35 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:39:35 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:39:36 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:39:36 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:39:37 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:39:37 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:39:38 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:39:38 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:39:39 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:39:39 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:39:40 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:39:40 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:39:41 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:39:41 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:39:42 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:39:42 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:39:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:39:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:39:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:39:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:39:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:39:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:39:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:39:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:39:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:39:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:39:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:39:42 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:39:42 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3124 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:39:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:39:42 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3124 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:39:42 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:39:42 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:39:42 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:39:42 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:39:42 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:39:42 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:39:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:39:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:39:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:39:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:39:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:39:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:39:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:39:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:39:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:39:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:39:47 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:39:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:39:47 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:39:48 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:39:48 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:39:48 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:39:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:39:48 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:39:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:39:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:39:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:39:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:39:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:39:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:39:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:39:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:39:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:39:48 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:39:48 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:39:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:39:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:39:48 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:39:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:39:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:39:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:39:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:39:49 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:39:49 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:39:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:39:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:39:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:39:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:39:50 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:39:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:39:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:39:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:39:50 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:39:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:39:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:39:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:39:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:39:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:39:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:39:50 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:39:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:39:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:39:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:39:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:39:51 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:39:51 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:39:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:39:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:39:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:39:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:39:52 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:39:52 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:39:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:39:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:39:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:39:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:39:53 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:39:53 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:39:53 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:39:54 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:39:54 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:39:55 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:39:55 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:39:56 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:39:56 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:39:57 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:39:57 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:39:58 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:39:58 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:39:59 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:39:59 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:40:00 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:40:00 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:40:01 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:40:01 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:40:01 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:40:02 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:40:02 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:40:03 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:40:03 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 06:40:04 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 06:40:04 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 06:40:05 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 06:40:05 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 06:40:06 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 06:40:06 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 06:40:07 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 06:40:07 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 06:40:08 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 06:40:08 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 06:40:08 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 06:40:09 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 06:40:09 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 06:40:10 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 06:40:10 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 06:40:11 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 06:40:11 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 06:40:12 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 06:40:12 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 06:40:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:40:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:40:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:40:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:40:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:40:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:40:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:40:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:40:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:40:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:40:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:40:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:40:13 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:40:13 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5470 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:40:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:40:13 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5470 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:40:13 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5470 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:40:13 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5470 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:40:13 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5470 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:40:13 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5470 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:40:13 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5470 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:40:13 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5470 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:40:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:40:18 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:40:18 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:40:18 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:40:18 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:40:18 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:40:18 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:40:18 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:40:18 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:40:18 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:40:18 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:40:18 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:40:18 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:40:18 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:40:18 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:40:18 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:40:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:40:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:40:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:40:19 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:40:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:40:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:40:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:40:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:40:19 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:40:19 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:40:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:40:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:40:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:40:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:40:20 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:40:20 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:40:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:40:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:40:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:40:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:40:21 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:40:21 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:40:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:40:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:40:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:40:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:40:22 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:40:22 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:40:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:40:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:40:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:40:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:40:23 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:40:23 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:40:24 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:40:24 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:40:25 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:40:25 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:40:26 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:40:26 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:40:26 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:40:27 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:40:27 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:40:28 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:40:28 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:40:29 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:40:29 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:40:30 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:40:30 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:40:31 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:40:31 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:40:32 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:40:32 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:40:33 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:40:33 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:40:34 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 06:40:34 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 06:40:34 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 06:40:35 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 06:40:35 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 06:40:36 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 06:40:36 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 06:40:37 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 06:40:37 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 06:40:38 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 06:40:38 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 06:40:39 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 06:40:39 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 06:40:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:40:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:40:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:40:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:40:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:40:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:40:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:40:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:40:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:40:40 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:40:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:40:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:40:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:40:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:40:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:40:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:40:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:40:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:40:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:40:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:40:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:40:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:40:45 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:40:45 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:40:45 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:40:45 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:40:45 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:40:45 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:40:45 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:40:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:40:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:40:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:40:46 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:40:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:40:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:40:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:40:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:40:46 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:40:46 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:40:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:40:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:40:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:40:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:40:47 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:40:47 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:40:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:40:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:40:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:40:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:40:48 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:40:48 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:40:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:40:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:40:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:40:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:40:49 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:40:49 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:40:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:40:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:40:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:40:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:40:50 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:40:50 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:40:51 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:40:51 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:40:52 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:40:52 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:40:53 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:40:53 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:40:54 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:40:54 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:40:54 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:40:55 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:40:55 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:40:56 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:40:56 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:40:57 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:40:57 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:40:58 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:40:58 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:40:59 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:40:59 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:41:00 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:41:00 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:41:01 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 06:41:01 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 06:41:02 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 06:41:02 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 06:41:02 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 06:41:03 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 06:41:03 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 06:41:04 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 06:41:04 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 06:41:05 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 06:41:05 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 06:41:06 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 06:41:06 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 06:41:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:41:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:41:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:41:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:41:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:41:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:41:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:41:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:41:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:41:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:41:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:41:07 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:41:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4788 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:41:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:41:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4788 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:41:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4788 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:41:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4788 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:41:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4788 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:41:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4788 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:41:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4788 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:41:07 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4788 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:41:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:41:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:41:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:41:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:41:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:41:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:41:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:41:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:41:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:41:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:41:12 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:41:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:41:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:41:12 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:41:12 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:41:12 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:41:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:41:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:41:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:41:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:41:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:41:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:41:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:41:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:41:13 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:41:14 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:41:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:41:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:41:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:41:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:41:14 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:41:15 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:41:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:41:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:41:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:41:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:41:15 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:41:15 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:41:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:41:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:41:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:41:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:41:16 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:41:16 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:41:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:41:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:41:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:41:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:41:17 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:41:17 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:41:18 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:41:18 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:41:19 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:41:19 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:41:20 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:41:20 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:41:21 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:41:21 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:41:22 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:41:22 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:41:22 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:41:23 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:41:23 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:41:24 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:41:24 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:41:25 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:41:25 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:41:26 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:41:26 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:41:27 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:41:27 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:41:28 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 06:41:28 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 06:41:29 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 06:41:29 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 06:41:30 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 06:41:30 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 06:41:30 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 06:41:31 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 06:41:31 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 06:41:32 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 06:41:32 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 06:41:33 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 06:41:33 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 06:41:34 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 06:41:34 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 06:41:35 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 06:41:35 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 06:41:36 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 06:41:36 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 06:41:37 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 06:41:37 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 06:41:37 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 06:41:38 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 06:41:38 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 06:41:39 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 06:41:39 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 06:41:40 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 06:41:40 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 06:41:41 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-10-30 06:41:41 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-10-30 06:41:42 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-10-30 06:41:42 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-10-30 06:41:43 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-10-30 06:41:43 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-10-30 06:41:44 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-10-30 06:41:44 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-10-30 06:41:45 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-10-30 06:41:45 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-10-30 06:41:45 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-10-30 06:41:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:41:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:41:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:41:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:41:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:41:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:41:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:41:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:41:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:41:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:41:46 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:41:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:41:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:41:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:41:51 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:41:51 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:41:51 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:41:51 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:41:51 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:41:51 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:41:51 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:41:51 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:41:51 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:41:51 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:41:51 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:41:51 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:41:51 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:41:51 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:41:51 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:41:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:41:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:41:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:41:52 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:41:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:41:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:41:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:41:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:41:52 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:41:53 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:41:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:41:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:41:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:41:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:41:53 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:41:54 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:41:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:41:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:41:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:41:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:41:54 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:41:55 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:41:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:41:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:41:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:41:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:41:55 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:41:55 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:41:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:41:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:41:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:41:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:41:56 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:41:56 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:41:57 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:41:57 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:41:58 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:41:58 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:41:59 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:41:59 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:42:00 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:42:00 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:42:01 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:42:01 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:42:02 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:42:02 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:42:02 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:42:03 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:42:03 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:42:04 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:42:04 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:42:05 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:42:05 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:42:06 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:42:06 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:42:07 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 06:42:07 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 06:42:08 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 06:42:08 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 06:42:09 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 06:42:09 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 06:42:10 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 06:42:10 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 06:42:10 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 06:42:11 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 06:42:11 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 06:42:12 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 06:42:12 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 06:42:13 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 06:42:13 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 06:42:14 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 06:42:14 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 06:42:15 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 06:42:15 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 06:42:16 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 06:42:16 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 06:42:17 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 06:42:17 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 06:42:17 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 06:42:18 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 06:42:18 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 06:42:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:42:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:42:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:42:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:42:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:42:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:42:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:42:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:42:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:42:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:42:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:42:19 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:42:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6093 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:42:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:42:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6093 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:42:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6093 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:42:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6093 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:42:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6093 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:42:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6093 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:42:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6093 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:42:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6093 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:42:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:42:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:42:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:42:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:42:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:42:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:42:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:42:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:42:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:42:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:42:24 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:24 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:42:24 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:42:24 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:42:24 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:42:24 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:42:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:42:24 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:42:24 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:42:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:42:24 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:42:24 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:42:24 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:42:24 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:42:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:42:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:42:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:42:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:42:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:42:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:42:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:42:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:42:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:42:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:42:29 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:29 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:42:30 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:42:30 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:42:30 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:42:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:42:30 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:42:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:42:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:42:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:42:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:42:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:42:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:42:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:42:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:42:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:42:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:42:30 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:42:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:42:35 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:42:35 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:42:35 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:42:35 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:42:35 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:42:35 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:42:35 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:42:35 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:42:35 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:42:35 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:35 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:42:35 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:42:35 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:42:35 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:42:35 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:42:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:42:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:42:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:42:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:42:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:42:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:42:36 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:42:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:42:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:42:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:42:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:42:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:42:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:42:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:42:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:42:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:42:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:42:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:42:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:42:41 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:42:41 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:42:41 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:42:41 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:42:41 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:42:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:42:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:42:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:42:41 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:42:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:42:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:42:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:42:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:42:42 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:42:42 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:42:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:42:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:42:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:42:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:42:43 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:42:43 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:42:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:42:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:42:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:42:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:42:44 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:42:44 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:42:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:42:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:42:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:42:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:42:45 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:42:45 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:42:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:42:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:42:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:42:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:42:46 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:42:46 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:42:47 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:42:47 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:42:48 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:42:48 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:42:49 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:42:49 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:42:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:42:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:42:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:42:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:42:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:42:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:42:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:42:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:42:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:42:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:42:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:42:49 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:42:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:42:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:42:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:42:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:42:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:42:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:42:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:42:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:42:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:42:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:42:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:42:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:42:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:42:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:42:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:42:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:42:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:42:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:42:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:42:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:42:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:42:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:42:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:42:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:42:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:42:54 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:42:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:42:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:42:55 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:42:55 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:42:55 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:42:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:42:55 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:42:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:42:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:42:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:42:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:42:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:42:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:42:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:42:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:42:55 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:42:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:42:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:42:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:42:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:42:56 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:42:56 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:42:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:42:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:42:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:42:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:42:57 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:42:57 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:42:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:42:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:42:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:42:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:42:57 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:42:58 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:42:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:42:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:42:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:42:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:42:58 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:42:59 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:42:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:42:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:42:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:42:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:42:59 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:43:00 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:43:00 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:43:01 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:43:01 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:43:02 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:43:02 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:43:03 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:43:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:43:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:43:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:43:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:43:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:43:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:43:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:43:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:43:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:43:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:43:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:43:03 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:43:03 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:43:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:43:03 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:43:03 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:43:03 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:43:03 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:43:03 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:43:03 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:43:03 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:43:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:43:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:43:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:43:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:43:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:43:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:43:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:43:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:43:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:43:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:43:08 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:43:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:43:08 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:43:08 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:43:08 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:43:08 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:43:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:43:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:43:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:43:09 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:43:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:43:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:43:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:43:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:43:09 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:43:10 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:43:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:43:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:43:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:43:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:43:10 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:43:11 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:43:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:43:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:43:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:43:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:43:11 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:43:12 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:43:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:43:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:43:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:43:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:43:12 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:43:12 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:43:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:43:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:43:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:43:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:43:13 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:43:13 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:43:14 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:43:14 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:43:15 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:43:15 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:43:16 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:43:16 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:43:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:43:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:43:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:43:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:43:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:43:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:43:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:43:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:43:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:43:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:43:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:43:16 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:43:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:43:16 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:43:16 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:43:16 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:43:16 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:43:16 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:43:16 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:43:16 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:43:16 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:43:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:43:21 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:43:21 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:43:21 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:43:21 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:43:21 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:43:21 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:43:21 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:43:21 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:43:21 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:43:21 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:43:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:43:21 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:43:22 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:43:22 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:43:22 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:43:22 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:43:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:43:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:43:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:43:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:43:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:43:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:43:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:43:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:43:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:43:22 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:43:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:43:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:43:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:43:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:43:23 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:43:23 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:43:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:43:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:43:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:43:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:43:24 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:43:24 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:43:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:43:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:43:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:43:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:43:25 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:43:25 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:43:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:43:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:43:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:43:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:43:26 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:43:26 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:43:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:43:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:43:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:43:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:43:27 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:43:27 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:43:27 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:43:28 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:43:28 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:43:29 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:43:29 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:43:30 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:43:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:43:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:43:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:43:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:43:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:43:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:43:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:43:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:43:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:43:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:43:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:43:30 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:43:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:43:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:43:35 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:43:35 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:43:35 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:43:35 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:43:35 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:43:35 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:43:35 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:43:35 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:43:35 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:43:35 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:43:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:43:35 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:43:35 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:43:36 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:43:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:43:36 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:43:36 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:43:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:43:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:43:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:43:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:43:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:43:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:43:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:43:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:43:36 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:43:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:43:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:43:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:43:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:43:36 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:43:37 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:43:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:43:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:43:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:43:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:43:37 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:43:38 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:43:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:43:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:43:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:43:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:43:38 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:43:39 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:43:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:43:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:43:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:43:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:43:39 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:43:40 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:43:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:43:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:43:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:43:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:43:40 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:43:41 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:43:41 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:43:42 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:43:42 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:43:43 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:43:43 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:43:43 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:43:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:43:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:43:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:43:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:43:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:43:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:43:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:43:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:43:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:43:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:43:44 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:43:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:43:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:43:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:43:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:43:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:43:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:43:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:43:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:43:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:43:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:43:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:43:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:43:49 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:43:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:43:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:43:49 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:43:49 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:43:49 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:43:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:43:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:43:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:43:50 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:43:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:43:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:43:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:43:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:43:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:43:51 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:43:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:43:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:43:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:43:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:43:51 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:43:51 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:43:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:43:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:43:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:43:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:43:52 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:43:52 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:43:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:43:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:43:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:43:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:43:53 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:43:53 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:43:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:43:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:43:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:43:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:43:54 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:43:54 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:43:55 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:43:55 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:43:56 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:43:56 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:43:57 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:43:57 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:43:58 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:43:58 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:43:58 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:43:59 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:43:59 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:44:00 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:44:00 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:44:01 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:44:01 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:44:02 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:44:02 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:44:03 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:44:03 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:44:04 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:44:04 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:44:05 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 06:44:05 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 06:44:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:44:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:44:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:44:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:44:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:44:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:44:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:44:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:44:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:44:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:44:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:44:05 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:44:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:44:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:44:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:44:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:44:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:44:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:44:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:44:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:44:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:44:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:44:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:44:10 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:44:11 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:44:11 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:44:11 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:44:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:44:11 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:44:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:44:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:44:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:44:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:44:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:44:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:44:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:44:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:44:11 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:44:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:44:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:44:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:44:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:44:12 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:44:12 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:44:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:44:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:44:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:44:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:44:13 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:44:13 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:44:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:44:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:44:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:44:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:44:14 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:44:14 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:44:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:44:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:44:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:44:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:44:14 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:44:15 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:44:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:44:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:44:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:44:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:44:15 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:44:16 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:44:16 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:44:17 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:44:17 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:44:18 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:44:18 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:44:19 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:44:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:44:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:44:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:44:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:44:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:44:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:44:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:44:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:44:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:44:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:44:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:44:19 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:44:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:44:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:44:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:44:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:44:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:44:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:44:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:44:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:44:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:44:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:44:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:44:24 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:24 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:44:24 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:44:24 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:44:24 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:44:24 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:44:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:44:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:44:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:44:25 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:44:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:44:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:44:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:44:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:44:25 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:44:26 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:44:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:44:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:44:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:44:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:44:26 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:44:27 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:44:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:44:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:44:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:44:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:44:27 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:44:28 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:44:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:44:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:44:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:44:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:44:28 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:44:29 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:44:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:44:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:44:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:44:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:44:29 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:44:30 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:44:30 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:44:30 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:44:31 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:44:31 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:44:32 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:44:32 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:44:33 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:44:33 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:44:34 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:44:34 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:44:35 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:44:35 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:44:36 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:44:36 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:44:37 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:44:37 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:44:37 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:44:38 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:44:38 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:44:39 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:44:39 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:44:40 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 06:44:40 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 06:44:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:44:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:44:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:44:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:44:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:44:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:44:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:44:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:44:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:44:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:44:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:44:40 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:44:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:44:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:44:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:44:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:44:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:44:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:44:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:44:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:44:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:44:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:44:45 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:44:45 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:45 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:44:46 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:44:46 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:44:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:44:46 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:44:46 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:44:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:44:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:44:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:44:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:44:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:44:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:44:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:44:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:44:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:44:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:44:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:44:46 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:44:46 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=122 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:44:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:44:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:44:46 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=122 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:44:46 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:44:46 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:44:46 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:44:46 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:44:46 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:44:46 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:44:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:44:51 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:44:51 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:44:51 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:44:51 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:44:51 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:44:51 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:44:51 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:44:51 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:44:51 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:44:51 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:51 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:44:52 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:44:52 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:44:52 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:44:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:44:52 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:44:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:44:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:44:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:44:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:44:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:44:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:44:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:44:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:44:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:44:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:44:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:44:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:44:52 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:44:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:44:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:44:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:44:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:44:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:44:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:44:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:44:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:44:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:44:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:44:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:44:57 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:44:57 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:44:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:44:57 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:44:57 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:44:57 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:44:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:44:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:44:57 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:44:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:45:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:45:02 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:45:02 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:45:02 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:45:02 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:45:02 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:45:02 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:45:02 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:45:02 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:45:02 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:45:02 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:02 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:45:03 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:45:03 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:45:03 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:45:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:45:03 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:45:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:45:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:45:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:45:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:45:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:45:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:45:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:45:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:45:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:45:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:45:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:45:03 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:45:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:45:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:45:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:45:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:45:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:45:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:45:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:45:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:45:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:45:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:45:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:45:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:45:08 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:45:08 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:45:08 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:45:08 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:45:08 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:45:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:45:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:45:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:45:08 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:45:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:45:08 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=125 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:45:08 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=125 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:45:08 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:45:08 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:45:08 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:45:08 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:45:08 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:45:08 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:45:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:45:13 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:45:13 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:45:13 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:45:13 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:45:13 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:45:13 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:45:13 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:45:13 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:45:13 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:45:13 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:13 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:45:14 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:45:14 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:45:14 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:45:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:45:14 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:45:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:45:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:45:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:45:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:45:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:45:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:45:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:45:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:45:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:45:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:45:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:45:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:45:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:45:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:45:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:45:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:45:14 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:45:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:45:19 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:45:19 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:45:19 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:45:19 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:45:19 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:45:19 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:45:19 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:45:19 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:45:19 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:45:19 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:19 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:45:20 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:45:20 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:45:20 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:45:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:45:20 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:45:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:45:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:45:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:45:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:45:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:45:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:45:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:45:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:45:20 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:45:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:45:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:45:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:45:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:45:21 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:45:21 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:45:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:45:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:45:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:45:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:45:21 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:45:22 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:45:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:45:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:45:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:45:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:45:22 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:45:23 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:45:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:45:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:45:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:45:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:45:23 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:45:24 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:45:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:45:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:45:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:45:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:45:24 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:45:25 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:45:25 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:45:26 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:45:26 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:45:27 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:45:27 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:45:28 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:45:28 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:45:28 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:45:29 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:45:29 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:45:30 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:45:30 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:45:31 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:45:31 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:45:32 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:45:32 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:45:33 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:45:33 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:45:34 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:45:34 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:45:35 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:45:35 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 06:45:36 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 06:45:36 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 06:45:36 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 06:45:37 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 06:45:37 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 06:45:38 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 06:45:38 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 06:45:39 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 06:45:39 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 06:45:40 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 06:45:40 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 06:45:41 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 06:45:41 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 06:45:42 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 06:45:42 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 06:45:43 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 06:45:43 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 06:45:44 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 06:45:44 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 06:45:44 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 06:45:45 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 06:45:45 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 06:45:46 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 06:45:46 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 06:45:47 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 06:45:47 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 06:45:48 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 06:45:48 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-10-30 06:45:49 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-10-30 06:45:49 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-10-30 06:45:50 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-10-30 06:45:50 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-10-30 06:45:51 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-10-30 06:45:51 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-10-30 06:45:51 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-10-30 06:45:52 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-10-30 06:45:52 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-10-30 06:45:53 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-10-30 06:45:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:45:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:45:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:45:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:45:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:45:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:45:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:45:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:45:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:45:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:45:53 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:45:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:45:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:45:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:45:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:45:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:45:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:45:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:45:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:45:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:45:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:45:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:45:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:45:58 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:45:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:45:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:45:59 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:45:59 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:45:59 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:45:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:45:59 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:45:59 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:45:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:45:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:45:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:45:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:46:00 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:46:00 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:46:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:46:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:46:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:46:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:46:01 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:46:01 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:46:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:46:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:46:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:46:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:46:01 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:46:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:46:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:46:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:46:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:46:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:46:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:46:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:46:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:46:02 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:46:02 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=774 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:46:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:46:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:46:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:46:02 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=774 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:46:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:46:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:46:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:46:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:46:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:46:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:46:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:46:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:46:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:46:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:46:07 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:07 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:46:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:46:07 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:46:07 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:46:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:46:07 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:46:08 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:46:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:46:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:46:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:46:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:46:08 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:46:09 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:46:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:46:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:46:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:46:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:46:09 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:46:10 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:46:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:46:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:46:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:46:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:46:10 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:46:11 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:46:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:46:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:46:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:46:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:46:11 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:46:11 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:46:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:46:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:46:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:46:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:46:12 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:46:12 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:46:13 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:46:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:46:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:46:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:46:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:46:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:46:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:46:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:46:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:46:13 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:46:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:46:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:46:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:46:18 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:46:18 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:46:18 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:46:18 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:46:18 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:46:18 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:46:18 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:46:18 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:46:18 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:46:18 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:18 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:46:19 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:46:19 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:46:19 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:46:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:46:19 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:46:19 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:46:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:46:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:46:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:46:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:46:20 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:46:20 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:46:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:46:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:46:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:46:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:46:21 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:46:21 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:46:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:46:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:46:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:46:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:46:22 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:46:22 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:46:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:46:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:46:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:46:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:46:23 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:46:23 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:46:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:46:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:46:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:46:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:46:24 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:46:24 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:46:24 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:46:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:46:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:46:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:46:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:46:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:46:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:46:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:46:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:46:25 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:46:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:46:25 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1418 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:46:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:46:25 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1418 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:46:25 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1418 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:46:25 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1418 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:46:25 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1418 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:46:25 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1418 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:46:25 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1418 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:46:25 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1418 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:46:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:46:30 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:46:30 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:46:30 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:46:30 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:46:30 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:46:30 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:46:30 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:46:30 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:46:30 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:46:30 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:30 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:46:30 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:46:30 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:46:30 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:46:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:46:30 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:46:31 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:46:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:46:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:46:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:46:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:46:31 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:46:32 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:46:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:46:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:46:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:46:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:46:32 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:46:33 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:46:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:46:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:46:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:46:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:46:33 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:46:34 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:46:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:46:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:46:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:46:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:46:34 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:46:35 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:46:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:46:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:46:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:46:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:46:35 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:46:36 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:46:36 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:46:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:46:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:46:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:46:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:46:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:46:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:46:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:46:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:46:36 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:46:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:46:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:46:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:46:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:46:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:46:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:46:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:46:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:46:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:46:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:46:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:46:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:46:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:46:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:46:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:46:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:46:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:46:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:46:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:46:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:46:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:46:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:46:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:46:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:46:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:46:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:46:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:46:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:46:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:46:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:46:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:46:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:46:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:46:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:46:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:46:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:46:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:46:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:46:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:46:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:46:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:46:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:46:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:46:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:46:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:46:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:46:42 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:46:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:42 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:46:42 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:46:42 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:46:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:46:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:42 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:46:42 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:46:42 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:46:42 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:46:42 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:46:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:46:42 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:46:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:46:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:46:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:46:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:46:43 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:46:43 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:46:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:46:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:46:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:46:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:46:44 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:46:44 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:46:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:46:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:46:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:46:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:46:45 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:46:45 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:46:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:46:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:46:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:46:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:46:46 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:46:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:46:46 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:46:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:46:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:46:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:46:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:46:47 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:46:47 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:46:48 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:46:48 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:46:49 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:46:49 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:46:49 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:46:50 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:46:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:46:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:46:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:46:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:46:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:46:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:46:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:46:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:46:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:46:50 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:46:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:46:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:46:55 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:46:55 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:46:55 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:46:55 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:46:55 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:46:55 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:46:55 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:46:55 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:46:55 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:46:55 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:46:55 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:46:56 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:46:56 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:46:56 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:46:56 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:46:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:46:56 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:46:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:46:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:46:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:46:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:46:57 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:46:57 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:46:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:46:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:46:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:46:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:46:57 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:46:58 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:46:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:46:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:46:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:46:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:46:58 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:46:59 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:46:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:46:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:46:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:46:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:46:59 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:47:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:47:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:47:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:47:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:47:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:47:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:47:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:47:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:47:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:47:00 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:47:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:47:00 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=982 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:47:00 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=982 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:47:00 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=982 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:47:00 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=982 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:47:00 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=982 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:47:00 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=982 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:47:00 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=982 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:47:00 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=982 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:47:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:47:05 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:47:05 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:47:05 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:47:05 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:47:05 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:47:05 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:47:05 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:47:05 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:47:05 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:47:05 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:05 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:47:05 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:47:05 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:47:05 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:47:05 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:47:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:47:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:47:05 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:47:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:47:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:47:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:47:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:47:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:47:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:47:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:47:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:47:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:47:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:47:10 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:47:11 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:47:11 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:47:11 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:47:11 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:47:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:47:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:47:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:47:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:47:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:47:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:47:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:47:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:47:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:47:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:47:11 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:47:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:47:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:47:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:47:16 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:47:16 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:47:16 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:47:16 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:47:16 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:47:16 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:47:16 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:47:16 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:47:16 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:47:16 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:16 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:47:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:47:16 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:47:16 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:47:16 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:47:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:47:16 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:47:16 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=117 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:47:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:47:16 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=117 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:47:16 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:47:16 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:47:16 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:47:16 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:47:16 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:47:16 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:47:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:47:21 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:47:21 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:47:21 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:47:21 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:47:21 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:47:21 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:47:21 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:47:21 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:47:21 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:47:21 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:21 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:47:22 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:47:22 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:47:22 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:47:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:47:22 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:47:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:47:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:47:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:47:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:47:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:47:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:47:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:47:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:47:22 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:47:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:47:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:47:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:47:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:47:23 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:47:23 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:47:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:47:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:47:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:47:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:47:24 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:47:24 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:47:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:47:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:47:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:47:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:47:25 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:47:25 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:47:25 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2024-10-30 06:47:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:47:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:47:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:47:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:47:25 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:47:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:47:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:47:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:47:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:47:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:47:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:47:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:47:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:47:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:47:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:47:25 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:47:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:47:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:47:30 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:47:30 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:47:30 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:47:30 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:47:30 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:47:30 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:47:30 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:47:30 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:47:30 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:47:30 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:30 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:47:31 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:47:31 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:47:31 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:47:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:47:31 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:47:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:47:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:47:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:47:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:47:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:47:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:47:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:47:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:47:31 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:47:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:47:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:47:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:47:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:47:32 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:47:32 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:47:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:47:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:47:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:47:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:47:32 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:47:33 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:47:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:47:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:47:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:47:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:47:33 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:47:34 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:47:34 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2024-10-30 06:47:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:47:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:47:34 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:47:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:47:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:47:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:47:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:47:34 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:47:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:47:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:47:34 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:47:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:47:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:47:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:47:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:47:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:47:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:47:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:47:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:47:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:47:34 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:47:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:47:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:47:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:47:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:47:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:47:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:47:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:47:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:47:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:47:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:47:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:47:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:47:39 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:47:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:47:40 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:47:40 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:47:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:47:40 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:47:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:47:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:47:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:47:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:47:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:47:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:47:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:47:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:47:40 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:47:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:47:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:47:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:47:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:47:41 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:47:41 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:47:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:47:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:47:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:47:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:47:42 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:47:42 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:47:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:47:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:47:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:47:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:47:43 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:47:43 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:47:43 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2024-10-30 06:47:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:47:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:47:43 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:47:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:47:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:47:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:47:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:47:44 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:47:44 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:47:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:47:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:47:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:47:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:47:45 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:47:45 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:47:45 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:47:46 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:47:46 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:47:47 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:47:47 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:47:48 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:47:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:47:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:47:48 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:47:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:47:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:47:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:47:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:47:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:47:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:47:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:47:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:47:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:47:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:47:48 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:47:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:47:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:47:53 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:47:53 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:47:53 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:47:53 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:47:53 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:47:53 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:47:53 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:47:53 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:47:53 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:47:53 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:47:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:47:53 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:47:53 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:47:54 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:47:54 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:47:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:47:54 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:47:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:47:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:47:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:47:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:47:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:47:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:47:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:47:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:47:54 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:47:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:47:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:47:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:47:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:47:54 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:47:55 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:47:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:47:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:47:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:47:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:47:55 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:47:56 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:47:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:47:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:47:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:47:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:47:56 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:47:57 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:47:57 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2024-10-30 06:47:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:47:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:47:57 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:47:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:47:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:47:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:47:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:47:57 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:47:58 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:47:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:47:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:47:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:47:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:47:58 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:47:59 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:47:59 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:48:00 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:48:00 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:48:01 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:48:01 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:48:01 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:48:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:48:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:48:02 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:48:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:48:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:48:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:48:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:48:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:48:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:48:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:48:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:48:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:48:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:48:02 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:48:02 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1868 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:48:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:48:02 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1868 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:48:02 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1868 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:48:02 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1868 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:48:02 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1868 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:48:02 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1869 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:48:02 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1869 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:48:02 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1869 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:48:02 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1869 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:48:02 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1869 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:48:02 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1869 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:48:02 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1869 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:48:02 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1869 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:48:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:48:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:48:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:48:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:48:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:48:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:48:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:48:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:48:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:48:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:48:07 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:07 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:48:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:48:07 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:48:07 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:48:07 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:48:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:48:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:48:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:48:08 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:48:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:48:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:48:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:48:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:48:08 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:48:09 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:48:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:48:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:48:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:48:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:48:09 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:48:09 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:48:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:48:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:48:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:48:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:48:10 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:48:10 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:48:10 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2024-10-30 06:48:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:48:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:48:10 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:48:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:48:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:48:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:48:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:48:11 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:48:11 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:48:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:48:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:48:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:48:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:48:12 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:48:12 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:48:13 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:48:13 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:48:14 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:48:14 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:48:15 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:48:15 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:48:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:48:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:48:15 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:48:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:48:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:48:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:48:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:48:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:48:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:48:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:48:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:48:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:48:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:48:15 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:48:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:48:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:48:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:48:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:48:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:48:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:48:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:48:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:48:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:48:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:48:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:48:20 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:20 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:48:21 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:48:21 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:48:21 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:48:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:48:21 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:48:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:48:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:48:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:48:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:48:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:48:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:48:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:48:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:48:21 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:48:21 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2024-10-30 06:48:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:48:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:48:21 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:48:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:48:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:48:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:48:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:48:22 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:48:22 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:48:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:48:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:48:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:48:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:48:23 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:48:23 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:48:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:48:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:48:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:48:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:48:24 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:48:24 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:48:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:48:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:48:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:48:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:48:25 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:48:25 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:48:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:48:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:48:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:48:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:48:25 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:48:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:48:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:48:26 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:48:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:48:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:48:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:48:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:48:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:48:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:48:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:48:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:48:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:48:26 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:48:26 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1214 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:48:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:48:26 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1214 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:48:26 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1214 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:48:26 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1214 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:48:26 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1214 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:48:26 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1214 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:48:26 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1214 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:48:26 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1214 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:48:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:48:31 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:48:31 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:48:31 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:48:31 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:48:31 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:48:31 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:48:31 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:48:31 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:48:31 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:48:31 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:31 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:48:31 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:48:31 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:48:31 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:48:31 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:48:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:48:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:48:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:48:32 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:48:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:48:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:48:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:48:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:48:32 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:48:33 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:48:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:48:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:48:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:48:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:48:33 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:48:34 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:48:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:48:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:48:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:48:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:48:34 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:48:34 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:48:34 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2024-10-30 06:48:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:48:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:48:35 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:48:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:48:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:48:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:48:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:48:35 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:48:36 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:48:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:48:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:48:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:48:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:48:36 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:48:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:48:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:48:36 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:48:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:48:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:48:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:48:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:48:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:48:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:48:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:48:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:48:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:48:36 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:48:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:48:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:48:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:48:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:48:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:48:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:48:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:48:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:48:42 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:48:42 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:48:42 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:48:42 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:48:42 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:48:42 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:48:42 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:48:42 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:48:42 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:48:42 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:42 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:48:42 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:48:42 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:48:42 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:48:42 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:48:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:48:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:48:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:48:42 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:48:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:48:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:48:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:48:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:48:43 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:48:43 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:48:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:48:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:48:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:48:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:48:44 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:48:44 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:48:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:48:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:48:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:48:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:48:45 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:48:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:48:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:48:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:48:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:48:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:48:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:48:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:48:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:48:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:48:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:48:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:48:45 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:48:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:48:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:48:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:48:50 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:48:50 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:48:50 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:48:50 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:48:50 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:48:50 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:48:50 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:48:50 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:48:50 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:48:50 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:50 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:48:51 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:48:51 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:48:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:48:51 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:48:51 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:48:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:48:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:48:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:48:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:48:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:48:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:48:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:48:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:48:51 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:48:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:48:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:48:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:48:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:48:52 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:48:52 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:48:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:48:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:48:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:48:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:48:53 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:48:53 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:48:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:48:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:48:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:48:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:48:53 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:48:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:48:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:48:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:48:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:48:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:48:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:48:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:48:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:48:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:48:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:48:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:48:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:48:54 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:48:54 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=786 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:48:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:48:54 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=786 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:48:54 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=786 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:48:54 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=786 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:48:54 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=786 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:48:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:48:59 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:48:59 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:48:59 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:48:59 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:48:59 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:48:59 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:48:59 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:48:59 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:48:59 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:48:59 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:48:59 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:48:59 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:48:59 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:48:59 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:48:59 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:48:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:48:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:48:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:49:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:49:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:49:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:49:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:49:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:49:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:49:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:49:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:49:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:49:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:49:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:49:00 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:49:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:49:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:49:05 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:49:05 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:49:05 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:49:05 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:49:05 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:49:05 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:49:05 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:49:05 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:49:05 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:49:05 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:05 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:49:05 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:49:05 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:49:05 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:49:05 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:49:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:49:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:49:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:49:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:49:05 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:49:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:49:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:49:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:49:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:49:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:49:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:49:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:49:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:49:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:49:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:49:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:49:10 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:49:11 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:49:11 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:49:11 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:49:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:49:11 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:49:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:49:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:49:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:49:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:49:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:49:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:49:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:49:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:49:11 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:49:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:49:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:49:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:49:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:49:12 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:49:12 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:49:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:49:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:49:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:49:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:49:13 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:49:13 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:49:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:49:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:49:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:49:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:49:14 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:49:14 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:49:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:49:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:49:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:49:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:49:15 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:49:15 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:49:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:49:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:49:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:49:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:49:16 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:49:16 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:49:17 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:49:17 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:49:18 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:49:18 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:49:18 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:49:19 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:49:19 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:49:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:49:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:49:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:49:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:49:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:49:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:49:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:49:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:49:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:49:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:49:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:49:20 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:49:20 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2017 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:49:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:49:20 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2017 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:49:20 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2017 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:49:20 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2017 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:49:20 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2017 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:49:20 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2017 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:49:20 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2017 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:49:20 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2017 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:49:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:49:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:49:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:49:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:49:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:49:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:49:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:49:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:49:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:49:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:49:25 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:49:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:49:25 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:49:25 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:49:25 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:49:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:49:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:49:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:49:26 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:49:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:49:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:49:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:49:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:49:26 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:49:27 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:49:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:49:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:49:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:49:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:49:27 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:49:28 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:49:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:49:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:49:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:49:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:49:28 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:49:29 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:49:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:49:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:49:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:49:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:49:29 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:49:30 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:49:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:49:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:49:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:49:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:49:30 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:49:30 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:49:31 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:49:31 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:49:32 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:49:32 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:49:33 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:49:33 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:49:34 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:49:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:49:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:49:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:49:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:49:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:49:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:49:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:49:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:49:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:49:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:49:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:49:34 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:49:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2016 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:49:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:49:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2016 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:49:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2016 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:49:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2016 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:49:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2017 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:49:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2017 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:49:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2017 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:49:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2017 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:49:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2017 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:49:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2017 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:49:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2017 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:49:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2017 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:49:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:49:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:49:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:49:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:49:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:49:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:49:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:49:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:49:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:49:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:49:39 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:49:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:49:40 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:49:40 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:49:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:49:40 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:49:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:49:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:49:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:49:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:49:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:49:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:49:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:49:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:49:40 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:49:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:49:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:49:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:49:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:49:41 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:49:41 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:49:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:49:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:49:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:49:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:49:41 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:49:42 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:49:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:49:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:49:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:49:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:49:42 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:49:43 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:49:43 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2024-10-30 06:49:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:49:43 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:49:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:49:43 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:49:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:49:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:49:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:49:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:49:43 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:49:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:49:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:49:44 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:49:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:49:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:49:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:49:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:49:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:49:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:49:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:49:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:49:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:49:44 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:49:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:49:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:49:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:49:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:49:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:49:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:49:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:49:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:49:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:49:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:49:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:49:49 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:49:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:49:49 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:49:49 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:49:49 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:49:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:49:49 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:49:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=135 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:49:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:49:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=135 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:49:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=135 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:49:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=135 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:49:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=135 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:49:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=135 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:49:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=135 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:49:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=135 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:49:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:49:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:49:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:49:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:49:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:49:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:49:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:49:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:49:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:49:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:49:54 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:49:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:49:55 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:49:55 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:49:55 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:49:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:49:55 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:49:55 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:49:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:49:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:49:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:49:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:49:56 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:49:56 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:49:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:49:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:49:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:49:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:49:57 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:49:57 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:49:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:49:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:49:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:49:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:49:58 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:49:58 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:49:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:49:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:49:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:49:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:49:59 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:49:59 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:49:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:49:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:49:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:49:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:50:00 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:50:00 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:50:01 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:50:01 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:50:01 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:50:02 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:50:02 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:50:03 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:50:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:50:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:50:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:50:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:50:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:50:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:50:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:50:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:50:03 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:50:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:50:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:50:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:50:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:50:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:50:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:50:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:50:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:50:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:50:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:50:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:50:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:50:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:50:08 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:50:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:50:09 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:50:09 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:50:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:50:09 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:50:09 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:50:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:50:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:50:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:50:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:50:09 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:50:10 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:50:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:50:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:50:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:50:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:50:10 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:50:11 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:50:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:50:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:50:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:50:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:50:11 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:50:12 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:50:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:50:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:50:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:50:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:50:12 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:50:13 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:50:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:50:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:50:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:50:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:50:13 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:50:14 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:50:14 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:50:15 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:50:15 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:50:16 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:50:16 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:50:16 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:50:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:50:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:50:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:50:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:50:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:50:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:50:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:50:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:50:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:50:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:50:17 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:50:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:50:17 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1858 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:50:17 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1858 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:50:17 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1858 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:50:17 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1858 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:50:17 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1858 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:50:17 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1858 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:50:17 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1858 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:50:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:50:22 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:50:22 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:50:22 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:50:22 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:50:22 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:50:22 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:50:22 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:50:22 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:50:22 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:50:22 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:22 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:50:22 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:50:22 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:50:22 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:50:22 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:50:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:50:23 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:50:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:50:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:50:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:50:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:50:23 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:50:24 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:50:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:50:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:50:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:50:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:50:24 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:50:24 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:50:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:50:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:50:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:50:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:50:25 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:50:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:50:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:50:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:50:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:50:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:50:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:50:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:50:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:50:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:50:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:50:25 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:50:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:50:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:50:30 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:50:30 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:50:30 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:50:30 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:50:30 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:50:30 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:50:30 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:50:30 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:50:30 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:50:30 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:30 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:50:31 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:50:31 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:50:31 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:50:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:50:31 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:50:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:50:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:50:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:50:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:50:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:50:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:50:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:50:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:50:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:50:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:50:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:50:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:50:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:50:31 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:50:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:50:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:50:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:50:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:50:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:50:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:50:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:50:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:50:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:50:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:50:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:50:31 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:50:31 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=209 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:50:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:50:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:50:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:50:31 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=209 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:50:31 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=209 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:50:31 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=209 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:50:31 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=209 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:50:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:50:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:50:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:50:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:50:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:50:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:50:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:50:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:50:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:50:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:50:36 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:36 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:50:37 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:50:37 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:50:37 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:50:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:50:37 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:50:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:50:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:50:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:50:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:50:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:50:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:50:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:50:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:50:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:50:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:50:37 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:50:37 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:50:37 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:50:37 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:50:37 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:50:37 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:50:37 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:50:37 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:50:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:50:42 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:50:42 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:50:42 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:50:42 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:50:42 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:50:42 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:50:42 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:50:42 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:50:42 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:50:42 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:42 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:50:42 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:50:42 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:50:42 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:50:42 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:50:43 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:50:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:50:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:50:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:50:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:50:43 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:50:44 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:50:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:50:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:50:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:50:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:50:44 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:50:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:50:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:50:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:50:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:50:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:50:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:50:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:50:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:50:44 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:50:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:50:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:50:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:50:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:50:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:50:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:50:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:50:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:50:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:50:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:50:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:50:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:50:49 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:50:50 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:50:50 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:50:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:50:50 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:50:50 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:50:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:50:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:50:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:50:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:50:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:50:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:50:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:50:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:50:50 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:50:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:50:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:50:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:50:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:50:51 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:50:51 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:50:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:50:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:50:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:50:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:50:52 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:50:52 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:50:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:50:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:50:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:50:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:50:53 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:50:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:50:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:50:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:50:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:50:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:50:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:50:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:50:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:50:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:50:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:50:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:50:53 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:50:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:50:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:50:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:50:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:50:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:50:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:50:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:50:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:50:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:50:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:50:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:50:58 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:50:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:50:58 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:50:58 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:50:58 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:50:58 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:50:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:50:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:50:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:50:59 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:50:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:50:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:50:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:50:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:50:59 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:51:00 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:51:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:51:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:51:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:51:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:51:00 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:51:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:51:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:51:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:51:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:51:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:51:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:51:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:51:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:51:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:51:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:51:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:51:00 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:51:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:51:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:51:05 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:51:05 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:51:05 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:51:05 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:51:05 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:51:05 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:51:05 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:51:05 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:51:05 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:51:05 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:05 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:51:06 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:51:06 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:51:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:51:06 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:51:06 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:51:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:51:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:51:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:51:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:51:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:51:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:51:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:51:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:51:06 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:51:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:51:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:51:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:51:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:51:07 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:51:07 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:51:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:51:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:51:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:51:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:51:08 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:51:08 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:51:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:51:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:51:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:51:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:51:09 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:51:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:51:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:51:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:51:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:51:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:51:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:51:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:51:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:51:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:51:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:51:09 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:51:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:51:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:51:09 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=720 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:51:09 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=720 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:51:09 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=720 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:51:09 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=720 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:51:09 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=720 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:51:09 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=720 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:51:09 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=720 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:51:09 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=720 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:51:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:51:14 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:51:14 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:51:14 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:51:14 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:51:14 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:51:14 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:51:14 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:51:14 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:51:14 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:51:14 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:14 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:51:14 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:51:14 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:51:14 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:51:14 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:51:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:51:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:51:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:51:15 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:51:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:51:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:51:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:51:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:51:15 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:51:16 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:51:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:51:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:51:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:51:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:51:16 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:51:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:51:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:51:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:51:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:51:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:51:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:51:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:51:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:51:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:51:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:51:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:51:16 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:51:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:51:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:51:21 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:51:21 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:51:21 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:51:21 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:51:21 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:51:21 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:51:21 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:51:21 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:51:21 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:51:21 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:21 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:51:22 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:51:22 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:51:22 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:51:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:51:22 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:51:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:51:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:51:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:51:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:51:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:51:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:51:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:51:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:51:22 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:51:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:51:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:51:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:51:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:51:23 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:51:23 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:51:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:51:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:51:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:51:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:51:24 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:51:24 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:51:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:51:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:51:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:51:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:51:25 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:51:25 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:51:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:51:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:51:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:51:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:51:26 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:51:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:51:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:51:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:51:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:51:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:51:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:51:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:51:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:51:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:51:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:51:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:51:26 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:51:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:51:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:51:31 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:51:31 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:51:31 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:51:31 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:51:31 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:51:31 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:51:31 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:51:31 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:51:31 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:51:31 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:31 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:51:31 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:51:31 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:51:31 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:51:31 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:51:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:51:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:51:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:51:32 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:51:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:51:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:51:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:51:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:51:32 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:51:33 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:51:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:51:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:51:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:51:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:51:33 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:51:34 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:51:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:51:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:51:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:51:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:51:34 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:51:34 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:51:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:51:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:51:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:51:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:51:35 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:51:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:51:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:51:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:51:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:51:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:51:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:51:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:51:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:51:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:51:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:51:35 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:51:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:51:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:51:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:51:40 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:51:40 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:51:40 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:51:40 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:51:40 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:51:40 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:51:40 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:51:40 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:51:40 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:51:40 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:40 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:51:41 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:51:41 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:51:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:51:41 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:51:41 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:51:41 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:51:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:51:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:51:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:51:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:51:42 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:51:42 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:51:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:51:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:51:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:51:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:51:43 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:51:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:51:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:51:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:51:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:51:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:51:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:51:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:51:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:51:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:51:43 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:51:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:51:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:51:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:51:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:51:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:51:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:51:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:51:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:51:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:51:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:51:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:51:48 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:51:48 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:51:48 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:51:48 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:51:48 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:51:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:51:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:51:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:51:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:51:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:51:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:51:49 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:51:50 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:51:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:51:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:51:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:51:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:51:50 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:51:51 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:51:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:51:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:51:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:51:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:51:51 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:51:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:51:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:51:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:51:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:51:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:51:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:51:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:51:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:51:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:51:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:51:51 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:51:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:51:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:51:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:51:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:51:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:51:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:51:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:51:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:51:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:51:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:51:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:51:56 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:51:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:51:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:51:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:51:57 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:51:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:51:57 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:51:57 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:51:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:51:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:51:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:51:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:51:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:51:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:51:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:51:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:51:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:51:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:51:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:51:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:51:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:51:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:51:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:51:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:51:57 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:51:57 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:51:57 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:51:57 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:51:57 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:51:57 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:51:57 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:52:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:52:02 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:52:02 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:52:02 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:52:02 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:52:02 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:52:02 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:52:02 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:52:02 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:52:02 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:52:02 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:02 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:52:03 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:52:03 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:52:03 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:52:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:52:03 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:52:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:52:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:52:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:52:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:52:03 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:52:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:52:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:52:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:52:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:52:03 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:52:04 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:52:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:52:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:52:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:52:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:52:04 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:52:05 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:52:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:52:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:52:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:52:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:52:05 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:52:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:52:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:52:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:52:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:52:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:52:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:52:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:52:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:52:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:52:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:52:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:52:06 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:52:06 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=773 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:06 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=773 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:06 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=773 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:06 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=773 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:06 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=773 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:06 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=773 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:06 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=773 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:06 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=773 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:52:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:52:11 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:52:11 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:52:11 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:52:11 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:52:11 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:52:11 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:52:11 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:52:11 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:52:11 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:52:11 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:11 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:52:11 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:52:11 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:52:11 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:52:11 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:52:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:52:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:52:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:52:11 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:52:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:52:16 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:52:16 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:52:16 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:52:16 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:52:16 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:52:16 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:52:16 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:52:16 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:52:16 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:52:16 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:16 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:52:17 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:52:17 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:52:17 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:52:17 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:52:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:52:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:52:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:52:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:52:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:52:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:52:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:52:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:52:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:52:17 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:52:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:52:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:52:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:52:22 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:52:22 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:52:22 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:52:22 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:52:22 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:52:22 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:52:22 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:52:22 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:52:22 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:52:22 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:22 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:52:22 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:52:22 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:52:22 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:52:22 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:52:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:52:22 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:52:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:52:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:52:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:52:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:52:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:52:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:52:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:52:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:52:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:52:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:52:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:52:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:52:27 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:52:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:52:28 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:52:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:52:28 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:52:28 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:52:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:52:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:52:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:52:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:52:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:52:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:52:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:52:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:52:28 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:52:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=119 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:52:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:52:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=119 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=119 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=119 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=119 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:52:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:52:33 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:52:33 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:52:33 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:52:33 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:52:33 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:52:33 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:52:33 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:52:33 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:52:33 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:52:33 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:33 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:52:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:52:34 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:52:34 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:52:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:52:34 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:52:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:52:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:52:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:52:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:52:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:52:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:52:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:52:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:52:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:52:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:52:34 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:52:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:52:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:52:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:52:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:52:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:52:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:52:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:52:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:52:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:52:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:52:39 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:52:39 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:52:39 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:52:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:52:39 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:52:39 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:52:40 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:52:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:52:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:52:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:52:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:52:40 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:52:40 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:52:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:52:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:52:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:52:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:52:41 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:52:41 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:52:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:52:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:52:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:52:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:52:42 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:52:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:52:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:52:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:52:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:52:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:52:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:52:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:52:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:52:42 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:52:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:52:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:52:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:52:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:52:43 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:52:43 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:52:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:52:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:52:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:52:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:52:44 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:52:44 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:52:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:52:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:52:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:52:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:52:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:52:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:52:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:52:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:52:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:52:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:52:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:52:44 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:52:44 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1254 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:52:44 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1254 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:44 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1254 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:44 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1254 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:44 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1254 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:44 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1254 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:44 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1254 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:44 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1254 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:52:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:52:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:52:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:52:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:52:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:52:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:52:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:52:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:52:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:52:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:52:49 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:52:50 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:52:50 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:52:50 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:52:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:52:50 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:52:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:52:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:52:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:52:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:52:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:52:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:52:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:52:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:52:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:52:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:52:50 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:52:50 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:52:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:52:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:52:50 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:50 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:50 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=123 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:50 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=123 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:50 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:50 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:50 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:50 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:50 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:50 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:52:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:52:55 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:52:55 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:52:55 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:52:55 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:52:55 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:52:55 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:52:55 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:52:55 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:52:55 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:52:55 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:55 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:52:55 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:52:55 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:52:55 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:52:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:52:55 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:52:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:52:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:52:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:52:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:52:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:52:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:52:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:52:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:52:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:52:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:52:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:52:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:52:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:52:56 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:52:56 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=123 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:52:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:52:56 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=123 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:56 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:56 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:56 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:56 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:56 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:52:56 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:53:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:53:01 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:53:01 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:53:01 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:53:01 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:53:01 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:53:01 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:53:01 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:53:01 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:53:01 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:53:01 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:01 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:53:01 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:53:01 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:53:01 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:01 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:53:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:53:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:53:01 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:53:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:53:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:53:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:53:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:53:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:53:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:53:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:53:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:53:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:53:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:53:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:53:06 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:53:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:53:07 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:53:07 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:53:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:07 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:53:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:53:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:53:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:53:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:53:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:53:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:53:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:53:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:53:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:53:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:53:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:53:07 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:53:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:53:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:53:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:53:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:53:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:53:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:53:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:53:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:53:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:53:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:53:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:53:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:53:12 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:53:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:53:12 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:53:12 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:12 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:53:12 [DEBUG] fake_trx.py:376 (BTS@172.18.83.20:5700) Recv FAKE_TRXC_DELAY cmd
2024-10-30 06:53:12 [INFO] fake_trx.py:379 (BTS@172.18.83.20:5700) Artificial TRXC delay set to 200
2024-10-30 06:53:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD FAKE_TRXC_DELAY
2024-10-30 06:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:53:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:53:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:53:13 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:53:14 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:53:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:14 [DEBUG] fake_trx.py:376 (BTS@172.18.83.20:5700) Recv FAKE_TRXC_DELAY cmd
2024-10-30 06:53:14 [INFO] fake_trx.py:379 (BTS@172.18.83.20:5700) Artificial TRXC delay set to 0
2024-10-30 06:53:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD FAKE_TRXC_DELAY
2024-10-30 06:53:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:53:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:53:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:53:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:53:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:53:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:53:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:53:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:53:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:53:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:53:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:53:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:53:14 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:53:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:53:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:53:19 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:53:19 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:53:19 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:53:19 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:53:19 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:53:19 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:53:19 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:53:19 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:53:19 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:53:19 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:19 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:53:19 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:53:20 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:53:20 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:53:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:20 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:53:20 [DEBUG] fake_trx.py:376 (BTS@172.18.83.20:5700) Recv FAKE_TRXC_DELAY cmd
2024-10-30 06:53:20 [INFO] fake_trx.py:379 (BTS@172.18.83.20:5700) Artificial TRXC delay set to 200
2024-10-30 06:53:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD FAKE_TRXC_DELAY
2024-10-30 06:53:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:20 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:53:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:53:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:53:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:53:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:20 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:53:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:21 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:53:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:21 [DEBUG] fake_trx.py:376 (BTS@172.18.83.20:5700) Recv FAKE_TRXC_DELAY cmd
2024-10-30 06:53:21 [INFO] fake_trx.py:379 (BTS@172.18.83.20:5700) Artificial TRXC delay set to 0
2024-10-30 06:53:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD FAKE_TRXC_DELAY
2024-10-30 06:53:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:53:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:53:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:53:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:53:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:53:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:53:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:53:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:53:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:53:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:53:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:53:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:53:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:53:21 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:53:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:53:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:53:26 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:53:26 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:53:26 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:53:26 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:53:26 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:53:26 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:53:26 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:53:26 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:53:26 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:53:26 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:26 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:53:27 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:53:27 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:53:27 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:53:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:27 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:53:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:53:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:53:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:53:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:53:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:53:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:53:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:53:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:53:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:53:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:53:27 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:53:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:53:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:53:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:53:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:53:32 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:53:32 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:53:32 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:53:32 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:53:32 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:53:32 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:53:32 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:53:32 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:53:32 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:53:32 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:32 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:53:32 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:53:32 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:32 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:53:32 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:53:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:53:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:53:32 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:53:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:53:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:53:37 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:53:37 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:53:37 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:53:37 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:53:37 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:53:37 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:53:37 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:53:37 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:53:37 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:53:37 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:53:37 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:53:38 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:53:38 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:53:38 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:53:38 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:53:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:53:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:53:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:53:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:53:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:53:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:53:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:53:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:53:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:53:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:53:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:53:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:53:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:53:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:53:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:53:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:53:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:53:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:53:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:53:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:53:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:38 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:53:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:53:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:53:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:53:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:53:39 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:53:39 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:53:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:53:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:53:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:53:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:53:40 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:53:40 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:53:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:53:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:53:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:53:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:53:41 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:53:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:53:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:53:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:53:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:53:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:53:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:53:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:53:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:53:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:53:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:53:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:53:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:41 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:53:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:53:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:53:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:53:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:53:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:53:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:53:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:53:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:53:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:53:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:53:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:53:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:53:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:53:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:53:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:53:42 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:53:42 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:53:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:53:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:53:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:53:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:53:43 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:53:43 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:53:44 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:53:44 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:53:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:53:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:53:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:53:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:53:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:53:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:53:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:53:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:53:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:53:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:53:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:53:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:44 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:53:45 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:53:45 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:53:46 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:53:46 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:53:47 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:53:47 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:53:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:53:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:53:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:53:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:53:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:53:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:53:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:53:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:53:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:53:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:53:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:53:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:53:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:53:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:53:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:53:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:53:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:53:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:53:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:53:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:53:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:53:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:53:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:48 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:53:48 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:53:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:53:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:53:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:53:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:53:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:53:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:53:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:53:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:53:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:53:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:48 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:53:48 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:53:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:53:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:53:49 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:53:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:53:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:53:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:53:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:53:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:53:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:53:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:53:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:49 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:53:49 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:53:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:49 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:53:49 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:53:50 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:53:50 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:53:51 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:53:51 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:53:51 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:53:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:53:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:53:52 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:53:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:53:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:53:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:53:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:53:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:53:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:53:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:53:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:52 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:53:52 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:53:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:53:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:53:52 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:53:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:53:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:53:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:53:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:53:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:53:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:53:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:53:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:52 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:53:52 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:53:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:52 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:53:52 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:53:53 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:53:53 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 06:53:54 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 06:53:54 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 06:53:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:53:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:53:55 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:53:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:53:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:53:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:53:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:53:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:53:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:53:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:53:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:55 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 06:53:55 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:53:55 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:53:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:55 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 06:53:56 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 06:53:56 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 06:53:57 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 06:53:57 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 06:53:58 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 06:53:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:53:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:53:58 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:53:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:53:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:53:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:53:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:53:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:53:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:53:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:53:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:58 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:53:58 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:53:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:53:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:53:58 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:53:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:53:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:53:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:53:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:53:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:53:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:53:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:53:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:58 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:53:58 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:53:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:58 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 06:53:59 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 06:53:59 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 06:53:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:53:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:53:59 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:53:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:53:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:53:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:53:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:53:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:53:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:53:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:53:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:53:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:53:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:53:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:53:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:53:59 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 06:53:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:53:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:53:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:53:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:53:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:53:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:53:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:53:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:54:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:00 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 06:54:00 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 06:54:01 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 06:54:01 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 06:54:02 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 06:54:02 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 06:54:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:54:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:54:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:54:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:03 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 06:54:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:54:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:54:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:54:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:03 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 06:54:04 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 06:54:04 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 06:54:05 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 06:54:05 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 06:54:06 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 06:54:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:54:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:54:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:54:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:06 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 06:54:06 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-10-30 06:54:07 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-10-30 06:54:07 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-10-30 06:54:08 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-10-30 06:54:08 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-10-30 06:54:09 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-10-30 06:54:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:54:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:54:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:54:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:54:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:54:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:54:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:09 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-10-30 06:54:10 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-10-30 06:54:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:54:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:54:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:54:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:10 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:54:10 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:54:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:10 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:54:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:54:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:54:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:54:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:10 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:54:10 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:54:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:10 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-10-30 06:54:11 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-10-30 06:54:11 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-10-30 06:54:12 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-10-30 06:54:12 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-10-30 06:54:13 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-10-30 06:54:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:13 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:54:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:54:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:54:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:54:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:13 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:54:13 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:54:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:13 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-10-30 06:54:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:13 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:54:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:54:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:54:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:54:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:13 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:54:13 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:54:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:14 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-10-30 06:54:14 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-10-30 06:54:14 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-10-30 06:54:15 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-10-30 06:54:15 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-10-30 06:54:16 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-10-30 06:54:16 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-10-30 06:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:16 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:54:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:54:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:54:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:54:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:17 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:54:17 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:54:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:17 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-10-30 06:54:17 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-10-30 06:54:18 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-10-30 06:54:18 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-10-30 06:54:19 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-10-30 06:54:19 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-10-30 06:54:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:20 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:54:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:54:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:54:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:54:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:20 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:54:20 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:54:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:20 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-10-30 06:54:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:20 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:54:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:54:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:54:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:54:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:20 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:54:20 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:54:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:20 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-10-30 06:54:21 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2024-10-30 06:54:21 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2024-10-30 06:54:22 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2024-10-30 06:54:22 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2024-10-30 06:54:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:22 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:54:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:54:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:54:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:54:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:54:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:54:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:54:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:54:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:54:22 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:54:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:54:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:54:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=9792 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:54:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=9792 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:54:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=9792 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:54:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=9792 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:54:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=9792 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:54:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=9792 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:54:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=9792 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:54:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=9792 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:54:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:54:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:54:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:54:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:54:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:54:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:54:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:54:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:54:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:54:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:54:27 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:54:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:54:28 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:54:28 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:28 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:54:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:54:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:54:28 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:28 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:54:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:54:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:54:28 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:28 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:54:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:54:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:29 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:54:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:54:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:54:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:54:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:54:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:54:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:54:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:54:29 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:54:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:54:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:54:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:54:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:54:34 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:54:34 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:54:34 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:54:34 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:54:34 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:54:34 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:54:34 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:54:34 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:54:34 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:54:34 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:34 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:54:34 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:54:34 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:54:34 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:34 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:54:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:34 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:54:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:54:35 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:54:35 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:35 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:54:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:54:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:54:35 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:54:35 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:54:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:54:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:54:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:54:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:36 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:54:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:54:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:54:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:54:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:54:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:54:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:54:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:54:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:54:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:54:36 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:54:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:54:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:54:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:54:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:54:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:54:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:54:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:54:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:54:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:54:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:54:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:54:41 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:54:41 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:54:41 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:54:41 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:41 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:54:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:54:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:54:42 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:42 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:42 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:54:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:42 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:54:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:54:42 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:43 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:54:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:54:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:54:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:54:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:54:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:43 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:54:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:54:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:54:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:54:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:54:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:54:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:54:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:54:43 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:54:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:54:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:54:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:54:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:54:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:54:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:54:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:54:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:54:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:54:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:54:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:54:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:54:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:54:48 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:54:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:54:49 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:54:49 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:49 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:54:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:54:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:54:49 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:49 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:54:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:54:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:54:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:54:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:54:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:50 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:54:50 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:54:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:50 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:54:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:54:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:54:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:54:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:54:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:50 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:54:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:54:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:54:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:54:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:54:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:54:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:54:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:54:50 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:54:50 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=496 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:54:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:54:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:54:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:54:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:54:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:54:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:54:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:54:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:54:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:54:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:54:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:54:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:54:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:54:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:54:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:54:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:54:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:54:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:54:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:54:56 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:54:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:54:56 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:54:56 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:54:56 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:56 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:54:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:56 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:54:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:54:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:54:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:54:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:54:57 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:54:57 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:54:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:54:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:54:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:54:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:54:58 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:54:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:54:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:54:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:54:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:54:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:54:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:54:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:54:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:54:58 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:54:58 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:54:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:54:58 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:54:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:54:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:54:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:54:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:54:59 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:54:59 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:55:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:55:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:55:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:55:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:55:00 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:55:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:55:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:55:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:55:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:55:00 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:55:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:55:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:55:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:55:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:55:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:55:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:55:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:55:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:55:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:55:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:55:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:55:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:55:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:55:00 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:55:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:55:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:55:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:55:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:55:01 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:55:01 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:55:02 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:55:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:55:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:55:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:55:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:55:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:55:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:55:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:55:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:55:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:55:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:55:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:55:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:55:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:55:02 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:55:02 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:55:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:55:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:55:02 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:55:03 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:55:03 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:55:03 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:55:04 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:55:04 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:55:05 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:55:05 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:55:06 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:55:06 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:55:07 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:55:07 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:55:08 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:55:08 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:55:09 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:55:09 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:55:10 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:55:10 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:55:11 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:55:11 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:55:11 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 06:55:12 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 06:55:12 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 06:55:13 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 06:55:13 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 06:55:14 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 06:55:14 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 06:55:15 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 06:55:15 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 06:55:16 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 06:55:16 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 06:55:17 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 06:55:17 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 06:55:18 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 06:55:18 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 06:55:19 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 06:55:19 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 06:55:19 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 06:55:20 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 06:55:20 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 06:55:21 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 06:55:21 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 06:55:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:55:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:55:22 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:55:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:55:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:55:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:55:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:55:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:55:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:55:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:55:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:55:22 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:55:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5688 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:55:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:55:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:55:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5688 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:55:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5689 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:55:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5689 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:55:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5689 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:55:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5689 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:55:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5689 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:55:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5689 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:55:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5689 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:55:22 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5689 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:55:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:55:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:55:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:55:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:55:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:55:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:55:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:55:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:55:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:55:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:55:27 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:55:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:55:27 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:55:27 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:55:27 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:55:27 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:55:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:55:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:55:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:55:28 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:55:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:55:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:55:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:55:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:55:28 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:55:29 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:55:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:55:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:55:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:55:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:55:29 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:55:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:55:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:55:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:55:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:55:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:55:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:55:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:55:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:55:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:55:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:55:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:55:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:55:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:55:29 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:55:29 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:55:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:55:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:55:30 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:55:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:55:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:55:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:55:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:55:30 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:55:30 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:55:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:55:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:55:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:55:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:55:31 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:55:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:55:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:55:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:55:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:55:31 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:55:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:55:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:55:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:55:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:55:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:55:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:55:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:55:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:55:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:55:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:55:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:55:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:55:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:55:31 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:55:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:55:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:55:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:55:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:55:32 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:55:32 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:55:33 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:55:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:55:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:55:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:55:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:55:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:55:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:55:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:55:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:55:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:55:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:55:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:55:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:55:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:55:33 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:55:33 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:55:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:55:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:55:33 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:55:34 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:55:34 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:55:35 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:55:35 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:55:36 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:55:36 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:55:37 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:55:37 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:55:38 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:55:38 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:55:38 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:55:39 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:55:39 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:55:40 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:55:40 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:55:41 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:55:41 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:55:42 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:55:42 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:55:43 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 06:55:43 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 06:55:44 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 06:55:44 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 06:55:45 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 06:55:45 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 06:55:45 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 06:55:46 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 06:55:46 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 06:55:47 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 06:55:47 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 06:55:48 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 06:55:48 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 06:55:49 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 06:55:49 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 06:55:50 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 06:55:50 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 06:55:51 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 06:55:51 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 06:55:52 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 06:55:52 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 06:55:53 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 06:55:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:55:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:55:53 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:55:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:55:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:55:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:55:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:55:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:55:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:55:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:55:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:55:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:55:53 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:55:53 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5693 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:55:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:55:53 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5693 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:55:53 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5693 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:55:53 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5693 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:55:53 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5693 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:55:53 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5693 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:55:53 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5693 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:55:53 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=5693 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:55:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:55:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:55:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:55:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:55:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:55:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:55:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:55:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:55:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:55:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:55:58 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:55:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:55:58 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:55:58 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:55:58 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:55:58 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:55:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:55:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:55:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:55:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:55:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:55:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:55:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:55:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:55:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:55:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:55:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:55:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:55:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:55:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:55:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:55:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:55:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:55:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:55:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:55:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:55:59 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:55:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:55:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:55:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:55:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:55:59 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:56:00 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:56:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:56:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:56:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:56:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:56:00 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:56:01 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:56:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:56:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:56:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:56:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:56:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:56:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:56:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:56:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:56:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:56:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:56:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:01 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:56:02 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:56:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:56:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:56:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:56:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:56:02 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:56:03 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:56:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:56:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:56:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:56:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:56:03 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:56:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:56:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:56:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:56:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:03 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:56:03 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:56:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:03 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:56:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:56:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:56:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:56:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:04 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:56:04 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:56:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:04 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:56:04 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:56:05 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:56:05 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:56:05 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:56:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:06 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:56:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:56:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:56:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:56:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:06 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:56:06 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:56:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:06 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:56:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:06 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:56:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:56:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:56:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:56:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:06 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:56:06 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:56:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:06 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:56:07 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:56:07 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:56:08 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:56:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:08 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:56:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:56:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:56:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:56:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:08 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:56:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:09 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:56:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:56:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:56:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:56:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:09 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:56:10 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:56:10 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:56:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:56:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:56:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:56:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:11 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:56:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:11 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:56:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:56:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:56:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:56:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:12 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:56:12 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:56:12 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:56:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:13 [WARNING] transceiver.py:250 (MS@172.18.83.22:6700) RX TRXD message (fn=3259 tn=5 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:56:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:56:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:56:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:56:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:13 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:56:13 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:56:13 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:56:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:13 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:56:14 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 06:56:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:14 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:56:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:56:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:56:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:56:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:14 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:56:14 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:56:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:14 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 06:56:15 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 06:56:15 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 06:56:16 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 06:56:16 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 06:56:17 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 06:56:17 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 06:56:18 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 06:56:18 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 06:56:19 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 06:56:19 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 06:56:20 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 06:56:20 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 06:56:20 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 06:56:21 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 06:56:21 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 06:56:22 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 06:56:22 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 06:56:23 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 06:56:23 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 06:56:24 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 06:56:24 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 06:56:25 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 06:56:25 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 06:56:26 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 06:56:26 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 06:56:27 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 06:56:27 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-10-30 06:56:27 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-10-30 06:56:28 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-10-30 06:56:28 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-10-30 06:56:29 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-10-30 06:56:29 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-10-30 06:56:30 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-10-30 06:56:30 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-10-30 06:56:31 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-10-30 06:56:31 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-10-30 06:56:32 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-10-30 06:56:32 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-10-30 06:56:33 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-10-30 06:56:33 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-10-30 06:56:34 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-10-30 06:56:34 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-10-30 06:56:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:34 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:56:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:56:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:56:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:56:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:56:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:56:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:56:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:56:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:56:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:56:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:56:34 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:56:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=7892 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:56:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=7892 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:56:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=7892 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:56:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=7892 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:56:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=7893 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:56:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=7893 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:56:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=7893 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:56:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=7893 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:56:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=7893 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:56:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=7893 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:56:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=7893 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:56:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=7893 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:56:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:56:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:56:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:56:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:56:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:56:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:56:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:56:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:56:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:56:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:56:39 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:56:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:56:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:56:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:56:40 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:56:40 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:40 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:56:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:56:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:56:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:56:40 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:40 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:56:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:56:40 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:40 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:40 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:56:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:56:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:56:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:56:41 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:41 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:41 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:56:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:56:41 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:41 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:56:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:56:41 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:56:41 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=379 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:56:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:56:41 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=379 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:56:41 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=379 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:56:41 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=379 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:56:41 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=379 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:56:41 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=379 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:56:41 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=379 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:56:41 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=379 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:56:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:56:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:56:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:56:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:56:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:56:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:56:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:56:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:56:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:56:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:56:46 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:56:46 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:56:47 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:56:47 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:56:47 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:56:47 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:56:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:47 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:56:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:56:47 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:56:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:56:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:48 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:56:48 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:56:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:48 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:56:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:56:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:56:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:56:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:56:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:48 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:56:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:56:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:56:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:56:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:48 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:56:48 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:56:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:48 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:49 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:56:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:56:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:49 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:56:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:49 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:56:49 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:50 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:56:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:56:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:56:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:56:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:50 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:56:50 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:56:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:50 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:56:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:56:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:56:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:56:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:56:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:50 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:56:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:56:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:56:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:56:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:56:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:56:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:56:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:56:50 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:56:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:56:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:56:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:56:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:56:55 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:56:55 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:56:55 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:56:55 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:56:55 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:56:55 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:56:55 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:56:55 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:56:55 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:56:55 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:56:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:56:55 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:56:56 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:56:56 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:56 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:56:56 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:56:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:56:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:56:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:56:56 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:56 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:56:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:56:56 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:56 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:56 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:56:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:56:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:57 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:56:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:56:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:56:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:57 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:56:57 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:56:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:57 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:56:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:56:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:56:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:56:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:57 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:56:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:56:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:56:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:56:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:56:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:57 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:56:57 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:56:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:56:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:56:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:56:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:56:58 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:56:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:56:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:56:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:56:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:56:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:56:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:56:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:56:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:56:58 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:56:58 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=496 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:56:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:56:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:57:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:57:03 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:57:03 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:57:03 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:57:03 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:57:03 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:57:03 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:57:03 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:57:03 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:57:03 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:57:03 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:03 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:57:03 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:57:03 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:57:03 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:03 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:57:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:04 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:57:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:57:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:57:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:57:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:57:04 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:57:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:57:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:57:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:57:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:04 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:57:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:57:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:57:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:57:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:57:05 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:57:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:57:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:57:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:57:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:05 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:57:05 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:57:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:05 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:57:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:57:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:57:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:57:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:57:06 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:57:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:06 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:57:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:57:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:57:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:57:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:06 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:57:06 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:57:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:06 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:57:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:57:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:57:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:57:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:57:07 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:57:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:07 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:57:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:57:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:57:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:57:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:07 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:57:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:57:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:57:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:57:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:57:08 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:57:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:57:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:57:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:57:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:08 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:57:09 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:57:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:57:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:57:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:57:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:09 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:57:09 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:57:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:09 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:57:10 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:57:10 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:57:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:11 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:57:11 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:57:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:57:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:57:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:57:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:11 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:57:11 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:57:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:11 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:57:11 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:57:12 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:57:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:12 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:57:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:57:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:57:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:57:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:57:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:57:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:57:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:57:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:57:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:57:12 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:57:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:57:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:57:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:57:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:57:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:57:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:57:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:57:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:57:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:57:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:57:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:57:17 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:17 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:57:18 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:57:18 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:57:18 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:18 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:57:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:57:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:57:18 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:18 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:57:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:18 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:57:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:57:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:57:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:57:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:57:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:19 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:57:19 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:57:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:19 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:57:19 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:57:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:57:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:57:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:57:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:57:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:19 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:57:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:57:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:57:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:57:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:57:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:57:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:57:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:57:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:57:19 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:57:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=445 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:57:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:57:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:57:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=445 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:57:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=445 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:57:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=445 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:57:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=445 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:57:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=445 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:57:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=445 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:57:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=445 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:57:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:57:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:57:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:57:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:57:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:57:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:57:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:57:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:57:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:57:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:57:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:57:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:57:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:57:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:57:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:57:25 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:57:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:57:25 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:25 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:57:25 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:57:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:57:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:57:25 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:25 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:57:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:25 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:57:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:57:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:57:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:57:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:57:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:57:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:57:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:57:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:26 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:57:26 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:57:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:26 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:57:26 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:57:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:57:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:57:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:57:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:57:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:27 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:57:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:57:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:57:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:57:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:57:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:57:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:57:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:57:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:57:27 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:57:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:57:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:57:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:57:32 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:57:32 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:57:32 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:57:32 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:57:32 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:57:32 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:57:32 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:57:32 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:57:32 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:57:32 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:57:32 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:57:32 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:57:32 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:32 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:57:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:57:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:57:32 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:32 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:57:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:57:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:33 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:57:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:57:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:57:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:57:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:57:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:57:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:57:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:57:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:33 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:57:33 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:57:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:33 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:57:33 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:57:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:57:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:57:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:57:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:57:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:34 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:57:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:57:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:57:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:57:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:57:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:57:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:57:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:57:34 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:57:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=444 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:57:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:57:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:57:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:57:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=444 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:57:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=444 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:57:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=444 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:57:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=444 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:57:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=445 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:57:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=445 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:57:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=445 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:57:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=445 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:57:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=445 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:57:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=445 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:57:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=445 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:57:34 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=445 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:57:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:57:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:57:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:57:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:57:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:57:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:57:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:57:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:57:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:57:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:57:39 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:57:39 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:57:39 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:39 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:57:39 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:57:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:57:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:57:39 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:40 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:57:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:57:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:57:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:57:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:40 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:57:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:57:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:57:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:57:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:57:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:57:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:57:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:57:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:40 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:57:40 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:57:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:40 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:57:41 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:57:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:57:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:57:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:57:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:57:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:41 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:57:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:57:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:57:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:57:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:57:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:57:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:57:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:57:41 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:57:41 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=445 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:57:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:57:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:57:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:57:41 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=445 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:57:41 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=445 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:57:41 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=445 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:57:41 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=445 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:57:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:57:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:57:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:57:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:57:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:57:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:57:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:57:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:57:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:57:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:57:46 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:46 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:57:46 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:57:46 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:46 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:57:46 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:57:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:57:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:57:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:57:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:47 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:57:47 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:57:47 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:57:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:57:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:57:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:57:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:57:47 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:57:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:47 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:57:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:57:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:57:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:57:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:48 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:57:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:57:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:57:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:57:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:57:48 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:57:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:57:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:57:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:57:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:48 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:57:48 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:57:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:49 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:57:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:57:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:57:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:57:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:57:49 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:57:50 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:57:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:57:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:57:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:57:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:57:50 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:57:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:50 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:57:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:57:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:57:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:57:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:57:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:57:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:57:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:57:50 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:57:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:57:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:57:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:57:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:57:55 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:57:55 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:57:55 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:57:55 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:57:55 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:57:55 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:57:55 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:57:55 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:57:55 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:57:55 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:57:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:57:55 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:57:56 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:57:56 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:57:56 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:57:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:56 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:57:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:57:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:57:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:57:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:57:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:57:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:57:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:56 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:57:56 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:57:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:56 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:57:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:57:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:57:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:57:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:57:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:57 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:57:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:57:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:57:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:57:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:57 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:57:57 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:57:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:57:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:57:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:57:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:57:58 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:57:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:57:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:57:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:57:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:57:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:57:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:57:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:57:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:57:58 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:57:58 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:57:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:57:58 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:57:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:57:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:57:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:57:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:57:59 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:57:59 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:57:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:57:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:57:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:57:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:58:00 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:58:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:00 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:58:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:58:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:58:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:58:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:58:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:58:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:58:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:58:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:58:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:58:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:58:00 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:58:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:58:05 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:58:05 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:58:05 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:58:05 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:58:05 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:58:05 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:58:05 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:58:05 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:58:05 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:58:05 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:05 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:58:05 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:58:05 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:58:05 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:58:05 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:58:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:58:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:58:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:58:06 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:06 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:06 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:58:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:06 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:58:07 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:58:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:58:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:58:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:58:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:58:07 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:58:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:58:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:58:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:58:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:58:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:58:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:08 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:58:08 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:58:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:08 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:58:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:58:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:58:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:58:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:58:08 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:58:09 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:58:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:58:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:58:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:58:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:58:09 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:58:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:10 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:58:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:58:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:58:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:58:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:58:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:58:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:58:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:58:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:58:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:58:10 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:58:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:58:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:58:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:58:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:58:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:58:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:58:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:58:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:58:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:58:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:58:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:58:15 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:15 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:58:15 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:58:15 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:15 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:58:15 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:58:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:58:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:58:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:58:16 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:58:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:16 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:58:16 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:58:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:58:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:58:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:58:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:58:16 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:58:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:16 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:58:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:58:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:58:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:58:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:58:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:58:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:58:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:58:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:16 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:58:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:58:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:58:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:58:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:58:17 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:58:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:58:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:58:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:58:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:58:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:58:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:17 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:58:17 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:58:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:17 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:58:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:58:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:58:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:58:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:58:18 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:58:18 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:58:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:58:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:58:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:58:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:58:19 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:58:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:19 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:58:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:58:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:58:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:58:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:58:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:58:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:58:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:58:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:58:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:58:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:58:19 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:58:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=990 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:58:19 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=990 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:58:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:58:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:58:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:58:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:58:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:58:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:58:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:58:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:58:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:58:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:58:24 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:24 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:58:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:58:25 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:58:25 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:58:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:25 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:58:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:58:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:58:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:58:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:58:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:58:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:58:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:58:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:58:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:58:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:58:25 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:58:25 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=121 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:58:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:58:25 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=121 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:58:25 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=121 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:58:25 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=122 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:58:25 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=122 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:58:25 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:58:25 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:58:25 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:58:25 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:58:25 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:58:25 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:58:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:58:30 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:58:30 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:58:30 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:58:30 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:58:30 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:58:30 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:58:30 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:58:30 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:58:30 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:58:30 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:30 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:58:30 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:58:30 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:58:30 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:30 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:58:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:58:30 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:58:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:58:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:58:35 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:58:35 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:58:35 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:58:35 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:58:35 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:58:35 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:58:35 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:58:35 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:58:35 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:58:35 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:35 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:58:36 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:58:36 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:58:36 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:58:36 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:58:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:58:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:58:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:58:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:58:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:58:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:58:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:58:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:58:36 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:58:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:58:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:58:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:58:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:58:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:58:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:58:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:58:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:58:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:58:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:58:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:58:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:58:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:58:41 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:58:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:58:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:58:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:58:41 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:58:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:58:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:58:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:58:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:58:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:58:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:58:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:58:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:58:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:58:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:58:46 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:58:46 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:58:47 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:58:47 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:58:47 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:58:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:47 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:58:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:58:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:58:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:58:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:58:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:58:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:58:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:58:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:47 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:58:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:58:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:58:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:58:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:58:47 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:58:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:58:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:58:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:58:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:58:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:58:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:58:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:58:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:48 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:58:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:58:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:58:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:58:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:58:48 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:58:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:58:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:58:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:58:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:58:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:58:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:58:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:58:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:49 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:58:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:58:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:58:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:58:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:58:49 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:58:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:58:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:58:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:58:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:58:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:58:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:58:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:58:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:50 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:58:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:58:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:58:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:58:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:58:50 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:58:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:58:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:58:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:58:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:58:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:58:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:58:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:58:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:51 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:58:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:58:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:58:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:58:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:58:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:58:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:58:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:58:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:58:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:58:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:51 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:58:51 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2024-10-30 06:58:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:51 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:58:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:52 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:58:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:58:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:58:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:58:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:58:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:58:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:52 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:58:52 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2024-10-30 06:58:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:52 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:58:52 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:58:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:52 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:58:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:58:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:58:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:58:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:58:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:58:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:58:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:58:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:53 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:58:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:58:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:58:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:58:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:58:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:58:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:58:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:58:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:53 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:58:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:58:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:58:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:58:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:58:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:58:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:58:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:54 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:58:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:58:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:58:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:54 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:58:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:58:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:58:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:58:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:58:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:58:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:54 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:58:54 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:58:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:54 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:58:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:55 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:58:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:58:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:58:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:58:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:58:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:58:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:55 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:58:55 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 06:58:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:55 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:58:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:55 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:58:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:58:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:58:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:58:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:58:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:58:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:55 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:58:55 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:58:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:55 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:58:56 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:58:56 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:58:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:56 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:58:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:58:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:58:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:58:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:58:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:58:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:56 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:58:56 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:58:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:57 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:58:57 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:58:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:57 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:58:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:58:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:58:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:58:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:58:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:58:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:57 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:58:57 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:58:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:58 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:58:58 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:58:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:58 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:58:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:58:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:58:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:58:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:58:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:58:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:58 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:58:58 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:58:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:59 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:58:59 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:58:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:59 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:58:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:58:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:58:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:58:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:58:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:58:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:58:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:58:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:58:59 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:58:59 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:58:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:58:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:59:00 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:59:00 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:59:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:59:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:59:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:59:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:59:00 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:59:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:59:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:59:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:59:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:59:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:59:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:59:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:59:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:59:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:59:00 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:59:00 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:59:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:59:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:59:01 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:59:01 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:59:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:59:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:59:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:59:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:59:01 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:59:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:59:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:59:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:59:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:59:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:59:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:59:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:59:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:59:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:59:01 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:59:01 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:59:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:59:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:59:02 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:59:02 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 06:59:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:59:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:59:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:59:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:59:02 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:59:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:59:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:59:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:59:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:59:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:59:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:59:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:59:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:59:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:59:02 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 06:59:02 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 06:59:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:59:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:59:02 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 06:59:03 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 06:59:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:59:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:59:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:59:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:59:03 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 06:59:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:59:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:59:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:59:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:59:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:59:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:59:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:59:03 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:59:03 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3705 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:59:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:59:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:59:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:59:03 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3705 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:59:03 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3705 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:59:03 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3705 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:59:03 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3705 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:59:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:59:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:59:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:59:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:59:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:59:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:59:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:59:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:59:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:59:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:59:08 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:59:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:59:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:59:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:59:09 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:59:09 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 06:59:09 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:59:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:59:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:59:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:59:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:59:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:59:09 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:59:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:59:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:59:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:59:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:59:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 06:59:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:59:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:59:10 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:59:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 06:59:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 06:59:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 06:59:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 06:59:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 06:59:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 06:59:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 06:59:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 06:59:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:59:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:59:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:59:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:59:10 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:59:10 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=347 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 06:59:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:59:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:59:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:59:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:59:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:59:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:59:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:59:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:59:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:59:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:59:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:59:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:59:15 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:59:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:59:15 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:59:15 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:59:16 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:59:16 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:59:17 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:59:17 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:59:18 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:59:18 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:59:19 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:59:19 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:59:19 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:59:20 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:59:20 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:59:21 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:59:21 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:59:22 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:59:22 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:59:23 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:59:23 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:59:24 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:59:24 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:59:25 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:59:25 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:59:26 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:59:26 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:59:27 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:59:27 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:59:27 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:59:28 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:59:28 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:59:29 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:59:29 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:59:30 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:59:30 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 06:59:31 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 06:59:31 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 06:59:32 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 06:59:32 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 06:59:33 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 06:59:33 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 06:59:34 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 06:59:34 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 06:59:35 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 06:59:35 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 06:59:35 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 06:59:36 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 06:59:36 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 06:59:37 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 06:59:37 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 06:59:38 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 06:59:38 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 06:59:39 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 06:59:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:59:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:59:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:59:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:59:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:59:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:59:39 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 06:59:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:59:44 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 06:59:44 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:59:44 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 06:59:44 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:59:44 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 06:59:44 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:59:44 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 06:59:44 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 06:59:44 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 06:59:44 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:59:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 06:59:44 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 06:59:44 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 06:59:45 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 06:59:45 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 06:59:46 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 06:59:46 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 06:59:47 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 06:59:47 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 06:59:48 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 06:59:48 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 06:59:49 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 06:59:49 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 06:59:49 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 06:59:50 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 06:59:50 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 06:59:51 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 06:59:51 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 06:59:52 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 06:59:52 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 06:59:53 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 06:59:53 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 06:59:54 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 06:59:54 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 06:59:55 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 06:59:55 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 06:59:56 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 06:59:56 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 06:59:57 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 06:59:57 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 06:59:57 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 06:59:58 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 06:59:58 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 06:59:59 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 06:59:59 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 07:00:00 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 07:00:00 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 07:00:01 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 07:00:01 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 07:00:02 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 07:00:02 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 07:00:03 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 07:00:03 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 07:00:04 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 07:00:04 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 07:00:05 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 07:00:05 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 07:00:05 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 07:00:06 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 07:00:06 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 07:00:07 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 07:00:07 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 07:00:08 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 07:00:08 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 07:00:09 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 07:00:09 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 07:00:10 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 07:00:10 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 07:00:11 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 07:00:11 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 07:00:12 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 07:00:12 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 07:00:13 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 07:00:13 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-10-30 07:00:13 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-10-30 07:00:14 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-10-30 07:00:14 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-10-30 07:00:15 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-10-30 07:00:15 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-10-30 07:00:16 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-10-30 07:00:16 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-10-30 07:00:17 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-10-30 07:00:17 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-10-30 07:00:18 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-10-30 07:00:18 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-10-30 07:00:19 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-10-30 07:00:19 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-10-30 07:00:20 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-10-30 07:00:20 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-10-30 07:00:21 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-10-30 07:00:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:00:21 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-10-30 07:00:21 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-10-30 07:00:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:00:22 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-10-30 07:00:22 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-10-30 07:00:23 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-10-30 07:00:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:00:23 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-10-30 07:00:24 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-10-30 07:00:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:00:24 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-10-30 07:00:25 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-10-30 07:00:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:00:25 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-10-30 07:00:26 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-10-30 07:00:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:00:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:00:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:00:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:00:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:00:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:00:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:00:26 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:00:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:00:31 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:00:31 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:00:31 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:00:31 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:00:31 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:00:31 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:00:31 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:00:31 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:00:31 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:00:31 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:00:31 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:00:31 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:00:31 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:00:31 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:00:31 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:00:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:00:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:00:31 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:00:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:00:32 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:00:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:00:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:00:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:00:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:00:32 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:00:33 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:00:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:00:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:00:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:00:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:00:33 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:00:34 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:00:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:00:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:00:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:00:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:00:34 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:00:35 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:00:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:00:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:00:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:00:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:00:35 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:00:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:00:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:00:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:00:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:00:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:00:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:00:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:00:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:00:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:00:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:00:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:00:35 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:00:35 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:00:35 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 07:00:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:00:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:00:36 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:00:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:00:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:00:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:00:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:00:36 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:00:37 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:00:37 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:00:37 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:00:38 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:00:38 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:00:39 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:00:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:00:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:00:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:00:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:00:39 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:00:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:00:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:00:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:00:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:00:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:00:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:00:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:00:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:00:39 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:00:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:00:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:00:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:00:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:00:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:00:39 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:00:40 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:00:40 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:00:41 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 07:00:41 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 07:00:42 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 07:00:42 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 07:00:43 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 07:00:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:00:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:00:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:00:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:00:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:00:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:00:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:00:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:00:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:00:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:00:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:00:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:00:43 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:00:43 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 07:00:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:00:43 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:00:43 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 07:00:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:00:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:00:44 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 07:00:44 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 07:00:45 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 07:00:45 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 07:00:45 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 07:00:46 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 07:00:46 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 07:00:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:00:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:00:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:00:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:00:47 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:00:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:00:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:00:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:00:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:00:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:00:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:00:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:00:47 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:00:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:00:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:00:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:00:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:00:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:00:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:00:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:00:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:00:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:00:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:00:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:00:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:00:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:00:52 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:00:52 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:00:52 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:00:52 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:00:52 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:00:52 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:00:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:00:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:00:52 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:00:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:00:53 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:00:53 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:00:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:00:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:00:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:00:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:00:53 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:00:53 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:00:54 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:00:54 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:00:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:00:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:00:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:00:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:00:54 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:00:54 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:00:55 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:00:55 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:00:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:00:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:00:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:00:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:00:55 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:00:55 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:00:56 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:00:56 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:00:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:00:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:00:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:00:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:00:56 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:00:56 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:00:57 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:00:57 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:00:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:00:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:00:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:00:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:00:57 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:00:57 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:00:58 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:00:58 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:00:58 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:00:58 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:00:58 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:00:59 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:00:59 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:00:59 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:00:59 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:01:00 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:00 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:01:00 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:01:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:01:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:01:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:01:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:01:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:01:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:01:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:01:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:01:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:01:00 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:01:00 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:01:00 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 07:01:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:00 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:01:01 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:01 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:01:01 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:01 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:01:02 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:02 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 07:01:02 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:02 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 07:01:03 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:03 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 07:01:03 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:03 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 07:01:04 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:04 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 07:01:04 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:04 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 07:01:05 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:05 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 07:01:05 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 07:01:05 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:05 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 07:01:05 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:06 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 07:01:06 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:06 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 07:01:06 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:07 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 07:01:07 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:07 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 07:01:07 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:08 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 07:01:08 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:01:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:01:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:01:08 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:01:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:01:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:01:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:01:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:01:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:01:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:01:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:01:08 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:01:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:01:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:01:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:08 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:08 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 07:01:09 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:09 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 07:01:09 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:09 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 07:01:10 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:10 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 07:01:10 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:10 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 07:01:11 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:11 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 07:01:11 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:11 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 07:01:12 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:12 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 07:01:12 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:12 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 07:01:12 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:13 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 07:01:13 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:13 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 07:01:13 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:13 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 07:01:14 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:14 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 07:01:14 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:14 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 07:01:15 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:15 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 07:01:15 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:01:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:01:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:01:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:01:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:01:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:01:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:01:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:01:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:01:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:01:15 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:15 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 07:01:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:01:15 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:01:15 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 07:01:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:16 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:16 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 07:01:16 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:16 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 07:01:17 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:17 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 07:01:17 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:17 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 07:01:18 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:18 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 07:01:18 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:18 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 07:01:19 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:19 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 07:01:19 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:19 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 07:01:19 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:20 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 07:01:20 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:20 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 07:01:20 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:21 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 07:01:21 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:21 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-10-30 07:01:21 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:21 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-10-30 07:01:22 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:22 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-10-30 07:01:22 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:22 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-10-30 07:01:23 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:01:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:01:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:01:23 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:01:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:01:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:01:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:01:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:01:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:01:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:01:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:01:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:01:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:01:23 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:01:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6719 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:01:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:01:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6719 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:01:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6719 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:01:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6719 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:01:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6719 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:01:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6719 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:01:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6720 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:01:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6720 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:01:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6720 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:01:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6720 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:01:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6720 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:01:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6720 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:01:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6720 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:01:23 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6720 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:01:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:01:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:01:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:01:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:01:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:01:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:01:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:01:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:01:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:01:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:01:28 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:01:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:01:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:01:28 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:01:28 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:01:28 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:01:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:01:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:29 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:01:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:01:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:01:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:01:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:01:29 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:01:30 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:01:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:01:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:01:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:01:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:01:30 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:01:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:01:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:01:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:01:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:01:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:01:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:01:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:01:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:01:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:01:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:01:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:01:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:01:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:01:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:31 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:01:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:01:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:01:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:01:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:01:31 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:01:32 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:01:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:01:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:01:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:01:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:01:32 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:01:33 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:01:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:01:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:01:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:01:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:01:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:01:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:01:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:01:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:01:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:01:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:01:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:01:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:01:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:01:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:01:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:01:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:01:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:01:33 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:01:33 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:01:34 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:01:34 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:01:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:01:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:01:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:01:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:01:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:01:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:01:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:01:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:01:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:01:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:01:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:01:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:01:35 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:01:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:01:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:01:40 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:01:40 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:01:40 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:01:40 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:01:40 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:01:40 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:01:40 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:01:40 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:01:40 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:01:40 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:01:40 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:01:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:01:40 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:01:40 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:40 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:01:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:01:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:01:40 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:41 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:01:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:01:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:01:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:01:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:01:41 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:01:42 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:01:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:01:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:01:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:01:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:01:42 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:01:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:01:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:01:43 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:01:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:01:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:01:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:01:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:01:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:01:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:01:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:01:43 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:01:43 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 07:01:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:43 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:01:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:01:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:01:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:01:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:01:43 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:01:44 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:01:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:01:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:01:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:01:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:01:44 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:01:45 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:01:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:01:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:01:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:01:45 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:01:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:01:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:01:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:01:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:01:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:01:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:01:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:01:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:01:45 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:01:45 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1053 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:01:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:01:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:01:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:01:50 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:01:50 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:01:50 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:01:50 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:01:50 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:01:50 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:01:50 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:01:50 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:01:50 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:01:50 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:01:50 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:01:50 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:01:50 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:01:50 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:01:50 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:01:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:01:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:51 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:01:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:01:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:01:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:01:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:01:51 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:01:52 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:01:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:01:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:01:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:01:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:01:52 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:01:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:01:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:01:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:01:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:01:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:01:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:01:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:01:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:01:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:01:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:01:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:01:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:01:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:01:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:53 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:01:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:01:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:01:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:01:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:01:53 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:01:54 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:01:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:01:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:01:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:01:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:01:54 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:01:54 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:01:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:01:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:01:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:01:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:01:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:01:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:01:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:01:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:01:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:01:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:01:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:01:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:01:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:01:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:01:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:01:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:01:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:01:55 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:01:55 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:01:56 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:01:56 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:01:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:01:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:01:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:01:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:01:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:01:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:01:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:01:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:01:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:01:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:01:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:01:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:01:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:01:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:01:57 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:02:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:02:02 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:02:02 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:02:02 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:02:02 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:02:02 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:02:02 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:02:02 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:02:02 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:02:02 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:02:02 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:02 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:02:02 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:02:02 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:02:02 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:02:02 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:02:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:02:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:02:02 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:03 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:02:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:02:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:02:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:02:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:02:03 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:02:04 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:02:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:02:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:02:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:02:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:02:04 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:02:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:02:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:02:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:02:04 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:02:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:02:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:02:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:02:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:02:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:02:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:02:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:02:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:02:04 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:02:04 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 07:02:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:04 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:02:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:02:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:02:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:02:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:02:05 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:02:05 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:02:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:02:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:02:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:02:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:02:06 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:02:06 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:02:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:02:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:02:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:02:06 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:02:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:02:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:02:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:02:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:02:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:02:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:02:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:02:07 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:02:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:02:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:02:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:02:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:02:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:02:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:02:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:02:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:02:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:02:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:02:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:02:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:02:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:02:12 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:02:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:02:12 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:02:12 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:02:12 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:02:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:02:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:12 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:02:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:02:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:02:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:02:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:02:13 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:02:13 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:02:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:02:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:02:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:02:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:02:14 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:02:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:02:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:02:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:02:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:02:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:02:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:02:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:02:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:02:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:02:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:02:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:02:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:02:14 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:02:14 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=595 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:02:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:02:14 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=595 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:02:14 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=595 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:02:14 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=595 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:02:14 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=595 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:02:14 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=595 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:02:14 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=595 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:02:14 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=595 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:02:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:02:19 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:02:19 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:02:19 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:02:19 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:02:19 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:02:19 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:02:19 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:02:19 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:02:19 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:02:19 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:19 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:02:20 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:02:20 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:02:20 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:02:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:02:20 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:02:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:02:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:02:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:02:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:02:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:02:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:02:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:02:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:02:20 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:02:20 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 07:02:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:20 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:02:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:02:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:02:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:02:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:02:21 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:02:21 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:02:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:02:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:02:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:02:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:02:22 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:02:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:02:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:02:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:02:22 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:02:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:02:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:02:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:02:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:02:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:02:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:02:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:02:22 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:02:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:02:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:02:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:02:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:02:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:02:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:02:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:02:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:02:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:02:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:02:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:02:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:02:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:02:27 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:02:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:02:28 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:02:28 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:02:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:02:28 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:02:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:02:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:02:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:02:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:02:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:02:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:02:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:02:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:02:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:02:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:02:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:02:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:02:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:02:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:02:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:02:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:02:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:02:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:02:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:02:28 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:02:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:02:33 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:02:33 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:02:33 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:02:33 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:02:33 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:02:33 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:02:33 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:02:33 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:02:33 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:02:33 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:33 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:02:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:02:33 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:02:33 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:02:33 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:02:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:02:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:34 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:02:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:02:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:02:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:02:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:02:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:02:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:02:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:02:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:02:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:02:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:02:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:02:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:02:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:02:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:02:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:02:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:02:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:02:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:34 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:02:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:02:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:02:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:02:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:02:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:02:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:02:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:02:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:02:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:02:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:02:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:02:34 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:02:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:02:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:02:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:02:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:02:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:02:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:02:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:02:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:02:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:02:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:02:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:02:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:02:39 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:02:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:02:40 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:02:40 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:02:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:02:40 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:02:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:02:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:02:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:02:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:02:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:02:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:02:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:02:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:02:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:02:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:02:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:40 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:02:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:02:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:02:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:02:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:02:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:02:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:02:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:02:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:02:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:02:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:02:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:02:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:02:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:02:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:02:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:02:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:02:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:02:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:41 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:02:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:02:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:02:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:02:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:02:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:02:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:02:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:02:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:02:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:02:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:02:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:02:41 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:02:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:02:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:02:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:02:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:02:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:02:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:02:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:02:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:02:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:02:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:02:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:02:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:02:46 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:46 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:02:46 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:02:46 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:02:46 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:02:46 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:02:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:02:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:02:46 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:47 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:02:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:02:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:02:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:02:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:02:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:02:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:02:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:02:47 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:02:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:02:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:02:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:02:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:02:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:02:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:02:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:02:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:02:47 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:02:47 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 07:02:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:47 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:02:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:02:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:02:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:02:47 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:02:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:02:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:02:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:02:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:02:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:02:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:02:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:02:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:02:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:02:47 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:02:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:02:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:02:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:02:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:02:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:02:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:02:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:02:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:02:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:02:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:02:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:02:52 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:52 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:02:53 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:02:53 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:02:53 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:02:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:02:53 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:02:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:02:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:02:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:02:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:02:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:02:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:02:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:02:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:02:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:02:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:02:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:02:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:02:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:02:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:02:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:02:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:02:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:02:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:02:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:02:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:02:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:02:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:02:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:02:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:53 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:02:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:02:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:02:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:02:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:02:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:02:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:02:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:02:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:02:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:02:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:02:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:02:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:02:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:02:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:02:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:02:54 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:02:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:02:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:02:54 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=231 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:02:54 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=231 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:02:54 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=231 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:02:54 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=231 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:02:54 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=231 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:02:54 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=231 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:02:54 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=231 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:02:54 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=231 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:02:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:02:59 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:02:59 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:02:59 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:02:59 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:02:59 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:02:59 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:02:59 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:02:59 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:02:59 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:02:59 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:02:59 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:02:59 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:02:59 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:02:59 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:02:59 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:02:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:02:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:02:59 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:02:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:03:00 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:03:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:03:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:03:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:03:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:03:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:03:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:03:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:03:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:03:00 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:03:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:03:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:03:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:03:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:03:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:03:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:03:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:03:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:03:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:03:00 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:03:00 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 07:03:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:03:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:03:00 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:03:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:03:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:03:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:03:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:03:00 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:03:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:03:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:03:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:03:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:03:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:03:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:03:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:03:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:03:00 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:03:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:03:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:03:00 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=360 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:03:00 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=360 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:03:00 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=360 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:03:00 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=360 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:03:00 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=360 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:03:00 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=360 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:03:00 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=360 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:03:00 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=360 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:03:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:03:05 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:03:05 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:03:05 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:03:05 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:03:05 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:03:05 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:03:05 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:03:05 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:03:05 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:03:05 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:05 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:03:06 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:03:06 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:03:06 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:03:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:03:06 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:03:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:03:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:03:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:03:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:03:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:03:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:03:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:03:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:03:06 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:03:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:03:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:03:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:03:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:03:07 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:03:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:03:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:03:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:03:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:03:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:03:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:03:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:03:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:03:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:03:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:03:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:03:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:03:07 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:03:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:03:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:03:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:03:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:03:08 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:03:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD NOHANDOVER
2024-10-30 07:03:08 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:03:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD NOHANDOVER
2024-10-30 07:03:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:03:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:03:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:03:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:03:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:03:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:03:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:03:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:03:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:03:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:03:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:03:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:03:08 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:03:08 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=623 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:03:08 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=623 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:03:08 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=623 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:03:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:03:13 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:03:13 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:03:13 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:03:13 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:03:13 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:03:13 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:03:13 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:03:13 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:03:13 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:03:13 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:13 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:03:14 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:03:14 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:03:14 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:03:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:03:14 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:03:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:03:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:03:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:03:14 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:03:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:03:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:03:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:03:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:03:15 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:03:15 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:03:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:03:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:03:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:03:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:03:16 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:03:16 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:03:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:03:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:03:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:03:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:03:16 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:03:17 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:03:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:03:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:03:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:03:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:03:17 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:03:18 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:03:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:03:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:03:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:03:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:03:18 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:03:19 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:03:19 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:03:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:03:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:03:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:03:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:03:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:03:20 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:03:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD NOHANDOVER
2024-10-30 07:03:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:03:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:03:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:03:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:03:20 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:03:21 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:03:21 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:03:22 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:03:22 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:03:23 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:03:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:03:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:03:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:03:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:03:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:03:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:03:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:03:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:03:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:03:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:03:23 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:03:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:03:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:03:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:03:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:03:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:03:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:03:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:03:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:03:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:03:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:03:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:03:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:03:28 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:03:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:03:28 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:03:28 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:03:28 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:03:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:03:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:03:29 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:03:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:03:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:03:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:03:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:03:29 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:03:30 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:03:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:03:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:03:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:03:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:03:30 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:03:31 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:03:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:03:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:03:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:03:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:03:31 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:03:32 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:03:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:03:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:03:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:03:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:03:32 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:03:32 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:03:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:03:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:03:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:03:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:03:33 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:03:33 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:03:34 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:03:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:03:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:03:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:03:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:03:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:03:34 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:03:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD NOHANDOVER
2024-10-30 07:03:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:03:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:03:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:03:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:03:35 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:03:35 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:03:36 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:03:36 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:03:37 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:03:37 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:03:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:03:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:03:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:03:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:03:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:03:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:03:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:03:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:03:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:03:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:03:37 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:03:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:03:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:03:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:03:42 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:03:42 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:03:42 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:03:42 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:03:42 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:03:42 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:03:42 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:03:42 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:03:42 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:03:42 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:42 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:03:43 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:03:43 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:03:43 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:03:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:03:43 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:03:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:03:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:03:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:03:43 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:03:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:03:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:03:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:03:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:03:44 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:03:44 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:03:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:03:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:03:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:03:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:03:45 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:03:45 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:03:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:03:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:03:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:03:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:03:46 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:03:46 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:03:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:03:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:03:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:03:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:03:47 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:03:47 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:03:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:03:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:03:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:03:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:03:48 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:03:48 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:03:48 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:03:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:03:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:03:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:03:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:03:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:03:49 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:03:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD NOHANDOVER
2024-10-30 07:03:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:03:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:03:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:03:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:03:49 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:03:50 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:03:50 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:03:51 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:03:51 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:03:52 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:03:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:03:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:03:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:03:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:03:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:03:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:03:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:03:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:03:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:03:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:03:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:03:52 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:03:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:03:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:03:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:03:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:03:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:03:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:03:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:03:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:03:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:03:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:03:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:03:57 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:03:57 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:03:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:03:58 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:03:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:03:58 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:03:58 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:03:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:03:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:03:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:03:58 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:03:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:03:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:03:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:03:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:03:58 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:03:59 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:03:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:03:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:03:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:03:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:03:59 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:04:00 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:04:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:04:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:04:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:04:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:04:00 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:04:01 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:04:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:04:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:04:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:04:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:04:01 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:04:02 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:04:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:04:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:04:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:04:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:04:02 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:04:03 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:04:03 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:04:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:04:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:04:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:04:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:04:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:04:04 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:04:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD NOHANDOVER
2024-10-30 07:04:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:04:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:04:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:04:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:04:04 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:04:05 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:04:05 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:04:06 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:04:06 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:04:06 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:04:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:04:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:04:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:04:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:04:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:04:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:04:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:04:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:04:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:04:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:04:07 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:04:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:04:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:04:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:04:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:04:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:04:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:04:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:04:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:04:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:04:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:04:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:04:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:04:12 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:04:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:04:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:04:12 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:04:12 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:04:12 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:04:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:04:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:04:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:04:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:04:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:04:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:04:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:04:13 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:04:14 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:04:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:04:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:04:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:04:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:04:14 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:04:15 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:04:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:04:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:04:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:04:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:04:15 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:04:15 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:04:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:04:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:04:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:04:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:04:16 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:04:16 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:04:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:04:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:04:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:04:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:04:17 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:04:17 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:04:18 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:04:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:04:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:04:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:04:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:04:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:04:18 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:04:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD NOHANDOVER
2024-10-30 07:04:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:04:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:04:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:04:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:04:19 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:04:19 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:04:20 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:04:20 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:04:21 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:04:21 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:04:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:04:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:04:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:04:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:04:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:04:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:04:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:04:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:04:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:04:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:04:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:04:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:04:21 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:04:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:04:26 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:04:26 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:04:26 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:04:26 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:04:26 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:04:26 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:04:26 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:04:26 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:04:26 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:04:26 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:04:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:04:26 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:04:27 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:04:27 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:04:27 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:04:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:04:27 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:04:27 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:04:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:04:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:04:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:04:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:04:28 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:04:28 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:04:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:04:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:04:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:04:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:04:29 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:04:29 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:04:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:04:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:04:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:04:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:04:30 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:04:30 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:04:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:04:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:04:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:04:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:04:31 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:04:31 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:04:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:04:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:04:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:04:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:04:31 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:04:32 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:04:32 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:04:33 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:04:33 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:04:34 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:04:34 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:04:35 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:04:35 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:04:36 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:04:36 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 07:04:37 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 07:04:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:04:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:04:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:04:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:04:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:04:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:04:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:04:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:04:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:04:37 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:04:37 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2288 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:04:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:04:37 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2288 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:04:37 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2288 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:04:37 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2288 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:04:37 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2288 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:04:37 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2288 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:04:37 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2288 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:04:37 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2288 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:04:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:04:42 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:04:42 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:04:42 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:04:42 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:04:42 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:04:42 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:04:42 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:04:42 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:04:42 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:04:42 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:04:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:04:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:04:42 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:04:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:04:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:04:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:04:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:04:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:04:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:04:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:04:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:04:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:04:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:04:47 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:04:47 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:04:47 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:04:47 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:04:47 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:04:47 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:04:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:04:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:04:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:04:48 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:04:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:04:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:04:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:04:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:04:48 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:04:49 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:04:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:04:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:04:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:04:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:04:49 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:04:50 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:04:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:04:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:04:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:04:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:04:50 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:04:51 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:04:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:04:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:04:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:04:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:04:51 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:04:52 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:04:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:04:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:04:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:04:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:04:52 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:04:53 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:04:53 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:04:54 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:04:54 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:04:54 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:04:55 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:04:55 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:04:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:04:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:04:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:04:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:04:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:04:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:04:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:04:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:04:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:04:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:04:56 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:04:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:04:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:05:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:05:01 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:05:01 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:05:01 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:05:01 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:05:01 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:05:01 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:05:01 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:05:01 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:05:01 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:05:01 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:05:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:05:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:05:01 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:05:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:05:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:05:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:05:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:05:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:05:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:05:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:05:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:05:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:05:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:05:06 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:05:06 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:05:06 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:05:06 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:05:06 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:05:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:05:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:05:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:05:07 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:05:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:05:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:05:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:05:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:05:07 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:05:07 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:05:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:05:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:05:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:05:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:05:08 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:05:08 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:05:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:05:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:05:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:05:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:05:09 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:05:09 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:05:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:05:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:05:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:05:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:05:10 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:05:10 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:05:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:05:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:05:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:05:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:05:11 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:05:11 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:05:12 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:05:12 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:05:13 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:05:13 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:05:14 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:05:14 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:05:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:05:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:05:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:05:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:05:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:05:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:05:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:05:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:05:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:05:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:05:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:05:14 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:05:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:05:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:05:19 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:05:19 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:05:19 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:05:19 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:05:19 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:05:19 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:05:19 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:05:19 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:05:19 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:05:19 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:05:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:05:19 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:05:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:05:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:05:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:05:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:05:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:05:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:05:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:05:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:05:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:05:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:05:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:05:24 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:24 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:05:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:05:25 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:05:25 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:05:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:05:25 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:05:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:05:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:05:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:05:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:05:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:05:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:05:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:05:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:05:25 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:05:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:05:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:05:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:05:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:05:26 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:05:26 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:05:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:05:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:05:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:05:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:05:27 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:05:27 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:05:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:05:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:05:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:05:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:05:28 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:05:28 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:05:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:05:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:05:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:05:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:05:28 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:05:29 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:05:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:05:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:05:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:05:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:05:29 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:05:30 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:05:30 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:05:31 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:05:31 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:05:32 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:05:32 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:05:33 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:05:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:05:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:05:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:05:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:05:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:05:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:05:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:05:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:05:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:05:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:05:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:05:33 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:05:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:05:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:05:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:05:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:05:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:05:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:05:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:05:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:05:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:05:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:05:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:05:38 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:05:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:05:38 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:05:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:05:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:05:43 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:05:43 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:05:43 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:05:43 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:05:43 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:05:43 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:05:43 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:05:43 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:05:43 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:05:43 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:43 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:05:43 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:05:43 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:05:43 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:05:43 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:05:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:05:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:05:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:05:44 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:05:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:05:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:05:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:05:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:05:44 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:05:45 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:05:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:05:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:05:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:05:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:05:45 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:05:46 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:05:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:05:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:05:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:05:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:05:46 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:05:47 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:05:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:05:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:05:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:05:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:05:47 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:05:48 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:05:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:05:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:05:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:05:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:05:48 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:05:49 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:05:49 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:05:49 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:05:50 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:05:50 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:05:51 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:05:51 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:05:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:05:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:05:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:05:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:05:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:05:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:05:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:05:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:05:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:05:51 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:05:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:05:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:05:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:05:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:05:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:05:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:05:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:05:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:05:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:05:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:05:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:05:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:05:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:05:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:05:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:05:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:05:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:05:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:05:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:05:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:05:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:05:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:05:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:05:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:05:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:05:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:05:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:05:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:05:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:05:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:05:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:05:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:05:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:05:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:05:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:05:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:05:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:05:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:05:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:05:57 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:05:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:05:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:05:57 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:06:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:06:02 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:06:02 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:06:02 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:06:02 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:06:02 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:06:02 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:06:02 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:06:02 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:06:02 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:06:02 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:02 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:06:02 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:06:02 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:06:02 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:06:02 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:06:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:06:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:06:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:06:02 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:06:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:06:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:06:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:06:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:06:03 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:06:03 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:06:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:06:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:06:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:06:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:06:04 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:06:04 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:06:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:06:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:06:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:06:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:06:05 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:06:05 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:06:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:06:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:06:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:06:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:06:06 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:06:06 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:06:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:06:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:06:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:06:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:06:07 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:06:07 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:06:08 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:06:08 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:06:09 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:06:09 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:06:10 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:06:10 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:06:10 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:06:11 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:06:11 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 07:06:12 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 07:06:12 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 07:06:13 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 07:06:13 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 07:06:14 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 07:06:14 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 07:06:15 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 07:06:15 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 07:06:16 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 07:06:16 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 07:06:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:06:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:06:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:06:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:06:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:06:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:06:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:06:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:06:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:06:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:06:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:06:16 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:06:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:06:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:06:21 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:06:21 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:06:21 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:06:21 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:06:21 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:06:21 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:06:21 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:06:21 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:06:21 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:06:21 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:06:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:06:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:06:21 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:06:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:06:26 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:06:26 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:06:26 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:06:26 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:06:26 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:06:26 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:06:26 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:06:26 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:06:26 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:06:26 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:26 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:06:27 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:06:27 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:06:27 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:06:27 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:06:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:06:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:06:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:06:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:06:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:06:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:06:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:06:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:06:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:06:27 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:06:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:06:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:06:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:06:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:06:28 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:06:28 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:06:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:06:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:06:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:06:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:06:29 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:06:29 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:06:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:06:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:06:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:06:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:06:30 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:06:30 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:06:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:06:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:06:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:06:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:06:30 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:06:31 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:06:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:06:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:06:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:06:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:06:31 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:06:32 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:06:32 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:06:33 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:06:33 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:06:34 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:06:34 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:06:35 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:06:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:06:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:06:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:06:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:06:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:06:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:06:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:06:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:06:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:06:35 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:06:35 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1864 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:06:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:06:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:06:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:06:35 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1864 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:06:35 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1864 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:06:35 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1864 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:06:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:06:40 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:06:40 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:06:40 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:06:40 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:06:40 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:06:40 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:06:40 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:06:40 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:06:40 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:06:40 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:06:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:06:40 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:06:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:06:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:06:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:06:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:06:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:06:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:06:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:06:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:06:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:06:45 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:06:45 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:06:45 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:06:45 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:06:45 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:06:45 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:06:45 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:06:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:06:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:06:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:06:46 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:06:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:06:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:06:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:06:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:06:46 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:06:47 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:06:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:06:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:06:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:06:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:06:47 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:06:48 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:06:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:06:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:06:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:06:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:06:48 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:06:49 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:06:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:06:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:06:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:06:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:06:49 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:06:50 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:06:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:06:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:06:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:06:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:06:50 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:06:50 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:06:51 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:06:51 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:06:52 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:06:52 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:06:53 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:06:53 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:06:54 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:06:54 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:06:55 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 07:06:55 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 07:06:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:06:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:06:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:06:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:06:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:06:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:06:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:06:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:06:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:06:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:06:55 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:06:55 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2301 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:06:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:06:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:06:55 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2301 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:06:55 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2301 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:06:55 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2301 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:06:55 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2301 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:06:55 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2301 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:07:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:07:00 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:07:00 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:07:00 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:07:00 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:07:00 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:07:00 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:07:00 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:07:00 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:07:00 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:07:00 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:07:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:07:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:07:00 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:07:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:07:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:07:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:07:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:07:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:07:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:07:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:07:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:07:05 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:07:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:07:05 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:07:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:07:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:07:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:07:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:07:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:07:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:07:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:07:06 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:07:06 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:07:06 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:07:06 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:07:06 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:07:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:07:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:07:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:07:06 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:07:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:07:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:07:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:07:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:07:07 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:07:07 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:07:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:07:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:07:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:07:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:07:08 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:07:08 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:07:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:07:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:07:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:07:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:07:09 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:07:09 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:07:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:07:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:07:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:07:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:07:10 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:07:10 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:07:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:07:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:07:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:07:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:07:11 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:07:11 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:07:12 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:07:12 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:07:13 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:07:13 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:07:14 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:07:14 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:07:14 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:07:15 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:07:15 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 07:07:16 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 07:07:16 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 07:07:17 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 07:07:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:07:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:07:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:07:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:07:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:07:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:07:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:07:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:07:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:07:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:07:17 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:07:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:07:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:07:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:07:22 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:07:22 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:07:22 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:07:22 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:07:22 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:07:22 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:07:22 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:07:22 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:07:22 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:07:22 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:07:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:07:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:07:22 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:07:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:07:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:07:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:07:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:07:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:07:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:07:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:07:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:07:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:07:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:07:27 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:07:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:07:28 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:07:28 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:07:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:07:28 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:07:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:07:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:07:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:07:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:07:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:07:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:07:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:07:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:07:28 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:07:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:07:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:07:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:07:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:07:29 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:07:29 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:07:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:07:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:07:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:07:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:07:30 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:07:30 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:07:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:07:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:07:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:07:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:07:30 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:07:31 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:07:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:07:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:07:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:07:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:07:31 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:07:32 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:07:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:07:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:07:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:07:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:07:32 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:07:33 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:07:33 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:07:34 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:07:34 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:07:35 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:07:35 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:07:36 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:07:36 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:07:37 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:07:37 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 07:07:38 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 07:07:38 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 07:07:38 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 07:07:39 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 07:07:39 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 07:07:40 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 07:07:40 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 07:07:41 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 07:07:41 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 07:07:42 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 07:07:42 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 07:07:43 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 07:07:43 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 07:07:44 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 07:07:44 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 07:07:45 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 07:07:45 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 07:07:45 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 07:07:46 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 07:07:46 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 07:07:47 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 07:07:47 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 07:07:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:07:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:07:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:07:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:07:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:07:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:07:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:07:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:07:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:07:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:07:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:07:48 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:07:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:07:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:07:53 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:07:53 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:07:53 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:07:53 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:07:53 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:07:53 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:07:53 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:07:53 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:07:53 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:07:53 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:07:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:07:53 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:07:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:07:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:07:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:07:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:07:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:07:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:07:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:07:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:07:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:07:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:07:58 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:07:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:07:58 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:07:58 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:07:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:07:58 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:07:58 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:07:59 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:07:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:07:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:07:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:07:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:07:59 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:08:00 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:08:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:08:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:08:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:08:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:08:00 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:08:01 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:08:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:08:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:08:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:08:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:08:01 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:08:02 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:08:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:08:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:08:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:08:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:08:02 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:08:03 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:08:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:08:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:08:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:08:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:08:03 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:08:04 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:08:04 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:08:04 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:08:05 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:08:05 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:08:06 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:08:06 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:08:07 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:08:07 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:08:08 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 07:08:08 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 07:08:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:08:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:08:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:08:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:08:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:08:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:08:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:08:08 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:08:08 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2269 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:08:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:08:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:08:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:08:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:08:13 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:08:13 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:08:13 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:08:13 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:08:13 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:08:13 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:08:13 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:08:13 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:08:13 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:08:13 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:08:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:08:13 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:08:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:08:18 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:08:18 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:08:18 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:08:18 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:08:18 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:08:18 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:08:18 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:08:18 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:08:18 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:08:18 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:18 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:08:19 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:08:19 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:08:19 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:08:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:08:19 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:08:19 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:08:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:08:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:08:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:08:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:08:20 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:08:20 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:08:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:08:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:08:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:08:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:08:21 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:08:21 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:08:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:08:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:08:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:08:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:08:22 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:08:22 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:08:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:08:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:08:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:08:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:08:23 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:08:23 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:08:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:08:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:08:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:08:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:08:24 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:08:24 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:08:25 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:08:25 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:08:26 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:08:26 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:08:26 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:08:27 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:08:27 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:08:28 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:08:28 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 07:08:29 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 07:08:29 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 07:08:30 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 07:08:30 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 07:08:31 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 07:08:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:08:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:08:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:08:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:08:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:08:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:08:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:08:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:08:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:08:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:08:31 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:08:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:08:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:08:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:08:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:08:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:08:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:08:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:08:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:08:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:08:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:08:36 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:08:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:08:36 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:08:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:08:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:08:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:08:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:08:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:08:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:08:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:08:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:08:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:08:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:08:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:08:41 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:08:42 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:08:42 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:08:42 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:08:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:08:42 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:08:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:08:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:08:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:08:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:08:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:08:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:08:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:08:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:08:42 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:08:42 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2024-10-30 07:08:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:08:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:08:42 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:08:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:08:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:08:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:08:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:08:42 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:08:43 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:08:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:08:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:08:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:08:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:08:43 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:08:44 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:08:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:08:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:08:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:08:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:08:44 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:08:45 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:08:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:08:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:08:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:08:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:08:45 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:08:46 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:08:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:08:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:08:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:08:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:08:46 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:08:47 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:08:47 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:08:48 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:08:48 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:08:49 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:08:49 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:08:50 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:08:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:08:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:08:50 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:08:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:08:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:08:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:08:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:08:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:08:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:08:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:08:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:08:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:08:50 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:08:50 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:08:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:08:50 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:08:50 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:08:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:08:55 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:08:55 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:08:55 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:08:55 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:08:55 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:08:55 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:08:55 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:08:55 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:08:55 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:08:55 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:08:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:08:55 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:08:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:09:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:09:00 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:09:00 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:09:00 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:09:00 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:09:00 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:09:00 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:09:00 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:09:00 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:09:00 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:09:00 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:00 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:09:00 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:09:00 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:09:00 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:09:00 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:09:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:09:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:09:00 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:09:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:09:01 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:09:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:09:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:09:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:09:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:09:01 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:09:02 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:09:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:09:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:09:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:09:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:09:02 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:09:03 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:09:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:09:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:09:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:09:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:09:03 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:09:03 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:09:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:09:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:09:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:09:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:09:04 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:09:04 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:09:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:09:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:09:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:09:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:09:05 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:09:05 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:09:06 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:09:06 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:09:07 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:09:07 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:09:08 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:09:08 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:09:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:09:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:09:08 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:09:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:09:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:09:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:09:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:09:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:09:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:09:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:09:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:09:08 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:09:08 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:09:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:09:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:09:08 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:09:08 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:09:08 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:09:08 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:09:08 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1865 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:09:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:09:13 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:09:13 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:09:13 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:09:13 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:09:13 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:09:13 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:09:13 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:09:13 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:09:13 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:09:13 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:09:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:09:13 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:09:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:09:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:09:18 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:09:18 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:09:18 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:09:18 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:09:18 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:09:18 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:09:18 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:09:18 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:09:18 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:09:18 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:18 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:09:19 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:09:19 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:09:19 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:09:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:09:19 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:09:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:09:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:09:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:09:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:09:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:09:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:09:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:09:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:09:19 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:09:19 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2024-10-30 07:09:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:09:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:09:19 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:09:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:09:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:09:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:09:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:09:20 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:09:20 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:09:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:09:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:09:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:09:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:09:21 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:09:21 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:09:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:09:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:09:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:09:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:09:22 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:09:22 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:09:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:09:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:09:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:09:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:09:23 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:09:23 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:09:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:09:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:09:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:09:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:09:24 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:09:24 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:09:24 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:09:25 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:09:25 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:09:26 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:09:26 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:09:27 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:09:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:09:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:09:27 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:09:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:09:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:09:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:09:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:09:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:09:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:09:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:09:27 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:09:27 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:09:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:09:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:09:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:09:27 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:09:27 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1866 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:09:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:09:32 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:09:32 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:09:32 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:09:32 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:09:32 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:09:32 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:09:32 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:09:32 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:09:32 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:09:32 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:09:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:09:32 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:09:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:09:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:09:37 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:09:37 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:09:37 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:09:37 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:09:37 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:09:37 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:09:37 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:09:37 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:09:37 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:09:37 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:37 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:09:38 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:09:38 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:09:38 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:09:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:09:38 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:09:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:09:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:09:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:09:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:09:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:09:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:09:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:09:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:09:38 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:09:38 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2024-10-30 07:09:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:09:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:09:38 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:09:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:09:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:09:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:09:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:09:38 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:09:39 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:09:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:09:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:09:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:09:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:09:39 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:09:40 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:09:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:09:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:09:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:09:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:09:40 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:09:41 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:09:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:09:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:09:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:09:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:09:41 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:09:42 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:09:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:09:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:09:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:09:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:09:42 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:09:43 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:09:43 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:09:44 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:09:44 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:09:45 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:09:45 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:09:46 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:09:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:09:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:09:46 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:09:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:09:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:09:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:09:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:09:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:09:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:09:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:09:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:09:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:09:46 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:09:46 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1860 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:09:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:09:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:09:51 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:09:51 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:09:51 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:09:51 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:09:51 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:09:51 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:09:51 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:09:51 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:09:51 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:09:51 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:09:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:09:51 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:09:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:09:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:09:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:09:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:09:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:09:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:09:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:09:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:09:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:09:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:09:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:09:56 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:09:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:09:56 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:09:56 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:09:56 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:09:56 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:09:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:09:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:09:56 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:09:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:09:57 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:09:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:09:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:09:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:09:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:09:57 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:09:58 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:09:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:09:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:09:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:09:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:09:58 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:09:59 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:09:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:09:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:09:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:09:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:09:59 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:09:59 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:10:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:10:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:10:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:10:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:10:00 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:10:00 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:10:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:10:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:10:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:10:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:10:01 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:10:01 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:10:02 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:10:02 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:10:03 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:10:03 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:10:04 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:10:04 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:10:05 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:10:05 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:10:06 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 07:10:06 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 07:10:07 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 07:10:07 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 07:10:07 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 07:10:08 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 07:10:08 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 07:10:09 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 07:10:09 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 07:10:10 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 07:10:10 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 07:10:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:10:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:10:10 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:10:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:10:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:10:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:10:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:10:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:10:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:10:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:10:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:10:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:10:10 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:10:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:10:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:10:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:10:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:10:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:10:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:10:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:10:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:10:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:10:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:10:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:10:15 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:10:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:10:15 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:10:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:10:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:10:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:10:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:10:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:10:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:10:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:10:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:10:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:10:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:10:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:10:20 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:20 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:10:21 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:10:21 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:10:21 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:10:21 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:10:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:10:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:10:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:10:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:10:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:10:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:10:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:10:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:10:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:10:21 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:10:21 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2024-10-30 07:10:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:10:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:10:21 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:10:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:10:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:10:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:10:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:10:22 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:10:22 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:10:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:10:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:10:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:10:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:10:23 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:10:23 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:10:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:10:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:10:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:10:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:10:24 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:10:24 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:10:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:10:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:10:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:10:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:10:25 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:10:25 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:10:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:10:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:10:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:10:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:10:26 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:10:26 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:10:26 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:10:27 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:10:27 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:10:28 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:10:28 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:10:29 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:10:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:10:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:10:29 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:10:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:10:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:10:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:10:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:10:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:10:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:10:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:10:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:10:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:10:29 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:10:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:10:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:10:34 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:10:34 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:10:34 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:10:34 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:10:34 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:10:34 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:10:34 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:10:34 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:10:34 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:10:34 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:10:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:10:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:10:34 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:10:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:10:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:10:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:10:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:10:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:10:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:10:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:10:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:10:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:10:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:10:39 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:10:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:10:40 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:10:40 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:10:40 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:10:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:10:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:10:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:10:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:10:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:10:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:10:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:10:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:10:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:10:40 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:10:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:10:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:10:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:10:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:10:40 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:10:41 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:10:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:10:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:10:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:10:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:10:41 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:10:42 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:10:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:10:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:10:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:10:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:10:42 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:10:43 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:10:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:10:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:10:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:10:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:10:43 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:10:44 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:10:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:10:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:10:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:10:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:10:44 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:10:45 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:10:45 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:10:46 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:10:46 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:10:47 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:10:47 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:10:47 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:10:48 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:10:48 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:10:49 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 07:10:49 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 07:10:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:10:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:10:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:10:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:10:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:10:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:10:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:10:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:10:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:10:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:10:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:10:50 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:10:50 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2302 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:10:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:10:50 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2302 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:10:50 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2302 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:10:50 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2302 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:10:50 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2302 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:10:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:10:55 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:10:55 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:10:55 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:10:55 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:10:55 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:10:55 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:10:55 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:10:55 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:10:55 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:10:55 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:10:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:10:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:10:55 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:11:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:11:00 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:11:00 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:11:00 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:11:00 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:11:00 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:11:00 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:11:00 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:11:00 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:11:00 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:11:00 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:00 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:11:00 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:11:00 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:11:00 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:11:00 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:11:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:11:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:11:00 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:11:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:11:01 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:11:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:11:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:11:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:11:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:11:01 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:11:02 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:11:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:11:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:11:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:11:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:11:02 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:11:03 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:11:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:11:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:11:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:11:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:11:03 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:11:03 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:11:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:11:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:11:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:11:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:11:04 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:11:04 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:11:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:11:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:11:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:11:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:11:05 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:11:05 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:11:06 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:11:06 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:11:07 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:11:07 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:11:08 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:11:08 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:11:09 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:11:09 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:11:10 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 07:11:10 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 07:11:10 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 07:11:11 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 07:11:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:11:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:11:11 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:11:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:11:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:11:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:11:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:11:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:11:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:11:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:11:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:11:11 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:11:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:11:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:11:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:11:16 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:11:16 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:11:16 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:11:16 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:11:16 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:11:16 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:11:16 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:11:16 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:11:16 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:11:16 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:11:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:11:16 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:11:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:11:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:11:21 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:11:21 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:11:21 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:11:21 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:11:21 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:11:21 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:11:21 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:11:21 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:11:21 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:11:21 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:21 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:11:22 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:11:22 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:11:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:11:22 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:11:22 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:11:22 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:11:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:11:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:11:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:11:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:11:23 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:11:23 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:11:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:11:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:11:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:11:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:11:24 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:11:24 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:11:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:11:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:11:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:11:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:11:25 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:11:25 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:11:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:11:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:11:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:11:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:11:26 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:11:26 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:11:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:11:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:11:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:11:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:11:27 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:11:27 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:11:27 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:11:28 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:11:28 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:11:29 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:11:29 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:11:30 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:11:30 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:11:31 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:11:31 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 07:11:32 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 07:11:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:11:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:11:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:11:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:11:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:11:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:11:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:11:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:11:32 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:11:32 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2292 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:11:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:11:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:11:32 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2292 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:11:32 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2292 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:11:32 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2292 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:11:32 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2292 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:11:32 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2292 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:11:32 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2293 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:11:32 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2293 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:11:32 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2293 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:11:32 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2293 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:11:32 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2293 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:11:32 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2293 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:11:32 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2293 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:11:32 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=2293 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:11:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:11:37 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:11:37 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:11:37 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:11:37 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:11:37 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:11:37 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:11:37 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:11:37 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:11:37 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:11:37 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:11:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:11:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:11:37 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:11:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:11:42 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:11:42 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:11:42 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:11:42 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:11:42 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:11:42 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:11:42 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:11:42 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:11:42 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:11:42 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:11:42 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:11:42 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:11:43 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:11:43 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:11:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:11:43 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:11:43 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:11:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:11:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:11:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:11:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:11:43 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:11:44 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:11:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:11:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:11:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:11:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:11:44 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:11:45 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:11:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:11:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:11:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:11:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:11:45 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:11:46 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:11:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:11:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:11:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:11:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:11:46 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:11:47 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:11:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:11:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:11:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:11:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:11:47 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:11:48 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:11:48 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:11:49 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:11:49 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:11:50 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:11:50 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:11:50 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:11:51 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:11:51 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:11:52 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 07:11:52 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 07:11:53 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 07:11:53 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 07:11:54 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 07:11:54 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 07:11:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:11:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:11:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:11:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:11:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:11:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:11:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:11:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:11:55 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:11:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:11:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:12:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:12:00 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:12:00 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:12:00 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:12:00 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:12:00 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:12:00 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:12:00 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:12:00 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:12:00 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:12:00 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:00 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:12:00 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:12:00 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:12:00 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:12:00 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:12:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:12:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:12:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:12:01 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:12:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:12:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:12:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:12:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:12:01 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:12:01 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:12:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:12:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:12:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:12:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:12:02 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:12:02 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:12:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:12:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:12:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:12:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:12:03 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:12:03 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:12:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:12:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:12:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:12:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:12:04 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:12:04 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:12:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:12:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:12:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:12:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:12:05 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:12:05 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:12:06 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:12:06 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:12:07 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:12:07 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:12:08 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:12:08 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:12:08 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:12:09 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:12:09 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 07:12:10 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 07:12:10 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 07:12:11 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 07:12:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:12:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:12:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:12:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:12:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:12:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:12:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:12:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:12:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:12:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:12:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:12:11 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:12:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:12:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:12:16 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:12:16 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:12:16 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:12:16 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:12:16 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:12:16 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:12:16 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:12:16 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:12:16 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:12:16 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:16 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:12:17 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:12:17 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:12:17 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:12:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:12:17 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:12:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:12:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:12:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:12:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:12:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:12:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:12:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:12:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:12:17 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:12:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:12:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:12:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:12:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:12:18 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:12:18 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:12:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:12:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:12:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:12:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:12:19 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:12:19 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:12:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:12:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:12:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:12:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:12:19 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:12:20 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:12:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:12:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:12:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:12:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:12:20 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:12:21 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:12:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:12:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:12:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:12:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:12:21 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:12:22 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:12:22 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:12:23 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:12:23 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:12:24 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:12:24 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:12:25 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:12:25 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:12:26 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:12:26 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 07:12:27 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 07:12:27 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 07:12:27 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 07:12:28 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 07:12:28 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 07:12:29 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 07:12:29 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 07:12:30 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 07:12:30 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 07:12:31 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 07:12:31 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 07:12:32 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 07:12:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:12:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:12:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:12:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:12:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:12:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:12:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:12:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:12:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:12:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:12:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:12:32 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:12:32 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3385 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:12:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:12:32 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3385 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:12:32 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3385 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:12:32 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3385 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:12:32 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3385 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:12:32 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3385 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:12:32 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3385 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:12:32 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3385 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:12:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:12:37 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:12:37 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:12:37 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:12:37 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:12:37 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:12:37 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:12:37 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:12:37 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:12:37 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:12:37 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:37 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:12:37 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:12:37 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:12:37 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:12:37 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:12:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:12:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:12:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:12:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:12:37 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:12:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:12:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:12:42 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:12:42 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:12:42 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:12:42 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:12:42 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:12:42 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:12:42 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:12:42 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:12:42 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:12:42 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:42 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:12:43 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:12:43 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:12:43 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:12:43 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:12:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:12:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:12:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:12:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:12:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:12:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:12:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:12:43 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:12:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:12:43 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:12:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:12:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:12:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:12:43 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:12:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:12:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:12:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:12:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:12:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:12:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:12:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:12:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:12:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:12:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:12:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:12:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:12:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:12:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:12:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:12:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:12:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:12:44 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:12:44 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 07:12:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:12:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:12:44 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:12:44 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:12:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:12:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:12:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:12:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:12:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:12:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:12:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:12:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:12:45 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:12:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:12:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:12:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:12:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:12:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:12:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:12:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:12:45 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:12:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:12:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:12:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:12:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:12:50 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:12:50 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:12:50 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:12:50 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:12:50 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:12:50 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:12:50 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:12:50 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:12:50 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:12:50 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:12:50 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:12:50 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:12:50 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:12:50 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:12:50 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:12:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:12:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:12:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:12:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:12:51 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:12:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:12:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:12:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:12:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:12:51 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:12:52 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:12:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:12:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:12:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:12:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:12:52 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:12:52 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:12:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:12:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:12:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:12:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:12:53 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:12:53 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:12:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:12:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:12:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:12:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:12:54 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:12:54 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:12:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:12:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:12:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:12:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:12:55 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:12:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:12:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:12:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:12:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:12:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:12:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:12:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:12:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:12:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:12:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:12:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:12:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:12:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:12:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:12:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:12:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:12:55 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:12:55 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 07:12:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:12:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:12:55 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:12:56 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:12:56 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:12:57 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:12:57 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:12:58 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:12:58 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:12:59 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:12:59 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:13:00 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 07:13:00 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 07:13:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:13:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:13:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:13:00 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:13:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:13:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:13:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:13:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:13:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:13:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:13:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:13:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:13:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:13:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:13:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:13:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:13:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:13:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:00 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 07:13:01 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 07:13:01 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 07:13:02 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 07:13:02 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 07:13:03 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 07:13:03 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 07:13:04 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 07:13:04 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 07:13:05 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 07:13:05 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 07:13:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:13:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:13:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:13:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:13:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:13:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:13:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:13:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:13:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:13:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:13:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:13:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:13:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:13:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:13:05 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:13:05 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 07:13:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:06 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 07:13:06 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 07:13:07 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 07:13:07 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 07:13:07 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 07:13:08 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 07:13:08 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 07:13:09 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 07:13:09 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 07:13:10 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 07:13:10 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 07:13:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:13:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:13:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:13:10 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:13:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:13:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:13:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:13:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:13:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:13:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:13:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:13:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:13:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:13:10 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:13:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:13:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:13:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:13:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:13:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:13:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:13:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:13:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:13:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:13:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:13:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:13:15 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:13:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:13:15 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:13:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:13:16 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:13:16 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:13:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:13:16 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:13:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:13:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:13:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:13:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:13:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:13:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:13:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:13:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:13:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:13:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:13:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:13:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:13:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:13:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:16 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:13:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:13:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:13:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:13:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:13:17 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:13:17 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:13:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:13:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:13:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:13:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:13:18 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:13:18 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:13:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:13:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:13:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:13:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:13:19 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:13:19 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:13:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:13:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:13:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:13:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:13:20 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:13:20 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:13:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:13:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:13:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:13:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:13:21 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:13:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:13:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:13:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:13:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:13:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:13:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:13:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:13:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:13:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:13:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:13:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:13:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:13:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:13:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:13:21 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:13:21 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 07:13:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:21 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:13:22 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:13:22 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:13:23 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:13:23 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:13:23 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:13:24 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:13:24 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:13:25 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:13:25 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 07:13:26 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 07:13:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:13:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:13:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:13:26 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:13:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:13:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:13:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:13:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:13:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:13:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:13:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:13:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:13:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:13:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:13:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:13:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:13:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:13:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:26 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 07:13:27 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 07:13:27 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 07:13:28 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 07:13:28 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 07:13:29 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 07:13:29 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 07:13:30 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 07:13:30 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 07:13:30 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 07:13:31 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 07:13:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:13:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:13:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:13:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:13:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:13:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:13:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:13:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:13:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:13:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:13:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:13:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:13:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:13:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:13:31 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:13:31 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 07:13:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:31 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 07:13:32 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 07:13:32 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 07:13:33 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 07:13:33 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 07:13:34 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 07:13:34 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 07:13:35 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 07:13:35 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 07:13:36 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 07:13:36 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 07:13:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:13:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:13:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:13:36 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:13:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:13:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:13:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:13:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:13:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:13:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:13:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:13:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:13:36 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:13:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:13:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:13:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:13:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:13:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:13:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:13:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:13:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:13:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:13:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:13:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:13:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:13:41 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:13:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:13:42 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:13:42 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:13:42 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:13:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:13:42 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:13:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:13:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:13:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:13:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:13:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:13:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:13:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:13:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:13:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:13:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:42 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:13:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:13:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:13:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:13:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:13:43 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:13:43 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:13:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:13:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:13:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:13:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:13:44 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:13:44 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:13:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:13:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:13:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:13:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:13:45 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:13:45 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:13:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:13:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:13:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:13:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:13:46 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:13:46 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:13:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:13:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:13:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:13:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:13:46 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:13:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:13:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:13:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:13:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:13:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:13:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:13:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:13:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:13:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:13:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:13:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:13:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:13:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:13:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:13:47 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:13:47 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 07:13:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:47 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:13:47 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:13:48 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:13:48 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:13:49 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:13:49 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:13:50 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:13:50 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:13:51 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:13:51 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 07:13:52 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 07:13:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:13:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:13:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:13:52 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:13:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:13:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:13:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:13:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:13:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:13:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:13:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:13:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:13:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:13:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:13:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:13:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:13:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:13:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:52 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 07:13:53 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 07:13:53 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 07:13:53 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 07:13:54 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 07:13:54 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 07:13:55 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 07:13:55 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 07:13:56 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 07:13:56 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 07:13:57 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 07:13:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:13:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:13:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:13:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:13:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:13:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:13:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:13:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:13:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:13:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:13:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:13:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:13:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:13:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:13:57 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:13:57 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 07:13:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:13:57 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 07:13:58 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 07:13:58 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 07:13:59 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 07:13:59 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 07:14:00 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 07:14:00 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 07:14:01 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 07:14:01 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 07:14:01 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 07:14:02 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 07:14:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:14:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:14:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:14:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:14:02 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:14:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:14:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:14:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:14:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:14:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:14:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:14:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:14:02 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:14:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:14:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:14:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:14:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:14:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:14:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:14:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:14:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:14:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:14:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:14:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:14:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:14:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:14:07 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:14:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:14:07 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:14:08 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:14:08 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:14:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:14:08 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:14:08 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:14:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:14:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:14:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:14:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:14:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:14:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:14:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:14:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:14:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:14:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:14:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:14:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:14:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:14:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:14:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:14:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:14:08 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:14:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:14:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:14:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:14:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:14:09 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:14:09 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:14:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:14:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:14:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:14:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:14:09 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:14:10 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:14:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:14:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:14:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:14:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:14:10 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:14:11 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:14:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:14:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:14:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:14:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:14:11 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:14:12 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:14:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:14:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:14:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:14:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:14:12 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:14:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:14:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:14:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:14:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:14:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:14:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:14:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:14:13 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:14:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:14:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:14:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:14:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:14:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:14:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:14:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:14:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:14:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:14:13 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:14:13 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 07:14:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:14:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:14:13 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:14:14 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:14:14 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:14:15 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:14:15 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:14:16 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:14:16 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:14:16 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:14:17 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 07:14:17 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 07:14:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:14:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:14:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:14:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:14:18 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:14:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:14:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:14:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:14:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:14:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:14:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:14:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:14:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:14:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:14:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:14:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:14:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:14:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:14:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:14:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:14:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:14:18 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 07:14:18 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 07:14:19 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 07:14:19 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 07:14:20 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 07:14:20 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 07:14:21 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 07:14:21 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 07:14:22 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 07:14:22 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 07:14:23 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 07:14:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:14:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:14:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:14:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:14:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:14:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:14:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:14:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:14:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:14:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:14:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:14:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:14:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:14:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:14:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:14:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:14:23 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:14:23 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 07:14:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:14:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:14:23 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 07:14:24 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 07:14:24 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 07:14:24 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 07:14:25 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 07:14:25 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 07:14:26 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 07:14:26 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 07:14:27 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 07:14:27 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 07:14:28 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 07:14:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:14:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:14:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:14:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:14:28 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:14:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:14:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:14:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:14:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:14:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:14:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:14:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:14:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:14:28 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:14:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4528 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:14:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:14:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:14:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4528 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:14:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4528 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:14:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4528 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:14:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4528 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:14:28 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=4528 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:14:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:14:33 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:14:33 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:14:33 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:14:33 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:14:33 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:14:33 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:14:33 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:14:33 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:14:33 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:14:33 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:14:33 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:14:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:14:33 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:14:33 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:14:33 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:14:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:14:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:14:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:14:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:14:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:14:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:14:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:14:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:14:34 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:14:34 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:14:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:14:34 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:14:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:14:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:14:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:14:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:14:34 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:14:35 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:14:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:14:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:14:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:14:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:14:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:14:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:14:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:14:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:14:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:14:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:14:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:14:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:14:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:14:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:14:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:14:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:14:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:14:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:14:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:14:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:14:35 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:14:35 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 07:14:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:14:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:14:35 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:14:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:14:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:14:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:14:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:14:36 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:14:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:14:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:14:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:14:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:14:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:14:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:14:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:14:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:14:36 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:14:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:14:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:14:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:14:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:14:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:14:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:14:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:14:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:14:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:14:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:14:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:14:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:14:41 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:14:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:14:41 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:14:41 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:14:41 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:14:41 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:14:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:14:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:14:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:14:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:14:42 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:14:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:14:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:14:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:14:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:14:42 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:14:43 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:14:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:14:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:14:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:14:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:14:43 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:14:43 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:14:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:14:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:14:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:14:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:14:44 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:14:44 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:14:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:14:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:14:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:14:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:14:45 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:14:45 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:14:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:14:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:14:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:14:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:14:46 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:14:46 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:14:47 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:14:47 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:14:48 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:14:48 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:14:49 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:14:49 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:14:50 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:14:50 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:14:51 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 07:14:51 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 07:14:51 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 07:14:52 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 07:14:52 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 07:14:53 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 07:14:53 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 07:14:54 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 07:14:54 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 07:14:55 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 07:14:55 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 07:14:56 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 07:14:56 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 07:14:57 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 07:14:57 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 07:14:58 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 07:14:58 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 07:14:59 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 07:14:59 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 07:14:59 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 07:15:00 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 07:15:00 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 07:15:01 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 07:15:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:15:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:15:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:15:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:15:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:15:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:15:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:15:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:15:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:15:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:15:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:15:01 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 07:15:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:15:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:15:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:15:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:15:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:15:01 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:15:01 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 07:15:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:15:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:15:02 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 07:15:02 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 07:15:03 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 07:15:03 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 07:15:04 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 07:15:04 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 07:15:05 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 07:15:05 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 07:15:06 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 07:15:06 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 07:15:06 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 07:15:07 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 07:15:07 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 07:15:08 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 07:15:08 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 07:15:09 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 07:15:09 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 07:15:10 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-10-30 07:15:10 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-10-30 07:15:11 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-10-30 07:15:11 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-10-30 07:15:12 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-10-30 07:15:12 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-10-30 07:15:13 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-10-30 07:15:13 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-10-30 07:15:14 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-10-30 07:15:14 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-10-30 07:15:14 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-10-30 07:15:15 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-10-30 07:15:15 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-10-30 07:15:16 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-10-30 07:15:16 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-10-30 07:15:17 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-10-30 07:15:17 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-10-30 07:15:18 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-10-30 07:15:18 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-10-30 07:15:19 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-10-30 07:15:19 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-10-30 07:15:20 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-10-30 07:15:20 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-10-30 07:15:21 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-10-30 07:15:21 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-10-30 07:15:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:15:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:15:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:15:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:15:21 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:15:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:15:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:15:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:15:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:15:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:15:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:15:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:15:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:15:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:15:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:15:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:15:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:15:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:15:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:15:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:15:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:15:21 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-10-30 07:15:22 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-10-30 07:15:22 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-10-30 07:15:23 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-10-30 07:15:23 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-10-30 07:15:24 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2024-10-30 07:15:24 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2024-10-30 07:15:25 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2024-10-30 07:15:25 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2024-10-30 07:15:26 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2024-10-30 07:15:26 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2024-10-30 07:15:27 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2024-10-30 07:15:27 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2024-10-30 07:15:28 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2024-10-30 07:15:28 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2024-10-30 07:15:29 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2024-10-30 07:15:29 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2024-10-30 07:15:29 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2024-10-30 07:15:30 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2024-10-30 07:15:30 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2024-10-30 07:15:31 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2024-10-30 07:15:31 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2024-10-30 07:15:32 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2024-10-30 07:15:32 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2024-10-30 07:15:33 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2024-10-30 07:15:33 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2024-10-30 07:15:34 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2024-10-30 07:15:34 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2024-10-30 07:15:35 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2024-10-30 07:15:35 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2024-10-30 07:15:36 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2024-10-30 07:15:36 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2024-10-30 07:15:36 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2024-10-30 07:15:37 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2024-10-30 07:15:37 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2024-10-30 07:15:38 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2024-10-30 07:15:38 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2024-10-30 07:15:39 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2024-10-30 07:15:39 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2024-10-30 07:15:40 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2024-10-30 07:15:40 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2024-10-30 07:15:41 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2024-10-30 07:15:41 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2024-10-30 07:15:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:15:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:15:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:15:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:15:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:15:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:15:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:15:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:15:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:15:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:15:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:15:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:15:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:15:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:15:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:15:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:15:41 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:15:41 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 07:15:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:15:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:15:42 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2024-10-30 07:15:42 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2024-10-30 07:15:43 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2024-10-30 07:15:43 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2024-10-30 07:15:44 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2024-10-30 07:15:44 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2024-10-30 07:15:44 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2024-10-30 07:15:45 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2024-10-30 07:15:45 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2024-10-30 07:15:46 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2024-10-30 07:15:46 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2024-10-30 07:15:47 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2024-10-30 07:15:47 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2024-10-30 07:15:48 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2024-10-30 07:15:48 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2024-10-30 07:15:49 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2024-10-30 07:15:49 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2024-10-30 07:15:50 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2024-10-30 07:15:50 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2024-10-30 07:15:51 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2024-10-30 07:15:51 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2024-10-30 07:15:51 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2024-10-30 07:15:52 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2024-10-30 07:15:52 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2024-10-30 07:15:53 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2024-10-30 07:15:53 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2024-10-30 07:15:54 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2024-10-30 07:15:54 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2024-10-30 07:15:55 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2024-10-30 07:15:55 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2024-10-30 07:15:56 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2024-10-30 07:15:56 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2024-10-30 07:15:57 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2024-10-30 07:15:57 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2024-10-30 07:15:58 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2024-10-30 07:15:58 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2024-10-30 07:15:59 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2024-10-30 07:15:59 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2024-10-30 07:15:59 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2024-10-30 07:16:00 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2024-10-30 07:16:00 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2024-10-30 07:16:01 [DEBUG] clck_gen.py:102 IND CLOCK 17442
2024-10-30 07:16:01 [DEBUG] clck_gen.py:102 IND CLOCK 17544
2024-10-30 07:16:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:02 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:16:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:16:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:16:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:16:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:16:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:16:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:16:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:16:02 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:16:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:16:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:16:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:16:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:16:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:16:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:16:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:16:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:16:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:16:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:16:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:16:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:16:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:16:07 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:16:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:16:07 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:16:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:16:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:16:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:16:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:16:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:16:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:16:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:16:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:16:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:16:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:16:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:16:12 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:16:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:16:12 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:16:12 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:12 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:16:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:16:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:16:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:16:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:16:13 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:13 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:13 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:16:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:16:13 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:13 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:16:13 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:16:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:16:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:16:14 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:16:14 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 07:16:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:16:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:16:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:16:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:16:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:14 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:16:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:16:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:16:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:16:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:16:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:16:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:16:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:16:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:16:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:14 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:16:14 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:16:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:16:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:16:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:16:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:16:15 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:16:15 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:16:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:16:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:16:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:16:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:16:16 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:16:16 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:16:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:16:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:16:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:16:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:16:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:16:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:16:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:16:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:16:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:16:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:16:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:16:17 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:16:17 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:16:18 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:16:18 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:16:19 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:16:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:16:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:16:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:16:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:16:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:16:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:16:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:16:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:19 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:16:20 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:16:20 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:16:21 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:16:21 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:16:21 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 07:16:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:16:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:16:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:16:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:16:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:16:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:16:22 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:16:22 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 07:16:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:22 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 07:16:22 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 07:16:23 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 07:16:23 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 07:16:24 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 07:16:24 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 07:16:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:24 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:16:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:16:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:16:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:16:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:16:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:16:24 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:16:24 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 07:16:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:25 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 07:16:25 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 07:16:26 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 07:16:26 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 07:16:27 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 07:16:27 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 07:16:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:27 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:16:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:16:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:16:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:16:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:16:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:16:27 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:16:27 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 07:16:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:28 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 07:16:28 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 07:16:28 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 07:16:29 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 07:16:29 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 07:16:30 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 07:16:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:30 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:16:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:16:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:16:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:16:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:16:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:16:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:16:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:16:30 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:16:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:16:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:16:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:16:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:16:35 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:16:35 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:16:35 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:16:35 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:16:35 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:16:35 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:16:35 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:16:35 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:16:35 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:16:35 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:16:35 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:16:36 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:16:36 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:16:36 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:16:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:36 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:16:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:16:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:16:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:16:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:16:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:16:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:16:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:16:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:16:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:36 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:16:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:16:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:16:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:16:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:16:36 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:16:37 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:16:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:16:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:16:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:16:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:16:37 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:16:38 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:16:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:16:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:16:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:16:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:16:38 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:16:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:16:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:16:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:16:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:16:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:16:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:16:39 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:16:39 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 07:16:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:39 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:16:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:16:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:16:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:16:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:16:39 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:16:40 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:16:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:16:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:16:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:16:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:16:40 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:16:41 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:16:41 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:16:42 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:16:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:42 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:16:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:16:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:16:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:16:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:16:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:16:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:16:42 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:16:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:16:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:16:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:43 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:16:43 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:16:43 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:16:44 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:16:44 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:16:45 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 07:16:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:16:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:16:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:16:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:16:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:16:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:16:45 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:16:45 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 07:16:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:45 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 07:16:46 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 07:16:46 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 07:16:47 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 07:16:47 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 07:16:48 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 07:16:48 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 07:16:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:49 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:16:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:16:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:16:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:16:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:16:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:16:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:16:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:16:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:16:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:16:49 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:16:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:16:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:16:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:16:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:16:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:16:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:16:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:16:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:16:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:16:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:16:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:16:54 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:16:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:16:54 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:16:54 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:16:54 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:16:54 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:16:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:16:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:16:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:16:55 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:16:55 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 07:16:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:55 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:16:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:16:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:16:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:16:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:16:55 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:16:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:55 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:16:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:16:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:16:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:16:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:16:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:16:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:16:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:16:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:16:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:55 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:16:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:16:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:16:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:16:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:16:56 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:16:56 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:16:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:16:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:16:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:16:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:16:57 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:16:57 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:16:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:16:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:16:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:16:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:16:58 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:16:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:16:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:16:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:16:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:16:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:16:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:16:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:16:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:16:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:16:58 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:16:58 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 07:16:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:16:58 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:16:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:16:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:16:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:16:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:16:59 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:16:59 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:17:00 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:17:00 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:17:01 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:17:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:17:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:17:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:17:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:17:01 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:17:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:17:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:17:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:17:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:17:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:17:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:17:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:17:01 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:17:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:17:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:17:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:17:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:17:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:17:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:17:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:17:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:17:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:17:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:17:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:17:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:17:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:17:06 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:17:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:17:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:17:06 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:17:07 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:17:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:17:07 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:17:07 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:17:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:17:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:17:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:17:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:17:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:17:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:17:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:17:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:17:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:17:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:17:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:17:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:17:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:17:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:17:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:17:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:17:07 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:17:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:17:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:17:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:17:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:17:07 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:17:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:17:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:17:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:17:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:17:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:17:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:17:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:17:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:17:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:17:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:17:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:17:08 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:17:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:17:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:17:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:17:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:17:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:17:08 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:17:08 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 07:17:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:17:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:17:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:17:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:17:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:17:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:17:08 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:17:09 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:17:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:17:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:17:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:17:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:17:09 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:17:10 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:17:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:17:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:17:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:17:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:17:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:17:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:17:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:17:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:17:10 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:17:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:17:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:17:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:17:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:17:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:17:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:17:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:17:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:17:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:17:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:17:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:17:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:17:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:17:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:17:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:17:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:17:10 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:17:11 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:17:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:17:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:17:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:17:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:17:11 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:17:12 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:17:12 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:17:13 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:17:13 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:17:13 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:17:14 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:17:14 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:17:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:17:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:17:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:17:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:17:15 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:17:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:17:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:17:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:17:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:17:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:17:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:17:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:17:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:17:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:17:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:17:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:17:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:17:15 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:17:15 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 07:17:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:17:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:17:15 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:17:16 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 07:17:16 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 07:17:17 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 07:17:17 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 07:17:18 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 07:17:18 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 07:17:19 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 07:17:19 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 07:17:20 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 07:17:20 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 07:17:21 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 07:17:21 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 07:17:21 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 07:17:22 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 07:17:22 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 07:17:23 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 07:17:23 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 07:17:24 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 07:17:24 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 07:17:25 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 07:17:25 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 07:17:26 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 07:17:26 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 07:17:27 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 07:17:27 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 07:17:28 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 07:17:28 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 07:17:28 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 07:17:29 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 07:17:29 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 07:17:30 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 07:17:30 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 07:17:31 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 07:17:31 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 07:17:32 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 07:17:32 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 07:17:33 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 07:17:33 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 07:17:34 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 07:17:34 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 07:17:35 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 07:17:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:17:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:17:35 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:17:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:17:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:17:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:17:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:17:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:17:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:17:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:17:35 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:17:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:17:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:17:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:17:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:17:40 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:17:40 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:17:40 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:17:40 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:17:40 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:17:40 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:17:40 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:17:40 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:17:40 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:17:40 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:17:40 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:17:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:17:40 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:17:40 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:17:40 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:17:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:17:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:17:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:17:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:17:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:17:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:17:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:17:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:17:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:17:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:17:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:17:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:17:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:17:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:17:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:17:41 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:17:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:17:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:17:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:17:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:17:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:17:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:17:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:17:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:17:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:17:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:17:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:17:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:17:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:17:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:17:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:17:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:17:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:17:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:17:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:17:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:17:41 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:17:41 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 07:17:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:17:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:17:41 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:17:42 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:17:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:17:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:17:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:17:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:17:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:17:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:17:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:17:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:17:42 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:17:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:17:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:17:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:17:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:17:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:17:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:17:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:17:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:17:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:17:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:17:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:17:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:17:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:17:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:17:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:17:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:17:42 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:17:43 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:17:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:17:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:17:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:17:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:17:43 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:17:44 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:17:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:17:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:17:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:17:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:17:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:17:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:17:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:17:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:17:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:17:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:17:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:17:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:17:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:17:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:17:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:17:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:17:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:17:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:17:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:17:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:17:44 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:17:44 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 07:17:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:17:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:17:44 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:17:45 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:17:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:17:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:17:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:17:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:17:45 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:17:46 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:17:46 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:17:47 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:17:47 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:17:47 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:17:48 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:17:48 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:17:49 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:17:49 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:17:50 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 07:17:50 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 07:17:51 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 07:17:51 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 07:17:52 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 07:17:52 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 07:17:53 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 07:17:53 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 07:17:54 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 07:17:54 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 07:17:55 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 07:17:55 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 07:17:55 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 07:17:56 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 07:17:56 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 07:17:57 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 07:17:57 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 07:17:58 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 07:17:58 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 07:17:59 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 07:17:59 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 07:18:00 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 07:18:00 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 07:18:01 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 07:18:01 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 07:18:02 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 07:18:02 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 07:18:02 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 07:18:03 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 07:18:03 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 07:18:04 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 07:18:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:18:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:18:04 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:18:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:18:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:18:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:18:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:18:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:18:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:18:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:18:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:18:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:18:04 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:18:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:18:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:18:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:18:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:18:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:18:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:18:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:18:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:18:09 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:18:09 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:18:09 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:18:09 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:18:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:18:09 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:18:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:18:10 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:18:10 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:18:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:18:10 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:18:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:18:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:18:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:18:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:18:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:18:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:18:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:18:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:18:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:18:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:18:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:18:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:18:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:18:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:18:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:18:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:18:10 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:18:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:18:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:18:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:18:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:18:11 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:18:11 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:18:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:18:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:18:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:18:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:18:12 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:18:12 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:18:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:18:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:18:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:18:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:18:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:18:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:18:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:18:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:18:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:18:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:18:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:18:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:18:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:18:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:18:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:18:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:18:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:18:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:18:12 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:18:12 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 07:18:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:18:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:18:12 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:18:13 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:18:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:18:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:18:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:18:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:18:13 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:18:14 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:18:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:18:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:18:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:18:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:18:14 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:18:15 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:18:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:18:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:18:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:18:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:18:15 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:18:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:18:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:18:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:18:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:18:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:18:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:18:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:18:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:18:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:18:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:18:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:18:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:18:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:18:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:18:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:18:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:18:15 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:18:16 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:18:16 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:18:17 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:18:17 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:18:18 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:18:18 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:18:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:18:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:18:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:18:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:18:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:18:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:18:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:18:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:18:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:18:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:18:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:18:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:18:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:18:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:18:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:18:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:18:18 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:18:18 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 07:18:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:18:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:18:19 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:18:19 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 07:18:19 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 07:18:20 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 07:18:20 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 07:18:21 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 07:18:21 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 07:18:22 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 07:18:22 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 07:18:23 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 07:18:23 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 07:18:24 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 07:18:24 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 07:18:25 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 07:18:25 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 07:18:26 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 07:18:26 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 07:18:27 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 07:18:27 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 07:18:27 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 07:18:28 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 07:18:28 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 07:18:29 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 07:18:29 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 07:18:30 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 07:18:30 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 07:18:31 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 07:18:31 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 07:18:32 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 07:18:32 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 07:18:33 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 07:18:33 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 07:18:34 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 07:18:34 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 07:18:34 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 07:18:35 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 07:18:35 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 07:18:36 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 07:18:36 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 07:18:37 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 07:18:37 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 07:18:38 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 07:18:38 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-10-30 07:18:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:18:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:18:38 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:18:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:18:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:18:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:18:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:18:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:18:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:18:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:18:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:18:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:18:38 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:18:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:18:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:18:43 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:18:43 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:18:43 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:18:43 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:18:43 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:18:43 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:18:43 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:18:43 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:18:43 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:18:43 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:18:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:18:43 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:18:44 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:18:44 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:18:44 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:18:44 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:18:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:18:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:18:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:18:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:18:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:18:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:18:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:18:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:18:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:18:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:18:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:18:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:18:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:18:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:18:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:18:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:18:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:18:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:18:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:18:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:18:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:18:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:18:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:18:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:18:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:18:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:18:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:18:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:18:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:18:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:18:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:18:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:18:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:18:44 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:18:44 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 07:18:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:18:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:18:44 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:18:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:18:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:18:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:18:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:18:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:18:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:18:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:18:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:18:45 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:18:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:18:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:18:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:18:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:18:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:18:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:18:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:18:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:18:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:18:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:18:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:18:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:18:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:18:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:18:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:18:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:18:45 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:18:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:18:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:18:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:18:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:18:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:18:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:18:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:18:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:18:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:18:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:18:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:18:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:18:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:18:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:18:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:18:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:18:45 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:18:45 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 07:18:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:18:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:18:45 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:18:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:18:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:18:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:18:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:18:46 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:18:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:18:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:18:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:18:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:18:46 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:18:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:18:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:18:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:18:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:18:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:18:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:18:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:18:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:18:46 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:18:46 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=532 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:18:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:18:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:18:46 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=532 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:18:46 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=532 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:18:46 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=532 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:18:46 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=532 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:18:46 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=532 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:18:46 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=532 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:18:46 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=532 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:18:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:18:51 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:18:51 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:18:51 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:18:51 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:18:51 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:18:51 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:18:51 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:18:51 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:18:51 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:18:51 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:18:51 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:18:51 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:18:51 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:18:51 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:18:51 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:18:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:18:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:18:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:18:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:18:52 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:18:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:18:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:18:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:18:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:18:52 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:18:53 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:18:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:18:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:18:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:18:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:18:53 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:18:54 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:18:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:18:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:18:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:18:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:18:54 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:18:55 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:18:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:18:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:18:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:18:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:18:55 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:18:55 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:18:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:18:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:18:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:18:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:18:56 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:18:56 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:18:57 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:18:57 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:18:58 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:18:58 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:18:59 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:18:59 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:19:00 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:19:00 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:19:01 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 07:19:01 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 07:19:02 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 07:19:02 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 07:19:03 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 07:19:03 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 07:19:03 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 07:19:04 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 07:19:04 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 07:19:05 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 07:19:05 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 07:19:06 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 07:19:06 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 07:19:07 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 07:19:07 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 07:19:08 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 07:19:08 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 07:19:09 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 07:19:09 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 07:19:10 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 07:19:10 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 07:19:11 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 07:19:11 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 07:19:11 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 07:19:12 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 07:19:12 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 07:19:13 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 07:19:13 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 07:19:14 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 07:19:14 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 07:19:15 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 07:19:15 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 07:19:16 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 07:19:16 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 07:19:17 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 07:19:17 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 07:19:18 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 07:19:18 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 07:19:18 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 07:19:19 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 07:19:19 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 07:19:20 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-10-30 07:19:20 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-10-30 07:19:21 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-10-30 07:19:21 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-10-30 07:19:22 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-10-30 07:19:22 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-10-30 07:19:23 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-10-30 07:19:23 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-10-30 07:19:24 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-10-30 07:19:24 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-10-30 07:19:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:19:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:19:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:19:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:19:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:19:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:19:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:19:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:19:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:19:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:19:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:19:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:19:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:19:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:19:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:19:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:19:24 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:19:24 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 07:19:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:19:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:19:25 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-10-30 07:19:25 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-10-30 07:19:26 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-10-30 07:19:26 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-10-30 07:19:26 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-10-30 07:19:27 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-10-30 07:19:27 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-10-30 07:19:28 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-10-30 07:19:28 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-10-30 07:19:29 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-10-30 07:19:29 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-10-30 07:19:30 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-10-30 07:19:30 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-10-30 07:19:31 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-10-30 07:19:31 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-10-30 07:19:32 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-10-30 07:19:32 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-10-30 07:19:33 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-10-30 07:19:33 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-10-30 07:19:33 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-10-30 07:19:34 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2024-10-30 07:19:34 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2024-10-30 07:19:35 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2024-10-30 07:19:35 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2024-10-30 07:19:36 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2024-10-30 07:19:36 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2024-10-30 07:19:37 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2024-10-30 07:19:37 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2024-10-30 07:19:38 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2024-10-30 07:19:38 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2024-10-30 07:19:39 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2024-10-30 07:19:39 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2024-10-30 07:19:40 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2024-10-30 07:19:40 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2024-10-30 07:19:41 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2024-10-30 07:19:41 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2024-10-30 07:19:41 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2024-10-30 07:19:42 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2024-10-30 07:19:42 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2024-10-30 07:19:43 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2024-10-30 07:19:43 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2024-10-30 07:19:44 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2024-10-30 07:19:44 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2024-10-30 07:19:45 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2024-10-30 07:19:45 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2024-10-30 07:19:46 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2024-10-30 07:19:46 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2024-10-30 07:19:47 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2024-10-30 07:19:47 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2024-10-30 07:19:48 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2024-10-30 07:19:48 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2024-10-30 07:19:48 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2024-10-30 07:19:49 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2024-10-30 07:19:49 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2024-10-30 07:19:50 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2024-10-30 07:19:50 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2024-10-30 07:19:51 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2024-10-30 07:19:51 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2024-10-30 07:19:52 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2024-10-30 07:19:52 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2024-10-30 07:19:53 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2024-10-30 07:19:53 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2024-10-30 07:19:54 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2024-10-30 07:19:54 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2024-10-30 07:19:55 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2024-10-30 07:19:55 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2024-10-30 07:19:56 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2024-10-30 07:19:56 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2024-10-30 07:19:56 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2024-10-30 07:19:57 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2024-10-30 07:19:57 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2024-10-30 07:19:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:19:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:19:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:19:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:19:58 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:19:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:19:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:19:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:19:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:19:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:19:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:19:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:19:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:19:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:19:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:19:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:19:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:19:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:19:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:19:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:19:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:19:58 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2024-10-30 07:19:58 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2024-10-30 07:19:59 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2024-10-30 07:19:59 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2024-10-30 07:20:00 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2024-10-30 07:20:00 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2024-10-30 07:20:01 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2024-10-30 07:20:01 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2024-10-30 07:20:02 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2024-10-30 07:20:02 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2024-10-30 07:20:03 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2024-10-30 07:20:03 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2024-10-30 07:20:03 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2024-10-30 07:20:04 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2024-10-30 07:20:04 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2024-10-30 07:20:05 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2024-10-30 07:20:05 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2024-10-30 07:20:06 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2024-10-30 07:20:06 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2024-10-30 07:20:07 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2024-10-30 07:20:07 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2024-10-30 07:20:08 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2024-10-30 07:20:08 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2024-10-30 07:20:09 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2024-10-30 07:20:09 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2024-10-30 07:20:10 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2024-10-30 07:20:10 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2024-10-30 07:20:11 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2024-10-30 07:20:11 [DEBUG] clck_gen.py:102 IND CLOCK 17442
2024-10-30 07:20:11 [DEBUG] clck_gen.py:102 IND CLOCK 17544
2024-10-30 07:20:12 [DEBUG] clck_gen.py:102 IND CLOCK 17646
2024-10-30 07:20:12 [DEBUG] clck_gen.py:102 IND CLOCK 17748
2024-10-30 07:20:13 [DEBUG] clck_gen.py:102 IND CLOCK 17850
2024-10-30 07:20:13 [DEBUG] clck_gen.py:102 IND CLOCK 17952
2024-10-30 07:20:14 [DEBUG] clck_gen.py:102 IND CLOCK 18054
2024-10-30 07:20:14 [DEBUG] clck_gen.py:102 IND CLOCK 18156
2024-10-30 07:20:15 [DEBUG] clck_gen.py:102 IND CLOCK 18258
2024-10-30 07:20:15 [DEBUG] clck_gen.py:102 IND CLOCK 18360
2024-10-30 07:20:16 [DEBUG] clck_gen.py:102 IND CLOCK 18462
2024-10-30 07:20:16 [DEBUG] clck_gen.py:102 IND CLOCK 18564
2024-10-30 07:20:17 [DEBUG] clck_gen.py:102 IND CLOCK 18666
2024-10-30 07:20:17 [DEBUG] clck_gen.py:102 IND CLOCK 18768
2024-10-30 07:20:18 [DEBUG] clck_gen.py:102 IND CLOCK 18870
2024-10-30 07:20:18 [DEBUG] clck_gen.py:102 IND CLOCK 18972
2024-10-30 07:20:19 [DEBUG] clck_gen.py:102 IND CLOCK 19074
2024-10-30 07:20:19 [DEBUG] clck_gen.py:102 IND CLOCK 19176
2024-10-30 07:20:19 [DEBUG] clck_gen.py:102 IND CLOCK 19278
2024-10-30 07:20:20 [DEBUG] clck_gen.py:102 IND CLOCK 19380
2024-10-30 07:20:20 [DEBUG] clck_gen.py:102 IND CLOCK 19482
2024-10-30 07:20:21 [DEBUG] clck_gen.py:102 IND CLOCK 19584
2024-10-30 07:20:21 [DEBUG] clck_gen.py:102 IND CLOCK 19686
2024-10-30 07:20:22 [DEBUG] clck_gen.py:102 IND CLOCK 19788
2024-10-30 07:20:22 [DEBUG] clck_gen.py:102 IND CLOCK 19890
2024-10-30 07:20:23 [DEBUG] clck_gen.py:102 IND CLOCK 19992
2024-10-30 07:20:23 [DEBUG] clck_gen.py:102 IND CLOCK 20094
2024-10-30 07:20:24 [DEBUG] clck_gen.py:102 IND CLOCK 20196
2024-10-30 07:20:24 [DEBUG] clck_gen.py:102 IND CLOCK 20298
2024-10-30 07:20:25 [DEBUG] clck_gen.py:102 IND CLOCK 20400
2024-10-30 07:20:25 [DEBUG] clck_gen.py:102 IND CLOCK 20502
2024-10-30 07:20:26 [DEBUG] clck_gen.py:102 IND CLOCK 20604
2024-10-30 07:20:26 [DEBUG] clck_gen.py:102 IND CLOCK 20706
2024-10-30 07:20:26 [DEBUG] clck_gen.py:102 IND CLOCK 20808
2024-10-30 07:20:27 [DEBUG] clck_gen.py:102 IND CLOCK 20910
2024-10-30 07:20:27 [DEBUG] clck_gen.py:102 IND CLOCK 21012
2024-10-30 07:20:28 [DEBUG] clck_gen.py:102 IND CLOCK 21114
2024-10-30 07:20:28 [DEBUG] clck_gen.py:102 IND CLOCK 21216
2024-10-30 07:20:29 [DEBUG] clck_gen.py:102 IND CLOCK 21318
2024-10-30 07:20:29 [DEBUG] clck_gen.py:102 IND CLOCK 21420
2024-10-30 07:20:30 [DEBUG] clck_gen.py:102 IND CLOCK 21522
2024-10-30 07:20:30 [DEBUG] clck_gen.py:102 IND CLOCK 21624
2024-10-30 07:20:31 [DEBUG] clck_gen.py:102 IND CLOCK 21726
2024-10-30 07:20:31 [DEBUG] clck_gen.py:102 IND CLOCK 21828
2024-10-30 07:20:32 [DEBUG] clck_gen.py:102 IND CLOCK 21930
2024-10-30 07:20:32 [DEBUG] clck_gen.py:102 IND CLOCK 22032
2024-10-30 07:20:33 [DEBUG] clck_gen.py:102 IND CLOCK 22134
2024-10-30 07:20:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:20:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:20:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:20:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:20:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:20:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:20:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:20:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:20:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:20:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:20:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:20:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:20:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:20:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:20:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:20:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:20:33 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:20:33 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 07:20:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:20:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:20:33 [DEBUG] clck_gen.py:102 IND CLOCK 22236
2024-10-30 07:20:34 [DEBUG] clck_gen.py:102 IND CLOCK 22338
2024-10-30 07:20:34 [DEBUG] clck_gen.py:102 IND CLOCK 22440
2024-10-30 07:20:34 [DEBUG] clck_gen.py:102 IND CLOCK 22542
2024-10-30 07:20:35 [DEBUG] clck_gen.py:102 IND CLOCK 22644
2024-10-30 07:20:35 [DEBUG] clck_gen.py:102 IND CLOCK 22746
2024-10-30 07:20:36 [DEBUG] clck_gen.py:102 IND CLOCK 22848
2024-10-30 07:20:36 [DEBUG] clck_gen.py:102 IND CLOCK 22950
2024-10-30 07:20:37 [DEBUG] clck_gen.py:102 IND CLOCK 23052
2024-10-30 07:20:37 [DEBUG] clck_gen.py:102 IND CLOCK 23154
2024-10-30 07:20:38 [DEBUG] clck_gen.py:102 IND CLOCK 23256
2024-10-30 07:20:38 [DEBUG] clck_gen.py:102 IND CLOCK 23358
2024-10-30 07:20:39 [DEBUG] clck_gen.py:102 IND CLOCK 23460
2024-10-30 07:20:39 [DEBUG] clck_gen.py:102 IND CLOCK 23562
2024-10-30 07:20:40 [DEBUG] clck_gen.py:102 IND CLOCK 23664
2024-10-30 07:20:40 [DEBUG] clck_gen.py:102 IND CLOCK 23766
2024-10-30 07:20:41 [DEBUG] clck_gen.py:102 IND CLOCK 23868
2024-10-30 07:20:41 [DEBUG] clck_gen.py:102 IND CLOCK 23970
2024-10-30 07:20:41 [DEBUG] clck_gen.py:102 IND CLOCK 24072
2024-10-30 07:20:42 [DEBUG] clck_gen.py:102 IND CLOCK 24174
2024-10-30 07:20:42 [DEBUG] clck_gen.py:102 IND CLOCK 24276
2024-10-30 07:20:43 [DEBUG] clck_gen.py:102 IND CLOCK 24378
2024-10-30 07:20:43 [DEBUG] clck_gen.py:102 IND CLOCK 24480
2024-10-30 07:20:44 [DEBUG] clck_gen.py:102 IND CLOCK 24582
2024-10-30 07:20:44 [DEBUG] clck_gen.py:102 IND CLOCK 24684
2024-10-30 07:20:45 [DEBUG] clck_gen.py:102 IND CLOCK 24786
2024-10-30 07:20:45 [DEBUG] clck_gen.py:102 IND CLOCK 24888
2024-10-30 07:20:46 [DEBUG] clck_gen.py:102 IND CLOCK 24990
2024-10-30 07:20:46 [DEBUG] clck_gen.py:102 IND CLOCK 25092
2024-10-30 07:20:47 [DEBUG] clck_gen.py:102 IND CLOCK 25194
2024-10-30 07:20:47 [DEBUG] clck_gen.py:102 IND CLOCK 25296
2024-10-30 07:20:48 [DEBUG] clck_gen.py:102 IND CLOCK 25398
2024-10-30 07:20:48 [DEBUG] clck_gen.py:102 IND CLOCK 25500
2024-10-30 07:20:49 [DEBUG] clck_gen.py:102 IND CLOCK 25602
2024-10-30 07:20:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:20:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:20:49 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:20:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:20:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:20:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:20:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:20:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:20:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:20:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:20:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:20:49 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:20:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=25677 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:20:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:20:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:20:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=25677 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:20:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=25677 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:20:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=25677 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:20:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=25677 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:20:49 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=25677 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:20:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:20:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:20:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:20:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:20:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:20:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:20:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:20:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:20:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:20:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:20:54 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:20:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:20:54 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:20:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:20:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:20:59 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:20:59 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:20:59 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:20:59 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:20:59 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:20:59 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:20:59 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:20:59 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:20:59 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:20:59 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:20:59 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:20:59 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:20:59 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:20:59 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:20:59 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:20:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:20:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:20:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:20:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:21:00 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:21:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:21:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:21:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:21:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:21:00 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:21:01 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:21:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:21:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:21:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:21:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:21:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:21:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:21:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:21:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:21:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:21:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:21:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:21:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:21:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:21:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:21:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:21:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:21:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:21:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:21:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:21:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:21:01 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:21:01 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 07:21:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:21:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:21:01 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:21:02 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:21:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:21:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:21:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:21:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:21:02 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:21:03 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:21:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:21:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:21:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:21:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:21:03 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:21:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:21:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:21:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:21:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:21:03 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:21:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:21:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:21:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:21:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:21:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:21:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:21:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:21:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:21:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:21:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:21:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:21:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:21:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:21:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:21:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:21:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:21:04 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:21:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:21:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:21:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:21:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:21:04 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:21:05 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:21:05 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:21:06 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:21:06 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:21:06 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:21:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:21:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:21:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:21:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:21:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:21:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:21:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:21:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:21:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:21:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:21:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:21:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:21:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:21:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:21:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:21:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:21:07 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:21:07 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 07:21:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:21:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:21:07 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:21:07 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:21:08 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:21:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:21:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:21:08 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:21:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:21:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:21:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:21:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:21:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:21:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:21:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:21:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:21:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:21:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:21:08 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:21:08 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1959 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:21:08 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=1959 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:21:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:21:13 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:21:13 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:21:13 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:21:13 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:21:13 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:21:13 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:21:13 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:21:13 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:21:13 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:21:13 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:21:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:21:13 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:21:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:21:14 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:21:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:21:14 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:21:14 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:21:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:21:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:21:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:21:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:21:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:21:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:21:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:21:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:21:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:21:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:21:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:21:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:21:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:21:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:21:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:21:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:21:14 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:21:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:21:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:21:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:21:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:21:14 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:21:15 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:21:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:21:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:21:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:21:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:21:15 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:21:16 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:21:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:21:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:21:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:21:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:21:16 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:21:17 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:21:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:21:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:21:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:21:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:21:17 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:21:18 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:21:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:21:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:21:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:21:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:21:18 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:21:19 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:21:19 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:21:20 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:21:20 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:21:20 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:21:21 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:21:21 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:21:22 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:21:22 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:21:23 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 07:21:23 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 07:21:24 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 07:21:24 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 07:21:25 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 07:21:25 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 07:21:26 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 07:21:26 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 07:21:27 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 07:21:27 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 07:21:28 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 07:21:28 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 07:21:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:21:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:21:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:21:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:21:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:21:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:21:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:21:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:21:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:21:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:21:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:21:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:21:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:21:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:21:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:21:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:21:28 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:21:28 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 07:21:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:21:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:21:28 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 07:21:29 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 07:21:29 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 07:21:30 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 07:21:30 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 07:21:31 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 07:21:31 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 07:21:32 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 07:21:32 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 07:21:33 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 07:21:33 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 07:21:34 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 07:21:34 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 07:21:35 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 07:21:35 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 07:21:35 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 07:21:36 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 07:21:36 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 07:21:37 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 07:21:37 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 07:21:38 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 07:21:38 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 07:21:39 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 07:21:39 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 07:21:40 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 07:21:40 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 07:21:41 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 07:21:41 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 07:21:42 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 07:21:42 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-10-30 07:21:43 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-10-30 07:21:43 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-10-30 07:21:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:21:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:21:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:21:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:21:43 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:21:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:21:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:21:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:21:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:21:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:21:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:21:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:21:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:21:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:21:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:21:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:21:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:21:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:21:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:21:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:21:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:21:43 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-10-30 07:21:44 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-10-30 07:21:44 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-10-30 07:21:45 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-10-30 07:21:45 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-10-30 07:21:46 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-10-30 07:21:46 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-10-30 07:21:47 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-10-30 07:21:47 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-10-30 07:21:48 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-10-30 07:21:48 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-10-30 07:21:49 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-10-30 07:21:49 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-10-30 07:21:50 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-10-30 07:21:50 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-10-30 07:21:50 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-10-30 07:21:51 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-10-30 07:21:51 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-10-30 07:21:52 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-10-30 07:21:52 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-10-30 07:21:53 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-10-30 07:21:53 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-10-30 07:21:54 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-10-30 07:21:54 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-10-30 07:21:55 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-10-30 07:21:55 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-10-30 07:21:56 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-10-30 07:21:56 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2024-10-30 07:21:57 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2024-10-30 07:21:57 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2024-10-30 07:21:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:21:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:21:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:21:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:21:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:21:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:21:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:21:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:21:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:21:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:21:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:21:58 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2024-10-30 07:21:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:21:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:21:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:21:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:21:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:21:58 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:21:58 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 07:21:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:21:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:21:58 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2024-10-30 07:21:58 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2024-10-30 07:21:59 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2024-10-30 07:21:59 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2024-10-30 07:22:00 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2024-10-30 07:22:00 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2024-10-30 07:22:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:22:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:22:01 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:22:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:22:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:22:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:22:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:22:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:22:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:22:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:22:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:22:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:22:01 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:22:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:22:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:22:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:22:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:22:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:22:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:22:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:22:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:22:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:22:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:22:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:22:06 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:22:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:22:06 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:22:06 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:22:06 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:22:06 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:22:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:22:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:22:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:22:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:22:07 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:22:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:22:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:22:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:22:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:22:07 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:22:08 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:22:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:22:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:22:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:22:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:22:08 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:22:09 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:22:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:22:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:22:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:22:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:22:09 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:22:10 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:22:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:22:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:22:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:22:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:22:10 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:22:10 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:22:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:22:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:22:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:22:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:22:11 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:22:11 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:22:12 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:22:12 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:22:13 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:22:13 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:22:14 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:22:14 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:22:15 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:22:15 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:22:16 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 07:22:16 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 07:22:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:22:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:22:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:22:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:22:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:22:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:22:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:22:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:22:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:22:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:22:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:22:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:22:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:22:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:22:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:22:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:22:16 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:22:16 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 07:22:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:22:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:22:17 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 07:22:17 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 07:22:18 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 07:22:18 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 07:22:18 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 07:22:19 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 07:22:19 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 07:22:20 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 07:22:20 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 07:22:21 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 07:22:21 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 07:22:22 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 07:22:22 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 07:22:23 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 07:22:23 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 07:22:24 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 07:22:24 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 07:22:25 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 07:22:25 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 07:22:25 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 07:22:26 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 07:22:26 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 07:22:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:22:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:22:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:22:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:22:27 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:22:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:22:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:22:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:22:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:22:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:22:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:22:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:22:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:22:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:22:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:22:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:22:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:22:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:22:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:22:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:22:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:22:27 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 07:22:27 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 07:22:28 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 07:22:28 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 07:22:29 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 07:22:29 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 07:22:30 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 07:22:30 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 07:22:31 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 07:22:31 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 07:22:32 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 07:22:32 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 07:22:33 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 07:22:33 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 07:22:33 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 07:22:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:22:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:22:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:22:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:22:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:22:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:22:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:22:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:22:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:22:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:22:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:22:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:22:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:22:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:22:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:22:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:22:34 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:22:34 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 07:22:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:22:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:22:34 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 07:22:34 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 07:22:35 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-10-30 07:22:35 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-10-30 07:22:36 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-10-30 07:22:36 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-10-30 07:22:37 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-10-30 07:22:37 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-10-30 07:22:38 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-10-30 07:22:38 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-10-30 07:22:39 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-10-30 07:22:39 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-10-30 07:22:40 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-10-30 07:22:40 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-10-30 07:22:40 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-10-30 07:22:41 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-10-30 07:22:41 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-10-30 07:22:42 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-10-30 07:22:42 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-10-30 07:22:43 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-10-30 07:22:43 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-10-30 07:22:44 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-10-30 07:22:44 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-10-30 07:22:45 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-10-30 07:22:45 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-10-30 07:22:46 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-10-30 07:22:46 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-10-30 07:22:47 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-10-30 07:22:47 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-10-30 07:22:48 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-10-30 07:22:48 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-10-30 07:22:48 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-10-30 07:22:49 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2024-10-30 07:22:49 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2024-10-30 07:22:50 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2024-10-30 07:22:50 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2024-10-30 07:22:51 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2024-10-30 07:22:51 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2024-10-30 07:22:52 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2024-10-30 07:22:52 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2024-10-30 07:22:53 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2024-10-30 07:22:53 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2024-10-30 07:22:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:22:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:22:54 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:22:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:22:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:22:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:22:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:22:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:22:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:22:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:22:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:22:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:22:54 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:22:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:22:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:22:59 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:22:59 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:22:59 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:22:59 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:22:59 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:22:59 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:22:59 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:22:59 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:22:59 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:22:59 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:22:59 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:22:59 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:22:59 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:22:59 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:22:59 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:22:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:22:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:22:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:22:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:22:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:22:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:22:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:22:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:23:00 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:23:00 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 07:23:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:00 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:23:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:23:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:23:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:23:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:23:00 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:23:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:23:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:23:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:23:00 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:23:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:23:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:23:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:23:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:23:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:23:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:23:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:23:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:23:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:23:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:23:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:23:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:23:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:23:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:00 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:23:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:23:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:23:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:23:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:23:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:23:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:23:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:23:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:23:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:23:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:23:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:23:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:23:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:23:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:23:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:23:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:23:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:23:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:23:01 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:23:01 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 07:23:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:01 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:23:01 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:23:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:23:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:23:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:23:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:23:02 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:23:02 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:23:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:23:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:23:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:23:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:23:03 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:23:03 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:23:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:23:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:23:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:23:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:23:04 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:23:04 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:23:05 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:23:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:23:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:23:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:23:05 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:23:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:23:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:23:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:23:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:23:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:23:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:23:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:23:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:23:05 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:23:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:23:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:23:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:23:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:23:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:23:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:23:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:23:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:23:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:23:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:23:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:23:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:23:10 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:23:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:23:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:23:11 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:23:11 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:23:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:23:11 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:23:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:23:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:23:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:23:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:23:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:23:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:23:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:23:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:23:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:23:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:23:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:23:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:23:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:23:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:11 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:23:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:23:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:23:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:23:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:23:11 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:23:12 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:23:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:23:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:23:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:23:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:23:12 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:23:13 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:23:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:23:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:23:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:23:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:23:13 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:23:14 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:23:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:23:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:23:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:23:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:23:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:23:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:23:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:23:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:23:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:23:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:23:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:23:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:23:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:23:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:23:14 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:23:14 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 07:23:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:23:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:23:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:23:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:23:14 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:23:15 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:23:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:23:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:23:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:23:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:23:15 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:23:16 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:23:16 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:23:17 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:23:17 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:23:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:23:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:23:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:23:17 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:23:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:23:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:23:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:23:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:23:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:23:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:23:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:23:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:23:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:23:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:23:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:23:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:23:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:23:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:17 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:23:18 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:23:18 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:23:19 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:23:19 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:23:20 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 07:23:20 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 07:23:21 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 07:23:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:23:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:23:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:23:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:23:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:23:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:23:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:23:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:23:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:23:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:23:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:23:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:23:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:23:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:23:21 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:23:21 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 07:23:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:21 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 07:23:22 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 07:23:22 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 07:23:23 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 07:23:23 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 07:23:24 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 07:23:24 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 07:23:25 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 07:23:25 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 07:23:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:23:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:23:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:23:25 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:23:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:23:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:23:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:23:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:23:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:23:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:23:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:23:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:23:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:23:25 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:23:25 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3285 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:23:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:23:25 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3285 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:23:25 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3285 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:23:25 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3285 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:23:25 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3285 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:23:25 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3285 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:23:25 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3286 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:23:25 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3286 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:23:25 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3286 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:23:25 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3286 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:23:25 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3286 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:23:25 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3286 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:23:25 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3286 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:23:25 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3286 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:23:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:23:30 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:23:30 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:23:30 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:23:30 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:23:30 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:23:30 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:23:30 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:23:30 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:23:30 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:23:30 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:23:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:23:30 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:23:31 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:23:31 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:23:31 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:23:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:23:31 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:23:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:23:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:23:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:23:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:23:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:23:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:23:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:23:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:23:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:23:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:23:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:23:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:23:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:23:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:23:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:23:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:23:31 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:23:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:23:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:23:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:23:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:23:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:23:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:23:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:23:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:23:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:23:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:23:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:23:31 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:23:31 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 07:23:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:23:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:23:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:23:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:23:32 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:23:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:23:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:23:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:23:32 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:23:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:23:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:23:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:23:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:23:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:23:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:23:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:23:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:23:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:23:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:23:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:23:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:23:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:23:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:32 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:23:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:23:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:23:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:23:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:23:32 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:23:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:23:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:23:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:23:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:23:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:23:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:23:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:23:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:23:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:23:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:23:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:23:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:23:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:23:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:23:33 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:23:33 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 07:23:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:33 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:23:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:23:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:23:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:23:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:23:33 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:23:34 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:23:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:23:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:23:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:23:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:23:34 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:23:35 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:23:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:23:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:23:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:23:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:23:35 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:23:36 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:23:36 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:23:37 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:23:37 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:23:38 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:23:38 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:23:39 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:23:39 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:23:40 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:23:40 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 07:23:40 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 07:23:41 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 07:23:41 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 07:23:42 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 07:23:42 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 07:23:43 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 07:23:43 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 07:23:44 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 07:23:44 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 07:23:45 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 07:23:45 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 07:23:46 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 07:23:46 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 07:23:47 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 07:23:47 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 07:23:47 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 07:23:48 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 07:23:48 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 07:23:49 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 07:23:49 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 07:23:50 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 07:23:50 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 07:23:51 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 07:23:51 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 07:23:52 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 07:23:52 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 07:23:53 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 07:23:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:23:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:23:53 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:23:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:23:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:23:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:23:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:23:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:23:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:23:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:23:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:23:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:23:53 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:23:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:23:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:23:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:23:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:23:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:23:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:23:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:23:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:23:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:23:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:23:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:23:58 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:23:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:23:58 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:23:58 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:23:58 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:23:58 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:23:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:23:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:23:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:23:59 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:23:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:23:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:23:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:23:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:23:59 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:24:00 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:24:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:24:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:24:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:24:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:24:00 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:24:01 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:24:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:24:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:24:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:24:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:24:01 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:24:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:24:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:24:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:24:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:24:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:24:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:24:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:24:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:24:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:24:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:24:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:24:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:24:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:24:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:24:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:24:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:24:01 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:24:01 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 07:24:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:24:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:24:01 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:24:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:24:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:24:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:24:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:24:02 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:24:02 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:24:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:24:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:24:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:24:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:24:03 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:24:03 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:24:04 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:24:04 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:24:05 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:24:05 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:24:06 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:24:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:24:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:24:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:24:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:24:06 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:24:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:24:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:24:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:24:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:24:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:24:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:24:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:24:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:24:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:24:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:24:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:24:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:24:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:24:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:24:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:24:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:24:06 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:24:07 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:24:07 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:24:08 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 07:24:08 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 07:24:09 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 07:24:09 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 07:24:09 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 07:24:10 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 07:24:10 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 07:24:11 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 07:24:11 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 07:24:12 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 07:24:12 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 07:24:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:24:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:24:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:24:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:24:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:24:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:24:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:24:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:24:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:24:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:24:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:24:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:24:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:24:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:24:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:24:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:24:12 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:24:12 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 07:24:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:24:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:24:13 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 07:24:13 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 07:24:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:24:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:24:13 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:24:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:24:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:24:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:24:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:24:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:24:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:24:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:24:13 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:24:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:24:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:24:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:24:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:24:18 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:24:18 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:24:18 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:24:18 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:24:18 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:24:18 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:24:18 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:24:18 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:24:18 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:24:18 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:24:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:24:18 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:24:19 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:24:19 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:24:19 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:24:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:24:19 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:24:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:24:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:24:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:24:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:24:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:24:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:24:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:24:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:24:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:24:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:24:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:24:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:24:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:24:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:24:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:24:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:24:19 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:24:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:24:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:24:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:24:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:24:20 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:24:20 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:24:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:24:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:24:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:24:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:24:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:24:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:24:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:24:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:24:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:24:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:24:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:24:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:24:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:24:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:24:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:24:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:24:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:24:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:24:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:24:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:24:21 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:24:21 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-10-30 07:24:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:24:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:24:21 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:24:21 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:24:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:24:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:24:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:24:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:24:22 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:24:22 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:24:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:24:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:24:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:24:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:24:23 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:24:23 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:24:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:24:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:24:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:24:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:24:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:24:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:24:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:24:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:24:23 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:24:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:24:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:24:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:24:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:24:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:24:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:24:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:24:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:24:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:24:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:24:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:24:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:24:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:24:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:24:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:24:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:24:23 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:24:24 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:24:24 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:24:25 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:24:25 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:24:26 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:24:26 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:24:27 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:24:27 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:24:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:24:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:24:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:24:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:24:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:24:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:24:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:24:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:24:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:24:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:24:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:24:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:24:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:24:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:24:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:24:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:24:28 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.83.22:6700) Recv SETFH cmd
2024-10-30 07:24:28 [INFO] transceiver.py:201 (MS@172.18.83.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-10-30 07:24:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:24:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:24:28 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:24:28 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 07:24:29 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 07:24:29 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 07:24:30 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 07:24:30 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 07:24:31 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 07:24:31 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 07:24:31 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 07:24:32 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 07:24:32 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 07:24:33 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 07:24:33 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 07:24:34 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 07:24:34 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-10-30 07:24:35 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-10-30 07:24:35 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-10-30 07:24:36 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-10-30 07:24:36 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-10-30 07:24:37 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-10-30 07:24:37 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-10-30 07:24:38 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-10-30 07:24:38 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-10-30 07:24:38 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-10-30 07:24:39 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-10-30 07:24:39 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-10-30 07:24:40 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-10-30 07:24:40 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-10-30 07:24:41 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-10-30 07:24:41 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-10-30 07:24:42 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-10-30 07:24:42 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-10-30 07:24:43 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-10-30 07:24:43 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-10-30 07:24:44 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-10-30 07:24:44 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-10-30 07:24:45 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-10-30 07:24:45 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-10-30 07:24:46 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-10-30 07:24:46 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-10-30 07:24:46 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-10-30 07:24:47 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-10-30 07:24:47 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-10-30 07:24:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:24:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:24:48 [INFO] transceiver.py:205 (MS@172.18.83.22:6700) Frequency hopping disabled
2024-10-30 07:24:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:24:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:24:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:24:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:24:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:24:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:24:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:24:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:24:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:24:48 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:24:48 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=6383 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:24:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:24:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:24:53 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:24:53 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:24:53 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:24:53 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:24:53 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:24:53 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:24:53 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:24:53 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:24:53 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:24:53 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:24:53 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:24:53 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:24:53 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:24:53 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:24:53 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:24:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:24:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:24:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:24:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:24:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:24:54 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:24:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:24:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:24:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:24:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:24:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:24:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:24:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:24:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:24:54 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:24:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:24:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:24:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:24:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:24:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:24:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:24:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:24:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:24:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:24:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:24:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:24:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:24:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:24:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:24:55 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:24:55 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=404 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:24:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:24:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:24:55 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=404 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:25:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:25:00 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:25:00 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:25:00 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:25:00 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:25:00 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:25:00 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:25:00 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:25:00 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:25:00 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:25:00 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:00 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:25:00 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:25:00 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:25:00 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:00 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:01 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:25:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:25:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:25:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:25:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:25:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:01 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:25:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:01 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:25:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:25:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:25:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:25:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:25:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:25:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:25:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:25:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:25:02 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:25:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:25:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:25:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:25:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:25:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:25:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:25:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:25:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:25:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:25:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:25:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:25:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:25:07 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:07 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:25:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:25:07 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:25:07 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:07 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:08 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:25:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:25:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:25:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:25:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:25:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:08 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:25:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:08 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:25:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:25:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:25:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:25:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:25:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:25:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:25:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:25:08 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:25:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:25:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:25:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:25:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:25:13 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:25:13 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:25:13 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:25:13 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:25:13 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:25:13 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:25:13 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:25:13 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:25:13 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:25:13 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:13 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:25:14 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:25:14 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:25:14 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:25:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:14 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:25:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:14 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:25:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:25:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:25:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:25:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:25:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:15 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:25:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:25:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:25:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:25:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:25:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:25:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:25:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:25:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:25:15 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:25:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:25:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:25:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:25:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:25:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:25:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:25:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:25:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:25:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:25:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:25:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:25:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:25:20 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:20 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:25:21 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:25:21 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:25:21 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:25:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:21 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:25:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:21 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:25:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:25:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:25:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:25:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:25:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:22 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:25:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:25:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:25:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:25:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:25:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:25:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:25:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:25:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:25:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:25:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:25:22 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:25:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:25:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:25:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:25:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:25:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:25:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:25:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:25:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:25:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:25:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:25:27 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:25:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:25:28 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:25:28 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:25:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:28 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:25:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:28 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:25:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:25:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:25:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:25:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:25:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:29 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:25:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:29 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:25:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:25:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:25:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:25:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:25:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:25:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:25:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:25:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:25:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:25:29 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:25:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:25:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:25:34 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:25:34 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:25:34 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:25:34 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:25:34 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:25:34 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:25:34 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:25:34 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:25:34 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:25:34 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:34 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:25:35 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:25:35 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:25:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:35 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:25:35 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:25:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:35 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:25:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:25:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:25:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:25:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:25:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:36 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:25:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:36 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:25:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:25:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:25:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:25:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:25:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:25:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:25:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:25:36 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:25:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:25:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:25:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:25:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:25:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:25:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:25:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:25:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:25:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:25:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:25:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:25:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:25:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:25:41 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:25:42 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:25:42 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:25:42 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:42 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:25:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:25:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:25:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:25:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:25:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:25:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:25:42 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:25:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:25:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:25:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:25:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:25:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:25:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:25:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:25:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:25:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:25:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:25:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:25:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:25:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:25:47 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:47 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:25:47 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:25:47 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:25:47 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:47 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:25:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:25:48 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:25:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:25:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:25:53 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:25:53 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:25:53 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:25:53 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:25:53 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:25:53 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:25:53 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:25:53 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:25:53 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:25:53 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:53 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:25:53 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:25:53 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:25:53 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:53 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:25:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:25:53 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:25:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:25:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:25:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:25:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:25:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:25:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:25:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:25:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:25:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:25:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:25:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:25:58 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:25:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:25:59 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:25:59 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:25:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:59 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:25:59 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:25:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:25:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:25:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:25:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:25:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:25:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:25:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:25:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:25:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:25:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:25:59 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:25:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:26:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:26:04 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:26:04 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:26:04 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:26:04 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:26:04 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:26:04 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:26:04 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:26:04 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:26:04 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:26:04 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:04 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:26:05 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:26:05 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:26:05 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:26:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:05 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:26:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:26:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:26:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:26:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:26:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:26:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:26:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:26:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:26:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:26:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:26:05 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:26:05 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=141 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:26:05 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=141 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:26:05 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=141 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:26:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:26:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:26:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:26:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:26:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:26:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:26:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:26:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:26:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:26:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:26:10 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:26:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:26:10 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:26:10 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:10 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:26:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:26:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:26:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:26:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:26:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:26:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:26:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:26:11 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:26:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:26:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:26:11 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=158 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:26:11 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=158 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:26:11 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=158 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:26:11 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=158 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:26:11 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=158 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:26:11 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=158 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:26:11 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=158 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:26:11 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=158 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:26:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:26:16 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:26:16 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:26:16 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:26:16 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:26:16 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:26:16 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:26:16 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:26:16 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:26:16 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:26:16 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:16 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:26:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:26:16 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:26:16 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:16 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:26:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:26:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:26:16 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:26:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:26:21 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:26:21 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:26:21 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:26:21 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:26:21 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:26:21 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:26:21 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:26:21 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:26:21 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:26:21 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:21 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:26:22 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:26:22 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:26:22 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:26:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:22 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:26:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:26:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:26:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:26:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:26:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:26:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:26:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:26:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:26:22 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:26:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:26:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:26:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:26:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:26:23 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:26:23 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:26:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:26:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:26:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:26:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:26:24 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:26:24 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:26:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:26:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:26:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:26:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:26:25 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:26:25 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:26:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:26:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:26:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:26:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:26:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:26:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:26:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:26:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:26:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:26:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:26:25 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:26:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:26:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:26:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:26:30 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:26:30 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:26:30 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:26:30 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:26:30 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:26:30 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:26:30 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:26:30 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:26:30 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:26:30 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:30 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:26:31 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:26:31 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:26:31 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:26:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:31 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:26:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:26:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:26:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:26:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:26:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:26:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:26:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:26:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:26:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 07:26:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:26:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:26:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:26:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:26:31 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:26:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:26:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:26:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:26:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:26:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:26:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:26:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:26:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:26:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:26:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:26:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:26:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:26:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:26:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:26:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:26:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:26:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:26:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:26:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:26:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:26:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:26:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:26:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:26:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:26:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:26:31 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:26:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:26:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:26:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:26:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:26:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:26:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:26:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:26:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:26:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:26:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:26:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:26:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:26:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:26:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:26:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:26:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:26:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:26:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:26:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:26:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:26:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:26:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:26:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:26:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:26:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:26:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:26:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:26:37 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:26:37 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:26:37 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:26:37 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:37 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:26:37 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:26:37 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:37 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:26:37 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:26:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:26:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:26:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:26:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:26:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:26:37 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:26:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:26:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:26:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:26:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:26:38 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:26:38 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:26:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:26:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:26:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:26:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:26:39 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:26:39 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-10-30 07:26:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:26:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:26:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:26:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:26:40 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-10-30 07:26:40 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-10-30 07:26:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:26:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:26:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:26:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:26:41 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-10-30 07:26:41 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-10-30 07:26:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:26:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:26:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:26:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:26:42 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-10-30 07:26:42 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-10-30 07:26:43 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-10-30 07:26:43 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-10-30 07:26:44 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-10-30 07:26:44 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-10-30 07:26:45 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-10-30 07:26:45 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-10-30 07:26:45 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-10-30 07:26:46 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-10-30 07:26:46 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-10-30 07:26:47 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-10-30 07:26:47 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-10-30 07:26:48 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-10-30 07:26:48 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-10-30 07:26:49 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-10-30 07:26:49 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-10-30 07:26:50 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-10-30 07:26:50 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-10-30 07:26:51 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-10-30 07:26:51 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-10-30 07:26:52 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-10-30 07:26:52 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-10-30 07:26:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:26:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:26:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:26:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:26:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:26:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:26:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:26:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:26:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:26:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:26:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:26:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:26:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:26:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:26:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:26:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:26:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:26:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:26:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:26:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:26:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:26:52 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:26:52 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3440 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:26:52 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3440 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:26:52 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3440 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:26:52 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3440 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:26:52 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3440 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:26:52 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=3440 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:26:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:26:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:26:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:26:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:26:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:26:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:26:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:26:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:26:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:26:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:26:57 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:26:57 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:26:58 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:26:58 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:26:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:58 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:26:58 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:26:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:26:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:26:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:26:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:26:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:26:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:26:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:26:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:26:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 07:26:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:26:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:26:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:26:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:26:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 07:26:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:26:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:26:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:26:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:26:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:26:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:26:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:26:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:26:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:26:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:26:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:26:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:26:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:26:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:26:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:26:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:26:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:26:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:26:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:26:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:26:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:26:58 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:26:58 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=196 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:26:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:26:58 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=196 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:26:58 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=196 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:26:58 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=196 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:26:58 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=196 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:26:58 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=196 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:26:58 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=196 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:26:58 [WARNING] transceiver.py:250 (BTS@172.18.83.20:5700) RX TRXD message (ver=1 fn=196 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:27:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:27:03 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:27:03 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:27:03 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:27:03 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:27:03 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:27:03 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:27:03 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:27:03 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:27:03 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:27:03 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:27:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:27:03 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-10-30 07:27:04 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-10-30 07:27:04 [DEBUG] fake_trx.py:272 (BTS@172.18.83.20:5700) Recv FAKE_TOA cmd
2024-10-30 07:27:04 [DEBUG] fake_trx.py:291 (BTS@172.18.83.20:5700) Recv FAKE_RSSI cmd
2024-10-30 07:27:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:27:04 [DEBUG] fake_trx.py:316 (BTS@172.18.83.20:5700) Recv FAKE_CI cmd
2024-10-30 07:27:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:27:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:27:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:27:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:27:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:27:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:27:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:27:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:27:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD HANDOVER
2024-10-30 07:27:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:27:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:27:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:27:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:27:04 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-10-30 07:27:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:27:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:27:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:27:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:27:05 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-10-30 07:27:05 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-10-30 07:27:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:27:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:27:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:27:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:27:06 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-10-30 07:27:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:27:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:27:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:27:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD ECHO
2024-10-30 07:27:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.83.22:6700) Ignore CMD SETSLOT
2024-10-30 07:27:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.83.22:6700) Recv RXTUNE cmd
2024-10-30 07:27:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.83.22:6700) Recv TXTUNE cmd
2024-10-30 07:27:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.83.22:6700) Recv POWERON CMD
2024-10-30 07:27:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.83.22:6700) Starting transceiver...
2024-10-30 07:27:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD NOHANDOVER
2024-10-30 07:27:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.83.22:6700) Recv POWEROFF cmd
2024-10-30 07:27:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.83.22:6700) Stopping transceiver...
2024-10-30 07:27:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.83.20:5700) Recv SETPOWER cmd
2024-10-30 07:27:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.83.20:5700/1) Recv SETPOWER cmd
2024-10-30 07:27:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.83.20:5700/2) Recv SETPOWER cmd
2024-10-30 07:27:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.83.20:5700/3) Recv SETPOWER cmd
2024-10-30 07:27:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:27:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:27:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:27:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:27:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:27:06 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:27:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:27:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:27:11 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:27:11 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:27:11 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:27:11 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:27:11 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:27:11 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:27:11 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:27:11 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:27:11 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:27:11 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:27:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:27:11 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:27:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:27:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:27:16 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:27:16 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:27:16 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:27:16 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:27:16 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:27:16 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:27:16 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:27:16 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:27:16 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:27:16 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:27:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:27:16 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:27:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:27:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:27:21 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.83.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.83.20:5700) Recv SETFORMAT cmd
2024-10-30 07:27:21 [INFO] ctrl_if_trx.py:201 (BTS@172.18.83.20:5700) TRXD header version 1 -> 1
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.83.20:5700/1) Recv RXTUNE cmd
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.83.20:5700/1) Recv TXTUNE cmd
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:27:21 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.83.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.83.20:5700/1) Recv NOMTXPOWER cmd
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.83.20:5700/1) Recv SETFORMAT cmd
2024-10-30 07:27:21 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.83.20:5700/1) TRXD header version 1 -> 1
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.83.20:5700/2) Recv RXTUNE cmd
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.83.20:5700/2) Recv TXTUNE cmd
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:27:21 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.83.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.83.20:5700/2) Recv RFMUTE cmd
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.83.20:5700/2) Recv NOMTXPOWER cmd
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.83.20:5700/2) Recv SETFORMAT cmd
2024-10-30 07:27:21 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.83.20:5700/2) TRXD header version 1 -> 1
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.83.20:5700/3) Recv RXTUNE cmd
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.83.20:5700/3) Recv TXTUNE cmd
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:27:21 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.83.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.83.20:5700/3) Recv RFMUTE cmd
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.83.20:5700/3) Recv NOMTXPOWER cmd
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.83.20:5700/3) Recv SETFORMAT cmd
2024-10-30 07:27:21 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.83.20:5700/3) TRXD header version 1 -> 1
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.83.20:5700) Recv RXTUNE cmd
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETTSC
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETTSC
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.83.20:5700) Recv TXTUNE cmd
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETTSC
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETRXGAIN
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETTSC
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETRXGAIN
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.83.20:5700) Recv NOMTXPOWER cmd
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETRXGAIN
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.83.20:5700) Recv POWERON CMD
2024-10-30 07:27:21 [INFO] ctrl_if_trx.py:109 (BTS@172.18.83.20:5700) Starting transceiver...
2024-10-30 07:27:21 [INFO] transceiver.py:236 Starting clock generator
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETRXGAIN
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.83.20:5700/1) Ignore CMD SETSLOT
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.83.20:5700/1) Recv RFMUTE cmd
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.83.20:5700) Ignore CMD SETSLOT
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.83.20:5700) Recv RFMUTE cmd
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.83.20:5700) Recv POWEROFF cmd
2024-10-30 07:27:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.83.20:5700) Stopping transceiver...
2024-10-30 07:27:21 [INFO] transceiver.py:239 Stopping clock generator
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.83.20:5700/3) Ignore CMD SETSLOT
2024-10-30 07:27:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.83.20:5700/2) Ignore CMD SETSLOT