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0.5724670TC_lu_imsi_auth3g_tmsifalsePASSED0MSC_Tests1.1271910TC_lu_imsi_auth3g_tmsi_check_imeifalsePASSED0MSC_Tests1.3792670TC_lu_imsi_auth3g_tmsi_check_imei_earlyfalsePASSED0MSC_Tests0.6106180TC_lu_imsi_auth_tmsifalsePASSED0MSC_Tests1.1676770TC_lu_imsi_auth_tmsi_check_imeifalsePASSED0MSC_Tests1.3617180TC_lu_imsi_auth_tmsi_check_imei_earlyfalsePASSED0MSC_Tests0.7408080TC_lu_imsi_auth_tmsi_check_imei_early_errfalsePASSED0MSC_Tests1.3252880TC_lu_imsi_auth_tmsi_check_imei_early_nackfalsePASSED0MSC_Tests1.1663810TC_lu_imsi_auth_tmsi_check_imei_errfalsePASSED0MSC_Tests1.2098940TC_lu_imsi_auth_tmsi_check_imei_nackfalsePASSED0MSC_Tests0.6032920TC_lu_imsi_auth_tmsi_encr_0134_1falsePASSED0MSC_Tests0.5948840TC_lu_imsi_auth_tmsi_encr_0134_34falsePASSED0MSC_Tests0.5713360TC_lu_imsi_auth_tmsi_encr_0134_34_no_cm3falsePASSED0MSC_Tests1.2808730TC_lu_imsi_auth_tmsi_encr_013_2falsePASSED0MSC_Tests0.5593040TC_lu_imsi_auth_tmsi_encr_13_13falsePASSED0MSC_Tests0.5436240TC_lu_imsi_auth_tmsi_encr_13_2falsePASSED0MSC_Tests0.4753450TC_lu_imsi_auth_tmsi_encr_1_13falsePASSED0MSC_Tests0.525570TC_lu_imsi_auth_tmsi_encr_3_1falsePASSED0MSC_Tests0.4723270TC_lu_imsi_auth_tmsi_encr_3_13falsePASSED0MSC_Tests1.137990TC_lu_imsi_auth_tmsi_encr_3_1_log_msc_debugfalsePASSED0MSC_Tests0.5462850TC_lu_imsi_auth_tmsi_encr_3_1_no_cmfalsePASSED0MSC_Tests0.6843080TC_lu_imsi_noauth_notmsifalsePASSED0MSC_Tests1.1694770TC_lu_imsi_noauth_notmsi_check_imeifalsePASSED0MSC_Tests1.3676190TC_lu_imsi_noauth_notmsi_check_imei_earlyfalsePASSED0MSC_Tests0.7912690TC_lu_imsi_noauth_tmsifalsePASSED0MSC_Tests1.1855850TC_lu_imsi_noauth_tmsi_check_imeifalsePASSED0MSC_Tests1.4196630TC_lu_imsi_noauth_tmsi_check_imei_earlyfalsePASSED0MSC_Tests0.5835680TC_lu_imsi_rejectfalsePASSED0MSC_Tests5.5479520TC_lu_imsi_timeout_gsupfalsePASSED667MSC_Tests7.580131Timeout waiting for ClearCommand/Release MSC_Tests.ttcn:7860 MSC_Tests control part MSC_Tests.ttcn:691 TC_lu_imsi_timeout_tmsi_realloc testcase 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