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97080TC_lu_imsi_auth3g_tmsifalsePASSED0MSC_Tests1.1782580TC_lu_imsi_auth3g_tmsi_check_imeifalsePASSED0MSC_Tests1.4202470TC_lu_imsi_auth3g_tmsi_check_imei_earlyfalsePASSED0MSC_Tests0.6470110TC_lu_imsi_auth_tmsifalsePASSED0MSC_Tests1.144420TC_lu_imsi_auth_tmsi_check_imeifalsePASSED0MSC_Tests1.3708620TC_lu_imsi_auth_tmsi_check_imei_earlyfalsePASSED0MSC_Tests1.2963630TC_lu_imsi_auth_tmsi_check_imei_early_errfalsePASSED0MSC_Tests1.3409670TC_lu_imsi_auth_tmsi_check_imei_early_nackfalsePASSED0MSC_Tests1.2315810TC_lu_imsi_auth_tmsi_check_imei_errfalsePASSED0MSC_Tests1.1476140TC_lu_imsi_auth_tmsi_check_imei_nackfalsePASSED0MSC_Tests0.599810TC_lu_imsi_auth_tmsi_encr_0134_1falsePASSED0MSC_Tests0.586830TC_lu_imsi_auth_tmsi_encr_0134_34falsePASSED0MSC_Tests0.5921920TC_lu_imsi_auth_tmsi_encr_0134_34_no_cm3falsePASSED0MSC_Tests0.5670280TC_lu_imsi_auth_tmsi_encr_013_2falsePASSED0MSC_Tests0.5847330TC_lu_imsi_auth_tmsi_encr_13_13falsePASSED0MSC_Tests1.1532730TC_lu_imsi_auth_tmsi_encr_13_2falsePASSED0MSC_Tests0.4580950TC_lu_imsi_auth_tmsi_encr_1_13falsePASSED0MSC_Tests0.5312430TC_lu_imsi_auth_tmsi_encr_3_1falsePASSED0MSC_Tests0.4677960TC_lu_imsi_auth_tmsi_encr_3_13falsePASSED0MSC_Tests1.1810490TC_lu_imsi_auth_tmsi_encr_3_1_log_msc_debugfalsePASSED0MSC_Tests0.566220TC_lu_imsi_auth_tmsi_encr_3_1_no_cmfalsePASSED0MSC_Tests0.603760TC_lu_imsi_noauth_notmsifalsePASSED0MSC_Tests1.1716880TC_lu_imsi_noauth_notmsi_check_imeifalsePASSED0MSC_Tests1.3140210TC_lu_imsi_noauth_notmsi_check_imei_earlyfalsePASSED0MSC_Tests0.834550TC_lu_imsi_noauth_tmsifalsePASSED0MSC_Tests1.1523170TC_lu_imsi_noauth_tmsi_check_imeifalsePASSED0MSC_Tests1.4148780TC_lu_imsi_noauth_tmsi_check_imei_earlyfalsePASSED0MSC_Tests0.5543760TC_lu_imsi_rejectfalsePASSED0MSC_Tests5.5539610TC_lu_imsi_timeout_gsupfalsePASSED756MSC_Tests7.557697Timeout waiting for ClearCommand/Release MSC_Tests.ttcn:7860 MSC_Tests control part MSC_Tests.ttcn:691 TC_lu_imsi_timeout_tmsi_realloc testcase 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