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5988230TC_lu_imsi_auth3g_tmsifalsePASSED0MSC_Tests1.1743280TC_lu_imsi_auth3g_tmsi_check_imeifalsePASSED0MSC_Tests1.3418960TC_lu_imsi_auth3g_tmsi_check_imei_earlyfalsePASSED0MSC_Tests0.6079510TC_lu_imsi_auth_tmsifalsePASSED0MSC_Tests1.0868750TC_lu_imsi_auth_tmsi_check_imeifalsePASSED0MSC_Tests1.372380TC_lu_imsi_auth_tmsi_check_imei_earlyfalsePASSED0MSC_Tests1.3028320TC_lu_imsi_auth_tmsi_check_imei_early_errfalsePASSED0MSC_Tests1.316080TC_lu_imsi_auth_tmsi_check_imei_early_nackfalsePASSED0MSC_Tests1.1831430TC_lu_imsi_auth_tmsi_check_imei_errfalsePASSED0MSC_Tests1.2376660TC_lu_imsi_auth_tmsi_check_imei_nackfalsePASSED0MSC_Tests0.5020140TC_lu_imsi_auth_tmsi_encr_0134_1falsePASSED0MSC_Tests1.3289560TC_lu_imsi_auth_tmsi_encr_0134_34falsePASSED0MSC_Tests1.2949410TC_lu_imsi_auth_tmsi_encr_0134_34_no_cm3falsePASSED0MSC_Tests0.5497680TC_lu_imsi_auth_tmsi_encr_013_2falsePASSED0MSC_Tests0.5985880TC_lu_imsi_auth_tmsi_encr_13_13falsePASSED0MSC_Tests0.5338610TC_lu_imsi_auth_tmsi_encr_13_2falsePASSED0MSC_Tests1.3213920TC_lu_imsi_auth_tmsi_encr_1_13falsePASSED0MSC_Tests0.5331370TC_lu_imsi_auth_tmsi_encr_3_1falsePASSED0MSC_Tests1.2830740TC_lu_imsi_auth_tmsi_encr_3_13falsePASSED0MSC_Tests1.1517970TC_lu_imsi_auth_tmsi_encr_3_1_log_msc_debugfalsePASSED0MSC_Tests0.4959650TC_lu_imsi_auth_tmsi_encr_3_1_no_cmfalsePASSED0MSC_Tests0.6650TC_lu_imsi_noauth_notmsifalsePASSED0MSC_Tests1.2296550TC_lu_imsi_noauth_notmsi_check_imeifalsePASSED0MSC_Tests1.3249970TC_lu_imsi_noauth_notmsi_check_imei_earlyfalsePASSED0MSC_Tests0.6904140TC_lu_imsi_noauth_tmsifalsePASSED0MSC_Tests1.1781140TC_lu_imsi_noauth_tmsi_check_imeifalsePASSED0MSC_Tests1.3782040TC_lu_imsi_noauth_tmsi_check_imei_earlyfalsePASSED0MSC_Tests0.5597310TC_lu_imsi_rejectfalsePASSED0MSC_Tests5.5407610TC_lu_imsi_timeout_gsupfalsePASSED766MSC_Tests7.517667Timeout waiting for ClearCommand/Release MSC_Tests.ttcn:7860 MSC_Tests control part MSC_Tests.ttcn:691 TC_lu_imsi_timeout_tmsi_realloc testcase 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