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5712760TC_lu_imsi_auth3g_tmsifalsePASSED0MSC_Tests1.1729010TC_lu_imsi_auth3g_tmsi_check_imeifalsePASSED0MSC_Tests1.3456940TC_lu_imsi_auth3g_tmsi_check_imei_earlyfalsePASSED0MSC_Tests0.5805390TC_lu_imsi_auth_tmsifalsePASSED0MSC_Tests1.1343030TC_lu_imsi_auth_tmsi_check_imeifalsePASSED0MSC_Tests0.7509670TC_lu_imsi_auth_tmsi_check_imei_earlyfalsePASSED0MSC_Tests0.7045810TC_lu_imsi_auth_tmsi_check_imei_early_errfalsePASSED0MSC_Tests0.6555870TC_lu_imsi_auth_tmsi_check_imei_early_nackfalsePASSED0MSC_Tests1.1451710TC_lu_imsi_auth_tmsi_check_imei_errfalsePASSED0MSC_Tests1.138950TC_lu_imsi_auth_tmsi_check_imei_nackfalsePASSED0MSC_Tests0.5274850TC_lu_imsi_auth_tmsi_encr_0134_1falsePASSED0MSC_Tests0.5274080TC_lu_imsi_auth_tmsi_encr_0134_34falsePASSED0MSC_Tests0.5392580TC_lu_imsi_auth_tmsi_encr_0134_34_no_cm3falsePASSED0MSC_Tests0.5348140TC_lu_imsi_auth_tmsi_encr_013_2falsePASSED0MSC_Tests0.5600540TC_lu_imsi_auth_tmsi_encr_13_13falsePASSED0MSC_Tests0.5382140TC_lu_imsi_auth_tmsi_encr_13_2falsePASSED0MSC_Tests0.5812550TC_lu_imsi_auth_tmsi_encr_1_13falsePASSED0MSC_Tests0.5388910TC_lu_imsi_auth_tmsi_encr_3_1falsePASSED0MSC_Tests0.5459240TC_lu_imsi_auth_tmsi_encr_3_13falsePASSED0MSC_Tests1.032470TC_lu_imsi_auth_tmsi_encr_3_1_log_msc_debugfalsePASSED0MSC_Tests0.5450650TC_lu_imsi_auth_tmsi_encr_3_1_no_cmfalsePASSED0MSC_Tests0.6381640TC_lu_imsi_noauth_notmsifalsePASSED0MSC_Tests1.1242890TC_lu_imsi_noauth_notmsi_check_imeifalsePASSED0MSC_Tests0.6515460TC_lu_imsi_noauth_notmsi_check_imei_earlyfalsePASSED0MSC_Tests0.8106370TC_lu_imsi_noauth_tmsifalsePASSED0MSC_Tests1.1886960TC_lu_imsi_noauth_tmsi_check_imeifalsePASSED0MSC_Tests1.3128090TC_lu_imsi_noauth_tmsi_check_imei_earlyfalsePASSED0MSC_Tests0.5366090TC_lu_imsi_rejectfalsePASSED0MSC_Tests5.6075910TC_lu_imsi_timeout_gsupfalsePASSED805MSC_Tests7.569167Timeout waiting for ClearCommand/Release MSC_Tests.ttcn:7860 MSC_Tests control part MSC_Tests.ttcn:691 TC_lu_imsi_timeout_tmsi_realloc testcase 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