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C_lu_imsi_auth3g_tmsifalsePASSED0MSC_Tests1.2275410TC_lu_imsi_auth3g_tmsi_check_imeifalsePASSED0MSC_Tests1.3730820TC_lu_imsi_auth3g_tmsi_check_imei_earlyfalsePASSED0MSC_Tests0.6482990TC_lu_imsi_auth_tmsifalsePASSED0MSC_Tests0.5087260TC_lu_imsi_auth_tmsi_check_imeifalsePASSED0MSC_Tests0.7232140TC_lu_imsi_auth_tmsi_check_imei_earlyfalsePASSED0MSC_Tests0.6781610TC_lu_imsi_auth_tmsi_check_imei_early_errfalsePASSED0MSC_Tests0.6618410TC_lu_imsi_auth_tmsi_check_imei_early_nackfalsePASSED0MSC_Tests0.464080TC_lu_imsi_auth_tmsi_check_imei_errfalsePASSED0MSC_Tests1.1407610TC_lu_imsi_auth_tmsi_check_imei_nackfalsePASSED0MSC_Tests0.5882750TC_lu_imsi_auth_tmsi_encr_0134_1falsePASSED0MSC_Tests0.6062240TC_lu_imsi_auth_tmsi_encr_0134_34falsePASSED0MSC_Tests0.5774730TC_lu_imsi_auth_tmsi_encr_0134_34_no_cm3falsePASSED0MSC_Tests1.1471440TC_lu_imsi_auth_tmsi_encr_013_2falsePASSED0MSC_Tests0.5110940TC_lu_imsi_auth_tmsi_encr_13_13falsePASSED0MSC_Tests0.5434670TC_lu_imsi_auth_tmsi_encr_13_2falsePASSED0MSC_Tests0.5629860TC_lu_imsi_auth_tmsi_encr_1_13falsePASSED0MSC_Tests0.542890TC_lu_imsi_auth_tmsi_encr_3_1falsePASSED0MSC_Tests1.176990TC_lu_imsi_auth_tmsi_encr_3_13falsePASSED0MSC_Tests0.4538290TC_lu_imsi_auth_tmsi_encr_3_1_log_msc_debugfalsePASSED0MSC_Tests0.5393440TC_lu_imsi_auth_tmsi_encr_3_1_no_cmfalsePASSED0MSC_Tests0.6235410TC_lu_imsi_noauth_notmsifalsePASSED0MSC_Tests0.5022010TC_lu_imsi_noauth_notmsi_check_imeifalsePASSED0MSC_Tests0.6680710TC_lu_imsi_noauth_notmsi_check_imei_earlyfalsePASSED0MSC_Tests0.7491010TC_lu_imsi_noauth_tmsifalsePASSED0MSC_Tests0.5687070TC_lu_imsi_noauth_tmsi_check_imeifalsePASSED0MSC_Tests0.67910TC_lu_imsi_noauth_tmsi_check_imei_earlyfalsePASSED0MSC_Tests0.576270TC_lu_imsi_rejectfalsePASSED0MSC_Tests5.5534350TC_lu_imsi_timeout_gsupfalsePASSED2277MSC_Tests7.606474Timeout waiting for ClearCommand/Release MSC_Tests.ttcn:7860 MSC_Tests control part MSC_Tests.ttcn:691 TC_lu_imsi_timeout_tmsi_realloc testcase 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