#1419 (Feb 10, 2026, 11:36:00 AM)

Started by timer

This run spent:

• 6 ms waiting;
• 1 min 20 sec build duration;
• 1 min 20 sec total from scheduled to completion.

• origin/master

• junit-xml-6347.log.[empty]

1. bts: as_rsl_meas_res(): tolerate bad RxQual in early reports (details)
2. bts: as_rsl_meas_res(): do not expect dummy UL SACCH (details)
3. bts: f_verify_ramp_up(): fix RxLev / dBm mixup (details)
4. bts: fix TC_rsl_ms_pwr_dyn_ass_updown: simulate a good C/I value (details)
5. bts: fix TC_rsl_ms_pwr_dyn_ass_updown: adjust the timers (details)
6. bts: TC_rsl_ms_pwr_dyn_ass_updown: misc improvements (details)