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block is received by the BTS before a DL\u000aSACCH block is generated and delivered to the testcase. In this case,\u000athe Timing Advance control loop may update the initial TA value that\u000awas set during RSL CHANnel ACTIVation.\u000a\u000aBy default, trxcon transmits UL SACCH blocks with TA=0, which is exactly\u000awhat triggers the TA control loop in this situation.\u000a\u000aTo avoid this, we explicitly signal the expected TA value to trxcon by\u000apre-populating the UL SACCH cache. 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