<?xml version="1.0"?>
<testsuite name='Titan' tests='44' failures='0' errors='0' skipped='0' inconc='0' time='183.00'>
  <testcase classname='S1GW_Tests' name='TC_setup' time='3.016000'/>
  <testcase classname='S1GW_Tests' name='TC_setup_multi' time='1.006109'/>
  <testcase classname='S1GW_Tests' name='TC_conn_term_by_mme' time='0.554174'/>
  <testcase classname='S1GW_Tests' name='TC_conn_term_mme_unavail' time='5.117649'/>
  <testcase classname='S1GW_Tests' name='TC_e_rab_setup' time='0.264512'/>
  <testcase classname='S1GW_Tests' name='TC_e_rab_setup3' time='0.290974'/>
  <testcase classname='S1GW_Tests' name='TC_e_rab_setup_multi' time='0.769357'/>
  <testcase classname='S1GW_Tests' name='TC_e_rab_setup3_multi' time='1.074736'/>
  <testcase classname='S1GW_Tests' name='TC_e_rab_release_ind' time='0.052729'/>
  <testcase classname='S1GW_Tests' name='TC_e_rab_setup_failure' time='0.240961'/>
  <testcase classname='S1GW_Tests' name='TC_e_rab_setup3_failure' time='0.256766'/>
  <testcase classname='S1GW_Tests' name='TC_e_rab_modify_req_rsp' time='0.289825'/>
  <testcase classname='S1GW_Tests' name='TC_e_rab_modify_req_rsp_multi' time='1.407139'/>
  <testcase classname='S1GW_Tests' name='TC_e_rab_modify_ind_cnf' time='0.367384'/>
  <testcase classname='S1GW_Tests' name='TC_e_rab_modify_ind_cnf_multi' time='1.604535'/>
  <testcase classname='S1GW_Tests' name='TC_initial_ctx_setup' time='0.261656'/>
  <testcase classname='S1GW_Tests' name='TC_initial_ctx_setup3' time='0.290773'/>
  <testcase classname='S1GW_Tests' name='TC_initial_ctx_setup_multi' time='0.790481'/>
  <testcase classname='S1GW_Tests' name='TC_initial_ctx_setup3_multi' time='1.013278'/>
  <testcase classname='S1GW_Tests' name='TC_initial_ctx_setup_failure' time='5.122625'/>
  <testcase classname='S1GW_Tests' name='TC_ue_ctx_release_req' time='0.068135'/>
  <testcase classname='S1GW_Tests' name='TC_ue_ctx_release_req3' time='0.055609'/>
  <testcase classname='S1GW_Tests' name='TC_ue_ctx_release_cmd_compl' time='0.259355'/>
  <testcase classname='S1GW_Tests' name='TC_ue_ctx_release_cmd_compl3' time='0.268641'/>
  <testcase classname='S1GW_Tests' name='TC_uemux_uldl_nas_release' time='1.053500'/>
  <testcase classname='S1GW_Tests' name='TC_uemux_e_rab_setup' time='1.813863'/>
  <testcase classname='S1GW_Tests' name='TC_uemux_e_rab_release_cmd' time='2.334516'/>
  <testcase classname='S1GW_Tests' name='TC_uemux_e_rab_release_ind' time='2.223512'/>
  <testcase classname='S1GW_Tests' name='TC_uemux_initial_ctx_setup' time='1.744281'/>
  <testcase classname='S1GW_Tests' name='TC_uemux_ue_ctx_release_req' time='2.386154'/>
  <testcase classname='S1GW_Tests' name='TC_uemux_ue_ctx_release_cmd' time='2.381325'/>
  <testcase classname='S1GW_Tests' name='TC_handover_preparation' time='0.275677'/>
  <testcase classname='S1GW_Tests' name='TC_handover_preparation_release' time='0.327385'/>
  <testcase classname='S1GW_Tests' name='TC_handover_res_alloc' time='0.292273'/>
  <testcase classname='S1GW_Tests' name='TC_handover_res_alloc_fail' time='0.323181'/>
  <testcase classname='S1GW_Tests' name='TC_pfcp_heartbeat' time='0.030946'/>
  <testcase classname='S1GW_Tests' name='TC_mme_pool_reject_fallback' time='0.559294'/>
  <testcase classname='S1GW_Tests' name='TC_mme_pool_timeout_fallback' time='5.676960'/>
  <testcase classname='S1GW_Tests' name='TC_mme_pool_all_reject' time='0.053370'/>
  <testcase classname='S1GW_Tests' name='TC_mme_pool_enb_disc_wait_s1setup_req' time='0.028966'/>
  <testcase classname='S1GW_Tests' name='TC_mme_pool_enb_disc_wait_s1setup_rsp' time='0.027025'/>
  <testcase classname='S1GW_Tests' name='TC_rest_mme_list' time='0.010504'/>
  <testcase classname='S1GW_Tests' name='TC_rest_mme_add_del' time='0.014944'/>
  <testcase classname='S1GW_Tests' name='TC_rest_mme_del_fallback' time='0.572365'/>
</testsuite>
