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p׫*XºNý¤!©r-’‰½8ktp©¥LÐ[[ LpqÓi ^ +Cû€á»3›a§Ä/>W‰ø1>áj 0•Îk’³¢9ãÈNä…õœ 9—QŽÙ9O~f"Ò%`*÷;0ž‘8¹²<>b?ÖB"Er¤P aRµ5[“W\j’_aÝDcBYÌl2Š×' êp!÷{"½[#Üq$£,%Я&ú'Uœ(Ÿ}))T*N#+ŸŽ,uU-|†.;/¢0a1vŽ2!Ÿ3Žj4ù¯5}:6?q7 8‰9*:êa;;4<çX=-ˆ>æ ?¬D@r}A&OB°FCÁDü E¾PFã#G9,H0'I¯J1K+VL7M#ªOUPñrQYR™NS®?T¤~UmV?W XÙYµEZÒ8[eŸ\£„]ë<^˜[_—§`Ába΂b²Lck7dnVeÕtf‘gùth²i&–jž!kÐ.lüLmè`nÒg­Ó„Ô9&ÕÓ±×+£Ø³tÙO ÚËuÜÐMÝ4ßRVà¿áÓŠâ¦Pä ®å10æ¶'ç9ïç–ðarñ~iò°˜ó°ôÒ$õ•öß÷qøA/ùú§ûµ³ü¤7ýˆ¦þ†2ÿ‰€§#Ê)‚(mZ¢!|>&æl'.œ2 C=D+uEŠ'FqIò?L QÆRÕ–S •T(YUªVª–WÍZXk4Y…˜Z\[L\Wu]Ò£^ _“t`Îxaʦbc5c³Md­{eš\f{Ig@§hfiL j}k…ªlå"mnnÇo‹Np5~(Ín*CG+ö~,Âg-;/h0²«1|2Qk3&4^5Œ 6-_7è8º‡9­”:;ÂC9 ?ˆ@ë›AnBª¥C¯ Eh3F°ŒGŸ"I JJzLÄUMNŽ£O4ŒPäŽQq£RùS TT'U-2VzwW¶–X½o[_e\Ø^9_ˆ¨`ÿbê$câ«dëeVUf‰ gthíKiG­jYkºlÈn&BqœBr%urv¢™wY/xzkyWz6+{ |=f}G~Ç]£€›#|„>w…¶"†õ‡•Cˆ ^‰E{ŠS“‹xŒë’t.Ž’H¬ “¡”gG•{X–=s—ø¬˜¡ž™n”š l›Ý}œ¬’Y*ž6ŸÀG¢Ô)£X¤õª¥ÐR¦Ex§—¨wZ©¬›ªÎH«˜¬G0­˜ ®ÿv±¥²Œ³e=´w+µ;±¶ó"·jŒ¸î–¹þgº½6»ðB¼<½¤ÀáÁÌT Â6Ä*™Å“ÆscÇg9ÈÉzÉmJÊœË} Ìw«Ï¶†ÐœfÑ4Ò¢ÓDgÔ|sÕµªÖb×±Ø2WÙüÚšÛb ÞÇŒßE•àøžáNâ§xãZ äþnåÊræå7ç ŽèSé…’êy®í×Jî¬ïwrðsñïò.¨óhôQõC8öå¢÷¨Šø=ù½ü×ýBCþè˜ÿHŠ€r{¼X‚ùJƒê„K…¦0†öD‡ò±ˆ\›‹.Œ*‰ú\Ž¶jòS¹;‘Ü_’>“2”°œ•:=–'—…Fš³—›ü+œuÐ,žÔvŸhW ¸¡G¦¢M—£[R¤´š¥«…¦Dm©˜*¬.$­»®EL¯“4°3-±9^²×³u¬´ÜxµFª¶:P·å™¸Æ7°Çt³Ê‡>Ë”Ì(Íý†Î¼­Ï‡ŠÐÖÑ-©ÒîÓbBÔÔÕ;‘ÖíN×+Û@UÜ…„Ýõ8Þ=Bßx^àŠ¯á®câ[‹ã(iäkgåÍæŽqç;\è\šëå€ìÏ“í‹nî†ï"ðæñækò·BóZ ô>¤õu‚öþ¨÷˜ øUû-…ü_YýPþŠ“ÿQ³€I†59‚6«ƒI„­¯…áV†„x‡á[ˆG’‹(3Œa‡¤rdo‘z&’A²“B¥”`b•<–)—£s˜ì—™¦š‰²›?ž~…ŸD  ‰¡¸ ¥¨1¦Ý|§Öeª´£«i¬uz¯íl°Zp±Ñ5µ®W¶‹@·n•¹ÞFºKi»xA¼½w¾W"¿5šÀHÁ´¬Â—wÃoCÄ!EÅãƃ ÇGEÈ0ÉJ2Ê?Q˧:Ì7pΠ2Ïn8Ðè@ÓQŒÔجÕ §Ö`!×~¡ØÀAÙÆÚ9<ÛüUÜȘÝ>ÞÔ-ßì°àÏ?ᦢâRãPäc¥å÷æK;çÂ!è:£éæ!êÚnë‹ìY«íâ î$ïŸðÏ&ñ†LòËpóÈ`ôò õ2Sö6œ÷é”øÎQùíuú­ûžü"/ýiyþx#ÿªT€_ÙZ‚.ƒõh„|‡…†$†Æ¢‡o‘ˆÿb‰|©ŠÑ ‹Œ'a«pŽ/‘°’烓Žg”¿<•Ɉ–C®—˜†™AFšÖ©›<œÝdd%ž<Ÿ&g <¡&g¢.#£Þ¡¤e™¥þd¦»w§¥¨‘˜©8ªº>«T‚¬"t­}!®“—¯Ö†°•R±b³œAµ}"¶ 8ÈVcÉ[DËÎ:Í4„ÏÑcÑÌ2Õ÷šÖô(ØZÛ´Ü+yÝ Þ(àûZáNMã:æ¼Yçf¢èÒ4éìPëà£ìæˆî„ƒñ™òš©óû,ô %ö;e÷÷ù6ü ‚ýDþ©®ÿ6’E‚Ú„½§ˆ‰Õ‹”ŽvÔ‰’‹d”ˆ)–†°˜#šÞ‡œ']ŸšU «¤¢ ˜¦P_§©n­°v®ï‚°r´1Ó`–Õ],×ÊOÙ7Xܵ/Þ¿àÈ‹âåçÉŸê†iìŽ|îwlð¾*óhõ9ƒøDvú¼=ý%oÿ5‚QS„/`†{ˆ9h‹”-•_D [û ../common/usr/lib/gcc/arm-none-eabi/12.2.1/include../../../include/libopencm3/efm32/common../../../include/libopencm3/efm32../../../include/libopencm3/efm32/lg../../../include/libopencm3/cm3dma_common.cstdint.hdma_common.hdma.hdma.hmemorymap.hmemorymap.hmemorymap.hcommon.hstdbool.h¥Z0>4! =)3u  <; =Å $/Ó -#/!.Ý   !æ   !ï   !ø   !   !Š   !“   !œ   !¥   !®   !·   !Á /É =Ô ;"/!.ß /ë .'.!.ó Kü    !„ K    !• .= .=¦     /¯    =¹'</0Ä'</0Î   " z " " >[Kæ!$!/!-K0ô$JK$JK’  ! / .!"!¢  !//"!²  ! / .!"!Á  ! / .!"!Ò  ! / .!"!à " =ë " =÷ ,  !! ./ .!"!‡ ( !“  !Á/ <!z&..//!Ø ! .!z&. 00!ë  ! -/!"!DMA_CH_CTRL_SIGSEL_EBIPXL0EMPTY 0SCB_BASE (SCS_BASE + 0x0D00)DMA_RDS_RDSCH0 DMA_RDS_RDSCHx(0)__FLT64_EPSILON__ 2.2204460492503131e-16F64DMA_CHREQMASKS_CH11SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(11)__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64DMA_CH5_CTRL DMA_CHx_CTRL(5)CORESIGHT_LSR_SLK (1<<1)__GCC_ATOMIC_WCHAR_T_LOCK_FREE 2DMA_IEN_CH11DONE DMA_IEN_CHxDONE(11)__CHAR_UNSIGNED__ 1DI_DAC0_CAL_2V5 MMIO32(DI_BASE + 0x1CC)DMA_CHENS_CH4SENS DMA_CHENS_CHxSENS(4)DMA_STATUS_CHNUM_MASK (0x1F << DMA_STATUS_CHNUM_SHIFT)dma_set_alt_src_inc(ch,inc) dma_desc_set_src_inc(DMA_ALTCTRLBASE, ch, inc)__FLT64_HAS_INFINITY__ 1UINT16_MAX __UINT16_MAX____LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GCC_DESTRUCTIVE_SIZE 64dma_set_desc_address__PTRDIFF_MAX__ 0x7fffffffuser_dataDMA_DESC_CH_CFG_SRC_PROT_CTRL_MASK (0x7 << DMA_DESC_CH_CFG_SRC_PROT_CTRL_SHIFT)__INTMAX_C(c) c ## LLDMA_IEN MMIO32(DMA_BASE + 0x100C)__INTMAX_MAX__ 0x7fffffffffffffffLLDMA_DESC_CH_CFG_DEST_INC_BYTE DMA_DESC_CH_CFG_DEST_INC(0)__TQ_IBIT__ 0__FLT64_DECIMAL_DIG__ 17DMA_CHPRIC MMIO32(DMA_BASE + 0x03C)WINT_MIN __WINT_MIN__INT_FAST64_MAXDMA_CHREQMASKC MMIO32(DMA_BASE + 0x024)DMA_CH_CTRL_SIGSEL_USART_TXEMPTY 2__ATOMIC_CONSUME 1__ULACCUM_FBIT__ 32__WCHAR_MAX__ 0xffffffffUDMA_CHALTC_CH5SALTC DMA_CHALTC_CHxSALTC(5)__ACCUM_MIN__ (-0X1P15K-0X1P15K)DMA_CHUSEBURSTS_CH1SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(1)DMA_CHPRIC_CH10SPRIC DMA_CHPRIC_CHxSPRIC(10)dma_desc_set_src_addressDMA_CHREQSTATUS_CH11SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(11)DMA_CHENS_CH2SENS DMA_CHENS_CHxSENS(2)DMA_DESC_CH_CFG_CYCLE_CTRL_MEM_SCAT_GATH_ALT DMA_DESC_CH_CFG_CYCLE_CTRL(5)INT64_MAX __INT64_MAX__INTMAX_MINdma_desc_set_modeDMA_CHWAITSTATUS_CH2WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(2)__DBL_MAX_10_EXP__ 308dma_r_power__FRACT_MIN__ (-0.5R-0.5R)__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLKDMA_CHENC_CH9SENC DMA_CHENC_CHxSENC(9)__USACCUM_MAX__ 0XFFFFP-8UHK__SFRACT_FBIT__ 7__INTMAX_WIDTH__ 64DMA_CHPRIC_CH6SPRIC DMA_CHPRIC_CHxSPRIC(6)__ARM_FEATURE_BF16_SCALAR_ARITHMETIC__SQ_IBIT__ 0__ORDER_PDP_ENDIAN__ 3412__SIZE_TYPE__ unsigned intDMA_CHALTC_CH4SALTC DMA_CHALTC_CHxSALTC(4)__FLT_HAS_DENORM__ 1__INT8_TYPE__ signed charsrc_startDI_MEM_INFO_FLASH MMIO16(DI_BASE + 0x1F8)LCD_BASE (PERIPH_BASE + 0x8A000)__USACCUM_MIN__ 0.0UHK__FLT32_DECIMAL_DIG__ 9__GCC_ATOMIC_LLONG_LOCK_FREE 1__DECIMAL_DIG__ 17__LDBL_MIN_EXP__ (-1021)INT_FAST16_MIN__LDBL_MANT_DIG__ 53DMA_CHUSEBURSTC_CH1SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(1)INT64_MIN (-INT64_MAX - 1)DMA_CH_CTRL_SIGSEL_TIMER1CC0 1__UINT8_C(c) cDI_DAC0_CAL_1V25 MMIO32(DI_BASE + 0x1C8)__INT16_TYPE__ short intDMA_CHENS_CH0SENS DMA_CHENS_CHxSENS(0)DMA_STATUS_STATE_RDSRCDATA 4__FLT64_MAX__ 1.7976931348623157e+308F64dma_desc_set_dest_sizeDI_AUXHFRCO_CALIB_BAND_21 MMIO8(DI_BASE + 0x1D8)DMA_RECTx(i) MMIO32(DMA_BASE + 0x1060 + ((i) * 0x4))BIT24 (1<<24)DMA_CHENC_CH7SENC DMA_CHENC_CHxSENC(7)DMA_CHWAITSTATUS_CH6WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(6)DMA_DESC_CH_CFG_DEST_INC_WORD DMA_DESC_CH_CFG_DEST_INC(2)DI_HFRCO_CALIB_BAND_21 MMIO8(DI_BASE + 0x1E0)INT_FAST64_MAX __INT_FAST64_MAX____GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1__STDC_HOSTED__ 1__ULLFRACT_FBIT__ 64DMA_IFC_CH1DONE DMA_IFC_CHxDONE(1)GNU C99 12.2.1 20221205 -mcpu=cortex-m3 -mthumb -mfloat-abi=soft -march=armv7-m -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sections__INT_FAST64_TYPE__ long long int__WINT_TYPE__ unsigned intDMA_CHENS MMIO32(DMA_BASE + 0x028)DMA_RDS MMIO32(DMA_BASE + 0x1014)DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV 0dma_calc_end_from_start__ARM_FEATURE_LDREX 7INT32_MIN (-INT32_MAX - 1)__FLT32_MAX_10_EXP__ 38DMA_CHWAITSTATUS_CH8WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(8)DMA_CHUSEBURSTC_CH3SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(3)DMA_CHALTC_CHxSALTC(i) (1 << (i))__USFRACT_MAX__ 0XFFP-8UHR__UINTPTR_MAX__ 0xffffffffUDMA_CH_CTRL_SOURCESEL_UART1 0b101101AES_BASE (PERIPH_BASE + 0xE0000)DMA_DESC_CH_CFG_CYCLE_CTRL_INVALD DMA_DESC_CH_CFG_CYCLE_CTRL(0)dma_desc_enable_next_useburstDMA_IF_CH3DONE DMA_IF_CHxDONE(3)DMA_CHSWREQ_CH10SWREQ DMA_CHSWREQ_CHxSWREQ(10)UINT32_MAX __UINT32_MAX__DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 2DI_CAL_TEMP_0 MMIO8(DI_BASE + 0x1B2)dma_enable_burst_onlyDMA_CHREQMASKC_CH2SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(2)__ULFRACT_FBIT__ 32DMA_STATUS_STATE_RDSRCENDPTR 2__FLT64_MIN_10_EXP__ (-307)__GNUC_EXECUTION_CHARSET_NAME "UTF-8"BIT10 (1<<10)__INT_FAST64_WIDTH__ 64__STDC_VERSION__ 199901LINT_LEAST64_MAX __INT_LEAST64_MAX__dma_desc_get_user_dataDMA_CH_CTRL_SIGSEL_USART0TXBL 1DMA_IFC_CH8DONE DMA_IFC_CHxDONE(8)DMA_CHSWREQ_CH0SWREQ DMA_CHSWREQ_CHxSWREQ(0)__SFRACT_EPSILON__ 0x1P-7HR__INT32_C(c) c ## Ldma_mem__ORDER_BIG_ENDIAN__ 4321__USACCUM_FBIT__ 8__USA_FBIT__ 16__SQ_FBIT__ 31DMA_STATUS_STATE_DONE 9DWT_BASE (PPBI_BASE + 0x1000)INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)DMA_DESC_CH_CFG_CYCLE_CTRL_SHIFT (0)DMA_CHREQMASKS_CH1SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(1)DMA_CH_CTRL_SOURCESEL_USART1 0b001101DMA_CH_CTRL_SIGSEL_USART_TXBL 1__UHQ_FBIT__ 16DMA_IFS_CH3DONE DMA_IFS_CHxDONE(3)__FLT64_MIN_EXP__ (-1021)DMA_CH6_CTRL DMA_CHx_CTRL(6)__PTRDIFF_WIDTH__ 32DMA_RDS_RDSCH6 DMA_RDS_RDSCHx(6)__UINT_FAST8_MAX__ 0xffffffffUdma_get_request_flagdma_desc_set_dest_incUINT16_C(c) __UINT16_C(c)DI_HFRCO_CALIB_BAND_14 MMIO8(DI_BASE + 0x1DF)DMA_CHALTS_CH8SALTS DMA_CHALTS_CHxSALTS(8)DMA_MODE_MEM_SCAT_GATH_PRIMDMA_DESC_CH_CFG_SRC_SIZE_NOINC DMA_DESC_CH_CFG_SRC_SIZE(3)__INT_FAST16_WIDTH__ 32INTMAX_C__VERSION__ "12.2.1 20221205"DMA_CH_CTRL_SIGSEL_ADC_SINGLE 0__VFP_FP__ 1__LLFRACT_MIN__ (-0.5LLR-0.5LLR)INT_FAST8_MAXDMA_CHREQMASKC_CH10SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(10)DMA_IEN_CH5DONE DMA_IEN_CHxDONE(5)DMA_CH4__UINT_FAST16_MAX__ 0xffffffffUDMA_IF_CHxDONE(x) (1 << (x))__INTPTR_TYPE__ int__INTPTR_MAX__ 0x7fffffffINT64_C(c) __INT64_C(c)DMA_DESC_CH_CFG_SRC_SIZE_MASK (0x3 << DMA_DESC_CH_CFG_SRC_SIZE_SHIFT)DMA_CHALTS_CH1SALTS DMA_CHALTS_CHxSALTS(1)DMA_CHWAITSTATUS MMIO32(DMA_BASE + 0x010)__UFRACT_MIN__ 0.0UR__THUMB_INTERWORK__ 1DMA_CHALTS_CH0SALTS DMA_CHALTS_CHxSALTS(0)DMA_CHALTS MMIO32(DMA_BASE + 0x030)LESENSE_BASE (PERIPH_BASE + 0x8C000)DI_MEM_INFO_RAM MMIO16(DI_BASE + 0x1FA)__FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX__DMA_CHUSEBURSTC_CH7SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(7)DMA_IF_CH7DONE DMA_IF_CHxDONE(7)DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0__UINT_LEAST8_TYPE__ unsigned charDMA_CHPRIS_CH5SPRIC DMA_CHPRIS_CHxSPRIC(5)__ACCUM_FBIT__ 15dma_set_dest_address(ch,dest) dma_desc_set_dest_address(DMA_CTRLBASE, ch, dest)__UACCUM_IBIT__ 16long intUINT8_MAXDMA_CHSREQSTATUS_CH10SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(10)SIZE_MAX __SIZE_MAX__dma_generate_software_requestdma_set_count(ch,count) dma_desc_set_count(DMA_CTRLBASE, ch, count)__INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17DMA_IF_CH5DONE DMA_IF_CHxDONE(5)__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1DMA_STATUS_STATE_STALLED 8__FLT32X_EPSILON__ 2.2204460492503131e-16F32xDI_DI_CRC MMIO16(DI_BASE + 0x1B0)__ARM_ARCH_7M__ 1NVIC_BASE (SCS_BASE + 0x0100)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32DMA_RDS_RDSCH5 DMA_RDS_RDSCHx(5)dma_enable_done_interrupt__UINTMAX_C(c) c ## ULLDMA_CHUSEBURSTS MMIO32(DMA_BASE + 0x018)__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed charDMA_DESC_CH_CFG_R_POWER_MASK (0xF << DMA_DESC_CH_CFG_R_POWER_SHIFT)dma_set_r_power(ch,r_power) dma_desc_set_r_power(DMA_CTRLBASE, ch, r_power)__GCC_ATOMIC_BOOL_LOCK_FREE 2DMA_IFS MMIO32(DMA_BASE + 0x1004)BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON____FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX__DMA_IF_CH11DONE DMA_IF_CHxDONE(11)__UINTMAX_TYPE__ long long unsigned int__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRDMA_CH_CTRL_SIGSEL_TIMER0UFOF 0dma_set_alt_dest_inc(ch,inc) dma_desc_set_dest_inc(DMA_ALTCTRLBASE, ch, inc)BBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)BIT23 (1<<23)__GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"UINT_FAST8_MAX __UINT_FAST8_MAX____FLT32X_MIN_10_EXP__ (-307)DMA_CHREQMASKC_CHxSREQMASKC(i) (1 << (i))__ELF__ 1UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICDMA_CH_CTRL_SOURCESEL_TIMER3 0b011011LIBOPENCM3_CM3_COMMON_H __bool_true_false_are_defined 1DMA_CH_CTRL_SIGSEL_I2C1RXDATAV 0__DBL_IS_IEC_60559__ 2__UINT_FAST32_MAX__ 0xffffffffU__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4DMA_CH_CTRL_SIGSEL_DAC0CH0 0DMA_CH_CTRL_SIGSEL_AES_DATA_RD 2USART0_BASE (PERIPH_BASE + 0x0C000)DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 2DMA_CH_CTRL_SIGSEL_LEUART1TXBL 1DMA_IFC_CH9DONE DMA_IFC_CHxDONE(9)__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32DMA_CH_CTRL_SOURCESEL_USART2 0b001110DMA_CH_CTRL_SIGSEL_EBI_PXL_FULL 2DMA_LOOP1 DMA_LOOPx(1)DMA_CHSWREQ_CH11SWREQ DMA_CHSWREQ_CHxSWREQ(11)BIT27 (1<<27)DMA_CHREQMASKS_CH7SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(7)DMA_CH_CTRL_SIGSEL_TIMER_UFOF 0DI_DAC0_OPAOFFSET MMIO32(DI_BASE + 0x0A8)DMA_CH_CTRL_SIGSEL_TIMER3CC2 3__UTA_FBIT__ 64INTMAX_C(c) __INTMAX_C(c)UINTMAX_MAX__FLT_DECIMAL_DIG__ 9DI_MEM_INFO_PAGE_SIZE MMIO8(DI_BASE + 0x1E7)DMA_CH_CTRL_SIGSEL_I2C1TXBL 1DMA_CHREQSTATUS_CHxSREQSTATUS(i) (1 << (i))__INT_LEAST32_MAX__ 0x7fffffffLsigned charDMA_CH_CTRL_SIGSEL_MSCWDATA 0uint8_tINT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)INT32_C(c) __INT32_C(c)DMA_STATUS_STATE_IDLE 0__GNUC_STDC_INLINE__ 1DMA_CONFIG_EN (1 << 0)dma_enable_with_privileged_access__FRACT_FBIT__ 15DMA_CH_CTRL_SIGSEL_LEUART_TXEMPTY 2__FLT_HAS_QUIET_NAN__ 1DMA_DESC_CH_CFG_SRC_INC_NOINC DMA_DESC_CH_CFG_SRC_INC(3)__GNUC_PATCHLEVEL__ 1__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2DMA_CHREQMASKS MMIO32(DMA_BASE + 0x020)PTRDIFF_MIN__FLT32_MIN_EXP__ (-125)__UINT_LEAST16_MAX__ 0xffffDMA_RDS_RDSCH10 DMA_RDS_RDSCHx(10)UINTPTR_MAX __UINTPTR_MAX____ARM_ARCH_PROFILE 77DMA_CH_CTRL_SIGSEL_TIMER0CC0 1INT32_MAXDMA_MEM_NONEDMA_CHPRIS_CH1SPRIC DMA_CHPRIS_CHxSPRIC(1)DI_UNIQUE_1 MMIO32(DI_BASE + 0x1F4)DMA_CH7_CTRL DMA_CHx_CTRL(7)__FLT64_MAX_10_EXP__ 308MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MIN__INT_FAST32_WIDTH__ 32DI_CMU_LFRCOCTRL MMIO32(DI_BASE + 0x020)DMA_DESC_CH_CFG_DEST_INC_NOINC DMA_DESC_CH_CFG_DEST_INC(3)__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38__SIG_ATOMIC_TYPE__ intDMA_DESC_CH_CFG_DEST_INC_MASK (0x3 << DMA_DESC_CH_CFG_DEST_INC_SHIFT)__FRACT_MAX__ 0X7FFFP-15R__GCC_IEC_559 0INT_LEAST32_MAX __INT_LEAST32_MAX__DMA_DESC_CH_CFG_CYCLE_CTRL_PINGPONG DMA_DESC_CH_CFG_CYCLE_CTRL(3)UINTMAX_CDMA_CHUSEBURSTC_CHxSUSEBURSTC(i) (1 << (i))DI_DAC0_CAL_VDD MMIO32(DI_BASE + 0x1D0)__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5DMA_CHUSEBURSTS_CH2SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(2)DMA_ERRORC_ERRORC (1 << 0)dma_enabledma_disable_alt_next_useburst(ch) dma_desc_disable_alt_next_useburst(DMA_CTRLBASE, ch)DMA_IF_CH0DONE DMA_IF_CHxDONE(0)DMA_CHWAITSTATUS_CH7WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(7)DMA_CHREQMASKS_CH9SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(9)dma_clear_done_interrupt_flag__UINT16_MAX__ 0xffffdma_desc_set_src_sizeDMA_CHPRIC_CH11SPRIC DMA_CHPRIC_CHxSPRIC(11)__TQ_FBIT__ 127DI_UNIQUE_0 MMIO32(DI_BASE + 0x1F0)dma_set_dest_inc(ch,inc) dma_desc_set_dest_inc(DMA_CTRLBASE, ch, inc)DI_DAC0_CAL MMIO32(DI_BASE + 0x050)uint16_tDMA_CHPRIC_CH9SPRIC DMA_CHPRIC_CHxSPRIC(9)DMA_DESC_CH_CFG_SRC_INC_WORD DMA_DESC_CH_CFG_SRC_INC(2)DMA_CHREQSTATUS_CH8SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(8)__thumb2__ 1__ULLACCUM_FBIT__ 32dma_set_mode(ch,mode) dma_desc_set_mode(DMA_CTRLBASE, ch, mode)DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT 3_BoolDMA_CH_CTRL_SIGSEL_UART1RXDATAV 0__FLT_DENORM_MIN__ 1.4012984643248171e-45FINT_FAST32_MIN (-INT_FAST32_MAX - 1)DMA_CHSWREQ_CH3SWREQ DMA_CHSWREQ_CHxSWREQ(3)__STRICT_ANSI__ 1__LACCUM_EPSILON__ 0x1P-31LKI2C1_BASE (PERIPH_BASE + 0x0A400)UINT_LEAST8_MAXDMA_CH_CTRL_SIGSEL_EBIDDEMPTY 3DMA_CH_CTRL_SIGSEL_TIMER3CC0 1UINT8_C(c) __UINT8_C(c)DMA_CHWAITSTATUS_CH10WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(10)__SIZEOF_LONG_DOUBLE__ 8dma_set_alt_dest_size(ch,size) dma_desc_set_dest_size(DMA_ALTCTRLBASE, ch, size)DMA_R_POWER_16__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__DMA_CHUSEBURSTC_CH2SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(2)DMA_R_POWER_256__USA_IBIT__ 16DMA_CHALTC_CH3SALTC DMA_CHALTC_CHxSALTC(3)__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1src_endDMA_MODE_PERIPH_SCAT_GATH_PRIMDMA_DESC_CH_CFG_NEXT_USEBURST (1 << 3)__SFRACT_MAX__ 0X7FP-7HR__UINT_FAST64_TYPE__ long long unsigned intdma_desc_disable_next_useburstDMA_RECT_DSTSTRIDE_SHIFT (21)__FLT_MIN__ 1.1754943508222875e-38F__HA_FBIT__ 7__FDPIC__DMA_CHPRIS_CH4SPRIC DMA_CHPRIS_CHxSPRIC(4)DMA_CH8_CTRL DMA_CHx_CTRL(8)DMA_CH_CTRL_SOURCESEL_MSC 0b110000__FLT32_IS_IEC_60559__ 2UINT64_C(c) __UINT64_C(c)DMA_CH_CTRL_SIGSEL_SHIFT (0)INT_FAST64_MINDMA_DESC_CHx_USER_DATA(base,x) MMIO32(DMA_DESC_CHx_BASE(base, x) + 0x0C)__USFRACT_IBIT__ 0DMA_CTRL_PRDU (1 << 1)__LDBL_EPSILON__ 2.2204460492503131e-16LDMA_LOOPx(i) MMIO32(DMA_BASE + 0x1020 + ((i) * 0x4))signal__USFRACT_MIN__ 0.0UHR__ARM_NEON__UINT8_MAX__ 0xffACMP1_BASE (PERIPH_BASE + 0x01400)__LDBL_MAX_EXP__ 1024DMA_CHENS_CH10SENS DMA_CHENS_CHxSENS(10)DI_AUXHFRCO_CALIB_BAND_7 MMIO8(DI_BASE + 0x1D5)BIT7 (1<<7)__DBL_HAS_DENORM__ 1sourceDMA_CHREQSTATUS_CH9SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(9)DMA_DESC_CH_CFG_DEST_SIZE_WORD DMA_DESC_CH_CFG_DEST_SIZE(2)dma_get_alt_user_data(ch) dma_desc_get_user_data(DMA_ALTCTRLBASE, ch)__DA_FBIT__ 31BIT17 (1<<17)__GXX_ABI_VERSION 1017__INT_LEAST16_MAX__ 0x7fffDMA_MEM_HALF_WORDID_BASE (SCS_BASE + 0x0FD0)DMA_RECT_HEIGHT(v) (((v) << DMA_RECT_HEIGHT_SHIFT) & DMA_RECT_HEIGHT_MASK)DMA_DESC_CH_CFG_SRC_SIZE(v) (((v) << DMA_DESC_CH_CFG_SRC_SIZE_SHIFT) & DMA_DESC_CH_CFG_SRC_SIZE_MASK)DMA_CHREQMASKC_CH9SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(9)DMA_CHREQMASKS_CH3SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(3)INT_LEAST8_MAX __INT_LEAST8_MAX__DI_PART_FAMILY MMIO8(DI_BASE + 0x1FE)__UINT32_C(c) c ## ULdma_desc_set_r_powerTIMER2_BASE (PERIPH_BASE + 0x10800)__UACCUM_MIN__ 0.0UKUINT32_C(c) __UINT32_C(c)__FLT_EPSILON__ 1.1920928955078125e-7FDMA_CHENC_CH4SENC DMA_CHENC_CHxSENC(4)DMA_CH_CTRL_SIGSEL_EBI_DD_EMPTY 3dma_disable_priorityDMA_CHALTS_CH4SALTS DMA_CHALTS_CHxSALTS(4)DMA_CH_CTRL_SIGSEL_MASK (0xF << DMA_CH_CTRL_SIGSEL_SHIFT)__PTRDIFF_TYPE__ int__ARM_ARCH_ISA_THUMBPCNT2_BASE (PERIPH_BASE + 0x86800)DMA_IFS_CH11DONE DMA_IFS_CHxDONE(11)DMA_STATUS_STATE_SHIFT (4)DMA_IEN_CH7DONE DMA_IEN_CHxDONE(7)DMA_R_POWER_32DMA_CHREQMASKC_CH5SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(5)__ARM_FEATURE_MATMUL_INT8__UINT8_TYPE__ unsigned charLIBOPENCM3_CM3_MEMORYMAP_H __GCC_ATOMIC_SHORT_LOCK_FREE 2DMA_DESC_CH_CFG_DEST_SIZE(v) (((v) << DMA_DESC_CH_CFG_DEST_SIZE_SHIFT) & DMA_DESC_CH_CFG_DEST_SIZE_MASK)DI_ADC0_CAL_2XVDD MMIO16(DI_BASE + 0x1BC)DMA_CH_CTRL_SOURCESEL_LESENSE 0b110010DMA_DESC_CHx_SRC_DATA_END_PTR(base,x) MMIO32(DMA_DESC_CHx_BASE(base, x) + 0x00)DI_EMU_BUBODUNREGCAL MMIO32(DI_BASE + 0x0C8)DMA_CH_CTRL_SIGSEL_LEUART0TXBL 1__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1DMA_ALTCTRLBASE MMIO32(DMA_BASE + 0x00C)DMA_CHPRIS_CH7SPRIC DMA_CHPRIS_CHxSPRIC(7)__LACCUM_FBIT__ 31SCS_BASE (PPBI_BASE + 0xE000)DMA_CH_CTRL_SIGSEL_LEUART_RXDATAV 0DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 2__FLT32_MIN__ 1.1754943508222875e-38F32__FLT32_HAS_QUIET_NAN__ 1__LDBL_HAS_INFINITY__ 1dma_modeDMA_CH_CTRL_SIGSEL_DAC_CH0 0__TA_FBIT__ 63LEUART1_BASE (PERIPH_BASE + 0x84400)MMIO8(addr) (*(volatile uint8_t *)(addr))DMA_CHPRIS_CH2SPRIC DMA_CHPRIS_CHxSPRIC(2)DMA_CHREQMASKS_CH10SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(10)__FLT32X_MAX_10_EXP__ 308dma_set_alt_user_data(ch,user_data) dma_desc_set_user_data(DMA_ALTCTRLBASE, ch, user_data)__ARM_ARCH_EXT_IDIV__ 1__ARM_PCS 1DMA_CHSREQSTATUS_CH2SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(2)bool _BoolDMA_IF_ERR (1UL << 31)UINTMAX_MAX __UINTMAX_MAX__DMA_CH_CTRL_SIGSEL_MSC_WDATA 0__SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)DMA_CHSREQSTATUS_CHxSREQSTATUS(i) (1 << (i))DMA_CHSREQSTATUS_CH8SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(8)__UINT_LEAST8_MAX__ 0xffMSC_BASE (PERIPH_BASE + 0xC0000)EMU_BASE (PERIPH_BASE + 0xC6000)DMA_CH_CTRL_SIGSEL_USART2RXDATAV 0BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)DMA_CHREQSTATUS MMIO32(DMA_BASE + 0xE10)INT16_MAX __INT16_MAX__DMA_CH_CTRL_SOURCESEL_MASK (0x3F << DMA_CH_CTRL_SOURCESEL_SHIFT)__PRAGMA_REDEFINE_EXTNAME 1DMA_CH_CTRL_SIGSEL(v) (((v) << DMA_CH_CTRL_SIGSEL_SHIFT) & DMA_CH_CTRL_SIGSEL_MASK)GPIO_BASE (PERIPH_BASE + 0x06000)__FLT32X_IS_IEC_60559__ 2DMA_CH_CTRL_SOURCESEL_DAC0 0b001010DMA_CH_CTRL_SIGSEL_EBI_PXL1_EMPTY 1DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))UINT32_MAXDMA_STATUS_EN (1 << 0)DMA_IFS_CH10DONE DMA_IFS_CHxDONE(10)DMA_IF_CH4DONE DMA_IF_CHxDONE(4)__INT_LEAST16_WIDTH__ 16DMA_CONFIG_CHPROT (1 << 5)DMA_IFC_CH6DONE DMA_IFC_CHxDONE(6)__DEC_EVAL_METHOD__ 2DMA_CHREQMASKS_CH2SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(2)__ARM_FEATURE_FP16_FMLDMA_CHALTC_CH11SALTC DMA_CHALTC_CHxSALTC(11)DMA_CH_CTRL_SOURCESEL_TIMER0 0b011000DMA_CHSWREQ_CH9SWREQ DMA_CHSWREQ_CHxSWREQ(9)DMA_ERRORC MMIO32(DMA_BASE + 0x04C)__USFRACT_EPSILON__ 0x1P-8UHRDMA_LOOP_WIDTH_SHIFT (0)DMA_DESC_CH_CFG_SRC_SIZE_HALFWORD DMA_DESC_CH_CFG_SRC_SIZE(1)DMA_DESC_CHx_BASE(base,x) ((base) + ((x) * DMA_DESC_CH_SIZE))__USFRACT_FBIT__ 8DI_AUXHFRCO_CALIB_BAND_28 MMIO8(DI_BASE + 0x1D9)CORESIGHT_LSR_SLI (1<<0)DMA_CHALTC_CH2SALTC DMA_CHALTC_CHxSALTC(2)DMA_CH_CTRL_SOURCESEL_TIMER1 0b011001DMA_CH_CTRL_SOURCESEL_UART0 0b101100dma_set_signal__INT_LEAST8_WIDTH__ 8DMA_DESC_CH_CFG_R_POWER_SHIFT (14)WDOG_BASE (PERIPH_BASE + 0x88000)__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX__DMA_CH_CTRL_SIGSEL_USART_RXDATAVRIGHT 3__UINT32_MAX__ 0xffffffffULDMA_CHPRIS_CH0SPRIC DMA_CHPRIS_CHxSPRIC(0)DI_HFRCO_CALIB_BAND_11 MMIO8(DI_BASE + 0x1DE)DMA_CH_CTRL_SOURCESEL_NONE 0b000000DMA_CHWAITSTATUS_CH4WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(4)DMA_STATUS MMIO32(DMA_BASE + 0x000)DMA_CHUSEBURSTS_CH11SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(11)__INT_LEAST8_MAX__ 0x7fDMA_CHUSEBURSTS_CH0SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(0)__GCC_ATOMIC_POINTER_LOCK_FREE 2__ARM_FEATURE_QBIT 1__ARM_FEATURE_CLZ 1dma_set_source__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXDMA_CH_CTRL_SOURCESEL_LEUART1 0b010001UINT_LEAST32_MAX __UINT_LEAST32_MAX__DMA_CHUSEBURSTC_CH4SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(4)__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024DMA_CHREQSTATUS_CH0SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(0)BIT21 (1<<21)__UINT_LEAST32_MAX__ 0xffffffffUL__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)n_minus_1dma_desc_set_src_inc__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1__ACCUM_MAX__ 0X7FFFFFFFP-15KDMA_CHREQMASKC_CH3SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(3)__INT8_MAX__ 0x7fdma_get_wait_on_request_flagDMA_CHALTS_CHxSALTS(i) (1 << (i))DMA_CHALTC_CH6SALTC DMA_CHALTC_CHxSALTC(6)__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16DMA_MODE_PERIPH_SCAT_GATH_ALT__SHRT_WIDTH__ 16__GCC_IEC_559_COMPLEX 0__ARM_FEATURE_MVEDMA_STATUS_STATE_WAITREQCLR 6__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intDMA_CHREQSTATUS_CH10SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(10)DMA_CH_CTRL_SIGSEL_TIMER0CC1 2__SOFTFP__ 1TIMER3_BASE (PERIPH_BASE + 0x10C00)UINT_LEAST16_MAX __UINT_LEAST16_MAX__I2C0_BASE (PERIPH_BASE + 0x0A000)INT_FAST32_MIN__FLT_EVAL_METHOD_TS_18661_3__ 0DMA_DESC_CH_CFG_DEST_SIZE_MASK (0x3 << DMA_DESC_CH_CFG_DEST_SIZE_SHIFT)__SCHAR_WIDTH__ 8dest_startBIT18 (1<<18)DMA_R_POWER_64SIZE_MAX__UINT_FAST8_TYPE__ unsigned int__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RDMA_CH0DMA_CH1DMA_CH2DMA_CH3__INT32_MAX__ 0x7fffffffLDMA_CH5DMA_CH6DMA_CH7DMA_CH8DMA_CH9BIT30 (1<<30)CMU_BASE (PERIPH_BASE + 0xC8000)__APCS_32__ 1__ARM_FEATURE_BF16_VECTOR_ARITHMETICDMA_IF_CH1DONE DMA_IF_CHxDONE(1)PPBI_BASE (0xE0000000U)DI_HFRCO_CALIB_BAND_7 MMIO8(DI_BASE + 0x1DD)__FLT32_MANT_DIG__ 24ACMP0_BASE (PERIPH_BASE + 0x01000)INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32dma_set_src_size(ch,size) dma_desc_set_src_size(DMA_CTRLBASE, ch, size)DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT 3DMA_CHREQSTATUS_CH2SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(2)__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN__DI_HFRCO_CALIB_BAND_28 MMIO8(DI_BASE + 0x1E1)DMA_DESC_CH_CFG_DEST_SIZE_NOINC DMA_DESC_CH_CFG_DEST_SIZE(3)INT8_MAX __INT8_MAX__DMA_CH_CTRL_SOURCESEL_AES 0b110001dma_enable_alternate_structureDMA_CHALTS_CH5SALTS DMA_CHALTS_CHxSALTS(5)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2DMA_CH_CTRL_SIGSEL_TIMER2CC0 1__DBL_MAX_EXP__ 1024__ATOMIC_RELEASE 3DMA_CH_CTRL_SIGSEL_USART2TXEMPTY 2UINT_FAST8_MAX__FLT_MANT_DIG__ 24DMA_CHPRIC_CH3SPRIC DMA_CHPRIC_CHxSPRIC(3)__UDQ_IBIT__ 0DMA_CH_CTRL_SIGSEL_EBI_PXLx_EMPTY(x) DMA_CH_CTRL_SIGSEL(x)DMA_CHUSEBURSTC_CH9SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(9)__OPTIMIZE_SIZE__ 1__OPTIMIZE__ 1DMA_CH_CTRL_SIGSEL_TIMER1CC1 2dma_set_src_address(ch,src) dma_desc_set_src_address(DMA_CTRLBASE, ch, src)DMA_CHENC_CH2SENC DMA_CHENC_CHxSENC(2)__FLT64_NORM_MAX__ 1.7976931348623157e+308F64DMA_CHPRIS_CH8SPRIC DMA_CHPRIS_CHxSPRIC(8)UINTPTR_MAXDI_DAC0_OPACTRL MMIO32(DI_BASE + 0x0A0)ADC0_BASE (PERIPH_BASE + 0x02000)__INT64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_SAT 1DMA_CH_CTRL_SIGSEL_UART0RXDATAV 0DMA_CHREQMASKC_CH11SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(11)__ULLFRACT_IBIT__ 0DMA_IFC_CH0DONE DMA_IFC_CHxDONE(0)DMA_IFS_ERR (1 << 31)DMA_STATUS_STATE_RDDSTENDPTR 3DI_EMU_BUACT MMIO32(DI_BASE + 0x0B8)DMA_DESC_CH_CFG_DEST_PROT_CTRL_SHIFT (21)DMA_CHx_CTRL(i) MMIO32(DMA_BASE + 0x1100 + ((i) * 0x4))DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0__GNUC__ 12DI_PART_NUMBER MMIO16(DI_BASE + 0x1FC)WCHAR_MAX__LONG_WIDTH__ 32TIMER1_BASE (PERIPH_BASE + 0x10400)__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16DMA_IEN_CH3DONE DMA_IEN_CHxDONE(3)__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0UDMA_CHENS_CH3SENS DMA_CHENS_CHxSENS(3)__UQQ_IBIT__ 0DMA_CHPRIC_CH7SPRIC DMA_CHPRIC_CHxSPRIC(7)CORESIGHT_LSR_OFFSET 0xfb4DMA_CH_CTRL_SOURCESEL_SHIFT (16)__GCC_ATOMIC_LONG_LOCK_FREE 2__ULACCUM_MIN__ 0.0ULK__LDBL_MAX__ 1.7976931348623157e+308L__ARM_ARCH 7dma_set_src_inc(ch,inc) dma_desc_set_src_inc(DMA_CTRLBASE, ch, inc)DMA_CHUSEBURSTS_CH10SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(10)DMA_CHALTC_CH7SALTC DMA_CHALTC_CHxSALTC(7)DI_AUXHFRCO_CALIB_BAND_11 MMIO8(DI_BASE + 0x1D6)__FLT_RADIX__ 2BIT3 (1<<3)long long intCORESIGHT_LAR_KEY 0xC5ACCE55DMA_IEN_CHxDONE(x) (1 << (x))__ARM_FEATURE_CMSERMU_BASE (PERIPH_BASE + 0xCA000)INTPTR_MAXDMA_DESC_CH_CFG_DEST_SIZE_BYTE DMA_DESC_CH_CFG_DEST_SIZE(0)__LDBL_HAS_QUIET_NAN__ 1DMA_DESC_CH_CFG_DEST_INC(v) (((v) << DMA_DESC_CH_CFG_DEST_INC_SHIFT) & DMA_DESC_CH_CFG_DEST_INC_MASK)DMA_CHUSEBURSTC_CH6SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(6)__LONG_LONG_WIDTH__ 64BIT6 (1<<6)DMA_CH_CTRL_SIGSEL_UART0TXEMPTY 2DMA_DESC_CH_CFG_DEST_SIZE_SHIFT (28)dma_enable_bus_error_interruptdma_set_done_interrupt_flag__ARM_FP__HA_IBIT__ 8__ARM_FEATURE_DSP__INTPTR_WIDTH__ 32LEUART0_BASE (PERIPH_BASE + 0x84000)DI_ADC0_CAL MMIO32(DI_BASE + 0x040)DMA_IEN_CH1DONE DMA_IEN_CHxDONE(1)BIT9 (1<<9)__FLT32X_MIN__ 2.2250738585072014e-308F32xDMA_IFS_CH1DONE DMA_IFS_CHxDONE(1)INTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024UINT16_MAXBIT20 (1<<20)__FLT64_MIN__ 2.2250738585072014e-308F64__INT_LEAST64_MAX__ 0x7fffffffffffffffLLDMA_CHPRIS_CH10SPRIC DMA_CHPRIS_CHxSPRIC(10)DMA_DESC_CH_CFG_CYCLE_CTRL_PERIPH_SCAT_GATH_ALT DMA_DESC_CH_CFG_CYCLE_CTRL(7)__ARM_ARCH_PROFILE__INT64_TYPE__ long long int__LFRACT_FBIT__ 31__CHAR_BIT__ 8DMA_CHWAITSTATUS_CH3WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(3)__SIZEOF_WCHAR_T__ 4dma_enable_single_and_burstDMA_CHREQSTATUS_CH7SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(7)DMA_IFS_CH9DONE DMA_IFS_CHxDONE(9)maskDMA_CHSWREQ_CH8SWREQ DMA_CHSWREQ_CHxSWREQ(8)DMA_CHSREQSTATUS_CH3SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(3)DMA_CH_CTRL_SIGSEL_UART0TXBL 1DMA_CHENC MMIO32(DMA_BASE + 0x02C)DMA_DESC_CH_CFG_SRC_PROT_CTRL_SHIFT (18)__UFRACT_MAX__ 0XFFFFP-16URdma_set_alt_mode(ch,mode) dma_desc_set_mode(DMA_ALTCTRLBASE, ch, mode)DMA_CHPRIS_CH6SPRIC DMA_CHPRIS_CHxSPRIC(6)INT64_MAXFPB_BASE (PPBI_BASE + 0x2000)dma_set_alt_src_address(ch,src) dma_desc_set_src_address(DMA_ALTCTRLBASE, ch, src)__UHA_FBIT__ 8INT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0EBI_BASE (PERIPH_BASE + 0x08000)STIR_BASE (SCS_BASE + 0x0F00)DMA_CH_CTRL_SIGSEL_EBIPXL1EMPTY 1__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__DI_AUXHFRCO_CALIB_BAND_1 MMIO8(DI_BASE + 0x1D4)DMA_CH_CTRL_SIGSEL_EBI_PXL0_EMPTY 0SYS_TICK_BASE (SCS_BASE + 0x0010)DMA_RDS_RDSCH7 DMA_RDS_RDSCHx(7)DMA_CHENS_CH5SENS DMA_CHENS_CHxSENS(5)count__UFRACT_FBIT__ 16BURTC_BASE (PERIPH_BASE + 0x81000)INT16_MIN (-INT16_MAX - 1)DMA_CH_CTRL_SIGSEL_AESDATARD 2dma_disable_alternate_structure__LDBL_MAX_10_EXP__ 308DMA_DESC_CH_SIZE (0x4 * 0x4)DMA_CHREQMASKC_CH6SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(6)DMA_IFS_CH7DONE DMA_IFS_CHxDONE(7)DMA_DESC_CHx_CFG(base,x) MMIO32(DMA_DESC_CHx_BASE(base, x) + 0x08)__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)dma_get_bus_error_flagdma_desc_set_count__SIZEOF_LONG_LONG__ 8DMA_DESC_CH_CFG_CYCLE_CTRL_AUTOREQUEST DMA_DESC_CH_CFG_CYCLE_CTRL(2)unsigned intDMA_CH_CTRL_SIGSEL_LEUART_TXBL 1DMA_CH_CTRL_SIGSEL_TIMER_CC1 DMA_CH_CTRL_SIGSEL_TIMER_CCx(1)DMA_DESC_CH_CFG_SRC_SIZE_SHIFT (24)DMA_STATUS_CHNUM_SHIFT (16)__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1DMA_RECT_DSTSTRIDE(v) (((v) << DMA_RECT_DSTSTRIDE_SHIFT) & DMA_RECT_DSTSTRIDE_MASK)__USACCUM_IBIT__ 8DMA_CHWAITSTATUS_CH5WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(5)ITM_BASE (PPBI_BASE + 0x0000)DMA_CHENS_CH11SENS DMA_CHENS_CHxSENS(11)/build/libopencm3/lib/efm32/lg__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UKDMA_CH_CTRL_SIGSEL_I2C_TXBL 1DMA_CHENS_CH8SENS DMA_CHENS_CHxSENS(8)DMA_IFS_CH4DONE DMA_IFS_CHxDONE(4)DMA_CH_CTRL_SIGSEL_DAC_CHx(x) DMA_CH_CTRL_SIGSEL(x)DMA_CTRLBASE MMIO32(DMA_BASE + 0x008)__FLT_EVAL_METHOD__ 0DMA_CHREQMASKS_CH4SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(4)dma_set_alt_dest_address(ch,dest) dma_desc_set_dest_address(DMA_ALTCTRLBASE, ch, dest)DMA_CHALTS_CH6SALTS DMA_CHALTS_CHxSALTS(6)__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32DMA_CH_CTRL_SIGSEL_UART1TXBL 1__ARM_FEATURE_LDREXDMA_IFS_CH5DONE DMA_IFS_CHxDONE(5)DMA_CH_CTRL_SOURCESEL_ADC0 0b001000__UQQ_FBIT__ 8INT16_Cdma_enable_next_useburst(ch) dma_desc_enable_next_useburst(DMA_CTRLBASE, ch)__ARM_FP16_ARGS__UACCUM_MAX__ 0XFFFFFFFFP-16UKINT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX____LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4__STDC__ 1DI_ADC0_CAL_VDD MMIO16(DI_BASE + 0x1B8)DMA_CHPRIS_CH9SPRIC DMA_CHPRIS_CHxSPRIC(9)__ARM_FEATURE_IDIV 1dma_enable_periph_request__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__dma_disable_channelDMA_CHUSEBURSTC MMIO32(DMA_BASE + 0x01C)DMA_CHWAITSTATUS_CH9WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(9)DMA_MODE_PING_PONG__ARM_FEATURE_COPROC 15DMA_IFC_CH7DONE DMA_IFC_CHxDONE(7)DMA_CHUSEBURSTS_CH5SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(5)UINT64_MAX __UINT64_MAX__dma_disableINT8_MINdma_enable_alt_next_useburst(ch) dma_desc_enable_alt_next_useburst(DMA_CTRLBASE, ch)PERIPH_BASE (0x40000000U)true 1DMA_RECT_HEIGHT_SHIFT (0)DMA_BASE (PERIPH_BASE + 0xC2000)UINTMAX_C(c) __UINTMAX_C(c)DMA_CHPRIC_CH0SPRIC DMA_CHPRIC_CHxSPRIC(0)__INT_FAST32_TYPE__ int__FLT32X_MIN_EXP__ (-1021)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)dma_disable_bus_error_interrupt__GCC_ATOMIC_CHAR_LOCK_FREE 2BIT28 (1<<28)DMA_DESC_CH_CFG_SRC_PROT_CTRL(v) (((v) << DMA_DESC_CH_CFG_SRC_PROT_CTRL_SHIFT) & DMA_DESC_CH_CFG_SRC_PROT_CTRL_SHIFT)DMA_IFC_CH11DONE DMA_IFC_CHxDONE(11)__LFRACT_EPSILON__ 0x1P-31LRDMA DMA_BASEDMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY 2DMA_CHENC_CH6SENC DMA_CHENC_CHxSENC(6)dma_get_user_data(ch) dma_desc_get_user_data(DMA_CTRLBASE, ch)DMA_RDS_RDSCH11 DMA_RDS_RDSCHx(11)dma_desc_set_dest_address__ARM_SIZEOF_MINIMAL_ENUM 1DMA_CH11_CTRL DMA_CHx_CTRL(11)__FLT32X_NORM_MAX__ 1.7976931348623157e+308F32x__arm__ 1dma_set_bus_error_interrupt_flagDMA_CH_CTRL_SOURCESEL_EBI 0b110011DMA_RECT_HEIGHT_MASK (0x3FF << DMA_RECT_HEIGHT_SHIFT)__FLT32_MIN_10_EXP__ (-37)DMA_CH_CTRL_SIGSEL_EBIPXLFULL 2DMA_CH_CTRL_SIGSEL_TIMER0CC2 3DI_CMU_HFRCOCTRL MMIO32(DI_BASE + 0x028)MMIO64(addr) (*(volatile uint64_t *)(addr))DI_ADC0_TEMP_0_READ_1V25 MMIO16(DI_BASE + 0x1BE)__ARM_FP16_FORMAT_ALTERNATIVEDMA_IFS_CH2DONE DMA_IFS_CHxDONE(2)__LDBL_NORM_MAX__ 1.7976931348623157e+308LDI_ADC0_BIASPROG MMIO32(DI_BASE + 0x048)DMA_CHWAITSTATUS_CHxWAITSTATUS(i) (1 << (i))../common/dma_common.c__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)DMA_CHALTS_CH10SALTS DMA_CHALTS_CHxSALTS(10)DMA_RDS_RDSCHx(i) (1 << (i))dest_endDMA_CHENC_CH5SENC DMA_CHENC_CHxSENC(5)PRS_BASE (PERIPH_BASE + 0xCC000)DMA_CHALTS_CH9SALTS DMA_CHALTS_CHxSALTS(9)DMA_CHUSEBURSTS_CH9SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(9)DMA_CHENS_CH7SENS DMA_CHENS_CHxSENS(7)DMA_RDS_RDSCH4 DMA_RDS_RDSCHx(4)DMA_CHSREQSTATUS_CH6SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(6)DMA_STATUS_STATE_WRDSTDATA 5DMA_CH_CTRL_SIGSEL_AES_XOR_DATA_WR 1__UDQ_FBIT__ 64__ARM_FEATURE_QRDMX__ARM_ARCH_ISA_THUMB 2dma_disable_loopBIT14 (1<<14)__WINT_WIDTH__ 32SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__TIMER0_BASE (PERIPH_BASE + 0x10000)UART0_BASE (PERIPH_BASE + 0x0E000)__USQ_IBIT__ 0MMIO16(addr) (*(volatile uint16_t *)(addr))BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN__DMA_CH_CTRL_SIGSEL_TIMER2CC1 2__SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)dma_set_user_data(ch,user_data) dma_desc_set_user_data(DMA_CTRLBASE, ch, user_data)__DBL_MIN_EXP__ (-1021)DMA_DESC_CH_CFG_N_MINUS_1_SHIFT (4)DMA_CHPRIC_CH8SPRIC DMA_CHPRIC_CHxSPRIC(8)DMA_CHUSEBURSTC_CH0SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(0)DMA_CHSWREQ_CHxSWREQ(i) (1 << (i))INT8_MIN (-INT8_MAX - 1)DMA_CH9_CTRL DMA_CHx_CTRL(9)DMA_CH_CTRL_SOURCESEL_I2C1 0b010101DMA_CH_CTRL_SIGSEL_TIMER_CC2 DMA_CH_CTRL_SIGSEL_TIMER_CCx(3)__FLT32_DIG__ 6DMA_CHSWREQ_CH5SWREQ DMA_CHSWREQ_CHxSWREQ(5)INT_LEAST16_MAXDMA_CHUSEBURSTC_CH8SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(8)DMA_IEN_CH2DONE DMA_IEN_CHxDONE(2)DMA_CHENC_CH8SENC DMA_CHENC_CHxSENC(8)BIT15 (1<<15)DMA_CHREQSTATUS_CH4SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(4)dma_enable_loopDMA_DESC_CH_CFG_DEST_INC_HALFWORD DMA_DESC_CH_CFG_DEST_INC(1)DMA_CH_CTRL_SIGSEL_TIMER3CC1 2__LDBL_HAS_DENORM__ 1__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)__UINT64_C(c) c ## ULLINT16_MAXDMA_RECT0 DMA_RECT(0)__ARM_FEATURE_CRYPTODMA_RECT_SRCSTRIDE(v) (((v) << DMA_RECT_SRCSTRIDE_SHIFT) & DMA_RECT_SRCSTRIDE_MASK)DMA_CHREQMASKC_CH4SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(4)__INT_LEAST32_TYPE__ long intdma_clear_bus_error_interrupt_flagDMA_CHSWREQ_CH7SWREQ DMA_CHSWREQ_CHxSWREQ(7)DMA_CHALTC_CH8SALTC DMA_CHALTC_CHxSALTC(8)__USQ_FBIT__ 32BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__FRACT_IBIT__ 0DI_CMU_AUXHFRCOCTRL MMIO32(DI_BASE + 0x030)DMA_CHWAITSTATUS_CH0WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(0)UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2dma_disable_next_useburst(ch) dma_desc_disable_next_useburst(DMA_CTRLBASE, ch)DMA_RECT_DSTSTRIDE_MASK (0x7FF << DMA_RECT_DSTSTRIDE_SHIFT)BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234size__FLT_NORM_MAX__ 3.4028234663852886e+38FDI_HFRCO_CALIB_BAND_1 MMIO8(DI_BASE + 0x1DC)DI_CMU_LCDCTRL MMIO32(DI_BASE + 0x078)long long unsigned intDMA_CHUSEBURSTS_CH4SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(4)__FLT_MIN_10_EXP__ (-37)BIT31 (1<<31)__ULACCUM_IBIT__ 32__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__ULLACCUM_EPSILON__ 0x1P-32ULLKUSB_BASE (PERIPH_BASE + 0xC4000)__DQ_FBIT__ 63INT_LEAST64_MAX__SACCUM_IBIT__ 8DMA_CONFIG MMIO32(DMA_BASE + 0x004)LIBOPENCM3_EFM32_MEMORYMAP_H DMA_CH_CTRL_SIGSEL_UART_TXEMPTY 2INT_LEAST8_MINDMA_RECT_SRCSTRIDE_MASK (0x7FF << DMA_RECT_SRCSTRIDE_SHIFT)DMA_CH_CTRL_SIGSEL_UART_RXDATAV 0BIT29 (1<<29)DMA_DESC_CH_CFG_CYCLE_CTRL_MASK (0x7 << DMA_DESC_CH_CFG_CYCLE_CTRL_SHIFT)__INT_FAST16_TYPE__ intDMA_CHSREQSTATUS_CH4SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(4)__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)__ULFRACT_MAX__ 0XFFFFFFFFP-32ULR__UINT_LEAST16_TYPE__ short unsigned intDMA_IFC_ERR (1 << 31)__ARM_FEATURE_FMA__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned intDMA_CHUSEBURSTC_CH11SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(11)DMA_DESC_CH_CFG_SRC_INC_BYTE DMA_DESC_CH_CFG_SRC_INC(0)__FLT32X_DIG__ 15DMA_CH_CTRL_SOURCESEL_TIMER2 0b011010DMA_DESC_CH_CFG_SRC_SIZE_BYTE DMA_DESC_CH_CFG_SRC_SIZE(0)__UTQ_FBIT__ 128DMA_CH_CTRL_SIGSEL_AES_DATA_WR 0DMA_IFC_CH3DONE DMA_IFC_CHxDONE(3)__LLACCUM_EPSILON__ 0x1P-31LLK__FINITE_MATH_ONLY__ 0RTC_BASE (PERIPH_BASE + 0x80000)DMA_DESC_CH_CFG_N_MINUS_1_MASK (0x3FF << DMA_DESC_CH_CFG_N_MINUS_1_SHIFT)dma_set_alt_count(ch,count) dma_desc_set_count(DMA_ALTCTRLBASE, ch, count)DMA_DESC_CH_CFG_SRC_INC(v) (((v) << DMA_DESC_CH_CFG_SRC_INC_SHIFT) & DMA_DESC_CH_CFG_SRC_INC_MASK)DMA_CH_CTRL_SIGSEL_ADC_SCAN 1PTRDIFF_MAX __PTRDIFF_MAX____SIZEOF_SHORT__ 2DMA_DESC_CHx_DEST_DATA_END_PTR(base,x) MMIO32(DMA_DESC_CHx_BASE(base, x) + 0x04)DMA_IFS_CHxDONE(x) (1 << (x))PCNT0_BASE (PERIPH_BASE + 0x86000)dma_disable_done_interruptUINT_FAST16_MAX__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKDMA_CH10DMA_CH11DMA_IEN_ERR (1 << 31)UINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRDMA_LOOP_EN (1 << 16)dma_desc_set_user_dataDMA_CHPRIC_CH1SPRIC DMA_CHPRIC_CHxSPRIC(1)__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intDMA_IFC_CH10DONE DMA_IFC_CHxDONE(10)INT32_MINDMA_IEN_CH8DONE DMA_IEN_CHxDONE(8)DMA_R_POWER_512DI_EMU_BUBODBUVINCAL MMIO32(DI_BASE + 0x0C0)BEGIN_DECLS DMA_CHENS_CHxSENS(i) (1 << (i))DMA_CH_CTRL_SIGSEL_LESENSE_BUF_DATAV 0DMA_IF_CH10DONE DMA_IF_CHxDONE(10)DMA_CHSREQSTATUS_CH7SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(7)DMA_CTRL_DESCRECT (1 << 0)DMA_CH_CTRL_SIGSEL_UART1TXEMPTY 2dma_get_done_interrupt_flagDMA_CHALTC MMIO32(DMA_BASE + 0x034)DMA_DESC_CH_CFG_CYCLE_CTRL_PERIPH_SCAT_GATH_PRIM DMA_DESC_CH_CFG_CYCLE_CTRL(6)DI_AUXHFRCO_CALIB_BAND_14 MMIO8(DI_BASE + 0x1D7)__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__FLT32X_MAX__ 1.7976931348623157e+308F32xDMA_CH_CTRL_SIGSEL_DAC_CH1 1DMA_DESC_CH_CFG_SRC_INC_MASK (0x3 << DMA_DESC_CH_CFG_SRC_INC_SHIFT)DMA_CHPRIS_CH11SPRIC DMA_CHPRIS_CHxSPRIC(11)__ARM_EABI__ 1INT16_MININTPTR_MIN__FLT_IS_IEC_60559__ 2__THUMBEL__ 1DMA_LOOP_WIDTH_MASK (0x3FF << DMA_LOOP_WIDTH_SHIFT)DMA_DESC_CH_CFG_CYCLE_CTRL_BASIC DMA_DESC_CH_CFG_CYCLE_CTRL(1)__QQ_IBIT__ 0DMA_MODE_INVALIDDI_BASE (0x0FE08000U)DMA_CHALTC_CH9SALTC DMA_CHALTC_CHxSALTC(9)__LLACCUM_FBIT__ 31DMA_IF_CH8DONE DMA_IF_CHxDONE(8)DMA_CHALTS_CH2SALTS DMA_CHALTS_CHxSALTS(2)WCHAR_MINdma_enable_with_unprivileged_access__GNUC_MINOR__ 2DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0__UINT_LEAST32_TYPE__ long unsigned intDMA_IFS_CH6DONE DMA_IFS_CHxDONE(6)__UHQ_IBIT__ 0__ARM_FEATURE_NUMERIC_MAXMIN__INTMAX_TYPE__ long long intdma_set_alt_src_size(ch,size) dma_desc_set_src_size(DMA_ALTCTRLBASE, ch, size)__GCC_ATOMIC_INT_LOCK_FREE 2DMA_CH2_CTRL DMA_CHx_CTRL(2)DMA_CH_CTRL_SIGSEL_OFF 0DMA_CHREQMASKS_CH6SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(6)INTMAX_MAXDMA_LOOP0 DMA_LOOPx(0)DMA_CHENC_CHxSENC(i) (1 << (i))__UINTMAX_MAX__ 0xffffffffffffffffULL__ARM_FEATURE_FP16_SCALAR_ARITHMETIC__LFRACT_MIN__ (-0.5LR-0.5LR)__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CCHANNEL_SUPPORT_LOOP(ch) (((ch) == DMA_CH0) || ((ch) == DMA_CH1))DI_ACMP0_CTRL MMIO32(DI_BASE + 0x060)DMA_CHENC_CH3SENC DMA_CHENC_CHxSENC(3)INT64_MINEFM32LG 1__SACCUM_MAX__ 0X7FFFP-7HKDI_ADC0_CAL_1V25 MMIO16(DI_BASE + 0x1B4)DI_EMU_BUINACT MMIO32(DI_BASE + 0x0B0)__UINTPTR_TYPE__ unsigned intDMA_CH3_CTRL DMA_CHx_CTRL(3)DMA_CH0_CTRL DMA_CHx_CTRL(0)UINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRDMA_CHSWREQ_CH2SWREQ DMA_CHSWREQ_CHxSWREQ(2)WCHAR_MAX __WCHAR_MAX__DMA_CHREQSTATUS_CH6SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(6)DMA_CH_CTRL_SOURCESEL_USART0 0b001100DMA_CH_CTRL_SIGSEL_I2C_RXDATAV 0__SIZEOF_SIZE_T__ 4UINT8_C__UINT64_TYPE__ long long unsigned int__INT64_C(c) c ## LL__LACCUM_IBIT__ 32DMA_STATUS_STATE_PERSCATTRANS 10__LDBL_MIN_10_EXP__ (-307)UART1_BASE (PERIPH_BASE + 0x0E400)dma_enable_priorityDMA_IF_CH2DONE DMA_IF_CHxDONE(2)dma_enable_channelDMA_CH_CTRL_SIGSEL_AESXORDATAWR 1DMA_MEM_BYTETPIU_BASE (PPBI_BASE + 0x40000)__LDBL_MIN__ 2.2250738585072014e-308L__LDBL_DENORM_MIN__ 4.9406564584124654e-324L__ARM_FEATURE_CDE__ACCUM_IBIT__ 16dma_channel_resetDMA_IEN_CH0DONE DMA_IEN_CHxDONE(0)CORESIGHT_LAR_OFFSET 0xfb0DMA_CHENC_CH1SENC DMA_CHENC_CHxSENC(1)DMA_CHUSEBURSTS_CH3SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(3)DMA_CHSWREQ_CH4SWREQ DMA_CHSWREQ_CHxSWREQ(4)DMA_CHREQMASKC_CH7SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(7)DMA_CHSWREQ_CH6SWREQ DMA_CHSWREQ_CHxSWREQ(6)short intDMA_IEN_CH10DONE DMA_IEN_CHxDONE(10)UINT_FAST32_MAX__UINT16_C(c) cDMA_IFC_CHxDONE(x) (1 << (x))__UDA_IBIT__ 32modeDMA_DESC_CH_CFG_CYCLE_CTRL(v) (((v) << DMA_DESC_CH_CFG_CYCLE_CTRL_SHIFT) & DMA_DESC_CH_CFG_CYCLE_CTRL_MASK)DMA_CHUSEBURSTS_CH6SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(6)DMA_CHPRIS MMIO32(DMA_BASE + 0x038)UINT_LEAST32_MAXdma_chDMA_CH_CTRL_SIGSEL_TIMER2UFOF 0BIT2 (1<<2)INT64_C__ATOMIC_RELAXED 0__ARM_FEATURE_COPROCDMA_CHENC_CH11SENC DMA_CHENC_CHxSENC(11)DMA_CH_CTRL_SOURCESEL(v) (((v) << DMA_CH_CTRL_SOURCESEL_SHIFT) & DMA_CH_CTRL_SOURCESEL_MASK)__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUSART1_BASE (PERIPH_BASE + 0x0C400)__FLT64_MANT_DIG__ 53dma_set_dest_size(ch,size) dma_desc_set_dest_size(DMA_CTRLBASE, ch, size)BIT5 (1<<5)DMA_CH10_CTRL DMA_CHx_CTRL(10)BIT1 (1<<1)startINT8_CDMA_CHREQMASKS_CH5SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(5)INT_LEAST32_MAX__USES_INITFINI__ 1DMA_CHPRIC_CH4SPRIC DMA_CHPRIC_CHxSPRIC(4)DMA_MODE_MEM_SCAT_GATH_ALTDMA_CH_CTRL_SIGSEL_AES_KEY_WR 3DMA_CHPRIC_CHxSPRIC(i) (1 << (i))__DBL_DECIMAL_DIG__ 17DMA_RDS_RDSCH3 DMA_RDS_RDSCHx(3)DMA_DESC_CH_CFG_DEST_PROT_CTRL(v) (((v) << DMA_DESC_CH_CFG_DEST_PROT_CTRL_SHIFT) & DMA_DESC_CH_CFG_DEST_PROT_CTRL_MASK)BIT8 (1<<8)DMA_CH_CTRL_SIGSEL_UART_TXBL 1INT16_C(c) __INT16_C(c)DMA_CH_CTRL_SIGSEL_USART1TXBL 1DMA_CHALTC_CH10SALTC DMA_CHALTC_CHxSALTC(10)__INT16_MAX__ 0x7fffDMA_CHREQMASKC_CH8SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(8)DMA_CH_CTRL_SIGSEL_TIMER_CC0 DMA_CH_CTRL_SIGSEL_TIMER_CCx(0)DMA_CHWAITSTATUS_CH11WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(11)DMA_CHREQSTATUS_CH1SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(1)__INT_WIDTH__ 32DMA_CH_CTRL_SOURCESEL_LEUART0 0b010000DMA_IFS_CH0DONE DMA_IFS_CHxDONE(0)__QQ_FBIT__ 7DMA_CHENS_CH1SENS DMA_CHENS_CHxSENS(1)DMA_CHPRIC_CH2SPRIC DMA_CHPRIC_CHxSPRIC(2)__SIG_ATOMIC_WIDTH__ 32DMA_DESC_CH_CFG_DEST_INC_SHIFT (30)DMA_CHWAITSTATUS_CH1WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(1)DMA_CHALTC_CH0SALTC DMA_CHALTC_CHxSALTC(0)__UTA_IBIT__ 64__ULLACCUM_IBIT__ 32DMA_CHUSEBURSTC_CH5SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(5)DMA_IFC MMIO32(DMA_BASE + 0x1008)__ULLFRACT_EPSILON__ 0x1P-64ULLRfalse 0DMA_CH_CTRL_SIGSEL_TIMER1CC2 3DI_ACMP1_CTRL MMIO32(DI_BASE + 0x068)__SIZEOF_WINT_T__ 4dma_get_bus_error_interrupt_flagDMA_CHPRIS_CH3SPRIC DMA_CHPRIS_CHxSPRIC(3)__ARM_FEATURE_UNALIGNED 1__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17DMA_CHPRIS_CHxSPRIC(i) (1 << (i))DAC0_BASE (PERIPH_BASE + 0x04000)DMA_DESC_CH_CFG_N_MINUS_1(v) (((v) << DMA_DESC_CH_CFG_N_MINUS_1_SHIFT) & DMA_DESC_CH_CFG_N_MINUS_1_MASK)__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)DMA_STATUS_STATE(v) (((v) << DMA_STATUS_STATE_SHIFT) & DMA_STATUS_STATE_MASK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1DMA_CH_CTRL_SIGSEL_TIMER3UFOF 0DMA_CHUSEBURSTS_CH7SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(7)__FLT32X_HAS_DENORM__ 1DMA_CHENC_CH10SENC DMA_CHENC_CHxSENC(10)DI_ADC0_CAL_2V5 MMIO16(DI_BASE + 0x1B6)DMA_MEM_WORD__TA_IBIT__ 64PCNT1_BASE (PERIPH_BASE + 0x86400)DMA_CHSREQSTATUS_CH5SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(5)dma_set_alt_r_power(ch,r_power) dma_desc_set_r_power(DMA_ALTCTRLBASE, ch, r_power)__ARM_ASM_SYNTAX_UNIFIED__ 1DMA_IF MMIO32(DMA_BASE + 0x1000)DMA_IFC_CH5DONE DMA_IFC_CHxDONE(5)DMA_CHREQMASKC_CH1SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(1)DMA_LOOP_WIDTH(v) (((v) << DMA_LOOP_WIDTH_SHIFT) & DMA_LOOP_WIDTH_MASK)DMA_CHUSEBURSTS_CHxSUSEBURSTS(i) (1 << (i))__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODDMA_CH_CTRL_SIGSEL_DAC0CH1 1DMA_CHSREQSTATUS_CH11SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(11)DMA_CH_CTRL_SIGSEL_TIMER_CCx(x) DMA_CH_CTRL_SIGSEL((x) + 1)DMA_CHENS_CH9SENS DMA_CHENS_CHxSENS(9)__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H DMA_DESC_CH_CFG_DEST_SIZE_HALFWORD DMA_DESC_CH_CFG_DEST_SIZE(1)DMA_CH_CTRL_SIGSEL_USART2TXBL 1DMA_CH_CTRL_SIGSEL_AESDATAWR 0DMA_CHALTS_CH3SALTS DMA_CHALTS_CHxSALTS(3)__GCC_CONSTRUCTIVE_SIZE 64SIG_ATOMIC_MAXDMA_CH_CTRL_SIGSEL_LEUART1RXDATAV 0__LLFRACT_IBIT__ 0DMA_CH4_CTRL DMA_CHx_CTRL(4)DMA_CH1_CTRL DMA_CHx_CTRL(1)uint32_tDMA_RECT_SRCSTRIDE_SHIFT (10)BIT12 (1<<12)DMA_DESC_CH_CFG_SRC_INC_SHIFT (26)DMA_CHREQMASKS_CH0SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(0)DMA_IFC_CH4DONE DMA_IFC_CHxDONE(4)DMA_R_POWER_1024MPU_BASE (SCS_BASE + 0x0D90)__SACCUM_EPSILON__ 0x1P-7HKDMA_DESC_CH_CFG_DEST_PROT_CTRL_MASK (0x7 << DMA_DESC_CH_CFG_DEST_PROT_CTRL_SHIFT)__GCC_ASM_FLAG_OUTPUTS__ 1DMA_CHREQMASKS_CHxSREQMASKS(i) (1 << (i))DMA_RDS_RDSCH8 DMA_RDS_RDSCHx(8)DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT 4__UINT_FAST16_TYPE__ unsigned intDMA_CTRL MMIO32(DMA_BASE + 0x1010)__UHA_IBIT__ 8__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULKDMA_RDS_RDSCH2 DMA_RDS_RDSCHx(2)__LDBL_DIG__ 15DMA_CHPRIC_CH5SPRIC DMA_CHPRIC_CHxSPRIC(5)DMA_MODE_AUTO_REQUESTUINT64_C__SIZE_WIDTH__ 32__LONG_LONG_MAX__ 0x7fffffffffffffffLLBIT16 (1<<16)__WINT_MIN__ 0UINT_LEAST16_MIN__FLT64_DIG__ 15DMA_CH_CTRL_SIGSEL_ADC0SCAN 1__WINT_MAX__ 0xffffffffUBIT22 (1<<22)DMA_R_POWER_1DMA_R_POWER_2DMA_R_POWER_4__INT_LEAST16_TYPE__ short intLETIMER0_BASE (PERIPH_BASE + 0x82000)DMA_DESC_CH_CFG_R_POWER(v) (((v) << DMA_DESC_CH_CFG_R_POWER_SHIFT) & DMA_DESC_CH_CFG_R_POWER_MASK)DMA_R_POWER_8DMA_CHALTS_CH7SALTS DMA_CHALTS_CHxSALTS(7)__DBL_MAX__ ((double)1.7976931348623157e+308L)DMA_STATUS_STATE_MASK (0xF << DMA_STATUS_STATE_SHIFT)short unsigned int__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1DMA_IFC_CH2DONE DMA_IFC_CHxDONE(2)__thumb__ 1DMA_IF_CH6DONE DMA_IF_CHxDONE(6)INT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1DMA_CH_CTRL_SIGSEL_AESKEYWR 3DMA_DESC_CH_CFG_SRC_INC_HALFWORD DMA_DESC_CH_CFG_SRC_INC(1)DMA_CH_CTRL_SIGSEL_USART_TXBLRIGHT 4dma_clear_bus_error_flag__HQ_FBIT__ 15DI_PROD_REV MMIO8(DI_BASE + 0x1FF)DMA_CHREQSTATUS_CH3SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(3)BIT26 (1<<26)VCMP_BASE (PERIPH_BASE + 0x00000)DMA_CHENS_CH6SENS DMA_CHENS_CHxSENS(6)__SIZE_MAX__ 0xffffffffUDMA_CHUSEBURSTC_CH10SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(10)DMA_IEN_CH6DONE DMA_IEN_CHxDONE(6)DMA_CH_CTRL_SIGSEL_I2C0TXBL 1DMA_CHREQMASKC_CH0SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(0)DMA_CHSWREQ MMIO32(DMA_BASE + 0x014)__ARM_ARCHDMA_STATUS_STATE_RDCHCTRLDATA 1DMA_CHALTS_CH11SALTS DMA_CHALTS_CHxSALTS(11)__LONG_MAX__ 0x7fffffffLDMA_CHSWREQ_CH1SWREQ DMA_CHSWREQ_CHxSWREQ(1)DMA_CHREQSTATUS_CH5SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(5)DMA_CH_CTRL_SOURCESEL_I2C0 0b010100DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0DMA_CHUSEBURSTS_CH8SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(8)INT_LEAST64_MINDMA_STATUS_STATE_WRCHCTRLDATA 7PTRDIFF_MAXDMA_CHSREQSTATUS MMIO32(DMA_BASE + 0xE18)DMA_CH_CTRL_SIGSEL_TIMER2CC2 3DMA_IF_CH9DONE DMA_IF_CHxDONE(9)__LLFRACT_EPSILON__ 0x1P-63LLR__ARM_FEATURE_SIMD32__FLT32X_MANT_DIG__ 53dma_disable_periph_requestDMA_CH_CTRL_SIGSEL_USART_RXDATAV 0__WCHAR_WIDTH__ 32DMA_CHENC_CH0SENC DMA_CHENC_CHxSENC(0)WINT_MAXDMA_DESC_CH_CFG_SRC_SIZE_WORD DMA_DESC_CH_CFG_SRC_SIZE(2)__INT16_C(c) cdma_set_loop_countDMA_R_POWER_128INT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32DMA_CHSREQSTATUS_CH9SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(9)DMA_IFS_CH8DONE DMA_IFS_CHxDONE(8)DMA_IEN_CH4DONE DMA_IEN_CHxDONE(4)DI_DAC0_BIASPROG MMIO32(DI_BASE + 0x058)DI_ADC0_CAL_5VDIFF MMIO16(DI_BASE + 0x1BA)__ATOMIC_ACQ_REL 4DMA_CHSREQSTATUS_CH1SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(1)__HQ_IBIT__ 0DMA_DESC_CH_CFG_CYCLE_CTRL_MEM_SCAT_GATH_PRIM DMA_DESC_CH_CFG_CYCLE_CTRL(4)__DBL_MIN_10_EXP__ (-307)DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT 4__UINT_FAST64_MAX__ 0xffffffffffffffffULLDMA_CHREQMASKS_CH8SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(8)__INT_FAST16_MAX__ 0x7fffffff__FLT32_NORM_MAX__ 3.4028234663852886e+38F32desc_baser_powerPTRDIFF_MIN (-PTRDIFF_MAX - 1)DMA_CHALTC_CH1SALTC DMA_CHALTC_CHxSALTC(1)USART2_BASE (PERIPH_BASE + 0x0C800)DMA_RDS_RDSCH9 DMA_RDS_RDSCHx(9)__DBL_MANT_DIG__ 53__ULFRACT_IBIT__ 0DMA_RDS_RDSCH1 DMA_RDS_RDSCHx(1)INT_FAST16_MAXITR_BASE (SCS_BASE + 0x0000)__INT_MAX__ 0x7fffffff__INT_LEAST64_TYPE__ long long intDMA_MODE_BASIC__ARM_FEATURE_CDE_COPROC__ULLACCUM_MIN__ 0.0ULLKDMA_IEN_CH9DONE DMA_IEN_CHxDONE(9)DMA_CHSREQSTATUS_CH0SREQSTATUS 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8í9:;4=N?dma_common.c$tdma_calc_end_from_start$dwm4.0.db7b1e6169e47a60f2e41023951d05f3wm4.memorymap.h.21.8c90486dae5eea2d8efddd23fe5d09d9wm4.memorymap.h.25.a0cb027d5a9b9fa93c8fdef75e5f5dc4wm4.common.h.21.c9066c2f6b12c71b40226ea6107829a4wm4.stdint.h.29.6d480f4ba0f60596e88234283d42444fwm4.stdbool.h.29.4a1c88fe569adb8d03217dd16982ca34wm4.common.h.67.5c568a1f62c8e726909b04e29f9e1fc0wm4.dma_common.h.40.9a2a2632a0fcbd3eca3c1e56e945509bdma_enable_with_privileged_accessdma_enable_with_unprivileged_accessdma_enabledma_disabledma_set_desc_addressdma_get_wait_on_request_flagdma_generate_software_requestdma_enable_burst_onlydma_enable_single_and_burstdma_enable_periph_requestdma_disable_periph_requestdma_enable_channeldma_disable_channeldma_disable_alternate_structuredma_enable_alternate_structuredma_enable_prioritydma_disable_prioritydma_get_bus_error_flagdma_clear_bus_error_flagdma_get_request_flagdma_get_bus_error_interrupt_flagdma_get_done_interrupt_flagdma_set_bus_error_interrupt_flagdma_set_done_interrupt_flagdma_clear_bus_error_interrupt_flagdma_clear_done_interrupt_flagdma_enable_bus_error_interruptdma_disable_bus_error_interruptdma_enable_done_interruptdma_disable_done_interruptdma_set_sourcedma_set_signaldma_channel_resetdma_set_loop_countdma_enable_loopdma_disable_loopdma_desc_set_dest_sizedma_desc_set_dest_incdma_desc_set_src_sizedma_desc_set_src_incdma_desc_set_r_powerdma_desc_enable_next_useburstdma_desc_disable_next_useburstdma_desc_set_countdma_desc_set_user_datadma_desc_get_user_datadma_desc_set_src_addressdma_desc_set_dest_addressdma_desc_set_mode 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E •J Y •h •m x •}  • ¢ •« •° Œ'Œ>ŒUŒiŠ€Š™Š³Š¾ŠÍŠàŠíˆˆˆ4ˆ?ˆPˆcˆtš†¸†Ï„å„ü‚‚)‚B‚[€q€ˆ~ž~µ|Ë|â|ù| z#z:zQzex{x’x©x½vÓvèvõt t"t9tMGdA{A“ªŽ  (08@HPX `#h&p)x,€/ˆ25˜8 ;¨>°A¸DÀGÈJÐMØPàSèVðYø\_beh k(n0q8t@vHxPzX|`~h€p‚x„€†ˆˆŠ˜Œ  %+17=C I#O&U)[,a/g2m5s8y;>…A‹D‘G—JM£P©S¯VµY»\Á_ÇbÍeÓhÙkßnåqëtñv÷xýz| ~€‚„!†'ˆ-Š3Œ”– •(—.˜8™@šI›OœU^•• ••••#•)•/•5•;•A•G•M•S•Y•_•e•k•q•w•}•ƒ•‰••••›•¡•§•­•³•¹•¿•Å•Ë•Ñ•×•Ý•ã•é•ï•õ•û••• ••••%•+•1•7•=•C•I•O•U•[•a•g•m•s•y••…•‹•‘•—••£•©•¯•µ•»•Á•Ç•Í•Ó•Ù•ß•å•ë•ñ•÷•ý•• ••••!•'•-•3•9•?•E•K•Q•W•]•c•i•o•u•{••‡••“•™•Ÿ•¥•«•±•·•½•Ã•É•Ï•Õ•Û•á•ç•í•ó•ù•ÿ•• ••••#•)•/•5•;•A•G•M•S•Y•_•e•k•q•w•}•ƒ•‰••••›•¡•§•­•³•¹•¿•Å•Ë•Ñ•×•Ý•ã•é•ï•õ•û••• ••••%•+•1•7•=•C•I•O•U•[•a•g•m•s•y••…•‹•‘•—••£•©•¯•µ•»•Á•Ç•Í•Ó•Ù•ß•å•ë•ñ•÷•ý•• ••••!•'•-•3•9•?•E•K•Q•W•]•c•i•o•u•{••‡••“•™•Ÿ•¥•«•±•·•½•Ã•É•Ï•Õ•Û•á•ç•í•ó•ù•ÿ•• ••••#•)•/•5•;•A•G•M•S•Y•_•e•k•q•w•}•ƒ•‰••••›•¡•§•­•³•¹•¿•Å•Ë•Ñ•×•Ý•ã•é•ï•õ•û••• ••••%•+•1•7•=•C•I•O•U•[•a•g•m•s•y••…•‹•‘•—••£•©•¯•µ•»•Á•Ç•Í•Ó•Ù•ß•å•ë•ñ•÷•ý•• ••••!•'•-•3•9•?•E•K•Q•W•]•c•i•o•u•{••‡••“•™•Ÿ•¥•«•±•·•½•Ã•É•Ï•Õ•Û•á•ç•í•ó•ù•ÿ• • • • • •# •) •/ •5 •; •A •G •M •S •Y •_ •e •k •q •w •} •ƒ •‰ • •• •› •¡ •§ •­ •³ •¹ •¿ •Å •Ë •Ñ •× •Ý •ã •é •ï •õ •û • • • • • • •% •+ •1 •7 •= •C •I •O •U •[ •a •g •m •s •y • •… •‹ •‘ •— •• ••••#•)•/•5•;•A•G•M•S•Y•_•e•k•q•• ••••#•)•/•5•;•A•G•M•S•Y•_•e•k•q•w•}•ƒ•‰••••›•¡•§•­•³•¹•¿•Å•Ë•Ñ•×•Ý•ã•é•ï•õ•û••• ••••%•+•1•7•=•C•I•O•U•[•a•g•m•s•y••…•‹•‘•—••£•©•¯•µ•»•Á•Ç•Í•Ó•Ù•ß•å•ë•ñ•÷•ý••• •••• ••••#•)•/•5•;•A•G•M•S•Y•_•e•k•q•x••†••”•›•¢•©•°•·•¾•Å•Ì•Ó•Ú•á•è•ï•ö•ý•• ••• •'•.•5•<•C•J•Q•X•_•f•m•t•{•‚•‰••—•ž•¥•¬•³•º•Á•È•Ï•Ö•Ý•ä•ë•ò•ù••••••#•*•1•8•?•F•M•T•[•b•i•p•w•~•…•Œ•“•š•¡•¨•¯•¶•½•Ä•Ë•Ò•Ù•à•ç•î•õ•ü•• ••••&•-•4•;•B•I•• ••••• ••••#•)•/•5•;•A•G•M•S•Y•_•e•k•q•w•}•ƒ•‰••••›•¡•§•­•³•¹•¿•Å•Ë•Ñ•×•Ý•ã•• ••••#•)•/•5•;•A•G•M•S•Y•_•e•k•q•w•}•ƒ•‰••••›•¡•§•­•³•¹•¿•Å•Ë•Ñ•×•Ý•ã•é•ï•õ•û••• ••••%•+•1•7•=•C•I•O•U•[•a•g•m•s•y••…•‹•‘•—••£•©•¯•µ•»•Â•É•Ð•×•Þ•å•ì•ó•ú••••••$•+•2•9•@•G•N•U•\•c•j•q•x••†••”•›•¢•©•°•·•¾•Å•Ì•Ó•Ú•á•è•ï•ö•ý•• ••• •'•.•5•<•C•J•Q•X•_•f•m•t•{•‚•‰••—•ž•¥•¬•³•º•Á•È•Ï•Ö•Ý•ä•ë•ò•ù••••••#•*•1•8•?•F•M•T•[•b•i•p•w•~•…•Œ•“•š•¡•¨•¯•¶•½•Ä•Ë•Ò•Ù•à•ç•î•õ•ü•• ••••&•-•4•;•B•I•P•W•^•e•l•s•z••ˆ••–••¤•«•²•¹•À•Ç•Î•Õ•Ü•ã•ê•ñ•ø•ÿ•• •••"•)•0•7•>•E•L•S•Z•a•h•o•v•}•„•‹•’•™• •§•®•µ•¼•Ã•Ê•Ñ•Ø•ß•æ•í•ô•û•• ••••%•,•3•:•A•H•O•V•]•d•k•r•y•€•‡•Ž•••œ•£•ª•±•¸•¿•Æ•Í•Ô•Û•â•é•ð•÷•þ•• •••!•(•/•6•=•D•K•R•Y•`•g•n•u•|•ƒ•Š•‘•˜•Ÿ•¦•­•´•»•Â•É•Ð•×•Þ•å•ì•ó•ú• • • • • •$ •+ •2 •9 •@ •G •N •U •\ •c •j •q •x • •† • •” •› •¢ •© •° •· •¾ •Å •Ì •Ó •Ú •á •è •ï •ö •ý • • • • • •' •. •5 •< •C •J •Q •X •_ •f •m •t •{ •‚ •‰ • •— •ž •¥ •¬ •³ •º •Á •È •Ï •Ö •Ý •ä •ë •ò •ù • • • • • •# •* •1 •8 •? •F •M •T •[ •b •i •p •w •~ •… •Œ •“ •š •¡ •¨ •¯ •¶ •½ •Ä •Ë •Ò •Ù •à •ç •î •õ •ü • • • • • •& •- •4 •; •B •I •P •W •^ •e •l •s •z • •ˆ • •– • •¤ •« •² •¹ •À •Ç •Î •Õ •Ü •ã •ê •ñ •ø •ÿ • • • • •" •) •0 •7 •> •E •L •S •Z •a •h •o •v •} •„ •‹ •’ •™ •  •§ •® •µ •¼ •Ã •Ê •Ñ •Ø •ß •æ •í •ô •û •• ••••%•,•3•:•A•H•O•V•]•j™´ Åê,Puš ¿#ä& ).,S/x25Â8ç;>ACD_G‚JžMÃPßSV Y<\d_Œb±eÖh+kgn‹q¯tív%xcz¡|ß~ý€‚`„}†›ˆÖŠ Œž$ž(4ž8 DžHTžXdžhtžx„žˆ”ž˜¤ž¨ ´ž¸#ÄžÈ&ÔžØ)äžè,ôžø/ž2ž5$ž(84ž8;DžH>TžXAdžhDtžxG„žˆJ”ž˜M¤ž¨P´ž¸SÄžÈVÔžØYäžè\ôžø_žbže$ž(h4ž8kLžPn\ž`qlžpt|ž€vŒžxœž z¬ž°|¼žÀ~̞Ѐܞà‚ôžø„ž†žˆ,ž0ŠDžHŒ.symtab.strtab.shstrtab.text.data.bss.text.dma_calc_end_from_start.text.dma_enable_with_privileged_access.text.dma_enable_with_unprivileged_access.text.dma_enable.text.dma_disable.text.dma_set_desc_address.text.dma_get_wait_on_request_flag.text.dma_generate_software_request.text.dma_enable_burst_only.text.dma_enable_single_and_burst.text.dma_enable_periph_request.text.dma_disable_periph_request.text.dma_enable_channel.text.dma_disable_channel.text.dma_disable_alternate_structure.text.dma_enable_alternate_structure.text.dma_enable_priority.text.dma_disable_priority.text.dma_get_bus_error_flag.text.dma_clear_bus_error_flag.text.dma_get_request_flag.text.dma_get_bus_error_interrupt_flag.text.dma_get_done_interrupt_flag.text.dma_set_bus_error_interrupt_flag.text.dma_set_done_interrupt_flag.text.dma_clear_bus_error_interrupt_flag.text.dma_clear_done_interrupt_flag.text.dma_enable_bus_error_interrupt.text.dma_disable_bus_error_interrupt.text.dma_enable_done_interrupt.text.dma_disable_done_interrupt.text.dma_set_source.text.dma_set_signal.text.dma_channel_reset.text.dma_set_loop_count.text.dma_enable_loop.text.dma_disable_loop.text.dma_desc_set_dest_size.text.dma_desc_set_dest_inc.text.dma_desc_set_src_size.text.dma_desc_set_src_inc.text.dma_desc_set_r_power.text.dma_desc_enable_next_useburst.text.dma_desc_disable_next_useburst.text.dma_desc_set_count.text.dma_desc_set_user_data.text.dma_desc_get_user_data.rel.text.dma_desc_set_src_address.rel.text.dma_desc_set_dest_address.text.dma_desc_set_mode.rel.debug_info.debug_abbrev.rel.debug_loclists.rel.debug_aranges.rel.debug_rnglists.rel.debug_macro.rel.debug_line.debug_str.comment.rel.debug_frame.ARM.attributes.groupÒ4 bŸÒ@ b ÒL b¡ÒX b¢Òd b£Òp b¤Ò| b¥Òˆ b¦”!”'”,”J° r¼ œÈ ­Ô ¿àÚðý!=(_8H X¹hÓxùˆ˜8¨S¸pÈ Ôªì Ñøó <0e@‰P®`Ôpô„˜*°?È4Wü(p$†<TºjÖ|ò’ ¨(¾LÌqÚ Šú§È Ä @tb;ë(ç @|b= B'V» # @„ˆ b@3DEU½A @ ¸bCY¨U @ĘbElº9h @\bG€ód| @ìXbI€Wœ | @D bK€ó$v| @d,˜bM€i%| @ü,°bO€q'| @¬/ bQ€'N| @Ì/ØbS€Û*"| @¤3(bU€ý*è| @Ì30bW€å+b| @ü4ÀbY‘G:H  @¼Eb[0C¾³¨0M÷'µt÷P± @LG b_ÂpÄú-ôú c±  `lJÙ