! / 0 0 0 0 2266 ` {   zzzzzBBBBBBf6f6f6f6f6f6f6f6f6f6f6f6bbb           q qgpio_setgpio_cleargpio_togglescu_pinmuxi2c0_initi2c0_tx_starti2c0_tx_bytei2c0_rx_bytei2c0_stopssp_disablessp_initssp_transferuart_initdummy_readuart_rx_data_readyuart_readuart_read_timeoutuart_writetimer_resettimer_enable_countertimer_disable_countertimer_set_countertimer_get_countertimer_get_prescalertimer_set_prescalertimer_set_modetimer_set_count_inputipc_halt_m0ipc_start_m0blocking_handlerusage_fault_handlerbus_fault_handlermem_manage_handlerhard_fault_handlerqei_isrc_can0_isrwwdt_isrrtc_isratimer_isrc_can1_isreventrouter_isrgint1_isrgint0_isrpin_int7_isrpin_int6_isrpin_int5_isrpin_int4_isrpin_int3_isrpin_int2_isrpin_int1_isrpin_int0_isrsgpio_isrspifi_isri2s1_isri2s0_isrusart3_isrusart2_isruart1_isrusart0_isrssp1_isrssp0_isradc1_isrspi_isri2c1_isri2c0_isradc0_isrmcpwm_isrtimer3_isrtimer2_isrtimer1_isrtimer0_isrritimer_isrsct_isrusb1_isrusb0_isrlcd_isrsdio_isrethernet_isrdma_isrm0core_isrdac_isrnull_handlerdebug_monitor_handlersys_tick_handlerpend_sv_handlersv_call_handlernmi_handlerreset_handlervector_tablesystick_set_reloadsystick_get_reloadsystick_set_frequencysystick_get_valuesystick_set_clocksourcesystick_interrupt_enablesystick_interrupt_disablesystick_counter_enablesystick_counter_disablesystick_get_countflagsystick_clearsystick_get_calibscb_reset_corescb_reset_systemscb_set_priority_groupingnvic_enable_irqnvic_disable_irqnvic_get_pending_irqnvic_set_pending_irqnvic_clear_pending_irqnvic_get_irq_enablednvic_set_prioritynvic_get_active_irqnvic_generate_software_interruptcm3_assert_failedcm3_assert_failed_verbose__dmb__ldrex__strexmutex_lockmutex_trylockmutex_unlockdwt_enable_cycle_counterdwt_read_cycle_countergpio.o/ 0 0 0 644 63380 ` ELF(<4(/. !"#$pGpGpG% D#O !^O %@4`Blint#Y~/~/TP#/.TQ *~*TP#*-TQ^%~%TP#%+TQ$ > :!; 9 I.?:!; 9!'@z% Uy: ; 9 I$ > .?: ; 9 '@z,#$A(?@)]e LDx"&J?H9I2qsg r&%r*~ScflV]\(_`m+' yxp h$ sdSC^.C&?qΏjOo yRG!oX D$+||0[|m8fMXGD6IMP>fRܘ!8Y(BVEJ.'[>=>g0E; Fx~A*9I &2k;G[Iq&$3QQ2\_([0S;hO ImZSY%mv% [Ml,g31SA_`9wW}gHEW3A"/{z{P?`.XFNbc'V.Jg[7mFh\b /}dEVF7 R-$oHcR8$Ia JRVZjYl.px+@8WvaRv9%R`?:xBZG/.. <#"k#%5EpWfTMSgA;]`9sof}l_{w K׊_wn36|5Y~l{=ejAMK 3I{ZU6ÇoohmNr1WxD=Y"(!>1wi\s2ns';6\N;ny(yWJIpv,QHvB:0k7Ud}_h+Z }=!n) x+iw`0H"K4yuNQ5U?ibB*SΆ[]6w!? Kj\e~Bb]?fCO[6?yZa@QSs#aINn ((w 4e&6Q CDc\#{;3 .pVuCZ?v,78J^+ܙ48FswLG9!t"%):fdn!eGfv_g hjgknOo9pvqe<tzRu7x#jyMzb{ ~;U|k%_FL2n\ *-h\8`fDP&[݁gng l> >eAHva)(FD>&vpDI) sa -dUVOHc~VuJW#QzIRw!E8 q"+tf.gqLtG /+}$c6/|!wo|7*}E˜RH_!O8&_'2C7DLEQ$FbIf9L QRSTxOUVTWPXgYZR[\f]I^_TB`haҎbscDd~keBfigqhRiPEjXlkl&mGnooFp>meP2J B !:&;())U* +6, -B.05u6h7=~8w9G:Z;?$@7A}IBHHb I!IJ~K5tL1M N7=OʈPiQ]hWXY^;Z[)a bȑcnwdzeJfUgth#!nkon2pq.rLwD{b[K&P.V_/DU01/2}34#5gP8J9:}|;3<=>?ss@x\AEB,CzDm0EFN/GiHkI/:JKjL]MNzOΓPB.Q/R2SThUQjV$W'^ aZ8dg#j-m@pՍs<vQ5y ~ĕQ,d z>5d ,$@]=j'XQC;x.`uX5/5l4-&]Q0)gQ`d  k-'#Fs?2obRNЖHy!8>LQi \T.5WY 3Ō ^ME+l1* =9"C;t&t[)}X'vU 4C9KM{ )uprx,/U(2’-,q r z(YPYIBCd]zN= o NZtWb/tZPCLCn't3ba /wE1d[.Y0DO#Tb>[GT~v9os]r UMJwpR9\tle~K3=#qTd(D1f_j-zلXQQ`Pb'ddxYrpuY|Pf%M 6ti_F\H{E\}X~6# nv77]{kxqJ!z2_?g4QJ5kA?X5NK^)bwEċ[7kA9e\zr4j|a? z' Hy+_m'PsmW^E?/dVSDPuk MW nu}\pLuW҃`^O{@? O*ou0YtC[K)Vcj09{#'P!!c9p7&)XXH_3wPgZk-tF'` H]Fh6hE)6v)W^[s6I0\WI$gq"C4 Sb(Ya-iT3xS$R*M Kq5" L)H1C@lH:Q49h q nމ&C3nkTOQ :{< g@3* @ e1^g6aOLD dG<A<i 5-9rKb0e6C864.N~."Eu]:DT~bj-j*SZ!;P@rTrky]pem"5|!#cU5Y*q,gL]o{ZaXuʂkdr(&2W<x;(`/ 4K<I s7CZLm2|lG lqL`w>r]} 1J:BؔC: "# ../usr/lib/gcc/arm-none-eabi/12.2.1/include../../../include/libopencm3/lpc43xx../../../include/libopencm3/cm3gpio.cstdint.hgpio.hcommon.hstdbool.hmemorymap.h%/*///GPIO_B4 (GPIO_PORT_BASE + 0x0004)GPIO_W247 (GPIO_PORT_BASE + 0x13DC)__DECIMAL_DIG__ 17GPIO_B121 (GPIO_PORT_BASE + 0x0079)__UHA_FBIT__ 8GPIO_B219 (GPIO_PORT_BASE + 0x00DB)GPIO_W67 (GPIO_PORT_BASE + 0x110C)__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64GPIO_B171 (GPIO_PORT_BASE + 0x00AB)GPIO_B207 (GPIO_PORT_BASE + 0x00CF)__GCC_ATOMIC_WCHAR_T_LOCK_FREE 2GPIO4_SET GPIO_SET(GPIO4)__CHAR_UNSIGNED__ 1ETHERNET_BASE (PERIPH_BASE_AHB + 0x10000)GPIO_W10 (GPIO_PORT_BASE + 0x1028)GPIO_B147 (GPIO_PORT_BASE + 0x0093)GPIO_B38 (GPIO_PORT_BASE + 0x0026)GPIO_B17 (GPIO_PORT_BASE + 0x0011)GPIO_B202 (GPIO_PORT_BASE + 0x00CA)GPIO_W227 (GPIO_PORT_BASE + 0x138C)__FLT64_HAS_INFINITY__ 1GPIO_W93 (GPIO_PORT_BASE + 0x1174)GPIO_W149 (GPIO_PORT_BASE + 0x1254)GPIO_W221 (GPIO_PORT_BASE + 0x1374)__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GNUC_MINOR__ 2__GCC_DESTRUCTIVE_SIZE 64__LACCUM_EPSILON__ 0x1P-31LKGPIO_W251 (GPIO_PORT_BASE + 0x13EC)__PTRDIFF_MAX__ 0x7fffffff__SACCUM_FBIT__ 7GPIO2 (GPIO_PORT_BASE + 0x2008)GPIO6_PIN GPIO_PIN(GPIO6)__INTMAX_MAX__ 0x7fffffffffffffffLL__TQ_IBIT__ 0__FLT64_DECIMAL_DIG__ 17GPIO_B149 (GPIO_PORT_BASE + 0x0095)GPIOPIN5 (1 << 5)I2C0_BASE (PERIPH_BASE_APB1 + 0x01000)GPIOPIN18 (1 << 18)GPIO_B8 (GPIO_PORT_BASE + 0x0008)__ATOMIC_CONSUME 1__ULACCUM_FBIT__ 32__WCHAR_MAX__ 0xffffffffUGPIO_B222 (GPIO_PORT_BASE + 0x00DE)OTP_BASE (0x40045000U)GPIO0_CLR GPIO_CLR(GPIO0)INT64_MAX __INT64_MAX__INTMAX_MIN__SIZEOF_LONG_LONG__ 8GPIO_B41 (GPIO_PORT_BASE + 0x0029)__DBL_MAX_10_EXP__ 308GPIO_B135 (GPIO_PORT_BASE + 0x0087)__FRACT_MIN__ (-0.5R-0.5R)__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLKGPIOPIN19 (1 << 19)__USACCUM_MAX__ 0XFFFFP-8UHK__SFRACT_FBIT__ 7__INTMAX_WIDTH__ 64__ARM_FEATURE_BF16_SCALAR_ARITHMETIC__SQ_IBIT__ 0__ORDER_PDP_ENDIAN__ 3412__ARM_FEATURE_IDIV 1gpiosC_CCAN1_BASE (PERIPH_BASE_APB1 + 0x04000)__FLT_HAS_DENORM__ 1__INT8_TYPE__ signed charGPIO_B3 (GPIO_PORT_BASE + 0x0003)GPIO_W193 (GPIO_PORT_BASE + 0x1304)__USACCUM_MIN__ 0.0UHK__FLT32_DECIMAL_DIG__ 9GPIO_B120 (GPIO_PORT_BASE + 0x0078)GPIO_W240 (GPIO_PORT_BASE + 0x13C0)__LDBL_MIN_EXP__ (-1021)GPIO_B13 (GPIO_PORT_BASE + 0x000D)__LDBL_MANT_DIG__ 53INT64_MIN (-INT64_MAX - 1)GPIO_W28 (GPIO_PORT_BASE + 0x1070)GPIO_B252 (GPIO_PORT_BASE + 0x00FC)__UINT8_C(c) cGPIO_W52 (GPIO_PORT_BASE + 0x10D0)__INT16_TYPE__ short intGPIO_B130 (GPIO_PORT_BASE + 0x0082)__FLT64_MAX__ 1.7976931348623157e+308F64GPIO_B37 (GPIO_PORT_BASE + 0x0025)USB0_BASE (PERIPH_BASE_AHB + 0x06000)GPIO_W157 (GPIO_PORT_BASE + 0x1274)UINT_FAST32_MAXGPIO_B98 (GPIO_PORT_BASE + 0x0062)GPIO_B71 (GPIO_PORT_BASE + 0x0047)GPIO_W153 (GPIO_PORT_BASE + 0x1264)GPIO_W169 (GPIO_PORT_BASE + 0x12A4)GPIO_W183 (GPIO_PORT_BASE + 0x12DC)INT_FAST64_MAX __INT_FAST64_MAX__gpio_clear__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1GPIO_W168 (GPIO_PORT_BASE + 0x12A0)GPIO7_PIN GPIO_PIN(GPIO7)__UINT_LEAST16_MAX__ 0xffff__STDC_HOSTED__ 1__ULLFRACT_FBIT__ 64GPIO6_CLR GPIO_CLR(GPIO6)__SIG_ATOMIC_TYPE__ intGPIO_W32 (GPIO_PORT_BASE + 0x1080)GPIO_B116 (GPIO_PORT_BASE + 0x0074)__INT_FAST64_TYPE__ long long int__WINT_TYPE__ unsigned intPERIPH_BASE_APB2 (0x400C0000U)GPIO_B150 (GPIO_PORT_BASE + 0x0096)GPIO3_MPIN GPIO_MPIN(GPIO3)GPIO_B57 (GPIO_PORT_BASE + 0x0039)INT32_MIN (-INT32_MAX - 1)GPIO_B221 (GPIO_PORT_BASE + 0x00DD)__FLT32_MAX_10_EXP__ 38GPIO_B235 (GPIO_PORT_BASE + 0x00EB)GPIO_W69 (GPIO_PORT_BASE + 0x1114)WWDT_BASE (PERIPH_BASE_APB0 + 0x00000)GPIO_W188 (GPIO_PORT_BASE + 0x12F0)__USFRACT_MAX__ 0XFFP-8UHR__FP_FAST_FMAF32 1TIMER1_BASE (PERIPH_BASE_APB0 + 0x05000)GPIO_B67 (GPIO_PORT_BASE + 0x0043)GPIO_B40 (GPIO_PORT_BASE + 0x0028)GPIOPIN0 (1 << 0)__FLT32_MIN_EXP__ (-125)ATIMER_BASE (0x40040000U)UINT32_MAX __UINT32_MAX__GPIO1_SET GPIO_SET(GPIO1)GPIO_B136 (GPIO_PORT_BASE + 0x0088)C_CAN0_BASE (PERIPH_BASE_APB3 + 0x02000)__ULFRACT_FBIT__ 32GPIO_W148 (GPIO_PORT_BASE + 0x1250)__FLT64_MIN_10_EXP__ (-307)GPIO_B2 (GPIO_PORT_BASE + 0x0002)BIT10 (1<<10)__INT_FAST64_WIDTH__ 64__STDC_VERSION__ 199901LINT_LEAST64_MAX __INT_LEAST64_MAX__GPIO_B175 (GPIO_PORT_BASE + 0x00AF)GPIO_B132 (GPIO_PORT_BASE + 0x0084)TIMER0_BASE (PERIPH_BASE_APB0 + 0x04000)__SFRACT_EPSILON__ 0x1P-7HRGPIO_B87 (GPIO_PORT_BASE + 0x0057)GPIO_B251 (GPIO_PORT_BASE + 0x00FB)__INT32_C(c) c ## LUINT32_C(c) __UINT32_C(c)__ORDER_BIG_ENDIAN__ 4321SIZE_MAXGPIO_W122 (GPIO_PORT_BASE + 0x11E8)__SQ_FBIT__ 31GPIO_W19 (GPIO_PORT_BASE + 0x104C)GPIO_B36 (GPIO_PORT_BASE + 0x0024)GPIO_B114 (GPIO_PORT_BASE + 0x0072)INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)GPIO_B97 (GPIO_PORT_BASE + 0x0061)GPIO_B70 (GPIO_PORT_BASE + 0x0046)GPIO_B92 (GPIO_PORT_BASE + 0x005C)__UHQ_FBIT__ 16GPIO_W154 (GPIO_PORT_BASE + 0x1268)__FLT64_MIN_EXP__ (-1021)__PTRDIFF_WIDTH__ 32GPIO_PIN_INTERRUPT_SIENR MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x008)__UINT_FAST8_MAX__ 0xffffffffUGPIO_B237 (GPIO_PORT_BASE + 0x00ED)GPIO_B74 (GPIO_PORT_BASE + 0x004A)UINT16_C(c) __UINT16_C(c)GPIO_B249 (GPIO_PORT_BASE + 0x00F9)__LACCUM_IBIT__ 32GPIO4_NOT GPIO_NOT(GPIO4)GPIO_W33 (GPIO_PORT_BASE + 0x1084)__INT_FAST16_WIDTH__ 32INTMAX_C__VERSION__ "12.2.1 20221205"GPIO_B220 (GPIO_PORT_BASE + 0x00DC)__VFP_FP__ 1GPIO5_MPIN GPIO_MPIN(GPIO5)__LLFRACT_MIN__ (-0.5LLR-0.5LLR)INT_FAST8_MAX__UINT_FAST16_MAX__ 0xffffffffU__INTPTR_MAX__ 0x7fffffffINT64_C(c) __INT64_C(c)GPIO_B161 (GPIO_PORT_BASE + 0x00A1)GPIO4_MASK GPIO_MASK(GPIO4)GPIO_PIN_INTERRUPT_IST MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x024)__GCC_IEC_559_COMPLEX 0CREG_BASE (0x40043000U)__UFRACT_MIN__ 0.0URGPIO_B91 (GPIO_PORT_BASE + 0x005B)__LDBL_HAS_QUIET_NAN__ 1WCHAR_MAX __WCHAR_MAX__GPIO_W115 (GPIO_PORT_BASE + 0x11CC)GPIO_B7 (GPIO_PORT_BASE + 0x0007)UINT_FAST16_MAX __UINT_FAST16_MAX__GPIO_B206 (GPIO_PORT_BASE + 0x00CE)GPIO_B217 (GPIO_PORT_BASE + 0x00D9)__UINT_LEAST8_TYPE__ unsigned charGPIO_W195 (GPIO_PORT_BASE + 0x130C)GPIO_W158 (GPIO_PORT_BASE + 0x1278)__ACCUM_FBIT__ 15GPIO_B145 (GPIO_PORT_BASE + 0x0091)__UACCUM_IBIT__ 16long intUINT8_MAXSIZE_MAX __SIZE_MAX__GPIO_W131 (GPIO_PORT_BASE + 0x120C)GPIO_B86 (GPIO_PORT_BASE + 0x0056)__INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1GPIO6_MPIN GPIO_MPIN(GPIO6)__FLT32X_EPSILON__ 2.2204460492503131e-16F32xGPIO_B163 (GPIO_PORT_BASE + 0x00A3)GPIO_W100 (GPIO_PORT_BASE + 0x1190)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32__UINTMAX_C(c) c ## ULLGPIO_B73 (GPIO_PORT_BASE + 0x0049)__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed charGPIO_B104 (GPIO_PORT_BASE + 0x0068)__GCC_ATOMIC_BOOL_LOCK_FREE 2BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON____FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX__GPIO_W179 (GPIO_PORT_BASE + 0x12CC)__THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRGPIO5 (GPIO_PORT_BASE + 0x2014)GPIO_B43 (GPIO_PORT_BASE + 0x002B)short unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)BIT7 (1<<7)BIT17 (1<<17)GPIOPIN4 (1 << 4)GPIOPIN27 (1 << 27)GPIO_W203 (GPIO_PORT_BASE + 0x132C)UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)GPIO2_CLR GPIO_CLR(GPIO2)__DBL_IS_IEC_60559__ 2__UINT_FAST32_MAX__ 0xffffffffUGPIO1_NOT GPIO_NOT(GPIO1)__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4WINT_MIN __WINT_MIN__LCD_BASE (PERIPH_BASE_AHB + 0x08000)GPIO_B105 (GPIO_PORT_BASE + 0x0069)GPIO_B122 (GPIO_PORT_BASE + 0x007A)GPIO_B78 (GPIO_PORT_BASE + 0x004E)GPIO_SET(port) MMIO32((port) + 0x200)__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32GPIO_W219 (GPIO_PORT_BASE + 0x136C)__FLT32X_MIN_EXP__ (-1021)GPDMA_BASE (PERIPH_BASE_AHB + 0x02000)GPIO_B205 (GPIO_PORT_BASE + 0x00CD)GPIO_W104 (GPIO_PORT_BASE + 0x11A0)GPIO_W250 (GPIO_PORT_BASE + 0x13E8)GPIO_B82 (GPIO_PORT_BASE + 0x0052)GPIO_W204 (GPIO_PORT_BASE + 0x1330)GPIO_B12 (GPIO_PORT_BASE + 0x000C)BIT27 (1<<27)GPIO_W220 (GPIO_PORT_BASE + 0x1370)GPIO_B83 (GPIO_PORT_BASE + 0x0053)GPIO_W82 (GPIO_PORT_BASE + 0x1148)GPIO_W11 (GPIO_PORT_BASE + 0x102C)__GNUC_EXECUTION_CHARSET_NAME "UTF-8"GPIO_B85 (GPIO_PORT_BASE + 0x0055)__UTA_FBIT__ 64SDIO_BASE (PERIPH_BASE_AHB + 0x04000)GPIO_W189 (GPIO_PORT_BASE + 0x12F4)GPIO_GROUP0_INTERRUPT_PORT_ENA(x) MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x040 + ((x)*4))__FLT_DECIMAL_DIG__ 9__thumb__ 1__INT_LEAST32_MAX__ 0x7fffffffLGPIO6_SET GPIO_SET(GPIO6)signed charGIMA_BASE (PERIPH_BASE_APB2 + 0x07000)GPIO_B245 (GPIO_PORT_BASE + 0x00F5)INT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)INT32_C(c) __INT32_C(c)GPIO_W87 (GPIO_PORT_BASE + 0x115C)__GNUC_STDC_INLINE__ 1GPIO_B51 (GPIO_PORT_BASE + 0x0033)GPIO6_NOT GPIO_NOT(GPIO6)__FRACT_FBIT__ 15GPIO_W156 (GPIO_PORT_BASE + 0x1270)__LLACCUM_EPSILON__ 0x1P-31LLK__GNUC_PATCHLEVEL__ 1__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2PTRDIFF_MINGPIO_W225 (GPIO_PORT_BASE + 0x1384)__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)GPIO_PIN_INTERRUPT_CIENR MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x00C)UINTPTR_MAX __UINTPTR_MAX____ARM_ARCH_PROFILE 77GPIO_W252 (GPIO_PORT_BASE + 0x13F0)GPIO_B42 (GPIO_PORT_BASE + 0x002A)GPIO_B188 (GPIO_PORT_BASE + 0x00BC)GPIO6 (GPIO_PORT_BASE + 0x2018)GPIO_W130 (GPIO_PORT_BASE + 0x1208)__FLT64_MAX_10_EXP__ 308MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINGPIOPIN30 (1 << 30)__INT_FAST32_WIDTH__ 32GPIO_B6 (GPIO_PORT_BASE + 0x0006)CGU_BASE (0x40050000U)__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38__FRACT_MAX__ 0X7FFFP-15RGNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -O2 -std=c99 -fno-common -ffunction-sections -fdata-sectionsINT_LEAST32_MAX __INT_LEAST32_MAX__GPIO_B77 (GPIO_PORT_BASE + 0x004D)GPIO_B28 (GPIO_PORT_BASE + 0x001C)__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5GPIO_W172 (GPIO_PORT_BASE + 0x12B0)GPIOPIN31 (1 << 31)GPIO_W84 (GPIO_PORT_BASE + 0x1150)GPIO_W105 (GPIO_PORT_BASE + 0x11A4)GPIO_B11 (GPIO_PORT_BASE + 0x000B)GPIO_W39 (GPIO_PORT_BASE + 0x109C)__UINT16_MAX__ 0xffff__LDBL_MIN__ 2.2250738585072014e-308L__TQ_FBIT__ 127GPIO_B84 (GPIO_PORT_BASE + 0x0054)GPIO7_MASK GPIO_MASK(GPIO7)GPIO4_PIN GPIO_PIN(GPIO4)GPIO_B107 (GPIO_PORT_BASE + 0x006B)__USQ_FBIT__ 32INT_FAST16_MINGPIO_B119 (GPIO_PORT_BASE + 0x0077)__thumb2__ 1__ULLACCUM_FBIT__ 32GPIO_W139 (GPIO_PORT_BASE + 0x122C)GPIO_W113 (GPIO_PORT_BASE + 0x11C4)GPIO_W91 (GPIO_PORT_BASE + 0x116C)INT_FAST32_MIN (-INT_FAST32_MAX - 1)__STRICT_ANSI__ 1GPIO_W76 (GPIO_PORT_BASE + 0x1130)GPIO_W160 (GPIO_PORT_BASE + 0x1280)GPIO_B80 (GPIO_PORT_BASE + 0x0050)GPIO_B31 (GPIO_PORT_BASE + 0x001F)UINT_LEAST8_MAXGPIO2_DIR GPIO_DIR(GPIO2)UINT8_C(c) __UINT8_C(c)GPIO_W71 (GPIO_PORT_BASE + 0x111C)__SIZEOF_LONG_DOUBLE__ 8GPIO_W152 (GPIO_PORT_BASE + 0x1260)GPIO_W234 (GPIO_PORT_BASE + 0x13A8)GPIO_W187 (GPIO_PORT_BASE + 0x12EC)__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__GPIO_B68 (GPIO_PORT_BASE + 0x0044)__USA_IBIT__ 16__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1PTRDIFF_MIN (-PTRDIFF_MAX - 1)GPIO_W36 (GPIO_PORT_BASE + 0x1090)__UINT_FAST64_TYPE__ long long unsigned intGPIO_B5 (GPIO_PORT_BASE + 0x0005)GPIO_B110 (GPIO_PORT_BASE + 0x006E)GPIO_GROUP0_INTERRUPT_PORT_POL(x) MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x020 + ((x)*4))__FLT_MIN__ 1.1754943508222875e-38FGPIO4_DIR GPIO_DIR(GPIO4)__HA_FBIT__ 7__FDPIC__GPIOPIN10 (1 << 10)GPIO_PIN_INTERRUPT_IENF MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x010)__FLT32_IS_IEC_60559__ 2GPIO_B39 (GPIO_PORT_BASE + 0x0027)GPIO_W207 (GPIO_PORT_BASE + 0x133C)GPIO_B27 (GPIO_PORT_BASE + 0x001B)GPIO_W103 (GPIO_PORT_BASE + 0x119C)INT_FAST64_MINADC0_BASE (PERIPH_BASE_APB3 + 0x03000)__USFRACT_IBIT__ 0GPIOPIN24 (1 << 24)__LDBL_EPSILON__ 2.2204460492503131e-16LGPIO_W224 (GPIO_PORT_BASE + 0x1380)__USFRACT_MIN__ 0.0UHRGPIO_B157 (GPIO_PORT_BASE + 0x009D)__ARM_NEON__UINT8_MAX__ 0xff__LDBL_MAX_EXP__ 1024GPIO_B106 (GPIO_PORT_BASE + 0x006A)INT16_C(c) __INT16_C(c)GPIOPIN14 (1 << 14)GPIO_B139 (GPIO_PORT_BASE + 0x008B)__DBL_HAS_DENORM__ 1GPIOPIN25 (1 << 25)GPIO_B152 (GPIO_PORT_BASE + 0x0098)GPIO_W45 (GPIO_PORT_BASE + 0x10B4)GPIO3 (GPIO_PORT_BASE + 0x200C)GPIO_B159 (GPIO_PORT_BASE + 0x009F)__DA_FBIT__ 31GPIO_W126 (GPIO_PORT_BASE + 0x11F8)GPIOPIN12 (1 << 12)GPIO_W80 (GPIO_PORT_BASE + 0x1140)__GXX_ABI_VERSION 1017GPIO_W212 (GPIO_PORT_BASE + 0x1350)__INT_LEAST16_MAX__ 0x7fffGPIO_B30 (GPIO_PORT_BASE + 0x001E)__FLT_DENORM_MIN__ 1.4012984643248171e-45FGPIO_W161 (GPIO_PORT_BASE + 0x1284)GPIO_B69 (GPIO_PORT_BASE + 0x0045)GPIO_B193 (GPIO_PORT_BASE + 0x00C1)__ULLACCUM_EPSILON__ 0x1P-32ULLKGPIO_W191 (GPIO_PORT_BASE + 0x12FC)GPIO7_CLR GPIO_CLR(GPIO7)GPIOPIN26 (1 << 26)GPIO_PIN(port) MMIO32((port) + 0x100)INT_LEAST8_MAX __INT_LEAST8_MAX__DAC_BASE (PERIPH_BASE_APB3 + 0x01000)GPIO_B46 (GPIO_PORT_BASE + 0x002E)GPIO_B108 (GPIO_PORT_BASE + 0x006C)__UINT32_C(c) c ## ULGPIO0_SET GPIO_SET(GPIO0)__UACCUM_MIN__ 0.0UKGPIO_B63 (GPIO_PORT_BASE + 0x003F)GPIO_W173 (GPIO_PORT_BASE + 0x12B4)__FLT_EPSILON__ 1.1920928955078125e-7FGPIOPIN3 (1 << 3)GPIO_W97 (GPIO_PORT_BASE + 0x1184)GPIO_B148 (GPIO_PORT_BASE + 0x0094)GPIO_B186 (GPIO_PORT_BASE + 0x00BA)__ARM_ARCH_ISA_THUMBGPIO_B89 (GPIO_PORT_BASE + 0x0059)GPIO_W135 (GPIO_PORT_BASE + 0x121C)GPIO_B253 (GPIO_PORT_BASE + 0x00FD)__ARM_FEATURE_MATMUL_INT8GPIO_W23 (GPIO_PORT_BASE + 0x105C)GPIO_B26 (GPIO_PORT_BASE + 0x001A)__GCC_ATOMIC_SHORT_LOCK_FREE 2GPIO_W206 (GPIO_PORT_BASE + 0x1338)GPIO_B60 (GPIO_PORT_BASE + 0x003C)GPIO_PIN_INTERRUPT_FALL MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x020)GPIO_DIR(port) MMIO32((port) + 0x00)__USACCUM_FBIT__ 8GPIO_W4 (GPIO_PORT_BASE + 0x1010)__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1GPIO_W124 (GPIO_PORT_BASE + 0x11F0)__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)__LACCUM_FBIT__ 31GPIO_W110 (GPIO_PORT_BASE + 0x11B8)GPIO_W114 (GPIO_PORT_BASE + 0x11C8)GPIO_B233 (GPIO_PORT_BASE + 0x00E9)GPIO_W218 (GPIO_PORT_BASE + 0x1368)EMC_BASE (PERIPH_BASE_AHB + 0x05000)__FLT32_HAS_QUIET_NAN__ 1GPIO_B239 (GPIO_PORT_BASE + 0x00EF)__LDBL_HAS_INFINITY__ 1GPIO4_MPIN GPIO_MPIN(GPIO4)__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))CCU1_BASE (0x40051000U)GPIO_W90 (GPIO_PORT_BASE + 0x1168)__FLT32X_MAX_10_EXP__ 308__ARM_ARCH_EXT_IDIV__ 1bool _BoolGPIO_PIN_INTERRUPT_IENR MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x004)GPIO_W216 (GPIO_PORT_BASE + 0x1360)UINTMAX_MAX __UINTMAX_MAX____SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)GPIO_W81 (GPIO_PORT_BASE + 0x1144)__UINT_LEAST8_MAX__ 0xffGPIO_B90 (GPIO_PORT_BASE + 0x005A)BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)GPIO_W208 (GPIO_PORT_BASE + 0x1340)INT16_MAX __INT16_MAX____FP_FAST_FMAF 1GPIO_W180 (GPIO_PORT_BASE + 0x12D0)GPIOPIN17 (1 << 17)GPIO5_NOT GPIO_NOT(GPIO5)GPIO_W228 (GPIO_PORT_BASE + 0x1390)__FLT32X_IS_IEC_60559__ 2GPIO_W164 (GPIO_PORT_BASE + 0x1290)PERIPH_BASE_APB3 (0x400E0000U)LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))UINT32_MAXGPIO_W237 (GPIO_PORT_BASE + 0x13B4)__INT_LEAST16_WIDTH__ 16I2S0_BASE (PERIPH_BASE_APB1 + 0x02000)GPIO_B15 (GPIO_PORT_BASE + 0x000F)__DEC_EVAL_METHOD__ 2SCT_BASE (PERIPH_BASE_AHB + 0x00000)__ARM_FEATURE_FP16_FMLGPIO_B76 (GPIO_PORT_BASE + 0x004C)GPIO_W182 (GPIO_PORT_BASE + 0x12D8)GPIO_W202 (GPIO_PORT_BASE + 0x1328)INT16_MIN (-INT16_MAX - 1)__USFRACT_EPSILON__ 0x1P-8UHRGPIO_PIN_INTERRUPT_RISE MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x01C)GPIO2_PIN GPIO_PIN(GPIO2)GPIO0_MPIN GPIO_MPIN(GPIO0)GPIO_B72 (GPIO_PORT_BASE + 0x0048)SCU_BASE (PERIPH_BASE_APB0 + 0x06000)GPIO_B10 (GPIO_PORT_BASE + 0x000A)__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLKGPIO_B187 (GPIO_PORT_BASE + 0x00BB)__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX__GPIO_B54 (GPIO_PORT_BASE + 0x0036)__UINT32_MAX__ 0xffffffffULGPIO3_CLR GPIO_CLR(GPIO3)GPIO_GROUP1_INTERRUPT_PORT_ENA(x) MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x040 + ((x)*4))__INT_LEAST8_MAX__ 0x7f__GCC_ATOMIC_POINTER_LOCK_FREE 2__ARM_FEATURE_QBIT 1__ARM_FEATURE_CLZ 1__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXGPIO_B45 (GPIO_PORT_BASE + 0x002D)GPIO_W29 (GPIO_PORT_BASE + 0x1074)__ARM_PCS_VFP 1__UINT64_TYPE__ long long unsigned intGPIO_B250 (GPIO_PORT_BASE + 0x00FA)__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024GPIO_W162 (GPIO_PORT_BASE + 0x1288)GPIO_W184 (GPIO_PORT_BASE + 0x12E0)GPIO_B9 (GPIO_PORT_BASE + 0x0009)GPIO_W68 (GPIO_PORT_BASE + 0x1110)GPIO_PIN_INTERRUPT_SIENF MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x014)GPIO_W2 (GPIO_PORT_BASE + 0x1008)__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1LPC43XX_GPIO_H __ACCUM_MAX__ 0X7FFFFFFFP-15KGPIO_B124 (GPIO_PORT_BASE + 0x007C)__INT8_MAX__ 0x7fGPIO0_NOT GPIO_NOT(GPIO0)BIT14 (1<<14)__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16USB1_BASE (PERIPH_BASE_AHB + 0x07000)BIT20 (1<<20)__ARM_FEATURE_MVE__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intGPIO_B14 (GPIO_PORT_BASE + 0x000E)GPIO_W74 (GPIO_PORT_BASE + 0x1128)GPIO_B125 (GPIO_PORT_BASE + 0x007D)GPIO_B75 (GPIO_PORT_BASE + 0x004B)GPIO_W215 (GPIO_PORT_BASE + 0x135C)UINT_LEAST16_MAX __UINT_LEAST16_MAX__GPIO_B192 (GPIO_PORT_BASE + 0x00C0)GPIO_W198 (GPIO_PORT_BASE + 0x1318)INT_FAST32_MINGPIO_W229 (GPIO_PORT_BASE + 0x1394)../gpio.c__SCHAR_WIDTH__ 8BIT18 (1<<18)UINT_FAST16_MAX__UINT_FAST8_TYPE__ unsigned int__LLACCUM_IBIT__ 32GPIO_W13 (GPIO_PORT_BASE + 0x1034)__FRACT_EPSILON__ 0x1P-15RBIT24 (1<<24)GPIO_W43 (GPIO_PORT_BASE + 0x10AC)__INT32_MAX__ 0x7fffffffLGPIO_B154 (GPIO_PORT_BASE + 0x009A)GPIOPIN9 (1 << 9)UINTMAX_MAXGPIO_W112 (GPIO_PORT_BASE + 0x11C0)BIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_BF16_VECTOR_ARITHMETICGPIO_W109 (GPIO_PORT_BASE + 0x11B4)GPIO_B227 (GPIO_PORT_BASE + 0x00E3)__FLT32_MANT_DIG__ 24INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32GPIO_B44 (GPIO_PORT_BASE + 0x002C)EVENTROUTER_BASE (0x40044000U)__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN__GPIO_W200 (GPIO_PORT_BASE + 0x1320)__USFRACT_FBIT__ 8INT8_MAX __INT8_MAX__GPIO5_SET GPIO_SET(GPIO5)BIT28 (1<<28)GPIO_W108 (GPIO_PORT_BASE + 0x11B0)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2INTMAX_C(c) __INTMAX_C(c)GPIO_W163 (GPIO_PORT_BASE + 0x128C)__DBL_MAX_EXP__ 1024GPIO_W34 (GPIO_PORT_BASE + 0x1088)__ATOMIC_RELEASE 3GPIO_W95 (GPIO_PORT_BASE + 0x117C)UINT_FAST8_MAX__FLT_MANT_DIG__ 24USART0_BASE (PERIPH_BASE_APB0 + 0x01000)__UDQ_IBIT__ 0GPIO_B123 (GPIO_PORT_BASE + 0x007B)CCU2_BASE (0x40052000U)GPIO1_MPIN GPIO_MPIN(GPIO1)__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UKGPIO_W129 (GPIO_PORT_BASE + 0x1204)__FLT64_NORM_MAX__ 1.7976931348623157e+308F64PERIPH_BASE_APB1 (0x400A0000U)GPIO_B254 (GPIO_PORT_BASE + 0x00FE)UINTPTR_MAXGPIO_NOT(port) MMIO32((port) + 0x300)__LDBL_DENORM_MIN__ 4.9406564584124654e-324LTIMER3_BASE (PERIPH_BASE_APB2 + 0x04000)__INT64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_SAT 1GPIO_MPIN(port) MMIO32((port) + 0x180)GPIO_W75 (GPIO_PORT_BASE + 0x112C)GPIO_B185 (GPIO_PORT_BASE + 0x00B9)__ULLFRACT_IBIT__ 0GPIO_W6 (GPIO_PORT_BASE + 0x1018)GPIO_B93 (GPIO_PORT_BASE + 0x005D)SPI_PORT_BASE (0x40100000U)MMIO16(addr) (*(volatile uint16_t *)(addr))GPIO_B143 (GPIO_PORT_BASE + 0x008F)GPIO5_DIR GPIO_DIR(GPIO5)LPC43XX 1__GNUC__ 12GPIO_W159 (GPIO_PORT_BASE + 0x127C)GPIO1_CLR GPIO_CLR(GPIO1)GPIO_B55 (GPIO_PORT_BASE + 0x0037)WCHAR_MAXGPIO_B66 (GPIO_PORT_BASE + 0x0042)GPIO_B218 (GPIO_PORT_BASE + 0x00DA)__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0UGPIO_B177 (GPIO_PORT_BASE + 0x00B1)GPIO_B94 (GPIO_PORT_BASE + 0x005E)__UQQ_IBIT__ 0GPIO_W222 (GPIO_PORT_BASE + 0x1378)GPIO_B48 (GPIO_PORT_BASE + 0x0030)__GCC_ATOMIC_LONG_LOCK_FREE 2__ULACCUM_MIN__ 0.0ULKGPIO_W5 (GPIO_PORT_BASE + 0x1014)__LDBL_MAX__ 1.7976931348623157e+308L__ARM_ARCH 7GPIO_B133 (GPIO_PORT_BASE + 0x0085)/build/libopencm3/lib/lpc43xx/m4GPIO_B160 (GPIO_PORT_BASE + 0x00A0)__FLT_RADIX__ 2BIT3 (1<<3)long long intGPIO_W197 (GPIO_PORT_BASE + 0x1314)__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAXGPIO_W178 (GPIO_PORT_BASE + 0x12C8)GPIO_W238 (GPIO_PORT_BASE + 0x13B8)SGPIO_PORT_BASE (0x40101000U)GPIO_W49 (GPIO_PORT_BASE + 0x10C4)GPIO7 (GPIO_PORT_BASE + 0x201C)GPIO_W85 (GPIO_PORT_BASE + 0x1154)PERIPH_BASE_APB0 (0x40080000U)__LONG_LONG_WIDTH__ 64BIT6 (1<<6)GPIO_B142 (GPIO_PORT_BASE + 0x008E)GPIO_B33 (GPIO_PORT_BASE + 0x0021)__UINT_FAST64_MAX__ 0xffffffffffffffffULLGPIO_B29 (GPIO_PORT_BASE + 0x001D)__ARM_FPGPIO_W165 (GPIO_PORT_BASE + 0x1294)__HA_IBIT__ 8GPIO_B201 (GPIO_PORT_BASE + 0x00C9)__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1BIT9 (1<<9)__FLT32X_MIN__ 2.2250738585072014e-308F32xINTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024UINT16_MAXGPIO_W151 (GPIO_PORT_BASE + 0x125C)__FLT64_MIN__ 2.2250738585072014e-308F64__INTMAX_C(c) c ## LLGPIO_B180 (GPIO_PORT_BASE + 0x00B4)GPIO_W136 (GPIO_PORT_BASE + 0x1220)__FLT_EVAL_METHOD_TS_18661_3__ 0__ARM_ARCH_PROFILE__INT64_TYPE__ long long intGPIO_W48 (GPIO_PORT_BASE + 0x10C0)__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4GPIO_W147 (GPIO_PORT_BASE + 0x124C)GPIO_W235 (GPIO_PORT_BASE + 0x13AC)GPIO_B162 (GPIO_PORT_BASE + 0x00A2)GPIO_B166 (GPIO_PORT_BASE + 0x00A6)GPIO_W177 (GPIO_PORT_BASE + 0x12C4)GPIO_W241 (GPIO_PORT_BASE + 0x13C4)GPIO_B190 (GPIO_PORT_BASE + 0x00BE)__UFRACT_MAX__ 0XFFFFP-16URGPIO_B59 (GPIO_PORT_BASE + 0x003B)INT64_MAXGPIO_B176 (GPIO_PORT_BASE + 0x00B0)GPIO1 (GPIO_PORT_BASE + 0x2004)INT_FAST64_MIN (-INT_FAST64_MAX - 1)SSP1_BASE (PERIPH_BASE_APB2 + 0x05000)GPIO_B88 (GPIO_PORT_BASE + 0x0058)GPIO_W255 (GPIO_PORT_BASE + 0x13FC)SPIFI_BASE (PERIPH_BASE_AHB + 0x03000)__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__GPIO_W47 (GPIO_PORT_BASE + 0x10BC)GPIO_W77 (GPIO_PORT_BASE + 0x1134)GPIO_B138 (GPIO_PORT_BASE + 0x008A)GPIO_W118 (GPIO_PORT_BASE + 0x11D8)GPIO_W53 (GPIO_PORT_BASE + 0x10D4)__UFRACT_FBIT__ 16GPIO0_PIN GPIO_PIN(GPIO0)__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)GPIO_W42 (GPIO_PORT_BASE + 0x10A8)__LDBL_MAX_10_EXP__ 308GPIO_B21 (GPIO_PORT_BASE + 0x0015)GPIO_W3 (GPIO_PORT_BASE + 0x100C)GPIO1_MASK GPIO_MASK(GPIO1)GPIO_B231 (GPIO_PORT_BASE + 0x00E7)GPIO_W94 (GPIO_PORT_BASE + 0x1178)__INT_FAST32_TYPE__ intGPIO_B200 (GPIO_PORT_BASE + 0x00C8)GPIO_B62 (GPIO_PORT_BASE + 0x003E)unsigned intGPIO_W73 (GPIO_PORT_BASE + 0x1124)__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1GPIO0_DIR GPIO_DIR(GPIO0)GPIO_B158 (GPIO_PORT_BASE + 0x009E)GPIO_B210 (GPIO_PORT_BASE + 0x00D2)__USACCUM_IBIT__ 8GPIO_W140 (GPIO_PORT_BASE + 0x1230)GPIO_MASK(port) MMIO32((port) + 0x80)__ARM_ARCH_7EM__ 1__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UKGPIO_W236 (GPIO_PORT_BASE + 0x13B0)GPIO_B141 (GPIO_PORT_BASE + 0x008D)GPIO_B134 (GPIO_PORT_BASE + 0x0086)GPIO_W120 (GPIO_PORT_BASE + 0x11E0)__FLT_EVAL_METHOD__ 0GPIO_B165 (GPIO_PORT_BASE + 0x00A5)GPIO_PORT_BASE (0x400F4000U)__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32GPIO_B79 (GPIO_PORT_BASE + 0x004F)GPIO_W16 (GPIO_PORT_BASE + 0x1040)__ARM_FEATURE_LDREXGPIO_B58 (GPIO_PORT_BASE + 0x003A)__UQQ_FBIT__ 8GPIO_B230 (GPIO_PORT_BASE + 0x00E6)__HQ_FBIT__ 15GPIOPIN8 (1 << 8)__ARM_FP16_ARGS__GCC_IEC_559 0GPIO_W127 (GPIO_PORT_BASE + 0x11FC)INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX__GPIO_B127 (GPIO_PORT_BASE + 0x007F)__LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4GPIO4_CLR GPIO_CLR(GPIO4)__STDC__ 1GPIO_W244 (GPIO_PORT_BASE + 0x13D0)GPIO_B240 (GPIO_PORT_BASE + 0x00F0)GPIOPIN20 (1 << 20)__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__GPIO_B65 (GPIO_PORT_BASE + 0x0041)__UINT8_TYPE__ unsigned charGPIO_W63 (GPIO_PORT_BASE + 0x10FC)gpio_setGPIO_W7 (GPIO_PORT_BASE + 0x101C)__ARM_FEATURE_COPROC 15GPIO_W192 (GPIO_PORT_BASE + 0x1300)GPIO_W119 (GPIO_PORT_BASE + 0x11DC)UINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"GPIO0 (GPIO_PORT_BASE + 0x2000)INT8_MINGPIO_B195 (GPIO_PORT_BASE + 0x00C3)GPIO_W37 (GPIO_PORT_BASE + 0x1094)true 1__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)GPIO_B226 (GPIO_PORT_BASE + 0x00E2)__LDBL_MIN_10_EXP__ (-307)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1__GCC_ATOMIC_CHAR_LOCK_FREE 2GPIO5_PIN GPIO_PIN(GPIO5)__LFRACT_EPSILON__ 0x1P-31LRGPIO_W106 (GPIO_PORT_BASE + 0x11A8)GPIO_B18 (GPIO_PORT_BASE + 0x0012)GPIO_W27 (GPIO_PORT_BASE + 0x106C)GPIO_W196 (GPIO_PORT_BASE + 0x1310)__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX__GPIO_W141 (GPIO_PORT_BASE + 0x1234)__FLT32X_NORM_MAX__ 1.7976931348623157e+308F32x__arm__ 1INT_FAST64_MAXGPIO_W138 (GPIO_PORT_BASE + 0x1228)GPIO_W9 (GPIO_PORT_BASE + 0x1024)GPIO_W210 (GPIO_PORT_BASE + 0x1348)GPIO_B47 (GPIO_PORT_BASE + 0x002F)__FLT32_MIN_10_EXP__ (-37)GPIO_W231 (GPIO_PORT_BASE + 0x139C)GPIO_B164 (GPIO_PORT_BASE + 0x00A4)MMIO64(addr) (*(volatile uint64_t *)(addr))GPIO_W88 (GPIO_PORT_BASE + 0x1160)__ARM_FP16_FORMAT_ALTERNATIVE__LDBL_NORM_MAX__ 1.7976931348623157e+308LGPIO_W78 (GPIO_PORT_BASE + 0x1138)INTPTR_MINGPIO_W254 (GPIO_PORT_BASE + 0x13F8)__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)GPIO_W199 (GPIO_PORT_BASE + 0x131C)GPIO_B155 (GPIO_PORT_BASE + 0x009B)__TA_IBIT__ 64GPIO_B208 (GPIO_PORT_BASE + 0x00D0)GPIO_B191 (GPIO_PORT_BASE + 0x00BF)__FLT32_MIN__ 1.1754943508222875e-38F32GPIO_B126 (GPIO_PORT_BASE + 0x007E)GPIO_W46 (GPIO_PORT_BASE + 0x10B8)PERIPH_BASE_AHB (0x40000000U)GPIO_W20 (GPIO_PORT_BASE + 0x1050)__ARM_FEATURE_QRDMXGPIO_W245 (GPIO_PORT_BASE + 0x13D4)GPIO_B184 (GPIO_PORT_BASE + 0x00B8)__ARM_ARCH_ISA_THUMB 2GPIO_W190 (GPIO_PORT_BASE + 0x12F8)GPIO_W213 (GPIO_PORT_BASE + 0x1354)__LONG_LONG_MAX__ 0x7fffffffffffffffLL__WINT_WIDTH__ 32GPIO_B215 (GPIO_PORT_BASE + 0x00D7)SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__GPIO_B194 (GPIO_PORT_BASE + 0x00C2)BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN__GPIO_W99 (GPIO_PORT_BASE + 0x118C)__SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__DBL_MIN_EXP__ (-1021)__LDBL_HAS_DENORM__ 1GPIO_W194 (GPIO_PORT_BASE + 0x1308)GPIO_B32 (GPIO_PORT_BASE + 0x0020)INT8_MIN (-INT8_MAX - 1)GPIO_W167 (GPIO_PORT_BASE + 0x129C)GPIO_GROUP1_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x09000)GPIOPIN28 (1 << 28)__FLT32_DIG__ 6INT_LEAST16_MAXGPIO_W111 (GPIO_PORT_BASE + 0x11BC)BIT15 (1<<15)BACKUP_REG_BASE (0x40041000U)GPIOPIN15 (1 << 15)GPIO_W142 (GPIO_PORT_BASE + 0x1238)GPIO_B56 (GPIO_PORT_BASE + 0x0038)GPIO_B225 (GPIO_PORT_BASE + 0x00E1)BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1GPIO_GROUP0_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x08000)__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1INT32_MAXGPIO_W233 (GPIO_PORT_BASE + 0x13A4)GPIOPIN29 (1 << 29)__ACCUM_MIN__ (-0X1P15K-0X1P15K)GPIO_B196 (GPIO_PORT_BASE + 0x00C4)__ARM_FEATURE_CRYPTO__INT_LEAST32_TYPE__ long intGPIO_W79 (GPIO_PORT_BASE + 0x113C)GPIOPIN16 (1 << 16)GPIO_W51 (GPIO_PORT_BASE + 0x10CC)GPIO_W18 (GPIO_PORT_BASE + 0x1048)GPIO_W102 (GPIO_PORT_BASE + 0x1198)BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULLGPIO5_MASK GPIO_MASK(GPIO5)__FRACT_IBIT__ 0I2C1_BASE (PERIPH_BASE_APB3 + 0x00000)UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2GPIO_B25 (GPIO_PORT_BASE + 0x0019)BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234GPIO7_SET GPIO_SET(GPIO7)__FLT_NORM_MAX__ 3.4028234663852886e+38FGPIO_B183 (GPIO_PORT_BASE + 0x00B7)long long unsigned intGPIO_W246 (GPIO_PORT_BASE + 0x13D8)__FLT_MIN_10_EXP__ (-37)BIT31 (1<<31)GPIO7_MPIN GPIO_MPIN(GPIO7)__ULACCUM_IBIT__ 32__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2GPIO_W38 (GPIO_PORT_BASE + 0x1098)__PTRDIFF_TYPE__ intGPIO_W41 (GPIO_PORT_BASE + 0x10A4)__APCS_32__ 1__DQ_FBIT__ 63GPIO_W56 (GPIO_PORT_BASE + 0x10E0)GPIO_B144 (GPIO_PORT_BASE + 0x0090)INT_LEAST64_MAX__SACCUM_IBIT__ 8GPIO_B236 (GPIO_PORT_BASE + 0x00EC)__UHQ_IBIT__ 0INT_LEAST8_MINGPIO_W176 (GPIO_PORT_BASE + 0x12C0)GPIO_W170 (GPIO_PORT_BASE + 0x12A8)BIT29 (1<<29)__INT_FAST16_TYPE__ intGPIO_B169 (GPIO_PORT_BASE + 0x00A9)GPIO6_DIR GPIO_DIR(GPIO6)INT64_C__ULFRACT_MAX__ 0XFFFFFFFFP-32ULRGPIO_B131 (GPIO_PORT_BASE + 0x0083)__UINT_LEAST16_TYPE__ short unsigned int__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned intGPIO_W89 (GPIO_PORT_BASE + 0x1164)GPIO_W59 (GPIO_PORT_BASE + 0x10EC)GPIO_B212 (GPIO_PORT_BASE + 0x00D4)__FLT32X_DIG__ 15GPIO_B179 (GPIO_PORT_BASE + 0x00B3)GPIO_B100 (GPIO_PORT_BASE + 0x0064)__UTQ_FBIT__ 128GPIO_W155 (GPIO_PORT_BASE + 0x126C)__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffffGPIO_W133 (GPIO_PORT_BASE + 0x1214)GPIO_B244 (GPIO_PORT_BASE + 0x00F4)GPIO3_DIR GPIO_DIR(GPIO3)GPIO_B189 (GPIO_PORT_BASE + 0x00BD)PTRDIFF_MAX __PTRDIFF_MAX____SIZEOF_SHORT__ 2GPIO_W209 (GPIO_PORT_BASE + 0x1344)GPIO_W239 (GPIO_PORT_BASE + 0x13BC)GPIO6_MASK GPIO_MASK(GPIO6)GPIO_B174 (GPIO_PORT_BASE + 0x00AE)__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKGPIO_W242 (GPIO_PORT_BASE + 0x13C8)GPIO_W22 (GPIO_PORT_BASE + 0x1058)UINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRGPIO_W40 (GPIO_PORT_BASE + 0x10A0)GPIOPIN7 (1 << 7)__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intGPIO_W121 (GPIO_PORT_BASE + 0x11E4)GPIO_B170 (GPIO_PORT_BASE + 0x00AA)GPIO_B146 (GPIO_PORT_BASE + 0x0092)SSP0_BASE (PERIPH_BASE_APB0 + 0x03000)GPIO_B182 (GPIO_PORT_BASE + 0x00B6)QEI_BASE (PERIPH_BASE_APB2 + 0x06000)WCHAR_MINGPIO_B140 (GPIO_PORT_BASE + 0x008C)GPIO_B137 (GPIO_PORT_BASE + 0x0089)BEGIN_DECLS GPIO_B213 (GPIO_PORT_BASE + 0x00D5)GPIO_B99 (GPIO_PORT_BASE + 0x0063)GPIO_W60 (GPIO_PORT_BASE + 0x10F0)GPIO_W72 (GPIO_PORT_BASE + 0x1120)GPIO_B20 (GPIO_PORT_BASE + 0x0014)GPIO_W57 (GPIO_PORT_BASE + 0x10E4)GPIO2_MASK GPIO_MASK(GPIO2)GPIO_W50 (GPIO_PORT_BASE + 0x10C8)__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__FLT32X_MAX__ 1.7976931348623157e+308F32xGPIO_B168 (GPIO_PORT_BASE + 0x00A8)GPIO_W117 (GPIO_PORT_BASE + 0x11D4)GPIO_B238 (GPIO_PORT_BASE + 0x00EE)__ARM_EABI__ 1INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1__ARM_FEATURE_DSP 1GPIO_B178 (GPIO_PORT_BASE + 0x00B2)USART3_BASE (PERIPH_BASE_APB2 + 0x02000)__QQ_IBIT__ 0GPIO_W12 (GPIO_PORT_BASE + 0x1030)GPIO_W98 (GPIO_PORT_BASE + 0x1188)GPIO_B153 (GPIO_PORT_BASE + 0x0099)GPIO_B209 (GPIO_PORT_BASE + 0x00D1)GPIO_W144 (GPIO_PORT_BASE + 0x1240)__LLACCUM_FBIT__ 31GPIO_B243 (GPIO_PORT_BASE + 0x00F3)GPIO3_PIN GPIO_PIN(GPIO3)__UINTMAX_TYPE__ long long unsigned int__FLT32X_MIN_10_EXP__ (-307)GPIO_B16 (GPIO_PORT_BASE + 0x0010)__USQ_IBIT__ 0__UINT_LEAST32_TYPE__ long unsigned intGPIO_B50 (GPIO_PORT_BASE + 0x0032)GPIO_W243 (GPIO_PORT_BASE + 0x13CC)__ARM_FEATURE_NUMERIC_MAXMIN__INTMAX_TYPE__ long long int__GCC_ATOMIC_INT_LOCK_FREE 2GPIO_W35 (GPIO_PORT_BASE + 0x108C)GPIO_W30 (GPIO_PORT_BASE + 0x1078)GPIO_B198 (GPIO_PORT_BASE + 0x00C6)INTMAX_MAXGPIO_W21 (GPIO_PORT_BASE + 0x1054)TIMER2_BASE (PERIPH_BASE_APB2 + 0x03000)GPIO_B117 (GPIO_PORT_BASE + 0x0075)GPIO_GROUP1_INTERRUPT_PORT_POL(x) MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x020 + ((x)*4))__ARM_FEATURE_FP16_SCALAR_ARITHMETICGPIO_B229 (GPIO_PORT_BASE + 0x00E5)__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1GPIO_W181 (GPIO_PORT_BASE + 0x12D4)GPIO_B95 (GPIO_PORT_BASE + 0x005F)__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CGPIO2_SET GPIO_SET(GPIO2)GPIO_W248 (GPIO_PORT_BASE + 0x13E0)GPIO_B214 (GPIO_PORT_BASE + 0x00D6)GPIOPIN2 (1 << 2)INT64_MIN__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intGPIO_W26 (GPIO_PORT_BASE + 0x1068)UINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRGPIO5_CLR GPIO_CLR(GPIO5)GPIO_W58 (GPIO_PORT_BASE + 0x10E8)GPIO4 (GPIO_PORT_BASE + 0x2010)GPIO_B81 (GPIO_PORT_BASE + 0x0051)__SIZEOF_SIZE_T__ 4GPIO_B167 (GPIO_PORT_BASE + 0x00A7)PMC_BASE (0x40042000U)GPIO_W230 (GPIO_PORT_BASE + 0x1398)__INT64_C(c) c ## LLgpioportgpio_toggleGPIO_W223 (GPIO_PORT_BASE + 0x137C)UART1_BASE (PERIPH_BASE_APB0 + 0x02000)GPIO_B232 (GPIO_PORT_BASE + 0x00E8)__LONG_MAX__ 0x7fffffffL__ARM_FEATURE_CDE__ACCUM_IBIT__ 16GPIO_W64 (GPIO_PORT_BASE + 0x1100)GPIO_B211 (GPIO_PORT_BASE + 0x00D3)GPIO3_SET GPIO_SET(GPIO3)GPIO_B242 (GPIO_PORT_BASE + 0x00F2)GPIO_W145 (GPIO_PORT_BASE + 0x1244)short intGPIO_W175 (GPIO_PORT_BASE + 0x12BC)__UINT16_C(c) cGPIO_W214 (GPIO_PORT_BASE + 0x1358)__UDA_IBIT__ 32GPIO_W232 (GPIO_PORT_BASE + 0x13A0)GPIO_B1 (GPIO_PORT_BASE + 0x0001)UINT_LEAST32_MAXGPIO_B197 (GPIO_PORT_BASE + 0x00C5)BIT2 (1<<2)GPIO_W24 (GPIO_PORT_BASE + 0x1060)__ATOMIC_RELAXED 0GPIO_W31 (GPIO_PORT_BASE + 0x107C)__ARM_FEATURE_COPROCGPIO_W96 (GPIO_PORT_BASE + 0x1180)__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53GPIO1_DIR GPIO_DIR(GPIO1)__ARM_FEATURE_FMA 1LPC43XX_M4 1BIT5 (1<<5)GPIO_B35 (GPIO_PORT_BASE + 0x0023)BIT1 (1<<1)GPIO_B224 (GPIO_PORT_BASE + 0x00E0)INT8_CINT_LEAST32_MAXGPIO3_MASK GPIO_MASK(GPIO3)__USES_INITFINI__ 1I2S1_BASE (PERIPH_BASE_APB1 + 0x03000)GPIO_W249 (GPIO_PORT_BASE + 0x13E4)__DBL_DECIMAL_DIG__ 17GPIO_B228 (GPIO_PORT_BASE + 0x00E4)BIT8 (1<<8)GPIO_GROUP1_INTERRUPT_CTRL MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x000)GPIO_W62 (GPIO_PORT_BASE + 0x10F8)GPIO7_NOT GPIO_NOT(GPIO7)GPIO_W14 (GPIO_PORT_BASE + 0x1038)GPIO_B248 (GPIO_PORT_BASE + 0x00F8)__INT16_MAX__ 0x7fffGPIO_W0 (GPIO_PORT_BASE + 0x1000)__INT_WIDTH__ 32__ARM_FEATURE_SIMD32 1GPIO_W123 (GPIO_PORT_BASE + 0x11EC)GPIO_B199 (GPIO_PORT_BASE + 0x00C7)__QQ_FBIT__ 7RITIMER_BASE (PERIPH_BASE_APB2 + 0x00000)GPIO_B255 (GPIO_PORT_BASE + 0x00FF)__SIG_ATOMIC_WIDTH__ 32GPIO_B111 (GPIO_PORT_BASE + 0x006F)__FLT64_EPSILON__ 2.2204460492503131e-16F64GPIO_W217 (GPIO_PORT_BASE + 0x1364)INT16_CGPIO_W101 (GPIO_PORT_BASE + 0x1194)__UTA_IBIT__ 64__ULLACCUM_IBIT__ 32__SHRT_WIDTH__ 16RGU_BASE (0x40053000U)__ULLFRACT_EPSILON__ 0x1P-64ULLRfalse 0GPIO_W146 (GPIO_PORT_BASE + 0x1248)__UINT_LEAST32_MAX__ 0xffffffffUL__SIZEOF_WINT_T__ 4__ARM_FEATURE_UNALIGNED 1__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17GPIO_B0 (GPIO_PORT_BASE + 0x0000)GPIO_W128 (GPIO_PORT_BASE + 0x1200)GPIO_B241 (GPIO_PORT_BASE + 0x00F1)GPIO_W116 (GPIO_PORT_BASE + 0x11D0)__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)GPIOPIN13 (1 << 13)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1GPIO_B24 (GPIO_PORT_BASE + 0x0018)__FLT32X_HAS_DENORM__ 1GPIO_W25 (GPIO_PORT_BASE + 0x1064)__ULLACCUM_MIN__ 0.0ULLKGPIO_W150 (GPIO_PORT_BASE + 0x1258)GPIO_PIN_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x07000)GPIOPIN6 (1 << 6)GPIO_W55 (GPIO_PORT_BASE + 0x10DC)GPIO_W166 (GPIO_PORT_BASE + 0x1298)GPIO_W92 (GPIO_PORT_BASE + 0x1170)GPIO_W65 (GPIO_PORT_BASE + 0x1104)GPIO_B34 (GPIO_PORT_BASE + 0x0022)__ARM_ASM_SYNTAX_UNIFIED__ 1GPIO_W171 (GPIO_PORT_BASE + 0x12AC)GPIO_W253 (GPIO_PORT_BASE + 0x13F4)__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODGPIO_B103 (GPIO_PORT_BASE + 0x0067)RTC_BASE (0x40046000U)GPIO_W107 (GPIO_PORT_BASE + 0x11AC)__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H GPIO_B247 (GPIO_PORT_BASE + 0x00F7)GPIO_B113 (GPIO_PORT_BASE + 0x0071)AES_BASE (0x400F1000U)GPIO_B156 (GPIO_PORT_BASE + 0x009C)INT_LEAST64_MINGPIO1_PIN GPIO_PIN(GPIO1)__GCC_CONSTRUCTIVE_SIZE 64GPIO_W15 (GPIO_PORT_BASE + 0x103C)__LLFRACT_IBIT__ 0GPIO_W1 (GPIO_PORT_BASE + 0x1004)GPIO_W211 (GPIO_PORT_BASE + 0x134C)uint32_tBIT12 (1<<12)GPIO_W61 (GPIO_PORT_BASE + 0x10F4)GPIOPIN11 (1 << 11)__SACCUM_EPSILON__ 0x1P-7HK__GCC_ASM_FLAG_OUTPUTS__ 1GPIO_B64 (GPIO_PORT_BASE + 0x0040)GPIO_W8 (GPIO_PORT_BASE + 0x1020)__ARM_FP 4GPIO_W174 (GPIO_PORT_BASE + 0x12B8)GPIO_B181 (GPIO_PORT_BASE + 0x00B5)GPIO_B173 (GPIO_PORT_BASE + 0x00AD)__UINT_FAST16_TYPE__ unsigned int__UHA_IBIT__ 8GPIO_W66 (GPIO_PORT_BASE + 0x1108)GPIO_PIN_INTERRUPT_CIENF MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x018)__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULK__LDBL_DIG__ 15GPIO_B204 (GPIO_PORT_BASE + 0x00CC)UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXGPIO_B216 (GPIO_PORT_BASE + 0x00D8)BIT16 (1<<16)__WINT_MIN__ 0UINT_LEAST16_MINGPIO_W125 (GPIO_PORT_BASE + 0x11F4)__FLT64_DIG__ 15GPIO_B23 (GPIO_PORT_BASE + 0x0017)__WINT_MAX__ 0xffffffffUBIT22 (1<<22)__INT_LEAST8_WIDTH__ 8GPIOPIN21 (1 << 21)GPIO_W137 (GPIO_PORT_BASE + 0x1224)__INT_LEAST16_TYPE__ short intGPIO_W86 (GPIO_PORT_BASE + 0x1158)__DBL_MAX__ ((double)1.7976931348623157e+308L)GPIO_W44 (GPIO_PORT_BASE + 0x10B0)INT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1GPIO3_NOT GPIO_NOT(GPIO3)UINTMAX_CGPIO_W185 (GPIO_PORT_BASE + 0x12E4)GPIO_W83 (GPIO_PORT_BASE + 0x114C)INT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1__UINTPTR_MAX__ 0xffffffffUGPIO_B129 (GPIO_PORT_BASE + 0x0081)GPIO_B102 (GPIO_PORT_BASE + 0x0066)GPIOPIN1 (1 << 1)__bool_true_false_are_defined 1USART2_BASE (PERIPH_BASE_APB2 + 0x01000)GPIO_B151 (GPIO_PORT_BASE + 0x0097)BIT26 (1<<26)GPIO_B234 (GPIO_PORT_BASE + 0x00EA)__SIZE_MAX__ 0xffffffffU__FLT32X_HAS_INFINITY__ 1GPIO_B246 (GPIO_PORT_BASE + 0x00F6)GPIO_B112 (GPIO_PORT_BASE + 0x0070)GPIO_B109 (GPIO_PORT_BASE + 0x006D)GPIO_B19 (GPIO_PORT_BASE + 0x0013)GPIO_PIN_INTERRUPT_ISEL MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x000)__ARM_ARCHGPIO_W143 (GPIO_PORT_BASE + 0x123C)__SFRACT_IBIT__ 0MCPWM_BASE (PERIPH_BASE_APB1 + 0x00000)GPIO0_MASK GPIO_MASK(GPIO0)GPIOPIN23 (1 << 23)LPC43XX_MEMORYMAP_H __ARM_FEATURE_LDREX 7PTRDIFF_MAXGPIO_W54 (GPIO_PORT_BASE + 0x10D8)GPIO_W201 (GPIO_PORT_BASE + 0x1324)__SIZE_TYPE__ unsigned intGPIO7_DIR GPIO_DIR(GPIO7)GPIO_B172 (GPIO_PORT_BASE + 0x00AC)__LLFRACT_EPSILON__ 0x1P-63LLRGPIO2_NOT GPIO_NOT(GPIO2)GPIO_W70 (GPIO_PORT_BASE + 0x1118)__SFRACT_MAX__ 0X7FP-7HR__FLT32X_MANT_DIG__ 53GPIO_W226 (GPIO_PORT_BASE + 0x1388)GPIO_W205 (GPIO_PORT_BASE + 0x1334)__WCHAR_WIDTH__ 32GPIO_B203 (GPIO_PORT_BASE + 0x00CB)GPIO_GROUP0_INTERRUPT_CTRL MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x000)WINT_MAX__INT16_C(c) cGPIO_W134 (GPIO_PORT_BASE + 0x1218)INT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32GPIOPIN22 (1 << 22)GPIO_CLR(port) MMIO32((port) + 0x280)GPIO2_MPIN GPIO_MPIN(GPIO2)GPIO_B49 (GPIO_PORT_BASE + 0x0031)GPIO_B22 (GPIO_PORT_BASE + 0x0016)GPIO_W17 (GPIO_PORT_BASE + 0x1044)__ATOMIC_ACQ_REL 4ADC1_BASE (PERIPH_BASE_APB3 + 0x04000)__HQ_IBIT__ 0__DBL_MIN_10_EXP__ (-307)GPIO_B118 (GPIO_PORT_BASE + 0x0076)GPIO_B96 (GPIO_PORT_BASE + 0x0060)GPIO_B223 (GPIO_PORT_BASE + 0x00DF)__FLT32_NORM_MAX__ 3.4028234663852886e+38F32GPIO_W186 (GPIO_PORT_BASE + 0x12E8)GPIO_B61 (GPIO_PORT_BASE + 0x003D)GPIO_B128 (GPIO_PORT_BASE + 0x0080)GPIO_B101 (GPIO_PORT_BASE + 0x0065)UINT64_C(c) __UINT64_C(c)__UINTMAX_MAX__ 0xffffffffffffffffULL__DBL_MANT_DIG__ 53__ULFRACT_IBIT__ 0INT_FAST16_MAX__INT_MAX__ 0x7fffffff__INT_LEAST64_TYPE__ long long intGPIO_B115 (GPIO_PORT_BASE + 0x0073)GPIO_B53 (GPIO_PORT_BASE + 0x0035)GPIO_B52 (GPIO_PORT_BASE + 0x0034)__ARM_FEATURE_CDE_COPROCGPIO_W132 (GPIO_PORT_BASE + 0x1210)UINT32_CGCC: (15:12.2.rel1-1) 12.2.1 20221205 |   A3aeabi)7E-M M  "        %'!#) 2c+(+Z c n gpio.c$twm4.0.ac8f3cbd7733ee78183be95102ca936awm4.common.h.21.c9066c2f6b12c71b40226ea6107829a4wm4.stdint.h.29.6d480f4ba0f60596e88234283d42444fwm4.stdbool.h.29.4a1c88fe569adb8d03217dd16982ca34wm4.common.h.67.5c568a1f62c8e726909b04e29f9e1fc0wm4.memorymap.h.22.395ffb693017d551ed93d11c39ba4361wm4.gpio.h.46.2a912037b60fe08c1ef966b6326bdfdagpio_setgpio_cleargpio_toggle "&-4;BIPUcjx}     $-3<B #)/5;AGMSY_ekqw} %+17=CIOU[agmsy !'-39?EKQW]ciou{ #)/5;AGMSY_ekqw} %+17=CIOU[agmsy !'-39?EKQW]ciou{ #)/5;AGMSY_ekqw} %+17=CIOU[agmsy !'-39?EKQW]ciou{     # ) / 5 ; A G M S Y _ e k q w }                            % + 1 7 = C I O U [ a g m s y          #)/5;AGMSY_ekqx  '.5<CJQX_fmt{#*18?FMT[bipw~ &-4;BI  #)/5;AGMSY_ekqw} #)/5;AGMSY_ekqw} %+17=CIOU\ #)/5;AGMSY_ekqw} %+18?FMT[bipw~ &-4;BIPW^elsz ")07>ELSZahov} %,3:AHOV]dkry !(/6=DKRY`gnu|$+29@GNU\cjqx  '.5<CJQX_fmt{#*18?FMT[bipw~     & - 4 ; B I P W ^ e l s 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:,;55s/Dtbu_xFQyZzA{h.|D}Q~UL_17& 6>9&QjLbieg`h>D=X/ +#ilQK / 8&1n)U!>m  mZ]a<wRK n6]Y=' Z"3%Aa[VN7[$Y%=6,W@'M)eH&qE;4#$o-4?(S=BTkPTcXnR= jLVs K<#7a `G% 5R_jDc3_%Y,^lRT3Hb##?5 J_*T3^m+FAUX_jObi A(k] %O;4V*cZk0J){jQB%^fVGbc ../usr/lib/gcc/arm-none-eabi/12.2.1/include../../../include/libopencm3/lpc43xx../../../include/libopencm3/cm3scu.cstdint.hscu.hcommon.hstdbool.hmemorymap.h(!SCU_SFSP5_2 SCU_SFS(PIN_GROUP5, PIN2)SCU_SFSP2_12 SCU_SFS(PIN_GROUP2, PIN12)SCU_SFSPB_5 SCU_SFS(PIN_GROUPB, PIN5)__DECIMAL_DIG__ 17__FLT64_EPSILON__ 2.2204460492503131e-16F64SCU_CONF_FUNCTION1 (0x1)PERIPH_BASE_APB3 (0x400E0000U)__FLT_HAS_QUIET_NAN__ 1__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64__WCHAR_MIN__ 0USCU_SFSP2_4 SCU_SFS(PIN_GROUP2, PIN4)__GCC_ATOMIC_WCHAR_T_LOCK_FREE 2__CHAR_UNSIGNED__ 1ETHERNET_BASE (PERIPH_BASE_AHB + 0x10000)PIN2 0x008SCU_SFSPD_14 SCU_SFS(PIN_GROUPD, PIN14)SCU_SFSP2_11 SCU_SFS(PIN_GROUP2, PIN11)__FLT64_HAS_INFINITY__ 1SCU_SFSPE_2 SCU_SFS(PIN_GROUPE, PIN2)__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GCC_DESTRUCTIVE_SIZE 64__LACCUM_EPSILON__ 0x1P-31LKSCU_SFSP4_0 SCU_SFS(PIN_GROUP4, PIN0)__PTRDIFF_MAX__ 0x7fffffff__ARM_FEATURE_FMA 1SCU_SFSP8_5 SCU_SFS(PIN_GROUP8, PIN5)__INTMAX_C(c) c ## LLSCU_SFSP5_1 SCU_SFS(PIN_GROUP5, PIN1)__INTMAX_MAX__ 0x7fffffffffffffffLL__TQ_IBIT__ 0__FLT64_DECIMAL_DIG__ 17WINT_MIN __WINT_MIN__INT_FAST64_MAX__ATOMIC_CONSUME 1__LFRACT_MIN__ (-0.5LR-0.5LR)__WCHAR_MAX__ 0xffffffffU__ACCUM_MIN__ (-0X1P15K-0X1P15K)OTP_BASE (0x40045000U)SCU_CONF_FUNCTION7 (0x7)SCU_SFSP7_1 SCU_SFS(PIN_GROUP7, PIN1)INT64_MAX __INT64_MAX__INTMAX_MINP1_18SCU_SFSP2_13 SCU_SFS(PIN_GROUP2, PIN13)__DBL_MAX_10_EXP__ 308__FRACT_MIN__ (-0.5R-0.5R)__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLK__USACCUM_MAX__ 0XFFFFP-8UHK__SFRACT_FBIT__ 7__INTMAX_WIDTH__ 64P8_6__ARM_FEATURE_BF16_SCALAR_ARITHMETIC__SQ_IBIT__ 0__ORDER_PDP_ENDIAN__ 3412__SIZE_TYPE__ unsigned intSCU_CONF_FUNCTION4 (0x4)C_CCAN1_BASE (PERIPH_BASE_APB1 + 0x04000)__FLT_HAS_DENORM__ 1__INT8_TYPE__ signed char__FLT32_MIN__ 1.1754943508222875e-38F32__USACCUM_MIN__ 0.0UHKSCU_SFSPB_4 SCU_SFS(PIN_GROUPB, PIN4)__FLT32_DECIMAL_DIG__ 9LCD_BASE (PERIPH_BASE_AHB + 0x08000)SCU_SFSPF_9 SCU_SFS(PIN_GROUPF, PIN9)__LDBL_MIN_EXP__ (-1021)SCU_SFSP1_2 SCU_SFS(PIN_GROUP1, PIN2)__LDBL_MANT_DIG__ 53INT64_MIN (-INT64_MAX - 1)SCU_SFSP5_7 SCU_SFS(PIN_GROUP5, PIN7)__UINT8_C(c) c__INT16_TYPE__ short int__FLT64_MAX__ 1.7976931348623157e+308F64USB0_BASE (PERIPH_BASE_AHB + 0x06000)UINT_FAST32_MAXINT_FAST64_MAX __INT_FAST64_MAX____GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1SCU_SFSP8_4 SCU_SFS(PIN_GROUP8, PIN4)__UINT_LEAST16_MAX__ 0xffffINT8_MAX__ULLFRACT_FBIT__ 64__SIG_ATOMIC_TYPE__ int__INT_FAST64_TYPE__ long long int__ARM_FEATURE_COPROC 15PERIPH_BASE_APB2 (0x400C0000U)PIN_GROUPE (SCU_BASE + 0x700)INT32_MIN (-INT32_MAX - 1)__FLT32_MAX_10_EXP__ 38WWDT_BASE (PERIPH_BASE_APB0 + 0x00000)__USFRACT_MAX__ 0XFFP-8UHR__FP_FAST_FMAF32 1SCU_SFSP9_1 SCU_SFS(PIN_GROUP9, PIN1)__UINTPTR_MAX__ 0xffffffffUBIT29 (1<<29)SCU_SFSP7_7 SCU_SFS(PIN_GROUP7, PIN7)__FLT32_MIN_EXP__ (-125)PIN_GROUPB (SCU_BASE + 0x580)P4_0P4_1P4_2P4_3P4_4P4_5P4_6P4_7__ULFRACT_FBIT__ 32P4_9SCU_SFSPA_2 SCU_SFS(PIN_GROUPA, PIN2)__FLT64_MIN_10_EXP__ (-307)__GNUC_EXECUTION_CHARSET_NAME "UTF-8"SCU_SFSPE_7 SCU_SFS(PIN_GROUPE, PIN7)BIT10 (1<<10)P9_0P9_1P9_2P9_3P9_4P9_5P9_6SCU_SFSP1_1 SCU_SFS(PIN_GROUP1, PIN1)__SFRACT_EPSILON__ 0x1P-7HRSCU_SFSP5_6 SCU_SFS(PIN_GROUP5, PIN6)PIN6 0x018__INT32_C(c) c ## LUINT32_C(c) __UINT32_C(c)__ORDER_BIG_ENDIAN__ 4321SIZE_MAXSCU_SFSPF_0 SCU_SFS(PIN_GROUPF, PIN0)__SQ_FBIT__ 31INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)__UHQ_FBIT__ 16PC_0PC_1PC_2PC_3PC_4PC_5PC_6PC_7PC_8PC_9__UINT_FAST8_MAX__ 0xffffffffUSCU_SFSP6_9 SCU_SFS(PIN_GROUP6, PIN9)UINT16_C(c) __UINT16_C(c)__LACCUM_IBIT__ 32SCU_SFSPE_12 SCU_SFS(PIN_GROUPE, PIN12)__INT_FAST16_WIDTH__ 32INTMAX_C__VERSION__ "12.2.1 20221205"__VFP_FP__ 1__LLFRACT_MIN__ (-0.5LLR-0.5LLR)INT_FAST8_MAXSCU_CONF_FUNCTION5 (0x5)SCU_SFSP2_1 SCU_SFS(PIN_GROUP2, PIN1)__UINT_FAST16_MAX__ 0xffffffffU__INTPTR_MAX__ 0x7fffffffINT64_C(c) __INT64_C(c)SCU_SFSPD_12 SCU_SFS(PIN_GROUPD, PIN12)SCU_SFSCLK3 MMIO32(SCU_BASE + 0xC0C)CREG_BASE (0x40043000U)__UFRACT_MIN__ 0.0URSCU_SFSP2_8 SCU_SFS(PIN_GROUP2, PIN8)__LDBL_HAS_QUIET_NAN__ 1WCHAR_MAX __WCHAR_MAX____FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX__SCU_SDA_EFP (BIT8)SCU_SFSPA_1 SCU_SFS(PIN_GROUPA, PIN1)INT8_C(c) __INT8_C(c)SCU_SFSP0_1 SCU_SFS(PIN_GROUP0, PIN1)SCU_SFSPE_6 SCU_SFS(PIN_GROUPE, PIN6)AES_BASE (0x400F1000U)__ACCUM_FBIT__ 15SCU_SFSP6_11 SCU_SFS(PIN_GROUP6, PIN11)__UACCUM_IBIT__ 16long intUINT8_MAXSCU_SFSP1_0 SCU_SFS(PIN_GROUP1, PIN0)SIZE_MAX __SIZE_MAX____INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1__FLT32X_EPSILON__ 2.2204460492503131e-16F32xPIN11 0x02C__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32__FLT64_MAX_10_EXP__ 308__UINTMAX_C(c) c ## ULL__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed charscu_grp_pin_t__GCC_ATOMIC_BOOL_LOCK_FREE 2BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON____FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX__TIMER1_BASE (PERIPH_BASE_APB0 + 0x05000)__THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRshort unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)__GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"UINT_FAST8_MAX __UINT_FAST8_MAX____FLT32X_MIN_10_EXP__ (-307)UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)__DBL_IS_IEC_60559__ 2__UINT_FAST32_MAX__ 0xffffffffU__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4PIN3 0x00C__FLT_MIN_10_EXP__ (-37)P2_12SCU_SFSPD_4 SCU_SFS(PIN_GROUPD, PIN4)__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32SCU_SSP_IO (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)__FLT32X_MIN_EXP__ (-1021)GPDMA_BASE (PERIPH_BASE_AHB + 0x02000)SCU_SFSPD_10 SCU_SFS(PIN_GROUPD, PIN10)SCU_SFSPA_0 SCU_SFS(PIN_GROUPA, PIN0)SCU_SFSPE_5 SCU_SFS(PIN_GROUPE, PIN5)I2C0_BASE (PERIPH_BASE_APB1 + 0x01000)BIT27 (1<<27)SCU_SFSP2_5 SCU_SFS(PIN_GROUP2, PIN5)SCU_SFSP8_8 SCU_SFS(PIN_GROUP8, PIN8)SCU_SFSP8_0 SCU_SFS(PIN_GROUP8, PIN0)__UTA_FBIT__ 64INTMAX_C(c) __INTMAX_C(c)PIN_GROUP3 (SCU_BASE + 0x180)P1_1__FLT_DECIMAL_DIG__ 9SCU_SFSP7_0 SCU_SFS(PIN_GROUP7, PIN0)__INT_LEAST32_MAX__ 0x7fffffffLsigned charGIMA_BASE (PERIPH_BASE_APB2 + 0x07000)P2_10P2_11INTMAX_MIN (-INTMAX_MAX - 1)P2_13INT32_C(c) __INT32_C(c)__GNUC_STDC_INLINE__ 1SCU_SFS(group,pin) MMIO32((group) + (pin))SCU_CONF_FUNCTION6 (0x6)__FRACT_FBIT__ 15__LLACCUM_EPSILON__ 0x1P-31LLK__GNUC_PATCHLEVEL__ 1__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2PTRDIFF_MINP4_10SCU_SFSPF_4 SCU_SFS(PIN_GROUPF, PIN4)UINTPTR_MAX __UINTPTR_MAX____ARM_ARCH_PROFILE 77__LACCUM_FBIT__ 31SCU_SFSP9_6 SCU_SFS(PIN_GROUP9, PIN6)_STDBOOL_H __UHA_IBIT__ 8__FLT_DIG__ 6MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINCGU_BASE (0x40050000U)P6_10P6_11P6_12END_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38SCU_SFSP1_5 SCU_SFS(PIN_GROUP1, PIN5)__FRACT_MAX__ 0X7FFFP-15R__ACCUM_EPSILON__ 0x1P-15KINT_LEAST32_MAX __INT_LEAST32_MAX__UINTMAX_C__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5SCU_SFSPD_3 SCU_SFS(PIN_GROUPD, PIN3)SCU_SFSPF_8 SCU_SFS(PIN_GROUPF, PIN8)SCU_SFSPE_8 SCU_SFS(PIN_GROUPE, PIN8)__UINT16_MAX__ 0xffffSCU_SFSPD_0 SCU_SFS(PIN_GROUPD, PIN0)__TQ_FBIT__ 127SCU_SFSP8_7 SCU_SFS(PIN_GROUP8, PIN7)SCU_SFSP4_9 SCU_SFS(PIN_GROUP4, PIN9)__LDBL_MAX_EXP__ 1024scu_confINT_FAST16_MINSCU_SFSP2_10 SCU_SFS(PIN_GROUP2, PIN10)SCU_SFSP1_20 SCU_SFS(PIN_GROUP1, PIN20)__thumb2__ 1__ULLACCUM_FBIT__ 32MCPWM_BASE (PERIPH_BASE_APB1 + 0x00000)PIN4 0x010INT_FAST32_MIN (-INT_FAST32_MAX - 1)__ARM_BF16_FORMAT_ALTERNATIVE__STRICT_ANSI__ 1UINT_LEAST8_MAXSCU_SFSP2_2 SCU_SFS(PIN_GROUP2, PIN2)UINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8SCU_SFSP2_6 SCU_SFS(PIN_GROUP2, PIN6)__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX____USA_IBIT__ 16__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1PTRDIFF_MIN (-PTRDIFF_MAX - 1)SCU_SFSPE_13 SCU_SFS(PIN_GROUPE, PIN13)__UINT_FAST64_TYPE__ long long unsigned int__STDC_VERSION__ 199901L__FLT_MIN__ 1.1754943508222875e-38F__HA_FBIT__ 7SCU_SFSP1_4 SCU_SFS(PIN_GROUP1, PIN4)__FDPIC__SCU_SFSP6_10 SCU_SFS(PIN_GROUP6, PIN10)PIN12 0x030__FLT32_IS_IEC_60559__ 2PIN7 0x01CP0_0P0_1INT_FAST64_MINADC0_BASE (PERIPH_BASE_APB3 + 0x03000)__USFRACT_IBIT__ 0PF_11SCU_SFSP3_0 SCU_SFS(PIN_GROUP3, PIN0)__USFRACT_MIN__ 0.0UHRSCU_SFSP7_5 SCU_SFS(PIN_GROUP7, PIN5)__ARM_NEONP5_0P5_1P5_2P5_3P5_4P5_5P5_6P5_7PIN_GROUP2 (SCU_BASE + 0x100)PD_10__DBL_HAS_DENORM__ 1PD_12PD_13PD_14PD_15PD_16__DA_FBIT__ 31long long intBIT17 (1<<17)__GXX_ABI_VERSION 1017__INT_LEAST16_MAX__ 0x7fffPIN5 0x014PF_10__FLT_DENORM_MIN__ 1.4012984643248171e-45F__USES_INITFINI__ 1INT_LEAST8_MAX __INT_LEAST8_MAX__PD_0PD_1PD_2__UINT32_C(c) c ## ULPD_4PD_5PD_6PD_7__UACCUM_MIN__ 0.0UKPD_9SCU_SFSPA_4 SCU_SFS(PIN_GROUPA, PIN4)__FLT_EPSILON__ 1.1920928955078125e-7FSCU_SFSPE_9 SCU_SFS(PIN_GROUPE, PIN9)SCU_ENAIO0 MMIO32(SCU_BASE + 0xC88)SCU_SFSPC_14 SCU_SFS(PIN_GROUPC, PIN14)SCU_SFSP4_7 SCU_SFS(PIN_GROUP4, PIN7)__PTRDIFF_TYPE__ int__ARM_ARCH_ISA_THUMBSDIO_BASE (PERIPH_BASE_AHB + 0x04000)__UACCUM_EPSILON__ 0x1P-16UK__ARM_FEATURE_MATMUL_INT8SCU_SFSPC_0 SCU_SFS(PIN_GROUPC, PIN0)__GCC_ATOMIC_SHORT_LOCK_FREE 2PIN13 0x034SCU_SFSPD_1 SCU_SFS(PIN_GROUPD, PIN1)__USACCUM_FBIT__ 8__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1SCU_CONF_EPUN_DIS_PULLUP (BIT4)__ELF__ 1SCU_SFSPB_0 SCU_SFS(PIN_GROUPB, PIN0)SCU_SFSPC_1 SCU_SFS(PIN_GROUPC, PIN1)EMC_BASE (PERIPH_BASE_AHB + 0x05000)__FLT32_HAS_QUIET_NAN__ 1SCU_SFSPE_15 SCU_SFS(PIN_GROUPE, PIN15)__LDBL_HAS_INFINITY__ 1__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))CCU1_BASE (0x40051000U)__FLT32X_MAX_10_EXP__ 308SCU_SFSPC_10 SCU_SFS(PIN_GROUPC, PIN10)SCU_SFSP3_3 SCU_SFS(PIN_GROUP3, PIN3)__INT_FAST16_MAX__ 0x7fffffffbool _Bool__UQQ_IBIT__ 0UINTMAX_MAX __UINTMAX_MAX____SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)SCU_SFSP1_10 SCU_SFS(PIN_GROUP1, PIN10)__UINT_LEAST8_MAX__ 0xff__GCC_ATOMIC_LONG_LOCK_FREE 2SCU_SFSP1_9 SCU_SFS(PIN_GROUP1, PIN9)BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)EVENTROUTER_BASE (0x40044000U)INT16_MAX __INT16_MAX____FP_FAST_FMAF 1PIN_GROUP5 (SCU_BASE + 0x280)__FLT32X_IS_IEC_60559__ 2PIN10 0x028INT_LEAST64_MAX __INT_LEAST64_MAX__SCU_SFSPD_7 SCU_SFS(PIN_GROUPD, PIN7)SCU_SFSPC_7 SCU_SFS(PIN_GROUPC, PIN7)LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))UINT32_MAXSCU_SFSP7_3 SCU_SFS(PIN_GROUP7, PIN3)__INT_LEAST16_WIDTH__ 16I2S0_BASE (PERIPH_BASE_APB1 + 0x02000)SCU_LCD (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)SCT_BASE (PERIPH_BASE_AHB + 0x00000)__ARM_FEATURE_FP16_FMLSCU_SFSP1_8 SCU_SFS(PIN_GROUP1, PIN8)INT16_MIN (-INT16_MAX - 1)__USFRACT_EPSILON__ 0x1P-8UHRSCU_PINTSEL1 MMIO32(SCU_BASE + 0xE04)SCU_SFSP4_6 SCU_SFS(PIN_GROUP4, PIN6)__USFRACT_FBIT__ 8__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLKSCU_SCL_ZIF_DIS (BIT7)BIT22 (1<<22)__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX____UINT32_MAX__ 0xffffffffULUSART0_BASE (PERIPH_BASE_APB0 + 0x01000)__INT_LEAST8_MAX__ 0x7fSCU_SFSPF_10 SCU_SFS(PIN_GROUPF, PIN10)__GCC_ATOMIC_POINTER_LOCK_FREE 2__ARM_FEATURE_QBIT 1__ARM_FEATURE_CLZ 1__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXPIN_GROUPC (SCU_BASE + 0x600)__ARM_PCS_VFP 1__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024PIN_GROUPA (SCU_BASE + 0x500)SCU_SFSPD_2 SCU_SFS(PIN_GROUPD, PIN2)BIT21 (1<<21)__UINT_LEAST32_MAX__ 0xffffffffUL__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1__ACCUM_MAX__ 0X7FFFFFFFP-15KSCU_SFSP2_3 SCU_SFS(PIN_GROUP2, PIN3)__INT8_MAX__ 0x7fBIT14 (1<<14)__INT_FAST16_TYPE__ int__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16__UINT_FAST16_TYPE__ unsigned int__SHRT_WIDTH__ 16__GCC_IEC_559_COMPLEX 0__ARM_FEATURE_MVESCU_SFSP0_0 SCU_SFS(PIN_GROUP0, PIN0)__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intSCU_SFSP4_5 SCU_SFS(PIN_GROUP4, PIN5)SCU_CONF_EHD_NORMAL_DRIVE_20MILLIA (0x300)UINT_LEAST16_MAX __UINT_LEAST16_MAX__BIT7 (1<<7)P4_8INT_FAST32_MIN__FLT_EVAL_METHOD_TS_18661_3__ 0__SCHAR_WIDTH__ 8BIT18 (1<<18)UINT_FAST16_MAX__UINT_FAST8_TYPE__ unsigned int__LLACCUM_IBIT__ 32SCU_SFSP6_1 SCU_SFS(PIN_GROUP6, PIN1)__FRACT_EPSILON__ 0x1P-15RBIT24 (1<<24)SCU_SFSP2_9 SCU_SFS(PIN_GROUP2, PIN9)__INT32_MAX__ 0x7fffffffLSCU_SFSP7_2 SCU_SFS(PIN_GROUP7, PIN2)UINTMAX_MAXBIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__APCS_32__ 1__ARM_FEATURE_BF16_VECTOR_ARITHMETIC__FLT32_MANT_DIG__ 24INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32PTRDIFF_MAX __PTRDIFF_MAX____UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN____LDBL_EPSILON__ 2.2204460492503131e-16LBIT28 (1<<28)UINT32_MAX __UINT32_MAX____GCC_ATOMIC_CHAR16_T_LOCK_FREE 2SCU_SFSPF_6 SCU_SFS(PIN_GROUPF, PIN6)__DBL_MAX_EXP__ 1024SCU_SCL_EHD (BIT2)__ATOMIC_RELEASE 3SCU_SFSUSB MMIO32(SCU_BASE + 0xC80)__FLT32X_HAS_DENORM__ 1__FLT_MANT_DIG__ 24SCU_SFSPC_13 SCU_SFS(PIN_GROUPC, PIN13)__UDQ_IBIT__ 0CCU2_BASE (0x40052000U)__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UKSCU_SFSPD_5 SCU_SFS(PIN_GROUPD, PIN5)__FLT64_NORM_MAX__ 1.7976931348623157e+308F64PERIPH_BASE_APB1 (0x400A0000U)UINTPTR_MAXSCU_ENAIO2 MMIO32(SCU_BASE + 0xC90)PIN_GROUPD (SCU_BASE + 0x680)__LDBL_DENORM_MIN__ 4.9406564584124654e-324LTIMER3_BASE (PERIPH_BASE_APB2 + 0x04000)__INT64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_SAT 1__ULLFRACT_IBIT__ 0SCU_SFSPF_1 SCU_SFS(PIN_GROUPF, PIN1)SPI_PORT_BASE (0x40100000U)MMIO16(addr) (*(volatile uint16_t *)(addr))PIN16 0x040SCU_SFSP9_2 SCU_SFS(PIN_GROUP9, PIN2)LPC43XX 1SCU_SFSPC_3 SCU_SFS(PIN_GROUPC, PIN3)__GNUC__ 12SCU_SFSP6_0 SCU_SFS(PIN_GROUP6, PIN0)WCHAR_MAXSCU_SFSPB_6 SCU_SFS(PIN_GROUPB, PIN6)__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16SCU_SFSPE_10 SCU_SFS(PIN_GROUPE, PIN10)P1_0__UFRACT_EPSILON__ 0x1P-16URP1_2P1_3P1_4P1_5P1_6P1_7P1_8P1_9__ULACCUM_MIN__ 0.0ULK__LDBL_MAX__ 1.7976931348623157e+308L__ARM_ARCH 7P6_0P6_1P6_2P6_3P6_4P6_5P6_6P6_7P6_8P6_9__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAX__ARM_FEATURE_DOTPRODSCU_SFSP6_12 SCU_SFS(PIN_GROUP6, PIN12)SGPIO_PORT_BASE (0x40101000U)long long unsigned intPERIPH_BASE_APB0 (0x40080000U)__LONG_LONG_WIDTH__ 64BIT6 (1<<6)__UINT_FAST64_MAX__ 0xffffffffffffffffULL__ARM_FP__HA_IBIT__ 8__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1BIT9 (1<<9)__FLT32X_MIN__ 2.2250738585072014e-308F32xSCU_SFSP3_2 SCU_SFS(PIN_GROUP3, PIN2)INTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024UINT16_MAXBIT20 (1<<20)PE_0__FLT64_MIN__ 2.2250738585072014e-308F64PE_2PE_3PE_4PE_5PE_6PE_7PE_8PE_9__INT64_TYPE__ long long int__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4__FLT_RADIX__ 2SCU_SFSP1_16 SCU_SFS(PIN_GROUP1, PIN16)SCU_CONF_EHS_FAST (BIT5)__UFRACT_MAX__ 0XFFFFP-16URSCU_SFSPC_12 SCU_SFS(PIN_GROUPC, PIN12)INT64_MAX__UHA_FBIT__ 8INT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0SSP1_BASE (PERIPH_BASE_APB2 + 0x05000)SPIFI_BASE (PERIPH_BASE_AHB + 0x03000)__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__SCU_SFSP8_6 SCU_SFS(PIN_GROUP8, PIN6)UINT8_CSCU_SFSP9_5 SCU_SFS(PIN_GROUP9, PIN5)__UFRACT_FBIT__ 16__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)__LDBL_MAX_10_EXP__ 308SCU_SFSPC_2 SCU_SFS(PIN_GROUPC, PIN2)__INT_FAST32_TYPE__ int__SIZEOF_LONG_LONG__ 8SCU_SFSP6_6 SCU_SFS(PIN_GROUP6, PIN6)unsigned intSCU_SFSP3_1 SCU_SFS(PIN_GROUP3, PIN1)__FLT_MIN_EXP__ (-125)__DEC_EVAL_METHOD__ 2SCU_SFSP7_6 SCU_SFS(PIN_GROUP7, PIN6)SCU_SFSP1_17 SCU_SFS(PIN_GROUP1, PIN17)SCU_SFSP4_2 SCU_SFS(PIN_GROUP4, PIN2)__USACCUM_IBIT__ 8__ARM_ARCH_7EM__ 1SCU_ENAIO1 MMIO32(SCU_BASE + 0xC8C)PIN18 0x048__FLT64_HAS_DENORM__ 1__ULLACCUM_IBIT__ 32__UINTMAX_TYPE__ long long unsigned intSCU_SFSPD_6 SCU_SFS(PIN_GROUPD, PIN6)GPIO_PIN_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x07000)__FLT_EVAL_METHOD__ 0GPIO_PORT_BASE (0x400F4000U)__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32PIN_GROUPF (SCU_BASE + 0x780)__ARM_FEATURE_LDREXSCU_SFSPC_5 SCU_SFS(PIN_GROUPC, PIN5)__UQQ_FBIT__ 8__WINT_TYPE__ unsigned int__ARM_FP16_ARGS__GCC_IEC_559 0DAC_BASE (PERIPH_BASE_APB3 + 0x01000)INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX__SCU_SDA_EZI_EN (BIT11)__LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4C_CAN0_BASE (PERIPH_BASE_APB3 + 0x02000)__STDC__ 1SCU_SFSP1_6 SCU_SFS(PIN_GROUP1, PIN6)__ARM_FEATURE_IDIV 1SCU_SFSPD_9 SCU_SFS(PIN_GROUPD, PIN9)__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__/build/libopencm3/lib/lpc43xx/m4__UINT8_TYPE__ unsigned charSCU_GPIO_PUP (SCU_CONF_EZI_EN_IN_BUFFER)__UINT_FAST32_TYPE__ unsigned int__UINT_LEAST8_TYPE__ unsigned charSCU_SFSP4_8 SCU_SFS(PIN_GROUP4, PIN8)UINT64_MAX __UINT64_MAX__GNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -O2 -std=c99 -fno-common -ffunction-sections -fdata-sectionsINT8_MINSCU_SFSP1_18 SCU_SFS(PIN_GROUP1, PIN18)__ARM_ARCH_PROFILESCU_SFSPF_5 SCU_SFS(PIN_GROUPF, PIN5)true 1__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)SCU_SFSP4_3 SCU_SFS(PIN_GROUP4, PIN3)P2_1PIN_GROUP8 (SCU_BASE + 0x400)__LDBL_MIN_10_EXP__ (-307)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)P2_4__GCC_ATOMIC_CHAR_LOCK_FREE 2SCU_SFSPC_11 SCU_SFS(PIN_GROUPC, PIN11)P2_7__LFRACT_EPSILON__ 0x1P-31LR__ARM_SIZEOF_MINIMAL_ENUM 1unsigned char__FLT32X_NORM_MAX__ 1.7976931348623157e+308F32xSCU_SDA_EHD (BIT10)__arm__ 1__FLT32_MIN_10_EXP__ (-37)MMIO64(addr) (*(volatile uint64_t *)(addr))INT8_MAX __INT8_MAX____ARM_FP16_FORMAT_ALTERNATIVE__LDBL_NORM_MAX__ 1.7976931348623157e+308LUSART3_BASE (PERIPH_BASE_APB2 + 0x02000)SCU_SFSPE_14 SCU_SFS(PIN_GROUPE, PIN14)__BIGGEST_ALIGNMENT__ 8P7_1__TA_IBIT__ 64SCU_GPIO_FAST (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)P7_4PERIPH_BASE_AHB (0x40000000U)P7_7__ARM_FEATURE_QRDMX__ARM_ARCH_ISA_THUMB 2__LONG_LONG_MAX__ 0x7fffffffffffffffLL__WINT_WIDTH__ 32SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__SCU_SFSPC_9 SCU_SFS(PIN_GROUPC, PIN9)SCU_SFSP6_2 SCU_SFS(PIN_GROUP6, PIN2)__USQ_IBIT__ 0SCU_SFSI2C0 MMIO32(SCU_BASE + 0xC84)BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN____SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__DBL_MIN_EXP__ (-1021)SCU_SFSP6_3 SCU_SFS(PIN_GROUP6, PIN3)SCU_EMCDELAYCLK MMIO32(SCU_BASE + 0xD00)INT8_MIN (-INT8_MAX - 1)GPIO_GROUP1_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x09000)SCU_EMC_IO (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)__FLT32_DIG__ 6INT_LEAST16_MAXBIT15 (1<<15)BACKUP_REG_BASE (0x40041000U)UINT16_CSCU_SFSP9_0 SCU_SFS(PIN_GROUP9, PIN0)__LDBL_HAS_DENORM__ 1__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1INT32_MAXSCU_SFSP5_5 SCU_SFS(PIN_GROUP5, PIN5)__UINT64_C(c) c ## ULLPIN8 0x020__ARM_FEATURE_CRYPTO__INT_LEAST32_TYPE__ long intSCU_SFSP3_5 SCU_SFS(PIN_GROUP3, PIN5)SCU_SFSPE_4 SCU_SFS(PIN_GROUPE, PIN4)BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__FRACT_IBIT__ 0I2C1_BASE (PERIPH_BASE_APB3 + 0x00000)SCU_SFSPC_6 SCU_SFS(PIN_GROUPC, PIN6)UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2PA_2P2_0__ORDER_LITTLE_ENDIAN__ 1234P2_2P2_3__FLT_NORM_MAX__ 3.4028234663852886e+38FP2_5P2_6__UINT8_MAX__ 0xffP2_8P2_9BIT31 (1<<31)__ULACCUM_IBIT__ 32__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2P7_0__ULLACCUM_EPSILON__ 0x1P-32ULLKP7_2P7_3__DQ_FBIT__ 63P7_5P7_6INT_LEAST64_MAX__SACCUM_IBIT__ 8P1_10P1_11P1_12P1_13P1_14P1_15P1_16P1_17CLK2P1_19PIN14 0x038__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)__ULFRACT_MAX__ 0XFFFFFFFFP-32ULR__UINT_LEAST16_TYPE__ short unsigned intgroup_pin__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned intPA_0PA_1__FLT32X_DIG__ 15PA_3PA_4__UTQ_FBIT__ 128SCU_CONF_FUNCTION0 (0x0)__FINITE_MATH_ONLY__ 0PF_7PF_0PF_1PF_2PF_3PF_4PF_5PF_6__SIZEOF_SHORT__ 2PF_8PF_9__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKSCU_SFSPD_15 SCU_SFS(PIN_GROUPD, PIN15)UINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULR__DQ_IBIT__ 0P1_20__INT32_TYPE__ long intSSP0_BASE (PERIPH_BASE_APB0 + 0x03000)SCU_SFSP2_0 SCU_SFS(PIN_GROUP2, PIN0)SCU_SFSP6_8 SCU_SFS(PIN_GROUP6, PIN8)QEI_BASE (PERIPH_BASE_APB2 + 0x06000)WCHAR_MINSCU_SFSP3_4 SCU_SFS(PIN_GROUP3, PIN4)SCU_CLK_OUT (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)BEGIN_DECLS SCU_SFSPE_1 SCU_SFS(PIN_GROUPE, PIN1)SCU_SFSP1_13 SCU_SFS(PIN_GROUP1, PIN13)SCU_SFSCLK1 MMIO32(SCU_BASE + 0xC04)SCU_SFSPF_2 SCU_SFS(PIN_GROUPF, PIN2)SCU_SFSPD_8 SCU_SFS(PIN_GROUPD, PIN8)INTPTR_MAX __INTPTR_MAX__SCU_SFSP5_0 SCU_SFS(PIN_GROUP5, PIN0)__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__LLFRACT_EPSILON__ 0x1P-63LLR__FLT32X_MAX__ 1.7976931348623157e+308F32xPIN1 0x004__ARM_EABI__ 1SCU_SFSCLK2 MMIO32(SCU_BASE + 0xC08)INT16_MININTPTR_MIN__FLT_IS_IEC_60559__ 2__THUMBEL__ 1__ARM_FEATURE_DSP 1PIN15 0x03CSCU_SFSPD_11 SCU_SFS(PIN_GROUPD, PIN11)SCU_SCL_EFP (BIT0)__QQ_IBIT__ 0SCU_SFSPD_16 SCU_SFS(PIN_GROUPD, PIN16)SCU_SDA_ZIF_DIS (BIT15)SCU_SFSP2_7 SCU_SFS(PIN_GROUP2, PIN7)__LLACCUM_FBIT__ 31ATIMER_BASE (0x40040000U)__GNUC_MINOR__ 2__UINT_LEAST32_TYPE__ long unsigned intSCU_SFSP7_4 SCU_SFS(PIN_GROUP7, PIN4)__UHQ_IBIT__ 0__ARM_FEATURE_NUMERIC_MAXMINPIN_GROUP0 (SCU_BASE + 0x000)__INTMAX_TYPE__ long long intSCU_CONF_EZI_EN_IN_BUFFER (BIT6)__GCC_ATOMIC_INT_LOCK_FREE 2TIMER0_BASE (PERIPH_BASE_APB0 + 0x04000)SCU_SFSPB_3 SCU_SFS(PIN_GROUPB, PIN3)INT_LEAST8_MININTMAX_MAXSCU_SFSP1_14 SCU_SFS(PIN_GROUP1, PIN14)TIMER2_BASE (PERIPH_BASE_APB2 + 0x03000)SCU_SFSPC_4 SCU_SFS(PIN_GROUPC, PIN4)PIN_GROUP9 (SCU_BASE + 0x480)__ARM_FEATURE_FP16_SCALAR_ARITHMETIC__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1__FLT64_HAS_QUIET_NAN__ 1SCU_BASE (PERIPH_BASE_APB0 + 0x06000)__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CSCU_SFSP4_4 SCU_SFS(PIN_GROUP4, PIN4)SCU_SFSPE_0 SCU_SFS(PIN_GROUPE, PIN0)INT64_MIN__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intPC_10__UINTPTR_TYPE__ unsigned intPC_12PC_13PC_14__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRSCU_SFSP1_12 SCU_SFS(PIN_GROUP1, PIN12)SCU_SFSP9_4 SCU_SFS(PIN_GROUP9, PIN4)__SIZEOF_SIZE_T__ 4__UINT64_TYPE__ long long unsigned int__INT64_C(c) c ## LLPIN_GROUP7 (SCU_BASE + 0x380)PE_10PE_11PE_12PE_13PE_14PE_15UART1_BASE (PERIPH_BASE_APB0 + 0x02000)__LDBL_MIN__ 2.2250738585072014e-308L__ARM_FEATURE_CDE__ACCUM_IBIT__ 16SCU_SFSPA_3 SCU_SFS(PIN_GROUPA, PIN3)CLK0CLK1CLK3short intSCU_CONF_EHD_NORMAL_DRIVE_8MILLIA (0x100)__UINT16_C(c) c__FLT64_MIN_EXP__ (-1021)__UDA_IBIT__ 32PIN_GROUP1 (SCU_BASE + 0x080)PC_11UINT_LEAST32_MAXSCU_SFSPB_2 SCU_SFS(PIN_GROUPB, PIN2)BIT2 (1<<2)INT64_C__ATOMIC_RELAXED 0__ARM_FEATURE_COPROC__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53LPC43XX_M4 1BIT5 (1<<5)BIT1 (1<<1)INT8_CINT_LEAST32_MAXBIT12 (1<<12)__ARM_ARCH_EXT_IDIV__ 1I2S1_BASE (PERIPH_BASE_APB1 + 0x03000)SCU_SFSP4_10 SCU_SFS(PIN_GROUP4, PIN10)__DBL_DECIMAL_DIG__ 17BIT8 (1<<8)SCU_SFSP8_2 SCU_SFS(PIN_GROUP8, PIN2)__ULACCUM_FBIT__ 32INT16_C(c) __INT16_C(c)PIN_GROUP6 (SCU_BASE + 0x300)SCU_SFSP9_3 SCU_SFS(PIN_GROUP9, PIN3)SCU_CONF_EPD_EN_PULLDOWN (BIT3)__INT16_MAX__ 0x7fffSCU_GPIO_PDN (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EZI_EN_IN_BUFFER)PIN_GROUP4 (SCU_BASE + 0x200)SCU_SFSPF_11 SCU_SFS(PIN_GROUPF, PIN11)__INT_WIDTH__ 32__ARM_FEATURE_SIMD32 1SCU_SCL_EZI_EN (BIT3)__QQ_FBIT__ 7RITIMER_BASE (PERIPH_BASE_APB2 + 0x00000)__SIG_ATOMIC_WIDTH__ 32SCU_I2C0_NOMINAL (SCU_SCL_EZI_EN | SCU_SDA_EZI_EN)SCU_PINTSEL0 MMIO32(SCU_BASE + 0xE00)INT16_CSCU_SFSPF_3 SCU_SFS(PIN_GROUPF, PIN3)__UTA_IBIT__ 64SCU_SFSPF_7 SCU_SFS(PIN_GROUPF, PIN7)RGU_BASE (0x40053000U)__ULLFRACT_EPSILON__ 0x1P-64ULLRfalse 0__STDC_HOSTED__ 1SCU_SFSP3_8 SCU_SFS(PIN_GROUP3, PIN8)__SIZEOF_WINT_T__ 4PMC_BASE (0x40042000U)INT_LEAST64_MIN__ARM_FEATURE_UNALIGNED 1__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17SCU_SFSP8_3 SCU_SFS(PIN_GROUP8, PIN3)SCU_SFSPB_1 SCU_SFS(PIN_GROUPB, PIN1)__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1SCU_SFSPE_11 SCU_SFS(PIN_GROUPE, PIN11)__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)__ULLACCUM_MIN__ 0.0ULLKSCU_SFSP5_4 SCU_SFS(PIN_GROUP5, PIN4)__INT_FAST32_WIDTH__ 32USB1_BASE (PERIPH_BASE_AHB + 0x07000)SCU_SFSP1_19 SCU_SFS(PIN_GROUP1, PIN19)SCU_CONF_FUNCTION2 (0x2)SCU_SFSP6_5 SCU_SFS(PIN_GROUP6, PIN5)PIN20 0x050__ARM_ASM_SYNTAX_UNIFIED__ 1SCU_CONF_ZIF_DIS_IN_GLITCH_FILT (BIT7)PE_1PIN17 0x044SCU_UART_RX_TX (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EZI_EN_IN_BUFFER)__UINT32_TYPE__ long unsigned intP3_0P3_1P3_2P3_3P3_4P3_5P3_6P3_7P3_8__ULLFRACT_MIN__ 0.0ULLRUINT_FAST8_MAXP8_0P8_1P8_2P8_3P8_4P8_5__GCC_CONSTRUCTIVE_SIZE 64P8_7P8_8__LLFRACT_IBIT__ 0uint32_tPD_3SCU_SFSP1_15 SCU_SFS(PIN_GROUP1, PIN15)__SACCUM_EPSILON__ 0x1P-7HK__GCC_ASM_FLAG_OUTPUTS__ 1PD_8SCU_SFSPC_8 SCU_SFS(PIN_GROUPC, PIN8)__ARM_FP 4LPC43XX_SCU_H PB_0PB_1PB_2PB_3PB_4PB_5PB_6__ULACCUM_EPSILON__ 0x1P-32ULKSCU_SFSP3_7 SCU_SFS(PIN_GROUP3, PIN7)__LDBL_DIG__ 15SCU_SFSP1_3 SCU_SFS(PIN_GROUP1, PIN3)UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXBIT16 (1<<16)SCU_GPIO_NOPULL (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EZI_EN_IN_BUFFER)__WINT_MIN__ 0UINT_LEAST16_MIN__FLT64_DIG__ 15__WINT_MAX__ 0xffffffffU../scu.c__INT_LEAST8_WIDTH__ 8SCU_SFSP5_3 SCU_SFS(PIN_GROUP5, PIN3)__INT_LEAST16_TYPE__ short intRTC_BASE (0x40046000U)GPIO_GROUP0_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x08000)__DBL_MAX__ ((double)1.7976931348623157e+308L)INT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1__thumb__ 1INT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1PIN9 0x024SCU_SFSP4_1 SCU_SFS(PIN_GROUP4, PIN1)__HQ_FBIT__ 15__bool_true_false_are_defined 1USART2_BASE (PERIPH_BASE_APB2 + 0x01000)BIT26 (1<<26)__SIZE_MAX__ 0xffffffffU__ARM_ARCH__LONG_MAX__ 0x7fffffffLSCU_SFSP6_4 SCU_SFS(PIN_GROUP6, PIN4)BIT25 (1<<25)SCU_SFSP6_7 SCU_SFS(PIN_GROUP6, PIN7)LPC43XX_MEMORYMAP_H __ARM_FEATURE_LDREX 7PTRDIFF_MAXSCU_SFSP3_6 SCU_SFS(PIN_GROUP3, PIN6)__USQ_FBIT__ 32__SFRACT_MAX__ 0X7FP-7HR__FLT32X_MANT_DIG__ 53SCU_CONF_FUNCTION3 (0x3)__WCHAR_WIDTH__ 32WINT_MAX__INT16_C(c) cSCU_SFSPE_3 SCU_SFS(PIN_GROUPE, PIN3)INT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32__PTRDIFF_WIDTH__ 32SCU_CLK_IN (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)SCU_I2C0_FAST (SCU_SCL_EFP | SCU_SCL_EHD | SCU_SCL_EZI_EN | SCU_SCL_ZIF_DIS | SCU_SDA_EFP | SCU_SDA_EHD | SCU_SDA_EZI_EN)__ATOMIC_ACQ_REL 4ADC1_BASE (PERIPH_BASE_APB3 + 0x04000)__HQ_IBIT__ 0__DBL_MIN_10_EXP__ (-307)SCU_SFSPD_13 SCU_SFS(PIN_GROUPD, PIN13)PD_11SCU_CONF_EHD_NORMAL_DRIVE_14MILLIA (0x200)scu_pinmuxSCU_SFSP1_7 SCU_SFS(PIN_GROUP1, PIN7)__FLT32_NORM_MAX__ 3.4028234663852886e+38F32SCU_SFSCLK0 MMIO32(SCU_BASE + 0xC00)UINT64_C(c) __UINT64_C(c)BIT3 (1<<3)__UINTMAX_MAX__ 0xffffffffffffffffULL__DBL_MANT_DIG__ 53SCU_SFSP8_1 SCU_SFS(PIN_GROUP8, PIN1)__ULFRACT_IBIT__ 0INT_FAST16_MAXSCU_SFSP1_11 SCU_SFS(PIN_GROUP1, PIN11)__INT_FAST64_WIDTH__ 64PIN19 0x04C__INT_MAX__ 0x7fffffff__INT_LEAST64_TYPE__ long long intPIN0 0x000__ARM_FEATURE_CDE_COPROCUINT32_CGCC: (15:12.2.rel1-1) 12.2.1 20221205 | A3aeabi)7E-M M  "     #%!' 1b*&)X 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<^l;08NPVY!AuoL|NUc1CsՑAX:/_`Y ../usr/lib/gcc/arm-none-eabi/12.2.1/include../../../include/libopencm3/lpc43xx../../../include/libopencm3/cm3i2c.cstdint.hi2c.hcommon.hstdbool.hmemorymap.hscu.hcgu.h, ""L$ x ! x.#$!=/!!    //.!> ! !!    /.!>=    / !.!>/!!CGU_PLL1_CTRL_FBSEL (1 << CGU_PLL1_CTRL_FBSEL_SHIFT)CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT (24)SCU_SFSP5_2 SCU_SFS(PIN_GROUP5, PIN2)SCU_SFSP2_12 SCU_SFS(PIN_GROUP2, PIN12)SCU_SFSPB_5 SCU_SFS(PIN_GROUPB, PIN5)__DECIMAL_DIG__ 17__UHA_FBIT__ 8CGU_BASE_OUT_CLK_PD (1 << CGU_BASE_OUT_CLK_PD_SHIFT)SCU_SFSP1_2 SCU_SFS(PIN_GROUP1, PIN2)CGU_BASE_UART2_CLK_PD (1 << CGU_BASE_UART2_CLK_PD_SHIFT)__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64SCU_SFSP2_4 SCU_SFS(PIN_GROUP2, PIN4)__GCC_ATOMIC_WCHAR_T_LOCK_FREE 2CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT (24)__CHAR_UNSIGNED__ 1ETHERNET_BASE (PERIPH_BASE_AHB + 0x10000)PIN2 0x008CGU_PLL0USB_STAT_FR (1 << CGU_PLL0USB_STAT_FR_SHIFT)SCU_SFSPD_14 SCU_SFS(PIN_GROUPD, PIN14)CGU_BASE_PHY_RX_CLK_AUTOBLOCK_SHIFT (11)CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT (24)__FLT64_HAS_INFINITY__ 1CGU_IDIVC_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVC_CTRL_CLK_SEL_SHIFT)SCU_SFSPE_2 SCU_SFS(PIN_GROUPE, PIN2)__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GNUC_MINOR__ 2I2C1_STAT I2C_STAT(I2C1)__LACCUM_EPSILON__ 0x1P-31LKSCU_SFSP4_0 SCU_SFS(PIN_GROUP4, PIN0)__PTRDIFF_MAX__ 0x7fffffff__SACCUM_FBIT__ 7SCU_SFSP8_5 SCU_SFS(PIN_GROUP8, PIN5)CGU_PLL0AUDIO_CTRL_SEL_EXT_SHIFT (13)__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)SCU_SFSP5_1 SCU_SFS(PIN_GROUP5, PIN1)__INTMAX_MAX__ 0x7fffffffffffffffLLSCU_SFSPB_1 SCU_SFS(PIN_GROUPB, PIN1)CGU_IDIVD_CTRL_CLK_SEL_SHIFT (24)__TQ_IBIT__ 0__FLT64_DECIMAL_DIG__ 17WINT_MIN __WINT_MIN__I2C0_BASE (PERIPH_BASE_APB1 + 0x01000)__ATOMIC_CONSUME 1__ULACCUM_FBIT__ 32__WCHAR_MAX__ 0xffffffffUCGU_BASE_CGU_OUT1_CLK_PD (1 << CGU_BASE_CGU_OUT1_CLK_PD_SHIFT)CGU_PLL0USB_MDIV_SELR(x) ((x) << CGU_PLL0USB_MDIV_SELR_SHIFT)OTP_BASE (0x40045000U)CGU_BASE_APLL_CLK MMIO32(CGU_BASE + 0x0C0)CGU_BASE_SSP1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT)CGU_PLL0AUDIO_MDIV MMIO32(CGU_BASE + 0x034)CGU_PLL0USB_CTRL_CLK_SEL_SHIFT (24)signed charINT64_MAX __INT64_MAX__INTMAX_MIN__SIZEOF_LONG_LONG__ 8SCU_SFSP2_13 SCU_SFS(PIN_GROUP2, PIN13)__DBL_MAX_10_EXP__ 308CGU_BASE_APLL_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_APLL_CLK_CLK_SEL_SHIFT)__FRACT_MIN__ (-0.5R-0.5R)__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLK__USACCUM_MAX__ 0XFFFFP-8UHK__SFRACT_FBIT__ 7__INTMAX_WIDTH__ 64__ARM_FEATURE_BF16_SCALAR_ARITHMETIC__SQ_IBIT__ 0__ORDER_PDP_ENDIAN__ 3412__SIZE_TYPE__ unsigned intSCU_CONF_FUNCTION4 (0x4)C_CCAN1_BASE (PERIPH_BASE_APB1 + 0x04000)__FLT_HAS_DENORM__ 1__INT8_TYPE__ signed char__SHRT_WIDTH__ 16CGU_BASE_SDIO_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT)__USACCUM_MIN__ 0.0UHKSCU_SFSPB_4 SCU_SFS(PIN_GROUPB, PIN4)__FLT32_DECIMAL_DIG__ 9CGU_BASE_UART1_CLK_AUTOBLOCK (1 << CGU_BASE_UART1_CLK_AUTOBLOCK_SHIFT)SCU_SFSPF_9 SCU_SFS(PIN_GROUPF, PIN9)__LDBL_MIN_EXP__ (-1021)INT_FAST16_MIN__LDBL_MANT_DIG__ 53INT64_MIN (-INT64_MAX - 1)SCU_SFSP5_7 SCU_SFS(PIN_GROUP5, PIN7)__UINT8_C(c) cI2C_MASK1(port) MMIO32((port) + 0x034)__INT16_TYPE__ short intCGU_BASE_PHY_RX_CLK_CLK_SEL(x) ((x) << CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT)CGU_BASE_USB0_CLK_CLK_SEL(x) ((x) << CGU_BASE_USB0_CLK_CLK_SEL_SHIFT)__FLT64_MAX__ 1.7976931348623157e+308F64USB0_BASE (PERIPH_BASE_AHB + 0x06000)CGU_BASE_PERIPH_CLK_AUTOBLOCK (1 << CGU_BASE_PERIPH_CLK_AUTOBLOCK_SHIFT)UINT_FAST32_MAXCGU_BASE_PHY_TX_CLK MMIO32(CGU_BASE + 0x07C)CGU_BASE_SDIO_CLK_PD_SHIFT (0)CGU_BASE_APB3_CLK_CLK_SEL_SHIFT (24)CGU_PLL0USB_CTRL_PD (1 << CGU_PLL0USB_CTRL_PD_SHIFT)INT_FAST64_MAX __INT_FAST64_MAX__CGU_PLL0AUDIO_CTRL_FRM (1 << CGU_PLL0AUDIO_CTRL_FRM_SHIFT)__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1__INT_FAST8_TYPE__ int__UINT_LEAST16_MAX__ 0xffff__STDC_HOSTED__ 1__ULLFRACT_FBIT__ 64__SIG_ATOMIC_TYPE__ intCGU_PLL0AUDIO_NP_DIV_PDEC(x) ((x) << CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT)CGU_BASE_SPIFI_CLK_CLK_SEL(x) ((x) << CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT)__INT_FAST64_TYPE__ long long int__WINT_TYPE__ unsigned intPERIPH_BASE_APB2 (0x400C0000U)PIN_GROUPE (SCU_BASE + 0x700)CGU_BASE_SPIFI_CLK_AUTOBLOCK (1 << CGU_BASE_SPIFI_CLK_AUTOBLOCK_SHIFT)I2C1_MASK2 I2C_MASK2(I2C1)INT32_MIN (-INT32_MAX - 1)__FLT32_MAX_10_EXP__ 38CGU_SRC_32K 0x00WWDT_BASE (PERIPH_BASE_APB0 + 0x00000)__USFRACT_MAX__ 0XFFP-8UHRCGU_PLL0USB_MDIV MMIO32(CGU_BASE + 0x024)__FP_FAST_FMAF32 1SCU_SFSP9_1 SCU_SFS(PIN_GROUP9, PIN1)TIMER1_BASE (PERIPH_BASE_APB0 + 0x05000)SCU_SFSP0_0 SCU_SFS(PIN_GROUP0, PIN0)__FLT32_MIN_EXP__ (-125)CGU_BASE_VADC_CLK_PD_SHIFT (0)I2C_ADR3(port) MMIO32((port) + 0x028)../i2c.cCGU_PLL0AUDIO_CTRL_DIRECTO (1 << CGU_PLL0AUDIO_CTRL_DIRECTO_SHIFT)PIN_GROUPB (SCU_BASE + 0x580)ATIMER_BASE (0x40040000U)UINT32_MAX __UINT32_MAX__CGU_IDIVB_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVB_CTRL_CLK_SEL_SHIFT)C_CAN0_BASE (PERIPH_BASE_APB3 + 0x02000)__ULFRACT_FBIT__ 32SCU_SFSP4_2 SCU_SFS(PIN_GROUP4, PIN2)SCU_SFSPA_2 SCU_SFS(PIN_GROUPA, PIN2)__FLT64_MIN_10_EXP__ (-307)I2C1_ADR0 I2C_ADR0(I2C1)SCU_SFSPE_7 SCU_SFS(PIN_GROUPE, PIN7)BIT10 (1<<10)__INT_FAST64_WIDTH__ 64__STDC_VERSION__ 199901LINT_LEAST64_MAX __INT_LEAST64_MAX__SCU_CONF_FUNCTION1 (0x1)CGU_BASE_SPI_CLK_AUTOBLOCK (1 << CGU_BASE_SPI_CLK_AUTOBLOCK_SHIFT)TIMER0_BASE (PERIPH_BASE_APB0 + 0x04000)SCU_SFSP1_1 SCU_SFS(PIN_GROUP1, PIN1)__SFRACT_EPSILON__ 0x1P-7HRCGU_PLLAUDIO_FRAC_PLLFRACT_CTRL(x) ((x) << CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT)SCU_SFSP5_6 SCU_SFS(PIN_GROUP5, PIN6)__INT32_C(c) c ## LUINT32_C(c) __UINT32_C(c)__ORDER_BIG_ENDIAN__ 4321SIZE_MAXCGU_PLL0USB_STAT_FR_SHIFT (1)SCU_SFSPF_0 SCU_SFS(PIN_GROUPF, PIN0)I2C1_SCLL I2C_SCLL(I2C1)INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)I2C_MASK0(port) MMIO32((port) + 0x030)CGU_PLL1_STAT_LOCK_SHIFT (0)CGU_IDIVD_CTRL_IDIV_MASK (0xf << CGU_IDIVD_CTRL_IDIV_SHIFT)__UHQ_FBIT__ 16CGU_IDIVB_CTRL_IDIV_SHIFT (2)__FLT64_MIN_EXP__ (-1021)__PTRDIFF_WIDTH__ 32SCU_SFSP8_3 SCU_SFS(PIN_GROUP8, PIN3)CGU_IDIVA_CTRL MMIO32(CGU_BASE + 0x048)CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT (0)__UINT_FAST8_MAX__ 0xffffffffUi2c0_initUINT16_C(c) __UINT16_C(c)CGU_BASE_CGU_OUT0_CLK_CLK_SEL(x) ((x) << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT)I2C0_ADR2 I2C_ADR2(I2C0)CGU_PLL0AUDIO_CTRL_BYPASS (1 << CGU_PLL0AUDIO_CTRL_BYPASS_SHIFT)CGU_BASE_SDIO_CLK_CLK_SEL(x) ((x) << CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT)__INT_FAST16_WIDTH__ 32CGU_PLL0USB_MDIV_SELI(x) ((x) << CGU_PLL0USB_MDIV_SELI_SHIFT)INTMAX_CCGU_BASE_VADC_CLK_AUTOBLOCK_SHIFT (11)__VFP_FP__ 1SCU_SFSP3_7 SCU_SFS(PIN_GROUP3, PIN7)__LLFRACT_MIN__ (-0.5LLR-0.5LLR)INT_FAST8_MAXSCU_CONF_FUNCTION5 (0x5)CGU_PLL0USB_MDIV_MDEC_SHIFT (0)I2C0_MASK3 I2C_MASK3(I2C0)__UINT_FAST16_MAX__ 0xffffffffUCGU_PLL0AUDIO_CTRL_PD_SHIFT (0)CGU_IDIVC_CTRL_PD_SHIFT (0)__INTPTR_MAX__ 0x7fffffffINT64_C(c) __INT64_C(c)SCU_SFSPD_12 SCU_SFS(PIN_GROUPD, PIN12)CGU_IDIVD_CTRL_CLK_SEL(x) ((x) << CGU_IDIVD_CTRL_CLK_SEL_SHIFT)SCU_SFSCLK3 MMIO32(SCU_BASE + 0xC0C)__GCC_IEC_559_COMPLEX 0CREG_BASE (0x40043000U)__UFRACT_MIN__ 0.0URSCU_SFSP2_8 SCU_SFS(PIN_GROUP2, PIN8)__LDBL_HAS_QUIET_NAN__ 1CGU_PLL0AUDIO_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT)WCHAR_MAX __WCHAR_MAX__CGU_BASE_M4_CLK_PD (1 << CGU_BASE_M4_CLK_PD_SHIFT)__FLT32X_HAS_INFINITY__ 1I2C_ADR2(port) MMIO32((port) + 0x024)CGU_FREQ_MON_CLK_SEL_SHIFT (24)SCU_SFSPA_1 SCU_SFS(PIN_GROUPA, PIN1)__UINT_LEAST8_TYPE__ unsigned charSCU_SFSP0_1 SCU_SFS(PIN_GROUP0, PIN1)SCU_SFSPE_6 SCU_SFS(PIN_GROUPE, PIN6)CGU_BASE_SPIFI_CLK MMIO32(CGU_BASE + 0x070)__ACCUM_FBIT__ 15CGU_PLL0USB_CTRL_PD_SHIFT (0)SCU_SFSP6_11 SCU_SFS(PIN_GROUP6, PIN11)__UACCUM_IBIT__ 16long intUINT8_MAXSCU_SFSP1_0 SCU_SFS(PIN_GROUP1, PIN0)SIZE_MAX __SIZE_MAX__CGU_PLL0USB_STAT MMIO32(CGU_BASE + 0x01C)I2C_DAT(port) MMIO32((port) + 0x008)__INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17CGU_PLL1_CTRL_NSEL_MASK (0x3 << CGU_PLL1_CTRL_NSEL_SHIFT)__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1__FLT32X_EPSILON__ 2.2204460492503131e-16F32xCGU_IDIVB_CTRL_PD (1 << CGU_IDIVB_CTRL_PD_SHIFT)PIN11 0x02CI2C1_ADR3 I2C_ADR3(I2C1)BIT13 (1<<13)__UDA_FBIT__ 32CGU_BASE (0x40050000U)__UINTMAX_C(c) c ## ULL__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed char__GCC_ATOMIC_BOOL_LOCK_FREE 2__SQ_FBIT__ 31BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON____FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX____THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRCGU_BASE_UART3_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART3_CLK_CLK_SEL_SHIFT)CGU_IDIVA_CTRL_CLK_SEL_SHIFT (24)CGU_PLL0AUDIO_CTRL_SEL_EXT (1 << CGU_PLL0AUDIO_CTRL_SEL_EXT_SHIFT)short unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)SCU_SFSP7_0 SCU_SFS(PIN_GROUP7, PIN0)BIT7 (1<<7)BIT17 (1<<17)__FLT32X_MIN_10_EXP__ (-307)CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_SHIFT (11)UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)I2C_CONCLR_SIC (1 << 3)__DBL_IS_IEC_60559__ 2__UINT_FAST32_MAX__ 0xffffffffUI2C_MMCTRL(port) MMIO32((port) + 0x01C)__SIZEOF_LONG__ 4PIN3 0x00CLCD_BASE (PERIPH_BASE_AHB + 0x08000)CGU_BASE_OUT_CLK MMIO32(CGU_BASE + 0x0AC)CGU_PLL1_CTRL_DIRECT (1 << CGU_PLL1_CTRL_DIRECT_SHIFT)SCU_SFSP2_7 SCU_SFS(PIN_GROUP2, PIN7)SCU_SFSPD_4 SCU_SFS(PIN_GROUPD, PIN4)__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32SCU_SSP_IO (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)__FLT32X_MIN_EXP__ (-1021)GPDMA_BASE (PERIPH_BASE_AHB + 0x02000)I2C_STAT(port) MMIO32((port) + 0x004)SCU_SFSPA_0 SCU_SFS(PIN_GROUPA, PIN0)SCU_SFSPE_5 SCU_SFS(PIN_GROUPE, PIN5)CGU_BASE_PHY_RX_CLK_PD_SHIFT (0)BIT27 (1<<27)UINTMAX_MAX __UINTMAX_MAX__CGU_IDIVE_CTRL MMIO32(CGU_BASE + 0x058)__GNUC_EXECUTION_CHARSET_NAME "UTF-8"SCU_SFSP8_0 SCU_SFS(PIN_GROUP8, PIN0)__UTA_FBIT__ 64SDIO_BASE (PERIPH_BASE_AHB + 0x04000)PIN_GROUP3 (SCU_BASE + 0x180)CGU_BASE_PHY_TX_CLK_PD (1 << CGU_BASE_PHY_TX_CLK_PD_SHIFT)__FLT_DECIMAL_DIG__ 9CGU_FREQ_MON_CLK_SEL(x) ((x) << CGU_FREQ_MON_CLK_SEL_SHIFT)__thumb__ 1__INT_LEAST32_MAX__ 0x7fffffffL__VERSION__ "12.2.1 20221205"GIMA_BASE (PERIPH_BASE_APB2 + 0x07000)CGU_PLL1_CTRL_CLK_SEL(x) ((x) << CGU_PLL1_CTRL_CLK_SEL_SHIFT)uint8_tINT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)CGU_BASE_LCD_CLK_AUTOBLOCK_SHIFT (11)INT32_C(c) __INT32_C(c)__GNUC_STDC_INLINE__ 1SCU_SFS(group,pin) MMIO32((group) + (pin))SCU_CONF_FUNCTION6 (0x6)__FRACT_FBIT__ 15CGU_BASE_VADC_CLK_CLK_SEL(x) ((x) << CGU_BASE_VADC_CLK_CLK_SEL_SHIFT)__FLT_HAS_QUIET_NAN__ 1__GNUC_PATCHLEVEL__ 1__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2PTRDIFF_MIN__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)CGU_BASE_UART0_CLK_AUTOBLOCK (1 << CGU_BASE_UART0_CLK_AUTOBLOCK_SHIFT)CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_SHIFT (12)UINTPTR_MAX __UINTPTR_MAX____ARM_ARCH_PROFILE 77CGU_BASE_APB3_CLK_PD_SHIFT (0)SCU_SFSP9_6 SCU_SFS(PIN_GROUP9, PIN6)__FLT64_MAX_10_EXP__ 308CGU_PLL1_CTRL_PSEL_SHIFT (8)MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MIN__INT_FAST32_WIDTH__ 32I2C_DATA_BUFFER(port) MMIO32((port) + 0x02C)SCU_SFSPD_11 SCU_SFS(PIN_GROUPD, PIN11)__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38SCU_SFSP1_5 SCU_SFS(PIN_GROUP1, PIN5)CGU_BASE_USB0_CLK_AUTOBLOCK_SHIFT (11)__FRACT_MAX__ 0X7FFFP-15RCGU_IDIVA_CTRL_IDIV_SHIFT (2)GNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -O2 -std=c99 -fno-common -ffunction-sections -fdata-sectionsINT_LEAST32_MAX __INT_LEAST32_MAX__CGU_IDIVE_CTRL_PD (1 << CGU_IDIVE_CTRL_PD_SHIFT)CGU_PLL0AUDIO_CTRL_DIRECTO_SHIFT (3)CGU_BASE_PHY_RX_CLK MMIO32(CGU_BASE + 0x078)CGU_BASE_UART0_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART0_CLK_CLK_SEL_SHIFT)__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5CGU_BASE_SPIFI_CLK_PD (1 << CGU_BASE_SPIFI_CLK_PD_SHIFT)SCU_SFSPD_3 SCU_SFS(PIN_GROUPD, PIN3)SCU_SFSPF_8 SCU_SFS(PIN_GROUPF, PIN8)CGU_IDIVB_CTRL_PD_SHIFT (0)CGU_PLL0USB_MDIV_SELP_MASK (0x1f << CGU_PLL0USB_MDIV_SELP_SHIFT)CGU_PLL0AUDIO_STAT_FR (1 << CGU_PLL0AUDIO_STAT_FR_SHIFT)CGU_BASE_SSP0_CLK_PD_SHIFT (0)CGU_BASE_SAFE_CLK_CLK_SEL(x) ((x) << CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT)CGU_IDIVE_CTRL_AUTOBLOCK (1 << CGU_IDIVE_CTRL_AUTOBLOCK_SHIFT)__UINT16_MAX__ 0xffffSCU_SFSPD_0 SCU_SFS(PIN_GROUPD, PIN0)CGU_PLL0USB_CTRL_AUTOBLOCK (1 << CGU_PLL0USB_CTRL_AUTOBLOCK_SHIFT)__TQ_FBIT__ 127I2C_CONSET_SI (1 << 3)SCU_SFSP4_9 SCU_SFS(PIN_GROUP4, PIN9)__USQ_FBIT__ 32CGU_BASE_UART0_CLK_AUTOBLOCK_SHIFT (11)CGU_IDIVC_CTRL_CLK_SEL_SHIFT (24)uint16_tSCU_SFSP2_10 SCU_SFS(PIN_GROUP2, PIN10)SCU_SFSP1_20 SCU_SFS(PIN_GROUP1, PIN20)__thumb2__ 1__ULLACCUM_FBIT__ 32CGU_SRC_ENET_TX 0x03PIN4 0x010CGU_BASE_SSP0_CLK MMIO32(CGU_BASE + 0x094)INT_FAST32_MIN (-INT_FAST32_MAX - 1)__STRICT_ANSI__ 1CGU_BASE_SPI_CLK_PD (1 << CGU_BASE_SPI_CLK_PD_SHIFT)CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT (24)UINT_LEAST8_MAXCGU_IDIVD_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVD_CTRL_CLK_SEL_SHIFT)SCU_SFSP2_2 SCU_SFS(PIN_GROUP2, PIN2)UINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8CGU_FREQ_MON_FCNT(x) ((x) << CGU_FREQ_MON_FCNT_SHIFT)SCU_SFSP2_6 SCU_SFS(PIN_GROUP2, PIN6)SCU_SFSP8_4 SCU_SFS(PIN_GROUP8, PIN4)__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__CGU_IDIVE_CTRL_PD_SHIFT (0)CGU_FREQ_MON_FCNT_SHIFT (9)CGU_BASE_VADC_CLK MMIO32(CGU_BASE + 0x08C)__USA_IBIT__ 16CGU_PLL0USB_CTRL_AUTOBLOCK_SHIFT (11)__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1CGU_FREQ_MON_MEAS (1 << CGU_FREQ_MON_MEAS_SHIFT)PTRDIFF_MIN (-PTRDIFF_MAX - 1)SCU_SFSPE_13 SCU_SFS(PIN_GROUPE, PIN13)CGU_BASE_APB3_CLK_CLK_SEL(x) ((x) << CGU_BASE_APB3_CLK_CLK_SEL_SHIFT)__UINT_FAST64_TYPE__ long long unsigned intCGU_PLL0AUDIO_STAT_FR_SHIFT (1)I2C0_MASK2 I2C_MASK2(I2C0)__FLT_MIN__ 1.1754943508222875e-38F__HA_FBIT__ 7SCU_SFSP1_4 SCU_SFS(PIN_GROUP1, PIN4)__FDPIC__I2C_ADR0(port) MMIO32((port) + 0x00C)SCU_SFSP6_10 SCU_SFS(PIN_GROUP6, PIN10)PIN12 0x030__FLT32_IS_IEC_60559__ 2CGU_BASE_PHY_TX_CLK_PD_SHIFT (0)CGU_BASE_UART2_CLK_AUTOBLOCK_SHIFT (11)CGU_FREQ_MON_CLK_SEL_MASK (0x1f << CGU_FREQ_MON_CLK_SEL_SHIFT)CGU_PLL0AUDIO_CTRL_BYPASS_SHIFT (1)INT_FAST64_MINADC0_BASE (PERIPH_BASE_APB3 + 0x03000)I2C0_CONCLR I2C_CONCLR(I2C0)SCU_SFSP2_11 SCU_SFS(PIN_GROUP2, PIN11)__LDBL_EPSILON__ 2.2204460492503131e-16LI2C_SCLL(port) MMIO32((port) + 0x014)SCU_SFSP3_0 SCU_SFS(PIN_GROUP3, PIN0)__USFRACT_MIN__ 0.0UHRSCU_SFSP7_5 SCU_SFS(PIN_GROUP7, PIN5)__ARM_NEONSCU_SFSP4_1 SCU_SFS(PIN_GROUP4, PIN1)__UINT8_MAX__ 0xffCGU_PLL0AUDIO_CTRL_AUTOBLOCK (1 << CGU_PLL0AUDIO_CTRL_AUTOBLOCK_SHIFT)CGU_BASE_APLL_CLK_PD (1 << CGU_BASE_APLL_CLK_PD_SHIFT)SCU_SFSP8_6 SCU_SFS(PIN_GROUP8, PIN6)__LDBL_MAX_EXP__ 1024SCU_CONF_FUNCTION7 (0x7)PIN_GROUP2 (SCU_BASE + 0x100)CGU_XTAL_OSC_CTRL_HF_SHIFT (2)i2c0_rx_byteCGU_PLL1_CTRL_FBSEL_SHIFT (6)__DBL_HAS_DENORM__ 1CGU_PLL0USB_MDIV_SELP(x) ((x) << CGU_PLL0USB_MDIV_SELP_SHIFT)SCU_CONF_ZIF_DIS_IN_GLITCH_FILT (BIT7)SCU_SFSP7_7 SCU_SFS(PIN_GROUP7, PIN7)I2C_READ 1CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT (24)CGU_SRC_IDIVB 0x0DCGU_BASE_PHY_RX_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT)CGU_BASE_SDIO_CLK_PD (1 << CGU_BASE_SDIO_CLK_PD_SHIFT)CGU_FREQ_MON_RCNT(x) ((x) << CGU_FREQ_MON_RCNT_SHIFT)__DA_FBIT__ 31SCU_SFSPE_11 SCU_SFS(PIN_GROUPE, PIN11)CGU_BASE_OUT_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_OUT_CLK_CLK_SEL_SHIFT)__GXX_ABI_VERSION 1017__INT_LEAST16_MAX__ 0x7fffPIN5 0x014CGU_FREQ_MON_RCNT_SHIFT (0)__FLT_DENORM_MIN__ 1.4012984643248171e-45FCGU_XTAL_OSC_CTRL_BYPASS (1 << CGU_XTAL_OSC_CTRL_BYPASS_SHIFT)__ULLACCUM_EPSILON__ 0x1P-32ULLKCGU_BASE_SPI_CLK MMIO32(CGU_BASE + 0x074)CGU_IDIVE_CTRL_CLK_SEL_SHIFT (24)CGU_PLL0USB_NP_DIV_PDEC_MASK (0x7f << CGU_PLL0USB_NP_DIV_PDEC_SHIFT)INT_LEAST8_MAX __INT_LEAST8_MAX__CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT (12)DAC_BASE (PERIPH_BASE_APB3 + 0x01000)SCU_SFSP1_19 SCU_SFS(PIN_GROUP1, PIN19)__UINT32_C(c) c ## ULCGU_BASE_PHY_RX_CLK_AUTOBLOCK (1 << CGU_BASE_PHY_RX_CLK_AUTOBLOCK_SHIFT)__UACCUM_MIN__ 0.0UKCGU_FREQ_MON_FCNT_MASK (0x3fff << CGU_FREQ_MON_FCNT_SHIFT)SCU_SFSPA_4 SCU_SFS(PIN_GROUPA, PIN4)__FLT_EPSILON__ 1.1920928955078125e-7FCGU_BASE_SPI_CLK_CLK_SEL_SHIFT (24)SCU_SFSPE_9 SCU_SFS(PIN_GROUPE, PIN9)__GCC_ATOMIC_SHORT_LOCK_FREE 2SCU_ENAIO0 MMIO32(SCU_BASE + 0xC88)LPC43XX_I2C_H I2C_CONSET_AA (1 << 2)CGU_BASE_UART2_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART2_CLK_CLK_SEL_SHIFT)__ARM_ARCH_ISA_THUMBCGU_PLL0USB_CTRL_FRM_SHIFT (6)CGU_BASE_SSP1_CLK MMIO32(CGU_BASE + 0x098)CGU_PLL0AUDIO_CTRL_CLKEN_SHIFT (4)CGU_BASE_UART1_CLK_AUTOBLOCK_SHIFT (11)__ARM_FEATURE_MATMUL_INT8SCU_SFSP8_8 SCU_SFS(PIN_GROUP8, PIN8)CGU_PLL1_CTRL_DIRECT_SHIFT (7)I2C_CONCLR_STAC (1 << 5)PIN13 0x034CGU_BASE_UART3_CLK_AUTOBLOCK_SHIFT (11)SCU_SFSPD_1 SCU_SFS(PIN_GROUPD, PIN1)CGU_BASE_PHY_TX_CLK_AUTOBLOCK (1 << CGU_BASE_PHY_TX_CLK_AUTOBLOCK_SHIFT)__USACCUM_FBIT__ 8CGU_SRC_PLL1 0x09__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1CGU_BASE_CGU_OUT0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT)CGU_PLL0USB_MDIV_MDEC_MASK (0x1ffff << CGU_PLL0USB_MDIV_MDEC_SHIFT)SCU_CONF_EPUN_DIS_PULLUP (BIT4)__LACCUM_FBIT__ 31SCU_SFSPB_0 SCU_SFS(PIN_GROUPB, PIN0)SCU_SFSPC_1 SCU_SFS(PIN_GROUPC, PIN1)CGU_BASE_APB1_CLK_PD_SHIFT (0)EMC_BASE (PERIPH_BASE_AHB + 0x05000)__FLT32_HAS_QUIET_NAN__ 1SCU_SFSPE_15 SCU_SFS(PIN_GROUPE, PIN15)INT32_MAX __INT32_MAX____LDBL_HAS_INFINITY__ 1CGU_SRC_GP_CLKIN 0x04__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))CCU1_BASE (0x40051000U)__FLT32X_MAX_10_EXP__ 308I2C1_DATA_BUFFER I2C_DATA_BUFFER(I2C1)CGU_BASE_PERIPH_CLK_CLK_SEL(x) ((x) << CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT)SCU_SFSP3_3 SCU_SFS(PIN_GROUP3, PIN3)__ARM_ARCH_EXT_IDIV__ 1CGU_IDIVD_CTRL_AUTOBLOCK_SHIFT (11)duty_cycle_countI2C_WRITE 0bool _Bool__FLT_MAX_EXP__ 128CGU_BASE_APB3_CLK_AUTOBLOCK (1 << CGU_BASE_APB3_CLK_AUTOBLOCK_SHIFT)__SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)SCU_SFSP1_10 SCU_SFS(PIN_GROUP1, PIN10)UINT_FAST16_MAX __UINT_FAST16_MAX____UINT_LEAST8_MAX__ 0xffCGU_PLL0AUDIO_MDIV_MDEC_SHIFT (0)CGU_XTAL_OSC_CTRL MMIO32(CGU_BASE + 0x018)CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT (0)SCU_SFSP1_9 SCU_SFS(PIN_GROUP1, PIN9)BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)PIN6 0x018CGU_IDIVE_CTRL_CLK_SEL(x) ((x) << CGU_IDIVE_CTRL_CLK_SEL_SHIFT)INT16_MAX __INT16_MAX____FP_FAST_FMAF 1CGU_IDIVA_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVA_CTRL_CLK_SEL_SHIFT)I2C1_ADR2 I2C_ADR2(I2C1)__FLT32X_IS_IEC_60559__ 2CGU_BASE_LCD_CLK MMIO32(CGU_BASE + 0x088)CGU_BASE_M4_CLK_CLK_SEL(x) ((x) << CGU_BASE_M4_CLK_CLK_SEL_SHIFT)PERIPH_BASE_APB3 (0x400E0000U)SCU_SFSPD_7 SCU_SFS(PIN_GROUPD, PIN7)SCU_SFSPC_7 SCU_SFS(PIN_GROUPC, PIN7)CGU_PLL1_CTRL_CLK_SEL_SHIFT (24)LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))UINT32_MAXCGU_PLL1_STAT MMIO32(CGU_BASE + 0x040)SCU_SFSPE_8 SCU_SFS(PIN_GROUPE, PIN8)__INT_LEAST16_WIDTH__ 16I2S0_BASE (PERIPH_BASE_APB1 + 0x02000)SCU_LCD (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)__DEC_EVAL_METHOD__ 2SCT_BASE (PERIPH_BASE_AHB + 0x00000)__ARM_FEATURE_FP16_FMLCGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT (24)CGU_PLL0USB_MDIV_MDEC(x) ((x) << CGU_PLL0USB_MDIV_MDEC_SHIFT)CGU_BASE_UART3_CLK_PD_SHIFT (0)SCU_SFSP1_8 SCU_SFS(PIN_GROUP1, PIN8)INT16_MIN (-INT16_MAX - 1)i2c0_stopSCU_PINTSEL1 MMIO32(SCU_BASE + 0xE04)SCU_SFSP7_3 SCU_SFS(PIN_GROUP7, PIN3)CGU_IDIVD_CTRL MMIO32(CGU_BASE + 0x054)CGU_BASE_USB0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_USB0_CLK_CLK_SEL_SHIFT)CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT (24)SCU_BASE (PERIPH_BASE_APB0 + 0x06000)__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLKCGU_BASE_SSP0_CLK_AUTOBLOCK (1 << CGU_BASE_SSP0_CLK_AUTOBLOCK_SHIFT)SCU_SCL_ZIF_DIS (BIT7)CGU_IDIVC_CTRL_PD (1 << CGU_IDIVC_CTRL_PD_SHIFT)__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX____UINT32_MAX__ 0xffffffffULUSART0_BASE (PERIPH_BASE_APB0 + 0x01000)I2C1_MASK3 I2C_MASK3(I2C1)__INT_LEAST8_MAX__ 0x7fSCU_SFSPF_10 SCU_SFS(PIN_GROUPF, PIN10)__GCC_ATOMIC_POINTER_LOCK_FREE 2__ARM_FEATURE_QBIT 1__ARM_FEATURE_CLZ 1__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXi2c0_tx_byteCGU_SRC_IRC 0x01PIN_GROUPC (SCU_BASE + 0x600)__ARM_PCS_VFP 1__UINT64_TYPE__ long long unsigned intCGU_BASE_SAFE_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT)__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024CGU_IDIVC_CTRL_AUTOBLOCK_SHIFT (11)SCU_SFSPD_2 SCU_SFS(PIN_GROUPD, PIN2)__UINT_LEAST32_MAX__ 0xffffffffUL__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)CGU_BASE_APLL_CLK_AUTOBLOCK (1 << CGU_BASE_APLL_CLK_AUTOBLOCK_SHIFT)__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1__ACCUM_MAX__ 0X7FFFFFFFP-15KSCU_SFSP2_3 SCU_SFS(PIN_GROUP2, PIN3)__INT8_MAX__ 0x7fCGU_OUTCLK_21_CTRL MMIO32(CGU_BASE + 0x0B0)BIT14 (1<<14)__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16PIN7 0x01CUSB1_BASE (PERIPH_BASE_AHB + 0x07000)BIT20 (1<<20)__ARM_FEATURE_MVE__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intCGU_PLL0USB_CTRL_CLKEN (1 << CGU_PLL0USB_CTRL_CLKEN_SHIFT)CGU_IDIVB_CTRL_CLK_SEL_SHIFT (24)SCU_SFSP4_5 SCU_SFS(PIN_GROUP4, PIN5)SCU_CONF_EHD_NORMAL_DRIVE_20MILLIA (0x300)UINT_LEAST16_MAX __UINT_LEAST16_MAX__INT_FAST32_MIN__FLT_EVAL_METHOD_TS_18661_3__ 0CGU_IDIVA_CTRL_IDIV_MASK (0x3 << CGU_IDIVA_CTRL_IDIV_SHIFT)__SCHAR_WIDTH__ 8CGU_PLL0AUDIO_NP_DIV_PDEC_MASK (0x7f << CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT)BIT18 (1<<18)UINT_FAST16_MAXSCU_SFSP2_1 SCU_SFS(PIN_GROUP2, PIN1)__UINT_FAST8_TYPE__ unsigned intCGU_BASE_UART1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART1_CLK_CLK_SEL_SHIFT)__LLACCUM_IBIT__ 32SCU_SFSP2_5 SCU_SFS(PIN_GROUP2, PIN5)__FRACT_EPSILON__ 0x1P-15RBIT24 (1<<24)CGU_PLL1_CTRL_MSEL_MASK (0xff << CGU_PLL1_CTRL_MSEL_SHIFT)SCU_SFSP2_9 SCU_SFS(PIN_GROUP2, PIN9)__INT32_MAX__ 0x7fffffffLSCU_SFSP7_2 SCU_SFS(PIN_GROUP7, PIN2)CGU_PLL0AUDIO_STAT_LOCK (1 << CGU_PLL0AUDIO_STAT_LOCK_SHIFT)UINTMAX_MAXBIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLLSCU_CONF_EHD_NORMAL_DRIVE_8MILLIA (0x100)__ARM_FEATURE_BF16_VECTOR_ARITHMETICCGU_IDIVA_CTRL_CLK_SEL(x) ((x) << CGU_IDIVA_CTRL_CLK_SEL_SHIFT)CGU_BASE_PERIPH_CLK_AUTOBLOCK_SHIFT (11)__FLT32_MANT_DIG__ 24CGU_IDIVA_CTRL_PD_SHIFT (0)INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32EVENTROUTER_BASE (0x40044000U)__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN____USFRACT_FBIT__ 8INT8_MAX __INT8_MAX__CGU_IDIVD_CTRL_PD_SHIFT (0)BIT28 (1<<28)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2INTMAX_C(c) __INTMAX_C(c)SCU_SFSPF_6 SCU_SFS(PIN_GROUPF, PIN6)__DBL_MAX_EXP__ 1024SCU_SCL_EHD (BIT2)__ATOMIC_RELEASE 3SCU_SFSUSB MMIO32(SCU_BASE + 0xC80)UINT_FAST8_MAX__FLT_MANT_DIG__ 24SCU_SFSPC_13 SCU_SFS(PIN_GROUPC, PIN13)CGU_BASE_APLL_CLK_CLK_SEL_SHIFT (24)__UDQ_IBIT__ 0CCU2_BASE (0x40052000U)__OPTIMIZE__ 1CGU_BASE_SSP0_CLK_PD (1 << CGU_BASE_SSP0_CLK_PD_SHIFT)__UACCUM_MAX__ 0XFFFFFFFFP-16UKCGU_BASE_APB3_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_APB3_CLK_CLK_SEL_SHIFT)SCU_SFSPD_5 SCU_SFS(PIN_GROUPD, PIN5)__FLT64_NORM_MAX__ 1.7976931348623157e+308F64PERIPH_BASE_APB1 (0x400A0000U)CGU_BASE_SDIO_CLK_AUTOBLOCK (1 << CGU_BASE_SDIO_CLK_AUTOBLOCK_SHIFT)UINTPTR_MAXSCU_ENAIO2 MMIO32(SCU_BASE + 0xC90)PIN_GROUPD (SCU_BASE + 0x680)__LDBL_DENORM_MIN__ 4.9406564584124654e-324LTIMER3_BASE (PERIPH_BASE_APB2 + 0x04000)__INT64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_SAT 1__ULLFRACT_IBIT__ 0CGU_IDIVA_CTRL_IDIV(x) ((x) << CGU_IDIVA_CTRL_IDIV_SHIFT)I2C0_DATA_BUFFER I2C_DATA_BUFFER(I2C0)SCU_SFSPF_1 SCU_SFS(PIN_GROUPF, PIN1)SPI_PORT_BASE (0x40100000U)CGU_BASE_LCD_CLK_PD (1 << CGU_BASE_LCD_CLK_PD_SHIFT)MMIO16(addr) (*(volatile uint16_t *)(addr))CGU_PLL0USB_NP_DIV_PDEC_SHIFT (0)PIN16 0x040SCU_SFSP9_2 SCU_SFS(PIN_GROUP9, PIN2)LPC43XX 1SCU_SFSPC_3 SCU_SFS(PIN_GROUPC, PIN3)__GNUC__ 12SCU_SFSP6_0 SCU_SFS(PIN_GROUP6, PIN0)CGU_BASE_UART1_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART1_CLK_CLK_SEL_SHIFT)WCHAR_MAXSCU_SFSPB_6 SCU_SFS(PIN_GROUPB, PIN6)__LONG_WIDTH__ 32CGU_BASE_OUT_CLK_AUTOBLOCK (1 << CGU_BASE_OUT_CLK_AUTOBLOCK_SHIFT)__FLT_MAX__ 3.4028234663852886e+38FI2C1_CONCLR I2C_CONCLR(I2C1)__UACCUM_FBIT__ 16SCU_SFSPE_10 SCU_SFS(PIN_GROUPE, PIN10)CGU_XTAL_OSC_CTRL_ENABLE_SHIFT (0)__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0U__UQQ_IBIT__ 0PIN8 0x020__GCC_ATOMIC_LONG_LOCK_FREE 2__ULACCUM_MIN__ 0.0ULK__USFRACT_EPSILON__ 0x1P-8UHR__LDBL_MAX__ 1.7976931348623157e+308L__ARM_ARCH 7SCU_SFSP1_15 SCU_SFS(PIN_GROUP1, PIN15)/build/libopencm3/lib/lpc43xx/m4__FLT_RADIX__ 2BIT3 (1<<3)long long intCGU_SRC_IDIVE 0x10__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAXSCU_SFSP6_12 SCU_SFS(PIN_GROUP6, PIN12)SGPIO_PORT_BASE (0x40101000U)I2C_MASK3(port) MMIO32((port) + 0x03C)CGU_PLL0USB_MDIV_SELI_MASK (0x3f << CGU_PLL0USB_MDIV_SELI_SHIFT)PERIPH_BASE_APB0 (0x40080000U)__LONG_LONG_WIDTH__ 64BIT6 (1<<6)CGU_FREQ_MON_MEAS_SHIFT (23)I2C0_MMCTRL I2C_MMCTRL(I2C0)CGU_PLL0USB_CTRL_DIRECTO (1 << CGU_PLL0USB_CTRL_DIRECTO_SHIFT)CGU_BASE_APB1_CLK MMIO32(CGU_BASE + 0x080)CGU_IDIVE_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVE_CTRL_CLK_SEL_SHIFT)__UINT_FAST64_MAX__ 0xffffffffffffffffULLCGU_BASE_M4_CLK_AUTOBLOCK_SHIFT (11)__ARM_FP__HA_IBIT__ 8__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1CGU_BASE_USB1_CLK_AUTOBLOCK_SHIFT (11)CGU_PLL0AUDIO_CTRL MMIO32(CGU_BASE + 0x030)BIT9 (1<<9)__FLT32X_MIN__ 2.2250738585072014e-308F32xSCU_SFSP3_2 SCU_SFS(PIN_GROUP3, PIN2)INTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024CGU_BASE_SAFE_CLK_PD_SHIFT (0)UINT16_MAXI2C_MASK2(port) MMIO32((port) + 0x038)CGU_PLL0USB_NP_DIV_PDEC(x) ((x) << CGU_PLL0USB_NP_DIV_PDEC_SHIFT)__FLT64_MIN__ 2.2250738585072014e-308F64__INTMAX_C(c) c ## LLCGU_PLL0USB_CTRL_BYPASS_SHIFT (1)SCU_SFSP3_6 SCU_SFS(PIN_GROUP3, PIN6)SCU_SFSPD_6 SCU_SFS(PIN_GROUPD, PIN6)__ARM_ARCH_PROFILE__INT64_TYPE__ long long intCGU_BASE_VADC_CLK_AUTOBLOCK (1 << CGU_BASE_VADC_CLK_AUTOBLOCK_SHIFT)__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4CGU_BASE_LCD_CLK_AUTOBLOCK (1 << CGU_BASE_LCD_CLK_AUTOBLOCK_SHIFT)CGU_BASE_USB1_CLK MMIO32(CGU_BASE + 0x068)SCU_SFSP1_16 SCU_SFS(PIN_GROUP1, PIN16)__GCC_ASM_FLAG_OUTPUTS__ 1SCU_CONF_EHS_FAST (BIT5)__UFRACT_MAX__ 0XFFFFP-16URSCU_SFSPC_12 SCU_SFS(PIN_GROUPC, PIN12)INT64_MAXCGU_BASE_USB1_CLK_PD_SHIFT (0)CGU_PLL0AUDIO_STAT_LOCK_SHIFT (0)CGU_IDIVA_CTRL_AUTOBLOCK (1 << CGU_IDIVA_CTRL_AUTOBLOCK_SHIFT)INT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0SSP1_BASE (PERIPH_BASE_APB2 + 0x05000)CGU_BASE_USB1_CLK_CLK_SEL(x) ((x) << CGU_BASE_USB1_CLK_CLK_SEL_SHIFT)SPIFI_BASE (PERIPH_BASE_AHB + 0x03000)__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__CGU_BASE_APB3_CLK_AUTOBLOCK_SHIFT (11)SCU_SFSP9_5 SCU_SFS(PIN_GROUP9, PIN5)__UFRACT_FBIT__ 16__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)CGU_XTAL_OSC_CTRL_BYPASS_SHIFT (1)CGU_FREQ_MON MMIO32(CGU_BASE + 0x014)__LDBL_MAX_10_EXP__ 308CGU_BASE_UART0_CLK_PD_SHIFT (0)I2C0 I2C0_BASESCU_SFSPC_2 SCU_SFS(PIN_GROUPC, PIN2)__INT_FAST32_TYPE__ intCGU_BASE_UART3_CLK_PD (1 << CGU_BASE_UART3_CLK_PD_SHIFT)SCU_SFSP6_6 SCU_SFS(PIN_GROUP6, PIN6)unsigned intCGU_BASE_SPI_CLK_PD_SHIFT (0)CGU_IDIVE_CTRL_AUTOBLOCK_SHIFT (11)I2C_CONCLR(port) MMIO32((port) + 0x018)SCU_SFSP3_1 SCU_SFS(PIN_GROUP3, PIN1)CGU_IDIVD_CTRL_AUTOBLOCK (1 << CGU_IDIVD_CTRL_AUTOBLOCK_SHIFT)__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1SCU_SFSP7_6 SCU_SFS(PIN_GROUP7, PIN6)CGU_PLL1_CTRL_PSEL(x) ((x) << CGU_PLL1_CTRL_PSEL_SHIFT)CGU_BASE_APB1_CLK_AUTOBLOCK_SHIFT (11)SCU_SFSP1_17 SCU_SFS(PIN_GROUP1, PIN17)PIN_GROUP7 (SCU_BASE + 0x380)__USACCUM_IBIT__ 8__ARM_ARCH_7EM__ 1PIN18 0x048__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UKCGU_BASE_OUT_CLK_CLK_SEL_SHIFT (24)SCU_SFSP4_6 SCU_SFS(PIN_GROUP4, PIN6)__FLT_EVAL_METHOD__ 0I2C_SCLH(port) MMIO32((port) + 0x010)CGU_OUTCLK_24_CTRL MMIO32(CGU_BASE + 0x0BC)GPIO_PORT_BASE (0x400F4000U)__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32I2C0_MASK0 I2C_MASK0(I2C0)CGU_BASE_LCD_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_LCD_CLK_CLK_SEL_SHIFT)PIN_GROUPF (SCU_BASE + 0x780)CGU_IDIVB_CTRL_AUTOBLOCK_SHIFT (11)__ARM_FEATURE_LDREXSCU_SFSPC_5 SCU_SFS(PIN_GROUPC, PIN5)__UQQ_FBIT__ 8CGU_PLL1_CTRL_AUTOBLOCK_SHIFT (11)CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK (1 << CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_SHIFT)INT16_CCGU_PLL0USB_CTRL_FRM (1 << CGU_PLL0USB_CTRL_FRM_SHIFT)__ARM_FP16_ARGS__GCC_IEC_559 0INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX__I2C1_SCLH I2C_SCLH(I2C1)__LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4__STDC__ 1i2c0_tx_startCGU_BASE_USB0_CLK_PD_SHIFT (0)SCU_SFSP1_6 SCU_SFS(PIN_GROUP1, PIN6)__ARM_FEATURE_IDIV 1SCU_SFSPD_9 SCU_SFS(PIN_GROUPD, PIN9)__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN____UINT8_TYPE__ unsigned charCGU_BASE_APB1_CLK_CLK_SEL(x) ((x) << CGU_BASE_APB1_CLK_CLK_SEL_SHIFT)SCU_GPIO_PUP (SCU_CONF_EZI_EN_IN_BUFFER)__ARM_FEATURE_COPROC 15CGU_PLL0USB_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT)SCU_SFSP4_8 SCU_SFS(PIN_GROUP4, PIN8)UINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"CGU_BASE_SAFE_CLK_PD (1 << CGU_BASE_SAFE_CLK_PD_SHIFT)INT8_MINSCU_SFSP1_18 SCU_SFS(PIN_GROUP1, PIN18)SCU_SFSPF_5 SCU_SFS(PIN_GROUPF, PIN5)CGU_PLL1_STAT_LOCK (1 << CGU_PLL1_STAT_LOCK_SHIFT)true 1I2C1_CONSET I2C_CONSET(I2C1)__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)SCU_SFSP4_3 SCU_SFS(PIN_GROUP4, PIN3)bytePIN_GROUP8 (SCU_BASE + 0x400)I2C_CONCLR_I2ENC (1 << 6)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__GCC_ATOMIC_CHAR_LOCK_FREE 2SCU_SFSPC_11 SCU_SFS(PIN_GROUPC, PIN11)CGU_PLL1_CTRL_PD (1 << CGU_PLL1_CTRL_PD_SHIFT)__LFRACT_EPSILON__ 0x1P-31LRI2C_CONSET_STA (1 << 5)CGU_PLLAUDIO_FRAC MMIO32(CGU_BASE + 0x03C)CGU_OUTCLK_22_CTRL MMIO32(CGU_BASE + 0x0B4)__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX____FLT32X_NORM_MAX__ 1.7976931348623157e+308F32xSCU_SDA_EHD (BIT10)__arm__ 1INT_FAST64_MAXCGU_BASE_SSP0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT)CGU_BASE_CGU_OUT1_CLK_PD_SHIFT (0)__FLT32_MIN_10_EXP__ (-37)CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT (24)MMIO64(addr) (*(volatile uint64_t *)(addr))CGU_PLL1_CTRL_MSEL(x) ((x) << CGU_PLL1_CTRL_MSEL_SHIFT)CGU_PLL0USB_MDIV_SELI_SHIFT (22)__ARM_FP16_FORMAT_ALTERNATIVE__LDBL_NORM_MAX__ 1.7976931348623157e+308LINTPTR_MINSCU_SFSPC_0 SCU_SFS(PIN_GROUPC, PIN0)CGU_BASE_USB0_CLK_CLK_SEL_SHIFT (24)__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)CGU_PLL1_CTRL_BYPASS (1 << CGU_PLL1_CTRL_BYPASS_SHIFT)CGU_BASE_UART2_CLK_CLK_SEL_SHIFT (24)CGU_BASE_UART2_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART2_CLK_CLK_SEL_SHIFT)__TA_IBIT__ 64SCU_GPIO_FAST (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)__FLT32_MIN__ 1.1754943508222875e-38F32CGU_BASE_USB1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_USB1_CLK_CLK_SEL_SHIFT)PERIPH_BASE_AHB (0x40000000U)CGU_IDIVC_CTRL_IDIV_SHIFT (2)CGU_XTAL_OSC_CTRL_HF (1 << CGU_XTAL_OSC_CTRL_HF_SHIFT)__ARM_FEATURE_QRDMXCGU_IDIVD_CTRL_IDIV_SHIFT (2)CGU_PLL0USB_MDIV_SELR_MASK (0xf << CGU_PLL0USB_MDIV_SELR_SHIFT)CGU_BASE_M4_CLK_CLK_SEL_SHIFT (24)I2C0_SCLH I2C_SCLH(I2C0)__LONG_LONG_MAX__ 0x7fffffffffffffffLL__WINT_WIDTH__ 32CGU_BASE_PHY_TX_CLK_CLK_SEL(x) ((x) << CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT)SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__CGU_BASE_CGU_OUT0_CLK MMIO32(CGU_BASE + 0x0C4)SCU_SFSI2C0 MMIO32(SCU_BASE + 0xC84)I2C0_ADR1 I2C_ADR1(I2C0)BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN____SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)CGU_BASE_CGU_OUT1_CLK_CLK_SEL(x) ((x) << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT)__DBL_MIN_EXP__ (-1021)SCU_SFSP6_3 SCU_SFS(PIN_GROUP6, PIN3)__LDBL_HAS_DENORM__ 1SCU_EMCDELAYCLK MMIO32(SCU_BASE + 0xD00)CGU_IDIVC_CTRL_AUTOBLOCK (1 << CGU_IDIVC_CTRL_AUTOBLOCK_SHIFT)INT8_MIN (-INT8_MAX - 1)GPIO_GROUP1_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x09000)CGU_PLL0USB_NP_DIV_NDEC_MASK (0x3ff << CGU_PLL0USB_NP_DIV_NDEC_SHIFT)SCU_EMC_IO (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)__FLT32_DIG__ 6INT_LEAST16_MAXCGU_BASE_M4_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_M4_CLK_CLK_SEL_SHIFT)CGU_PLL0USB_STAT_LOCK (1 << CGU_PLL0USB_STAT_LOCK_SHIFT)CGU_IDIVD_CTRL_PD (1 << CGU_IDIVD_CTRL_PD_SHIFT)BIT15 (1<<15)BACKUP_REG_BASE (0x40041000U)CGU_BASE_UART3_CLK_AUTOBLOCK (1 << CGU_BASE_UART3_CLK_AUTOBLOCK_SHIFT)SCU_SFSP9_0 SCU_SFS(PIN_GROUP9, PIN0)BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1GPIO_GROUP0_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x08000)__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1INT32_MAXSCU_SFSP5_5 SCU_SFS(PIN_GROUP5, PIN5)__ACCUM_MIN__ (-0X1P15K-0X1P15K)SCU_SFSP6_9 SCU_SFS(PIN_GROUP6, PIN9)__ARM_FEATURE_CRYPTOCGU_IDIVB_CTRL_CLK_SEL(x) ((x) << CGU_IDIVB_CTRL_CLK_SEL_SHIFT)__INT_LEAST32_TYPE__ long intCGU_BASE_LCD_CLK_CLK_SEL(x) ((x) << CGU_BASE_LCD_CLK_CLK_SEL_SHIFT)SCU_SFSPE_12 SCU_SFS(PIN_GROUPE, PIN12)SCU_SFSPE_4 SCU_SFS(PIN_GROUPE, PIN4)CGU_PLL0AUDIO_MDIV_MDEC_MASK (0x1ffff << CGU_PLL0AUDIO_MDIV_MDEC_SHIFT)CGU_BASE_UART1_CLK_CLK_SEL_SHIFT (24)CGU_BASE_APB1_CLK_CLK_SEL_SHIFT (24)BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULLCGU_BASE_CGU_OUT0_CLK_PD (1 << CGU_BASE_CGU_OUT0_CLK_PD_SHIFT)__FRACT_IBIT__ 0I2C1_BASE (PERIPH_BASE_APB3 + 0x00000)I2C1_DAT I2C_DAT(I2C1)UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2CGU_SRC_IDIVA 0x0CBIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234__FLT_NORM_MAX__ 3.4028234663852886e+38Flong long unsigned intSCU_SFSP3_5 SCU_SFS(PIN_GROUP3, PIN5)__FLT_MIN_10_EXP__ (-37)BIT31 (1<<31)CGU_BASE_USB0_CLK MMIO32(CGU_BASE + 0x060)__ULACCUM_IBIT__ 32I2C1 I2C1_BASE__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2SCU_SFSPF_4 SCU_SFS(PIN_GROUPF, PIN4)__PTRDIFF_TYPE__ int__APCS_32__ 1__DQ_FBIT__ 63INT_LEAST64_MAX__SACCUM_IBIT__ 8CGU_BASE_SSP1_CLK_AUTOBLOCK (1 << CGU_BASE_SSP1_CLK_AUTOBLOCK_SHIFT)__UHQ_IBIT__ 0CGU_BASE_SPI_CLK_CLK_SEL(x) ((x) << CGU_BASE_SPI_CLK_CLK_SEL_SHIFT)INT_LEAST8_MINPIN0 0x000I2C1_MMCTRL I2C_MMCTRL(I2C1)BIT29 (1<<29)__INT_FAST16_TYPE__ intSCU_SFSP6_2 SCU_SFS(PIN_GROUP6, PIN2)PIN14 0x038INT64_C__ULFRACT_MAX__ 0XFFFFFFFFP-32ULR__UINT_LEAST16_TYPE__ short unsigned intCGU_BASE_SPIFI_CLK_AUTOBLOCK_SHIFT (11)__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned int__FLT32X_DIG__ 15I2C1_MASK0 I2C_MASK0(I2C1)__UTQ_FBIT__ 128SCU_CONF_FUNCTION0 (0x0)CGU_BASE_UART0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART0_CLK_CLK_SEL_SHIFT)CGU_PLL0AUDIO_CTRL_MOD_PD_SHIFT (14)__LLACCUM_EPSILON__ 0x1P-31LLK__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffffSCU_SFSPC_14 SCU_SFS(PIN_GROUPC, PIN14)PIN_GROUP9 (SCU_BASE + 0x480)CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT (24)PIN_GROUPA (SCU_BASE + 0x500)PTRDIFF_MAX __PTRDIFF_MAX____SIZEOF_SHORT__ 2CGU_BASE_VADC_CLK_PD (1 << CGU_BASE_VADC_CLK_PD_SHIFT)I2C1_MASK1 I2C_MASK1(I2C1)SCU_GPIO_PDN (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EZI_EN_IN_BUFFER)CGU_BASE_SAFE_CLK MMIO32(CGU_BASE + 0x05C)CGU_PLL0USB_CTRL_DIRECTI (1 << CGU_PLL0USB_CTRL_DIRECTI_SHIFT)__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKSCU_SFSPD_15 SCU_SFS(PIN_GROUPD, PIN15)CGU_BASE_M4_CLK_AUTOBLOCK (1 << CGU_BASE_M4_CLK_AUTOBLOCK_SHIFT)CGU_PLL1_CTRL_BYPASS_SHIFT (1)CGU_IDIVE_CTRL_IDIV_SHIFT (2)UINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRCGU_BASE_UART0_CLK MMIO32(CGU_BASE + 0x09C)CGU_PLL0USB_CTRL_DIRECTI_SHIFT (2)CGU_BASE_USB0_CLK_PD (1 << CGU_BASE_USB0_CLK_PD_SHIFT)__DQ_IBIT__ 0I2C_CONSET_STO (1 << 4)__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intCGU_BASE_SDIO_CLK MMIO32(CGU_BASE + 0x090)CGU_PLL0USB_MDIV_SELR_SHIFT (28)CGU_BASE_APB3_CLK_PD (1 << CGU_BASE_APB3_CLK_PD_SHIFT)SSP0_BASE (PERIPH_BASE_APB0 + 0x03000)SCU_SFSPE_14 SCU_SFS(PIN_GROUPE, PIN14)SCU_SFSP2_0 SCU_SFS(PIN_GROUP2, PIN0)SCU_SFSP6_8 SCU_SFS(PIN_GROUP6, PIN8)QEI_BASE (PERIPH_BASE_APB2 + 0x06000)WCHAR_MINSCU_SFSP3_4 SCU_SFS(PIN_GROUP3, PIN4)CGU_SRC_ENET_RX 0x02SCU_CLK_OUT (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)BEGIN_DECLS CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK (1 << CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_SHIFT)SCU_SFSPE_1 SCU_SFS(PIN_GROUPE, PIN1)SCU_SFSP1_13 SCU_SFS(PIN_GROUP1, PIN13)SCU_SFSCLK1 MMIO32(SCU_BASE + 0xC04)CGU_IDIVD_CTRL_IDIV(x) ((x) << CGU_IDIVD_CTRL_IDIV_SHIFT)SCU_SFSPF_2 SCU_SFS(PIN_GROUPF, PIN2)CGU_BASE_PHY_RX_CLK_PD (1 << CGU_BASE_PHY_RX_CLK_PD_SHIFT)CGU_BASE_SAFE_CLK_AUTOBLOCK_SHIFT (11)SCU_SFSPD_8 SCU_SFS(PIN_GROUPD, PIN8)CGU_BASE_UART1_CLK_PD (1 << CGU_BASE_UART1_CLK_PD_SHIFT)CGU_BASE_UART3_CLK MMIO32(CGU_BASE + 0x0A8)SCU_SFSP5_0 SCU_SFS(PIN_GROUP5, PIN0)CGU_BASE_SDIO_CLK_AUTOBLOCK_SHIFT (11)__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15CGU_BASE_CGU_OUT1_CLK MMIO32(CGU_BASE + 0x0C8)__FLT32X_MAX__ 1.7976931348623157e+308F32xPIN1 0x004CGU_PLL0USB_STAT_LOCK_SHIFT (0)__ARM_EABI__ 1SCU_SFSCLK2 MMIO32(SCU_BASE + 0xC08)INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1CGU_BASE_USB0_CLK_AUTOBLOCK (1 << CGU_BASE_USB0_CLK_AUTOBLOCK_SHIFT)__ARM_FEATURE_DSP 1CGU_SRC_PLL0AUDIO 0x08USART3_BASE (PERIPH_BASE_APB2 + 0x02000)PIN15 0x03CCGU_BASE_UART3_CLK_CLK_SEL_SHIFT (24)SCU_SCL_EFP (BIT0)__QQ_IBIT__ 0SCU_SFSPD_16 SCU_SFS(PIN_GROUPD, PIN16)CGU_IDIVC_CTRL MMIO32(CGU_BASE + 0x050)CGU_PLL0AUDIO_NP_DIV MMIO32(CGU_BASE + 0x038)SCU_SDA_ZIF_DIS (BIT15)CGU_BASE_OUT_CLK_PD_SHIFT (0)CGU_SRC_PLL0USB 0x07__LLACCUM_FBIT__ 31CGU_BASE_UART2_CLK_PD_SHIFT (0)__UINTMAX_TYPE__ long long unsigned intCGU_PLL1_CTRL_AUTOBLOCK (1 << CGU_PLL1_CTRL_AUTOBLOCK_SHIFT)CGU_BASE_PHY_TX_CLK_AUTOBLOCK_SHIFT (11)__USQ_IBIT__ 0CGU_PLL0USB_NP_DIV_NDEC_SHIFT (12)__UINT_LEAST32_TYPE__ long unsigned intSCU_SFSP7_4 SCU_SFS(PIN_GROUP7, PIN4)CGU_SRC_XTAL 0x06__ARM_FEATURE_NUMERIC_MAXMINPIN_GROUP0 (SCU_BASE + 0x000)__INTMAX_TYPE__ long long intSCU_CONF_EZI_EN_IN_BUFFER (BIT6)CGU_BASE_UART0_CLK_PD (1 << CGU_BASE_UART0_CLK_PD_SHIFT)__GCC_ATOMIC_INT_LOCK_FREE 2CGU_IDIVC_CTRL_CLK_SEL(x) ((x) << CGU_IDIVC_CTRL_CLK_SEL_SHIFT)I2C0_STAT I2C_STAT(I2C0)SCU_SFSPB_3 SCU_SFS(PIN_GROUPB, PIN3)CGU_BASE_SPI_CLK_AUTOBLOCK_SHIFT (11)INTMAX_MAXSCU_SFSP1_14 SCU_SFS(PIN_GROUP1, PIN14)CGU_BASE_SPI_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SPI_CLK_CLK_SEL_SHIFT)TIMER2_BASE (PERIPH_BASE_APB2 + 0x03000)SCU_SFSPC_4 SCU_SFS(PIN_GROUPC, PIN4)SCU_SFSP6_1 SCU_SFS(PIN_GROUP6, PIN1)__ARM_FEATURE_FP16_SCALAR_ARITHMETIC__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1CGU_PLL1_CTRL_MSEL_SHIFT (16)SCU_SFSP6_7 SCU_SFS(PIN_GROUP6, PIN7)I2C_CONSET_I2EN (1 << 6)CGU_LPC43XX_CGU_H __LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CSCU_SFSP4_4 SCU_SFS(PIN_GROUP4, PIN4)CGU_BASE_SSP0_CLK_AUTOBLOCK_SHIFT (11)CGU_PLL0AUDIO_NP_DIV_NDEC_MASK (0x3ff << CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT)CGU_PLL1_CTRL MMIO32(CGU_BASE + 0x044)SCU_SFSPE_0 SCU_SFS(PIN_GROUPE, PIN0)INT64_MIN__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intCGU_BASE_APB1_CLK_AUTOBLOCK (1 << CGU_BASE_APB1_CLK_AUTOBLOCK_SHIFT)CGU_IDIVC_CTRL_IDIV_MASK (0xf << CGU_IDIVC_CTRL_IDIV_SHIFT)UINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRSCU_SFSP1_12 SCU_SFS(PIN_GROUP1, PIN12)SCU_SFSP9_4 SCU_SFS(PIN_GROUP9, PIN4)__SIZEOF_SIZE_T__ 4PMC_BASE (0x40042000U)CGU_BASE_UART2_CLK MMIO32(CGU_BASE + 0x0A4)__INT64_C(c) c ## LL__LACCUM_IBIT__ 32SCU_SDA_EFP (BIT8)__LDBL_MIN_10_EXP__ (-307)CGU_BASE_SSP1_CLK_AUTOBLOCK_SHIFT (11)CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ (1 << CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_SHIFT)UART1_BASE (PERIPH_BASE_APB0 + 0x02000)__LDBL_MIN__ 2.2250738585072014e-308LCGU_PLL0AUDIO_NP_DIV_NDEC(x) ((x) << CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT)__ARM_FEATURE_CDE__ACCUM_IBIT__ 16SCU_SFSPA_3 SCU_SFS(PIN_GROUPA, PIN3)CGU_BASE_SPIFI_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT)CGU_PLL1_CTRL_PD_SHIFT (0)CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT (24)CGU_BASE_USB1_CLK_CLK_SEL_SHIFT (24)__GCC_DESTRUCTIVE_SIZE 64I2C_CONSET(port) MMIO32((port) + 0x000)CGU_BASE_VADC_CLK_CLK_SEL_SHIFT (24)short intI2C0_DAT I2C_DAT(I2C0)CGU_BASE_APB1_CLK_PD (1 << CGU_BASE_APB1_CLK_PD_SHIFT)CGU_BASE_USB1_CLK_AUTOBLOCK (1 << CGU_BASE_USB1_CLK_AUTOBLOCK_SHIFT)__UINT16_C(c) cCGU_OUTCLK_23_CTRL MMIO32(CGU_BASE + 0x0B8)CGU_PLL0AUDIO_CTRL_CLK_SEL(x) ((x) << CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT)__UDA_IBIT__ 32PIN_GROUP1 (SCU_BASE + 0x080)UINT_LEAST32_MAXCGU_BASE_APLL_CLK_PD_SHIFT (0)SCU_SFSPB_2 SCU_SFS(PIN_GROUPB, PIN2)BIT2 (1<<2)__ATOMIC_RELAXED 0__ARM_FEATURE_COPROCCGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_MASK (0x3fffff << CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT)CGU_BASE_VADC_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_VADC_CLK_CLK_SEL_SHIFT)__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53__ARM_FEATURE_FMA 1LPC43XX_M4 1CGU_PLL0AUDIO_CTRL_DIRECTI (1 << CGU_PLL0AUDIO_CTRL_DIRECTI_SHIFT)BIT5 (1<<5)CGU_IDIVE_CTRL_IDIV_MASK (0xff << CGU_IDIVE_CTRL_IDIV_SHIFT)BIT1 (1<<1)INT8_CINT_LEAST32_MAX__USES_INITFINI__ 1I2S1_BASE (PERIPH_BASE_APB1 + 0x03000)SCU_SFSP4_10 SCU_SFS(PIN_GROUP4, PIN10)__DBL_DECIMAL_DIG__ 17CGU_BASE_SSP1_CLK_PD_SHIFT (0)BIT8 (1<<8)CGU_BASE_SSP1_CLK_CLK_SEL(x) ((x) << CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT)SCU_SFSP8_2 SCU_SFS(PIN_GROUP8, PIN2)INT16_C(c) __INT16_C(c)PIN_GROUP6 (SCU_BASE + 0x300)CGU_BASE_SPIFI_CLK_PD_SHIFT (0)SCU_SFSP9_3 SCU_SFS(PIN_GROUP9, PIN3)SCU_CONF_EPD_EN_PULLDOWN (BIT3)CGU_BASE_CGU_OUT1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT)__INT16_MAX__ 0x7fffI2C0_CONSET I2C_CONSET(I2C0)CGU_BASE_PERIPH_CLK MMIO32(CGU_BASE + 0x064)PIN_GROUP4 (SCU_BASE + 0x200)SCU_SFSPF_11 SCU_SFS(PIN_GROUPF, PIN11)CGU_XTAL_OSC_CTRL_ENABLE (1 << CGU_XTAL_OSC_CTRL_ENABLE_SHIFT)__INT_WIDTH__ 32__ARM_FEATURE_SIMD32 1SCU_SCL_EZI_EN (BIT3)CGU_IDIVA_CTRL_AUTOBLOCK_SHIFT (11)I2C0_ADR0 I2C_ADR0(I2C0)CGU_BASE_UART1_CLK MMIO32(CGU_BASE + 0x0A0)I2C_CONCLR_AAC (1 << 2)RITIMER_BASE (PERIPH_BASE_APB2 + 0x00000)CGU_SRC_IDIVD 0x0F__SIG_ATOMIC_WIDTH__ 32SCU_I2C0_NOMINAL (SCU_SCL_EZI_EN | SCU_SDA_EZI_EN)__FLT64_EPSILON__ 2.2204460492503131e-16F64SCU_PINTSEL0 MMIO32(SCU_BASE + 0xE00)SCU_SFSPC_9 SCU_SFS(PIN_GROUPC, PIN9)SCU_SFSPF_3 SCU_SFS(PIN_GROUPF, PIN3)__UTA_IBIT__ 64__ULLACCUM_IBIT__ 32CGU_PLL1_CTRL_NSEL(x) ((x) << CGU_PLL1_CTRL_NSEL_SHIFT)SCU_SFSPF_7 SCU_SFS(PIN_GROUPF, PIN7)RGU_BASE (0x40053000U)CGU_BASE_M4_CLK MMIO32(CGU_BASE + 0x06C)__ULLFRACT_EPSILON__ 0x1P-64ULLRfalse 0SCU_SFSP3_8 SCU_SFS(PIN_GROUP3, PIN8)__SIZEOF_WINT_T__ 4CGU_BASE_LCD_CLK_PD_SHIFT (0)__ARM_FEATURE_UNALIGNED 1__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17CGU_PLL0AUDIO_CTRL_MOD_PD (1 << CGU_PLL0AUDIO_CTRL_MOD_PD_SHIFT)I2C_ADR1(port) MMIO32((port) + 0x020)__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1CGU_IDIVC_CTRL_IDIV(x) ((x) << CGU_IDIVC_CTRL_IDIV_SHIFT)__FLT32X_HAS_DENORM__ 1CGU_IDIVB_CTRL_IDIV_MASK (0xf << CGU_IDIVB_CTRL_IDIV_SHIFT)__ULLACCUM_MIN__ 0.0ULLKSCU_SFSP5_4 SCU_SFS(PIN_GROUP5, PIN4)GPIO_PIN_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x07000)I2C0_SCLL I2C_SCLL(I2C0)CGU_IDIVE_CTRL_IDIV(x) ((x) << CGU_IDIVE_CTRL_IDIV_SHIFT)SCU_CONF_FUNCTION2 (0x2)SCU_SFSP6_5 SCU_SFS(PIN_GROUP6, PIN5)CGU_PLL0AUDIO_STAT MMIO32(CGU_BASE + 0x02C)PIN20 0x050CGU_IDIVB_CTRL MMIO32(CGU_BASE + 0x04C)__ARM_ASM_SYNTAX_UNIFIED__ 1CGU_PLL0AUDIO_MDIV_MDEC(x) ((x) << CGU_PLL0AUDIO_MDIV_MDEC_SHIFT)PIN17 0x044SCU_UART_RX_TX (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EZI_EN_IN_BUFFER)CGU_BASE_PERIPH_CLK_PD (1 << CGU_BASE_PERIPH_CLK_PD_SHIFT)__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODPIN10 0x028I2C1_ADR1 I2C_ADR1(I2C1)SCU_SFSP8_1 SCU_SFS(PIN_GROUP8, PIN1)RTC_BASE (0x40046000U)CGU_BASE_OUT_CLK_CLK_SEL(x) ((x) << CGU_BASE_OUT_CLK_CLK_SEL_SHIFT)SCU_SFSPD_10 SCU_SFS(PIN_GROUPD, PIN10)CGU_PLL0USB_CTRL_CLKEN_SHIFT (4)CGU_PLL0AUDIO_CTRL_CLKEN (1 << CGU_PLL0AUDIO_CTRL_CLKEN_SHIFT)__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H SCU_SFSPC_10 SCU_SFS(PIN_GROUPC, PIN10)AES_BASE (0x400F1000U)INT_LEAST64_MIN__GCC_CONSTRUCTIVE_SIZE 64PIN_GROUP5 (SCU_BASE + 0x280)__LLFRACT_IBIT__ 0CGU_IDIVB_CTRL_AUTOBLOCK (1 << CGU_IDIVB_CTRL_AUTOBLOCK_SHIFT)uint32_tBIT12 (1<<12)CGU_BASE_UART1_CLK_PD_SHIFT (0)__SACCUM_EPSILON__ 0x1P-7HKCGU_BASE_APLL_CLK_AUTOBLOCK_SHIFT (11)__ARM_ARCH_ISA_THUMB 2CGU_BASE_APLL_CLK_CLK_SEL(x) ((x) << CGU_BASE_APLL_CLK_CLK_SEL_SHIFT)SCU_SFSPC_8 SCU_SFS(PIN_GROUPC, PIN8)__ARM_FP 4LPC43XX_SCU_H CGU_BASE_SSP0_CLK_CLK_SEL(x) ((x) << CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT)__UINT_FAST16_TYPE__ unsigned intCGU_BASE_SAFE_CLK_AUTOBLOCK (1 << CGU_BASE_SAFE_CLK_AUTOBLOCK_SHIFT)__UHA_IBIT__ 8CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT (24)CGU_BASE_PERIPH_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT)__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULKI2C0_ADR3 I2C_ADR3(I2C0)__LDBL_DIG__ 15CGU_BASE_SSP1_CLK_PD (1 << CGU_BASE_SSP1_CLK_PD_SHIFT)SCU_SFSP1_3 SCU_SFS(PIN_GROUP1, PIN3)UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXBIT16 (1<<16)SCU_GPIO_NOPULL (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EZI_EN_IN_BUFFER)__WINT_MIN__ 0UINT_LEAST16_MIN__FLT64_DIG__ 15__WINT_MAX__ 0xffffffffUBIT22 (1<<22)__INT_LEAST8_WIDTH__ 8CGU_PLL0USB_CTRL MMIO32(CGU_BASE + 0x020)SCU_SFSP5_3 SCU_SFS(PIN_GROUP5, PIN3)__INT_LEAST16_TYPE__ short intCGU_PLL0USB_NP_DIV MMIO32(CGU_BASE + 0x028)__QQ_FBIT__ 7CGU_IDIVA_CTRL_PD (1 << CGU_IDIVA_CTRL_PD_SHIFT)CGU_PLL0USB_CTRL_DIRECTO_SHIFT (3)__DBL_MAX__ ((double)1.7976931348623157e+308L)CGU_SRC_IDIVC 0x0EINT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1UINTMAX_CCGU_PLL1_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL1_CTRL_CLK_SEL_SHIFT)CGU_PLL0AUDIO_CTRL_FRM_SHIFT (6)CGU_PLL0USB_CTRL_CLK_SEL(x) ((x) << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT)INT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1PIN9 0x024__UINTPTR_MAX__ 0xffffffffUSCU_SFSP8_7 SCU_SFS(PIN_GROUP8, PIN7)__HQ_FBIT__ 15__bool_true_false_are_defined 1USART2_BASE (PERIPH_BASE_APB2 + 0x01000)BIT26 (1<<26)I2C0_MASK1 I2C_MASK1(I2C0)__SIZE_MAX__ 0xffffffffUCGU_BASE_UART0_CLK_CLK_SEL_SHIFT (24)CGU_PLL1_CTRL_NSEL_SHIFT (12)CGU_BASE_PHY_TX_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT)CGU_FREQ_MON_RCNT_MASK (0x1ff << CGU_FREQ_MON_RCNT_SHIFT)CGU_BASE_CGU_OUT0_CLK_PD_SHIFT (0)__ARM_ARCH__LONG_MAX__ 0x7fffffffLSCU_SFSP6_4 SCU_SFS(PIN_GROUP6, PIN4)MCPWM_BASE (PERIPH_BASE_APB1 + 0x00000)CGU_PLL0AUDIO_CTRL_AUTOBLOCK_SHIFT (11)CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_SHIFT (11)LPC43XX_MEMORYMAP_H __ARM_FEATURE_LDREX 7PTRDIFF_MAXCGU_BASE_APB3_CLK MMIO32(CGU_BASE + 0x084)CGU_PLL0USB_MDIV_SELP_SHIFT (17)SCU_SDA_EZI_EN (BIT11)__LLFRACT_EPSILON__ 0x1P-63LLRCGU_PLL0USB_NP_DIV_NDEC(x) ((x) << CGU_PLL0USB_NP_DIV_NDEC_SHIFT)__SFRACT_MAX__ 0X7FP-7HR__FLT32X_MANT_DIG__ 53CGU_BASE_APB1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_APB1_CLK_CLK_SEL_SHIFT)SCU_CONF_FUNCTION3 (0x3)__WCHAR_WIDTH__ 32WINT_MAXSCU_SFSP4_7 SCU_SFS(PIN_GROUP4, PIN7)__INT16_C(c) cSCU_SFSPE_3 SCU_SFS(PIN_GROUPE, PIN3)INT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32__USFRACT_IBIT__ 0SCU_CLK_IN (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)SCU_SFSP7_1 SCU_SFS(PIN_GROUP7, PIN1)SCU_I2C0_FAST (SCU_SCL_EFP | SCU_SCL_EHD | SCU_SCL_EZI_EN | SCU_SCL_ZIF_DIS | SCU_SDA_EFP | SCU_SDA_EHD | SCU_SDA_EZI_EN)__ATOMIC_ACQ_REL 4ADC1_BASE (PERIPH_BASE_APB3 + 0x04000)SCU_SFSPC_6 SCU_SFS(PIN_GROUPC, PIN6)__HQ_IBIT__ 0__DBL_MIN_10_EXP__ (-307)SCU_SFSPD_13 SCU_SFS(PIN_GROUPD, PIN13)SCU_ENAIO1 MMIO32(SCU_BASE + 0xC8C)CGU_BASE_PERIPH_CLK_PD_SHIFT (0)CGU_PLL0AUDIO_CTRL_DIRECTI_SHIFT (2)CGU_BASE_LCD_CLK_CLK_SEL_SHIFT (24)CGU_BASE_M4_CLK_PD_SHIFT (0)SCU_CONF_EHD_NORMAL_DRIVE_14MILLIA (0x200)SCU_SFSP1_7 SCU_SFS(PIN_GROUP1, PIN7)__FLT32_NORM_MAX__ 3.4028234663852886e+38F32SCU_SFSCLK0 MMIO32(SCU_BASE + 0xC00)CGU_BASE_UART2_CLK_AUTOBLOCK (1 << CGU_BASE_UART2_CLK_AUTOBLOCK_SHIFT)UINT64_C(c) __UINT64_C(c)CGU_BASE_UART3_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART3_CLK_CLK_SEL_SHIFT)CGU_PLL0AUDIO_CTRL_PD (1 << CGU_PLL0AUDIO_CTRL_PD_SHIFT)CGU_BASE_USB1_CLK_PD (1 << CGU_BASE_USB1_CLK_PD_SHIFT)__UINTMAX_MAX__ 0xffffffffffffffffULLCGU_BASE_OUT_CLK_AUTOBLOCK_SHIFT (11)__DBL_MANT_DIG__ 53__ULFRACT_IBIT__ 0CGU_IDIVB_CTRL_IDIV(x) ((x) << CGU_IDIVB_CTRL_IDIV_SHIFT)INT_FAST16_MAXSCU_SFSP1_11 SCU_SFS(PIN_GROUP1, PIN11)PIN19 0x04C__INT_MAX__ 0x7fffffff__INT_LEAST64_TYPE__ long long int__ARM_FEATURE_CDE_COPROCCGU_PLL0USB_CTRL_BYPASS (1 << CGU_PLL0USB_CTRL_BYPASS_SHIFT)CGU_PLL1_CTRL_PSEL_MASK (0x3 << CGU_PLL1_CTRL_PSEL_SHIFT)UINT32_CGCC: (15:12.2.rel1-1) 12.2.1 20221205 | (CI  $ A3aeabi)7E-M M  "         -/!#%')+1 4e-[ 03 (  $i2c.c$t$dwm4.0.ac8f3cbd7733ee78183be95102ca936awm4.common.h.21.c9066c2f6b12c71b40226ea6107829a4wm4.stdint.h.29.6d480f4ba0f60596e88234283d42444fwm4.stdbool.h.29.4a1c88fe569adb8d03217dd16982ca34wm4.common.h.67.5c568a1f62c8e726909b04e29f9e1fc0wm4.memorymap.h.22.395ffb693017d551ed93d11c39ba4361wm4.i2c.h.45.c4ca94c213d8887803b1366d0112f9b7wm4.scu.h.36.013ea3915138f7d9730501011396d638wm4.cgu.h.37.c480a83e7590bba775f2472229e8edb0i2c0_initi2c0_tx_starti2c0_tx_bytei2c0_rx_bytei2c0_stop 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Z  B  .) ) 0 / CGU_PLL1_CTRL_FBSEL (1 << CGU_PLL1_CTRL_FBSEL_SHIFT)CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT (24)__DECIMAL_DIG__ 17__UHA_FBIT__ 8CGU_BASE_OUT_CLK_AUTOBLOCK (1 << CGU_BASE_OUT_CLK_AUTOBLOCK_SHIFT)ssp_frame_format_tCGU_BASE_UART0_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART0_CLK_CLK_SEL_SHIFT)CGU_BASE_UART2_CLK_PD (1 << CGU_BASE_UART2_CLK_PD_SHIFT)__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64__GCC_ATOMIC_WCHAR_T_LOCK_FREE 2CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT (24)__CHAR_UNSIGNED__ 1ETHERNET_BASE (PERIPH_BASE_AHB + 0x10000)slave_optionmaster_slaveCGU_BASE_PHY_RX_CLK_AUTOBLOCK_SHIFT (11)CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT (24)__FLT64_HAS_INFINITY__ 1CGU_IDIVC_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVC_CTRL_CLK_SEL_SHIFT)CGU_IDIVB_CTRL_CLK_SEL_SHIFT (24)__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)SSP1_SR SSP_SR(SSP1)__GCC_DESTRUCTIVE_SIZE 64__LACCUM_EPSILON__ 0x1P-31LK__PTRDIFF_MAX__ 0x7fffffff__ARM_FEATURE_FMA 1CGU_PLL0AUDIO_CTRL_SEL_EXT_SHIFT (13)__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)__INTMAX_MAX__ 0x7fffffffffffffffLLCGU_IDIVD_CTRL_CLK_SEL_SHIFT (24)__TQ_IBIT__ 0__FLT64_DECIMAL_DIG__ 17WINT_MIN __WINT_MIN__I2C0_BASE (PERIPH_BASE_APB1 + 0x01000)__ATOMIC_CONSUME 1__ULACCUM_FBIT__ 32__WCHAR_MAX__ 0xffffffffUCGU_PLL0USB_MDIV_SELR(x) ((x) << CGU_PLL0USB_MDIV_SELR_SHIFT)OTP_BASE (0x40045000U)CGU_BASE_APLL_CLK MMIO32(CGU_BASE + 0x0C0)CGU_BASE_SSP1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT)CGU_PLL0USB_CTRL_CLK_SEL_SHIFT (24)INT64_MAX __INT64_MAX__INTMAX_MIN__SIZEOF_LONG_LONG__ 8__DBL_MAX_10_EXP__ 308CGU_BASE_APLL_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_APLL_CLK_CLK_SEL_SHIFT)__FRACT_MIN__ (-0.5R-0.5R)__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLK__USACCUM_MAX__ 0XFFFFP-8UHK__SFRACT_FBIT__ 7__INTMAX_WIDTH__ 64__ARM_FEATURE_BF16_SCALAR_ARITHMETICSSP1_DR SSP_DR(SSP1)__ORDER_PDP_ENDIAN__ 3412__SIZE_TYPE__ unsigned intC_CCAN1_BASE (PERIPH_BASE_APB1 + 0x04000)__FLT_HAS_DENORM__ 1__INT8_TYPE__ signed char__SHRT_WIDTH__ 16CGU_BASE_SDIO_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT)__UINT_LEAST8_TYPE__ unsigned char__USACCUM_MIN__ 0.0UHKSSP_IMSC(port) MMIO32((port) + 0x014)__FLT32_DECIMAL_DIG__ 9CGU_BASE_UART1_CLK_AUTOBLOCK (1 << CGU_BASE_UART1_CLK_AUTOBLOCK_SHIFT)CGU_IDIVB_CTRL_IDIV(x) ((x) << CGU_IDIVB_CTRL_IDIV_SHIFT)__LDBL_MIN_EXP__ (-1021)CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_MASK (0x3fffff << CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT)__LDBL_MANT_DIG__ 53INT64_MIN (-INT64_MAX - 1)__UINT8_C(c) c__INT16_TYPE__ short intCGU_BASE_USB0_CLK_CLK_SEL(x) ((x) << CGU_BASE_USB0_CLK_CLK_SEL_SHIFT)__FLT64_MAX__ 1.7976931348623157e+308F64USB0_BASE (PERIPH_BASE_AHB + 0x06000)CGU_BASE_PERIPH_CLK_AUTOBLOCK (1 << CGU_BASE_PERIPH_CLK_AUTOBLOCK_SHIFT)UINT_FAST32_MAXCGU_BASE_PHY_TX_CLK MMIO32(CGU_BASE + 0x07C)SSP_DATA_12BITSINT_FAST64_MAX __INT_FAST64_MAX__CGU_PLL0AUDIO_CTRL_FRM (1 << CGU_PLL0AUDIO_CTRL_FRM_SHIFT)__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1__UINT_LEAST16_MAX__ 0xffff__STDC_HOSTED__ 1__ULLFRACT_FBIT__ 64__SIG_ATOMIC_TYPE__ intCGU_BASE_APB3_CLK_AUTOBLOCK (1 << CGU_BASE_APB3_CLK_AUTOBLOCK_SHIFT)CGU_BASE_SPIFI_CLK_CLK_SEL(x) ((x) << CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT)__INT_FAST64_TYPE__ long long int__ARM_FEATURE_COPROC 15PERIPH_BASE_APB2 (0x400C0000U)CGU_BASE_SPIFI_CLK_AUTOBLOCK (1 << CGU_BASE_SPIFI_CLK_AUTOBLOCK_SHIFT)ssp_wait_until_not_busyINT32_MIN (-INT32_MAX - 1)__FLT32_MAX_10_EXP__ 38CGU_SRC_32K 0x00WWDT_BASE (PERIPH_BASE_APB0 + 0x00000)__USFRACT_MAX__ 0XFFP-8UHRCGU_PLL0USB_MDIV MMIO32(CGU_BASE + 0x024)__FP_FAST_FMAF32 1CGU_PLL1_CTRL MMIO32(CGU_BASE + 0x044)TIMER1_BASE (PERIPH_BASE_APB0 + 0x05000)__FLT32_MIN_EXP__ (-125)CGU_BASE_VADC_CLK_PD_SHIFT (0)ATIMER_BASE (0x40040000U)UINT32_MAX __UINT32_MAX__CGU_IDIVB_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVB_CTRL_CLK_SEL_SHIFT)C_CAN0_BASE (PERIPH_BASE_APB3 + 0x02000)__ULFRACT_FBIT__ 32INT8_MIN (-INT8_MAX - 1)__FLT64_MIN_10_EXP__ (-307)__GNUC_EXECUTION_CHARSET_NAME "UTF-8"BIT10 (1<<10)__INT_FAST64_WIDTH__ 64__STDC_VERSION__ 199901LINT_LEAST64_MAX __INT_LEAST64_MAX__CGU_BASE_APB3_CLK_PD (1 << CGU_BASE_APB3_CLK_PD_SHIFT)CGU_BASE_SPI_CLK_AUTOBLOCK (1 << CGU_BASE_SPI_CLK_AUTOBLOCK_SHIFT)TIMER0_BASE (PERIPH_BASE_APB0 + 0x04000)SSP1_DMACR SSP_DMACR(SSP1)__SFRACT_EPSILON__ 0x1P-7HRCGU_PLLAUDIO_FRAC_PLLFRACT_CTRL(x) ((x) << CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT)CGU_IDIVB_CTRL_AUTOBLOCK (1 << CGU_IDIVB_CTRL_AUTOBLOCK_SHIFT)__INT32_C(c) c ## LUINT32_C(c) __UINT32_C(c)__ORDER_BIG_ENDIAN__ 4321SIZE_MAXCGU_PLL0USB_STAT_FR_SHIFT (1)__SQ_FBIT__ 31CGU_BASE_CGU_OUT1_CLK_PD_SHIFT (0)UINT32_CINT_LEAST32_MIN (-INT_LEAST32_MAX - 1)CGU_PLL1_STAT_LOCK_SHIFT (0)CGU_IDIVD_CTRL_IDIV_MASK (0xf << CGU_IDIVD_CTRL_IDIV_SHIFT)__UHQ_FBIT__ 16CGU_IDIVB_CTRL_IDIV_SHIFT (2)__FLT64_MIN_EXP__ (-1021)__PTRDIFF_WIDTH__ 32CGU_IDIVA_CTRL MMIO32(CGU_BASE + 0x048)CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT (0)__UINT_FAST8_MAX__ 0xffffffffUCGU_IDIVA_CTRL_AUTOBLOCK (1 << CGU_IDIVA_CTRL_AUTOBLOCK_SHIFT)UINT16_C(c) __UINT16_C(c)__LACCUM_IBIT__ 32CGU_PLL0AUDIO_CTRL_BYPASS (1 << CGU_PLL0AUDIO_CTRL_BYPASS_SHIFT)CGU_BASE_SDIO_CLK_CLK_SEL(x) ((x) << CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT)__INT_FAST16_WIDTH__ 32SSP1_ICR SSP_ICR(SSP1)INTMAX_C__VERSION__ "12.2.1 20221205"__VFP_FP__ 1CGU_PLL0AUDIO_CTRL_SEL_EXT (1 << CGU_PLL0AUDIO_CTRL_SEL_EXT_SHIFT)__LLFRACT_MIN__ (-0.5LLR-0.5LLR)INT_FAST8_MAXCGU_PLL0USB_MDIV_MDEC_SHIFT (0)CGU_BASE_APB3_CLK_CLK_SEL(x) ((x) << CGU_BASE_APB3_CLK_CLK_SEL_SHIFT)__UINT_FAST16_MAX__ 0xffffffffUCGU_PLL0AUDIO_CTRL_PD_SHIFT (0)CGU_IDIVC_CTRL_PD_SHIFT (0)__INTPTR_MAX__ 0x7fffffffINT64_C(c) __INT64_C(c)CGU_IDIVD_CTRL_CLK_SEL(x) ((x) << CGU_IDIVD_CTRL_CLK_SEL_SHIFT)CGU_BASE_CGU_OUT1_CLK MMIO32(CGU_BASE + 0x0C8)__GCC_IEC_559_COMPLEX 0CREG_BASE (0x40043000U)__UFRACT_MIN__ 0.0URCGU_PLL0AUDIO_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT)WCHAR_MAX __WCHAR_MAX__CGU_BASE_M4_CLK_PD (1 << CGU_BASE_M4_CLK_PD_SHIFT)__FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX__CGU_FREQ_MON_CLK_SEL_SHIFT (24)SSP_FRAM_MICROWIREINT8_C(c) __INT8_C(c)CGU_BASE_UART0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART0_CLK_CLK_SEL_SHIFT)__ACCUM_FBIT__ 15CGU_PLL0USB_CTRL_PD_SHIFT (0)SSP1_CPSR SSP_CPSR(SSP1)__UACCUM_IBIT__ 16long intUINT8_MAXCGU_BASE_SAFE_CLK_CLK_SEL_SHIFT (24)SIZE_MAX __SIZE_MAX__CGU_PLL0USB_STAT MMIO32(CGU_BASE + 0x01C)__INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17CGU_PLL1_CTRL_NSEL_MASK (0x3 << CGU_PLL1_CTRL_NSEL_SHIFT)__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1SSP_DATA_8BITS__SIZE_WIDTH__ 32CGU_BASE_UART2_CLK_AUTOBLOCK_SHIFT (11)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32__UINTMAX_C(c) c ## ULL__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed char__GCC_ATOMIC_BOOL_LOCK_FREE 2BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON____FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX____TA_FBIT__ 63__THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRCGU_BASE_UART3_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART3_CLK_CLK_SEL_SHIFT)CGU_BASE_UART3_CLK_CLK_SEL_SHIFT (24)short unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)CGU_BASE_PHY_RX_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT)BIT7 (1<<7)BIT17 (1<<17)__FLT32X_MIN_10_EXP__ (-307)__ELF__ 1UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_SHIFT (12)__DBL_IS_IEC_60559__ 2__UINT_FAST32_MAX__ 0xffffffffU__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4LCD_BASE (PERIPH_BASE_AHB + 0x08000)CGU_BASE_OUT_CLK MMIO32(CGU_BASE + 0x0AC)CGU_BASE_SSP0_CLK_PD (1 << CGU_BASE_SSP0_CLK_PD_SHIFT)__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32CGU_BASE_CGU_OUT0_CLK MMIO32(CGU_BASE + 0x0C4)GPDMA_BASE (PERIPH_BASE_AHB + 0x02000)CGU_BASE_UART0_CLK_PD (1 << CGU_BASE_UART0_CLK_PD_SHIFT)BIT18 (1<<18)__LONG_LONG_MAX__ 0x7fffffffffffffffLLSSP_DATA_5BITSBIT27 (1<<27)CGU_PLL0AUDIO_NP_DIV_PDEC_MASK (0x7f << CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT)__UTA_FBIT__ 64SDIO_BASE (PERIPH_BASE_AHB + 0x04000)CGU_BASE_PHY_TX_CLK_PD (1 << CGU_BASE_PHY_TX_CLK_PD_SHIFT)__FLT_DECIMAL_DIG__ 9CGU_FREQ_MON_CLK_SEL(x) ((x) << CGU_FREQ_MON_CLK_SEL_SHIFT)__thumb__ 1__INT_LEAST32_MAX__ 0x7fffffffLsigned charGIMA_BASE (PERIPH_BASE_APB2 + 0x07000)uint8_tINT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)CGU_BASE_LCD_CLK_AUTOBLOCK_SHIFT (11)INT32_C(c) __INT32_C(c)__GNUC_STDC_INLINE__ 1__SQ_IBIT__ 0CGU_BASE_VADC_CLK_CLK_SEL(x) ((x) << CGU_BASE_VADC_CLK_CLK_SEL_SHIFT)__LLACCUM_EPSILON__ 0x1P-31LLK__GNUC_PATCHLEVEL__ 1SSP1_CR0 SSP_CR0(SSP1)PTRDIFF_MIN__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)CGU_BASE_UART0_CLK_AUTOBLOCK (1 << CGU_BASE_UART0_CLK_AUTOBLOCK_SHIFT)UINTPTR_MAX __UINTPTR_MAX____ARM_ARCH_PROFILE 77SSP_DATA_11BITS__UHA_IBIT__ 8__FLT64_MAX_10_EXP__ 308CGU_PLL1_CTRL_PSEL_SHIFT (8)MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINSSP0_CR0 SSP_CR0(SSP0)CGU_BASE (0x40050000U)GPIO_PIN_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x07000)__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38CGU_BASE_UART0_CLK_PD_SHIFT (0)__FRACT_MAX__ 0X7FFFP-15RGNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -O2 -std=c99 -fno-common -ffunction-sections -fdata-sectionsINT_LEAST32_MAX __INT_LEAST32_MAX__CGU_IDIVE_CTRL_PD (1 << CGU_IDIVE_CTRL_PD_SHIFT)CGU_BASE_PHY_RX_CLK MMIO32(CGU_BASE + 0x078)__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5CGU_BASE_SPIFI_CLK_PD (1 << CGU_BASE_SPIFI_CLK_PD_SHIFT)CGU_PLL0AUDIO_CTRL_AUTOBLOCK_SHIFT (11)CGU_IDIVB_CTRL_PD_SHIFT (0)CGU_PLL0USB_MDIV_SELP_MASK (0x1f << CGU_PLL0USB_MDIV_SELP_SHIFT)CGU_PLL0AUDIO_STAT_FR (1 << CGU_PLL0AUDIO_STAT_FR_SHIFT)CGU_BASE_SSP0_CLK_PD_SHIFT (0)CGU_BASE_SAFE_CLK_CLK_SEL(x) ((x) << CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT)CGU_IDIVE_CTRL_AUTOBLOCK (1 << CGU_IDIVE_CTRL_AUTOBLOCK_SHIFT)__UINT16_MAX__ 0xffffCGU_PLL0USB_CTRL_AUTOBLOCK (1 << CGU_PLL0USB_CTRL_AUTOBLOCK_SHIFT)__TQ_FBIT__ 127CGU_BASE_UART0_CLK_AUTOBLOCK_SHIFT (11)CGU_PLL0USB_NP_DIV_PDEC_MASK (0x7f << CGU_PLL0USB_NP_DIV_PDEC_SHIFT)__LDBL_MAX_EXP__ 1024__USQ_FBIT__ 32INT_FAST16_MINCGU_BASE_UART2_CLK_AUTOBLOCK (1 << CGU_BASE_UART2_CLK_AUTOBLOCK_SHIFT)__thumb2__ 1__ULLACCUM_FBIT__ 32CGU_SRC_ENET_TX 0x03CGU_BASE_USB1_CLK_CLK_SEL(x) ((x) << CGU_BASE_USB1_CLK_CLK_SEL_SHIFT)CGU_BASE_SSP0_CLK MMIO32(CGU_BASE + 0x094)__STRICT_ANSI__ 1CGU_BASE_SPI_CLK_PD (1 << CGU_BASE_SPI_CLK_PD_SHIFT)UINT_LEAST8_MAXCGU_IDIVD_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVD_CTRL_CLK_SEL_SHIFT)SSP_RIS(port) MMIO32((port) + 0x018)UINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8CGU_BASE_OUT_CLK_PD (1 << CGU_BASE_OUT_CLK_PD_SHIFT)__GNUC_MINOR__ 2__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__CGU_IDIVE_CTRL_PD_SHIFT (0)CGU_FREQ_MON_FCNT_SHIFT (9)CGU_BASE_VADC_CLK MMIO32(CGU_BASE + 0x08C)__USA_IBIT__ 16CGU_PLL0USB_CTRL_AUTOBLOCK_SHIFT (11)__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1CGU_BASE_PHY_TX_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT)PTRDIFF_MIN (-PTRDIFF_MAX - 1)__UINT_FAST64_TYPE__ long long unsigned intCGU_PLL0AUDIO_STAT_FR_SHIFT (1)CGU_PLL1_CTRL_NSEL(x) ((x) << CGU_PLL1_CTRL_NSEL_SHIFT)__FLT_MIN__ 1.1754943508222875e-38F__HA_FBIT__ 7__FDPIC__CGU_IDIVA_CTRL_IDIV_SHIFT (2)CGU_BASE_SPI_CLK MMIO32(CGU_BASE + 0x074)CGU_BASE_UART2_CLK_CLK_SEL_SHIFT (24)__FLT32_IS_IEC_60559__ 2CGU_BASE_PHY_TX_CLK_PD_SHIFT (0)CGU_FREQ_MON_CLK_SEL_MASK (0x1f << CGU_FREQ_MON_CLK_SEL_SHIFT)CGU_PLL0AUDIO_CTRL_BYPASS_SHIFT (1)INT_FAST64_MINADC0_BASE (PERIPH_BASE_APB3 + 0x03000)__USFRACT_IBIT__ 0CGU_PLL0AUDIO_CTRL_DIRECTO_SHIFT (3)__USFRACT_MIN__ 0.0UHR__ARM_NEON__UINT8_MAX__ 0xffCGU_PLL0AUDIO_CTRL_AUTOBLOCK (1 << CGU_PLL0AUDIO_CTRL_AUTOBLOCK_SHIFT)CGU_BASE_APLL_CLK_PD (1 << CGU_BASE_APLL_CLK_PD_SHIFT)SSP_SR_TFE BIT0CGU_XTAL_OSC_CTRL_HF_SHIFT (2)CGU_PLL0AUDIO_MDIV_MDEC_SHIFT (0)INT16_C(c) __INT16_C(c)SSP_DATA_15BITSCGU_PLL1_CTRL_FBSEL_SHIFT (6)__DBL_HAS_DENORM__ 1CGU_PLL0USB_MDIV_SELP(x) ((x) << CGU_PLL0USB_MDIV_SELP_SHIFT)CGU_BASE_USB0_CLK_AUTOBLOCK_SHIFT (11)CGU_BASE_PERIPH_CLK_PD (1 << CGU_BASE_PERIPH_CLK_PD_SHIFT)CGU_SRC_IDIVB 0x0DCGU_BASE_SDIO_CLK_PD (1 << CGU_BASE_SDIO_CLK_PD_SHIFT)CGU_FREQ_MON_RCNT(x) ((x) << CGU_FREQ_MON_RCNT_SHIFT)__DA_FBIT__ 31CGU_BASE_OUT_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_OUT_CLK_CLK_SEL_SHIFT)__GXX_ABI_VERSION 1017__INT_LEAST16_MAX__ 0x7fffCGU_FREQ_MON_RCNT_SHIFT (0)__FLT_DENORM_MIN__ 1.4012984643248171e-45FSSP_DATA_7BITSCGU_XTAL_OSC_CTRL_BYPASS (1 << CGU_XTAL_OSC_CTRL_BYPASS_SHIFT)CGU_IDIVE_CTRL_CLK_SEL_SHIFT (24)INT_LEAST8_MAX __INT_LEAST8_MAX__CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT (12)DAC_BASE (PERIPH_BASE_APB3 + 0x01000)__UINT32_C(c) c ## ULCGU_BASE_PHY_RX_CLK_AUTOBLOCK (1 << CGU_BASE_PHY_RX_CLK_AUTOBLOCK_SHIFT)ssp_init__UACCUM_MIN__ 0.0UKSSP0_DMACR SSP_DMACR(SSP0)CGU_IDIVD_CTRL_AUTOBLOCK_SHIFT (11)__FLT_EPSILON__ 1.1920928955078125e-7FCGU_BASE_UART1_CLK_CLK_SEL_SHIFT (24)__PTRDIFF_TYPE__ int__ARM_ARCH_ISA_THUMBCGU_PLL0USB_CTRL_FRM_SHIFT (6)CGU_PLL0AUDIO_CTRL_CLKEN_SHIFT (4)__ARM_FEATURE_MATMUL_INT8CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT (24)CGU_PLL1_CTRL_DIRECT_SHIFT (7)__GCC_ATOMIC_SHORT_LOCK_FREE 2CGU_BASE_UART3_CLK_AUTOBLOCK_SHIFT (11)CGU_IDIVC_CTRL_PD (1 << CGU_IDIVC_CTRL_PD_SHIFT)CGU_BASE_PHY_TX_CLK_AUTOBLOCK (1 << CGU_BASE_PHY_TX_CLK_AUTOBLOCK_SHIFT)__USACCUM_FBIT__ 8CGU_SRC_PLL1 0x09__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1CGU_BASE_CGU_OUT0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT)CGU_PLL0USB_MDIV_MDEC_MASK (0x1ffff << CGU_PLL0USB_MDIV_MDEC_SHIFT)CGU_BASE_SPI_CLK_CLK_SEL_SHIFT (24)__LACCUM_FBIT__ 31CGU_BASE_APB1_CLK_PD_SHIFT (0)EMC_BASE (PERIPH_BASE_AHB + 0x05000)__FLT32_HAS_QUIET_NAN__ 1__LDBL_HAS_INFINITY__ 1CGU_SRC_GP_CLKIN 0x04__SACCUM_FBIT__ 7UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))CCU1_BASE (0x40051000U)__FLT32X_MAX_10_EXP__ 308CGU_BASE_PERIPH_CLK_CLK_SEL(x) ((x) << CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT)CGU_BASE_OUT_CLK_CLK_SEL(x) ((x) << CGU_BASE_OUT_CLK_CLK_SEL_SHIFT)__ARM_ARCH_EXT_IDIV__ 1ssp_portbool _BoolUINTMAX_MAX __UINTMAX_MAX__CGU_BASE_OUT_CLK_PD_SHIFT (0)__SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffCGU_BASE_PERIPH_CLK_AUTOBLOCK_SHIFT (11)CGU_XTAL_OSC_CTRL MMIO32(CGU_BASE + 0x018)CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT (0)BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)EVENTROUTER_BASE (0x40044000U)INT16_MAX __INT16_MAX____FP_FAST_FMAF 1__PRAGMA_REDEFINE_EXTNAME 1__FLT32X_IS_IEC_60559__ 2PERIPH_BASE_APB3 (0x400E0000U)SSP_CPSR(port) MMIO32((port) + 0x010)LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))UINT32_MAXCGU_PLL1_STAT MMIO32(CGU_BASE + 0x040)CGU_BASE_PHY_RX_CLK_PD_SHIFT (0)__INT_LEAST16_WIDTH__ 16I2S0_BASE (PERIPH_BASE_APB1 + 0x02000)CGU_PLL0USB_CTRL_DIRECTI_SHIFT (2)__DEC_EVAL_METHOD__ 2SCT_BASE (PERIPH_BASE_AHB + 0x00000)__ARM_FEATURE_FP16_FMLCGU_PLL0USB_MDIV_MDEC(x) ((x) << CGU_PLL0USB_MDIV_MDEC_SHIFT)SSP_DATA_10BITS__USFRACT_EPSILON__ 0x1P-8UHRssp_transferCGU_IDIVD_CTRL_IDIV(x) ((x) << CGU_IDIVD_CTRL_IDIV_SHIFT)CGU_IDIVD_CTRL MMIO32(CGU_BASE + 0x054)CGU_BASE_USB0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_USB0_CLK_CLK_SEL_SHIFT)CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT (24)SCU_BASE (PERIPH_BASE_APB0 + 0x06000)__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLKCGU_BASE_SSP0_CLK_AUTOBLOCK (1 << CGU_BASE_SSP0_CLK_AUTOBLOCK_SHIFT)__FRACT_FBIT__ 15__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX____UINT32_MAX__ 0xffffffffULUSART0_BASE (PERIPH_BASE_APB0 + 0x01000)CGU_BASE_M4_CLK_PD_SHIFT (0)__INT_LEAST8_MAX__ 0x7f__GCC_ATOMIC_POINTER_LOCK_FREE 2__ARM_FEATURE_QBIT 1__ARM_FEATURE_CLZ 1__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXCGU_SRC_IRC 0x01__ARM_PCS_VFP 1__UINT64_TYPE__ long long unsigned intCGU_BASE_SAFE_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT)__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024CGU_IDIVC_CTRL_AUTOBLOCK_SHIFT (11)__UINT_LEAST32_MAX__ 0xffffffffUL__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)CGU_BASE_APLL_CLK_AUTOBLOCK (1 << CGU_BASE_APLL_CLK_AUTOBLOCK_SHIFT)__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1__ACCUM_MAX__ 0X7FFFFFFFP-15K__INT8_MAX__ 0x7fCGU_OUTCLK_21_CTRL MMIO32(CGU_BASE + 0x0B0)BIT14 (1<<14)__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16USB1_BASE (PERIPH_BASE_AHB + 0x07000)BIT20 (1<<20)__ARM_FEATURE_MVE__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intCGU_PLL0USB_CTRL_CLKEN (1 << CGU_PLL0USB_CTRL_CLKEN_SHIFT)SSP_SLAVEUINT_LEAST16_MAX __UINT_LEAST16_MAX__SSP_SR_BSY BIT4INT_FAST32_MIN__FLT_EVAL_METHOD_TS_18661_3__ 0CGU_IDIVA_CTRL_IDIV_MASK (0x3 << CGU_IDIVA_CTRL_IDIV_SHIFT)__SCHAR_WIDTH__ 8CGU_BASE_PHY_RX_CLK_CLK_SEL(x) ((x) << CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT)cpol_cpha_formatUINT_FAST16_MAXCGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_SHIFT (11)__UINT_FAST8_TYPE__ unsigned intSSP1_NUM__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RBIT24 (1<<24)CGU_PLL1_CTRL_MSEL_MASK (0xff << CGU_PLL1_CTRL_MSEL_SHIFT)CGU_IDIVE_CTRL_IDIV_MASK (0xff << CGU_IDIVE_CTRL_IDIV_SHIFT)__INT32_MAX__ 0x7fffffffLCGU_PLL0AUDIO_STAT_LOCK (1 << CGU_PLL0AUDIO_STAT_LOCK_SHIFT)frame_formatUINTMAX_MAXBIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_BF16_VECTOR_ARITHMETIC__FLT32_MANT_DIG__ 24CGU_IDIVA_CTRL_PD_SHIFT (0)INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32SSP_DATA_16BITS__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned int__USFRACT_FBIT__ 8__LDBL_EPSILON__ 2.2204460492503131e-16LCGU_IDIVD_CTRL_PD_SHIFT (0)BIT28 (1<<28)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2INTMAX_C(c) __INTMAX_C(c)__DBL_MAX_EXP__ 1024SSP_SLAVE_OUT_ENABLE__ATOMIC_RELEASE 3data_sizeserial_clock_rate__FLT_MANT_DIG__ 24clockCGU_BASE_APLL_CLK_CLK_SEL_SHIFT (24)__UDQ_IBIT__ 0CCU2_BASE (0x40052000U)__OPTIMIZE__ 1__GCC_ATOMIC_INT_LOCK_FREE 2__UACCUM_MAX__ 0XFFFFFFFFP-16UKCGU_BASE_APB3_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_APB3_CLK_CLK_SEL_SHIFT)CGU_IDIVD_CTRL_AUTOBLOCK (1 << CGU_IDIVD_CTRL_AUTOBLOCK_SHIFT)__FLT64_NORM_MAX__ 1.7976931348623157e+308F64PERIPH_BASE_APB1 (0x400A0000U)SSP_DATA_6BITSUINTPTR_MAX__LDBL_DENORM_MIN__ 4.9406564584124654e-324LTIMER3_BASE (PERIPH_BASE_APB2 + 0x04000)__INT64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_SAT 1__ULLFRACT_IBIT__ 0SSP_DMACR(port) MMIO32((port) + 0x024)SPI_PORT_BASE (0x40100000U)CGU_BASE_LCD_CLK_PD (1 << CGU_BASE_LCD_CLK_PD_SHIFT)MMIO16(addr) (*(volatile uint16_t *)(addr))CGU_BASE_APB3_CLK_AUTOBLOCK_SHIFT (11)SSP_DMACR_TXDMAE 0x2LPC43XX 1__GNUC__ 12CGU_BASE_APLL_CLK_PD_SHIFT (0)CGU_BASE_UART1_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART1_CLK_CLK_SEL_SHIFT)WCHAR_MAXCGU_IDIVB_CTRL_AUTOBLOCK_SHIFT (11)__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16CGU_PLL1_CTRL_DIRECT (1 << CGU_PLL1_CTRL_DIRECT_SHIFT)__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0UCGU_PLL0USB_CTRL_PD (1 << CGU_PLL0USB_CTRL_PD_SHIFT)__UQQ_IBIT__ 0CGU_SRC_XTAL 0x06__GCC_ATOMIC_LONG_LOCK_FREE 2__ULACCUM_MIN__ 0.0ULKCGU_PLL0USB_NP_DIV_PDEC_SHIFT (0)__LDBL_MAX__ 1.7976931348623157e+308L__ARM_ARCH 7/build/libopencm3/lib/lpc43xx/m4__FLT_RADIX__ 2BIT3 (1<<3)long long intCGU_SRC_IDIVE 0x10__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAXSGPIO_PORT_BASE (0x40101000U)__LDBL_HAS_QUIET_NAN__ 1CGU_PLL0USB_MDIV_SELI_MASK (0x3f << CGU_PLL0USB_MDIV_SELI_SHIFT)PERIPH_BASE_APB0 (0x40080000U)__LONG_LONG_WIDTH__ 64BIT6 (1<<6)CGU_FREQ_MON_MEAS_SHIFT (23)CGU_PLL0USB_CTRL_DIRECTO (1 << CGU_PLL0USB_CTRL_DIRECTO_SHIFT)CGU_BASE_APB1_CLK MMIO32(CGU_BASE + 0x080)CGU_IDIVE_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVE_CTRL_CLK_SEL_SHIFT)__UINT_FAST64_MAX__ 0xffffffffffffffffULLCGU_BASE_M4_CLK_AUTOBLOCK_SHIFT (11)__ARM_FP__HA_IBIT__ 8INT_LEAST32_MAX__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1CGU_PLL0AUDIO_CTRL MMIO32(CGU_BASE + 0x030)BIT9 (1<<9)__FLT32X_MIN__ 2.2250738585072014e-308F32xINTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024CGU_BASE_SAFE_CLK_PD_SHIFT (0)UINT16_MAXCGU_PLL0USB_NP_DIV_PDEC(x) ((x) << CGU_PLL0USB_NP_DIV_PDEC_SHIFT)__FLT64_MIN__ 2.2250738585072014e-308F64__INTMAX_C(c) c ## LLCGU_PLL0USB_CTRL_BYPASS_SHIFT (1)CGU_BASE_USB1_CLK_AUTOBLOCK_SHIFT (11)CGU_BASE_M4_CLK MMIO32(CGU_BASE + 0x06C)__ARM_ARCH_PROFILE__INT64_TYPE__ long long int__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4CGU_BASE_USB1_CLK MMIO32(CGU_BASE + 0x068)CGU_PLL1_CTRL_CLK_SEL(x) ((x) << CGU_PLL1_CTRL_CLK_SEL_SHIFT)__UFRACT_MAX__ 0XFFFFP-16URCGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT (24)CGU_BASE_UART0_CLK_CLK_SEL_SHIFT (24)INT64_MAXCGU_BASE_USB1_CLK_PD_SHIFT (0)CGU_PLL0AUDIO_STAT_LOCK_SHIFT (0)INT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0SSP1_BASE (PERIPH_BASE_APB2 + 0x05000)SPIFI_BASE (PERIPH_BASE_AHB + 0x03000)__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__SSP_MODE_NORMAL__UFRACT_FBIT__ 16__UDQ_FBIT__ 64INT16_MIN (-INT16_MAX - 1)CGU_XTAL_OSC_CTRL_BYPASS_SHIFT (1)CGU_FREQ_MON MMIO32(CGU_BASE + 0x014)__LDBL_MAX_10_EXP__ 308CGU_BASE_UART2_CLK_PD_SHIFT (0)__INT_FAST32_TYPE__ intCGU_BASE_UART3_CLK_PD (1 << CGU_BASE_UART3_CLK_PD_SHIFT)unsigned intCGU_BASE_SPI_CLK_PD_SHIFT (0)CGU_IDIVE_CTRL_AUTOBLOCK_SHIFT (11)__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1SSP1 SSP1_BASECGU_BASE_APB1_CLK_AUTOBLOCK_SHIFT (11)CGU_IDIVE_CTRL_CLK_SEL(x) ((x) << CGU_IDIVE_CTRL_CLK_SEL_SHIFT)__USACCUM_IBIT__ 8__ARM_ARCH_7EM__ 1__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UKCGU_BASE_OUT_CLK_CLK_SEL_SHIFT (24)CGU_PLL0AUDIO_NP_DIV_PDEC(x) ((x) << CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT)__FLT_EVAL_METHOD__ 0CGU_OUTCLK_24_CTRL MMIO32(CGU_BASE + 0x0BC)GPIO_PORT_BASE (0x400F4000U)__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32SSP_MIS(port) MMIO32((port) + 0x01C)CGU_BASE_LCD_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_LCD_CLK_CLK_SEL_SHIFT)ssp_cpol_cpha_t__ARM_FEATURE_LDREXCGU_BASE_SPI_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SPI_CLK_CLK_SEL_SHIFT)__UQQ_FBIT__ 8CGU_PLL1_CTRL_AUTOBLOCK_SHIFT (11)CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK (1 << CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_SHIFT)__WINT_TYPE__ unsigned intCGU_PLL0USB_CTRL_FRM (1 << CGU_PLL0USB_CTRL_FRM_SHIFT)__ARM_FP16_ARGS__GCC_IEC_559 0SSP0_NUMINT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX____LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4__STDC__ 1CGU_BASE_USB0_CLK_PD_SHIFT (0)CGU_BASE_M4_CLK_CLK_SEL(x) ((x) << CGU_BASE_M4_CLK_CLK_SEL_SHIFT)__ARM_FEATURE_IDIV 1SSP0_RIS SSP_RIS(SSP0)__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN____UINT8_TYPE__ unsigned charCGU_BASE_APB1_CLK_CLK_SEL(x) ((x) << CGU_BASE_APB1_CLK_CLK_SEL_SHIFT)CGU_BASE_SDIO_CLK_AUTOBLOCK_SHIFT (11)SSP_CPOL_1_CPHA_0SSP_CPOL_1_CPHA_1CGU_PLL0USB_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT)UINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"CGU_BASE_SAFE_CLK_PD (1 << CGU_BASE_SAFE_CLK_PD_SHIFT)INT8_MINtrue 1CGU_PLL1_CTRL_PD (1 << CGU_PLL1_CTRL_PD_SHIFT)__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)CGU_BASE_VADC_CLK_AUTOBLOCK_SHIFT (11)__FLT32X_MIN_EXP__ (-1021)__FLT32X_EPSILON__ 2.2204460492503131e-16F32xINT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1__GCC_ATOMIC_CHAR_LOCK_FREE 2SSP_SR(port) MMIO32((port) + 0x00C)__LFRACT_EPSILON__ 0x1P-31LRCGU_PLLAUDIO_FRAC MMIO32(CGU_BASE + 0x03C)CGU_BASE_UART1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART1_CLK_CLK_SEL_SHIFT)CGU_OUTCLK_22_CTRL MMIO32(CGU_BASE + 0x0B4)__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX____FLT32X_NORM_MAX__ 1.7976931348623157e+308F32x__arm__ 1INT_FAST64_MAXCGU_BASE_SSP0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT)CGU_BASE_APB3_CLK_PD_SHIFT (0)__FLT32_MIN_10_EXP__ (-37)CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT (24)MMIO64(addr) (*(volatile uint64_t *)(addr))CGU_PLL1_CTRL_MSEL(x) ((x) << CGU_PLL1_CTRL_MSEL_SHIFT)CGU_PLL0USB_MDIV_SELI_SHIFT (22)INT8_MAX __INT8_MAX____ARM_FP16_FORMAT_ALTERNATIVE__LDBL_NORM_MAX__ 1.7976931348623157e+308LUSART3_BASE (PERIPH_BASE_APB2 + 0x02000)CGU_BASE_USB0_CLK_CLK_SEL_SHIFT (24)__BIGGEST_ALIGNMENT__ 8CGU_IDIVB_CTRL_PD (1 << CGU_IDIVB_CTRL_PD_SHIFT)CGU_PLL1_CTRL_BYPASS (1 << CGU_PLL1_CTRL_BYPASS_SHIFT)CGU_BASE_UART2_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART2_CLK_CLK_SEL_SHIFT)SSP_SR_TNF BIT1__TA_IBIT__ 64CGU_PLL0USB_NP_DIV_NDEC_SHIFT (12)__FLT32_MIN__ 1.1754943508222875e-38F32__ARM_EABI__ 1CGU_BASE_USB1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_USB1_CLK_CLK_SEL_SHIFT)PERIPH_BASE_AHB (0x40000000U)CGU_IDIVC_CTRL_IDIV_SHIFT (2)CGU_XTAL_OSC_CTRL_HF (1 << CGU_XTAL_OSC_CTRL_HF_SHIFT)SSP_SR_RFF BIT3__ARM_FEATURE_QRDMXCGU_IDIVD_CTRL_IDIV_SHIFT (2)CGU_PLL0USB_MDIV_SELR_MASK (0xf << CGU_PLL0USB_MDIV_SELR_SHIFT)CGU_BASE_M4_CLK_CLK_SEL_SHIFT (24)__ARM_ARCH_ISA_THUMB 2WCHAR_MIN __WCHAR_MIN____WINT_WIDTH__ 32SSP0 SSP0_BASESIG_ATOMIC_MAX __SIG_ATOMIC_MAX__CGU_BASE_USB0_CLK_PD (1 << CGU_BASE_USB0_CLK_PD_SHIFT)BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN____SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)CGU_BASE_CGU_OUT1_CLK_CLK_SEL(x) ((x) << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT)__DBL_MIN_EXP__ (-1021)__LDBL_HAS_DENORM__ 1INT_FAST32_MIN (-INT_FAST32_MAX - 1)GPIO_GROUP1_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x09000)__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2CGU_PLL0USB_NP_DIV_NDEC_MASK (0x3ff << CGU_PLL0USB_NP_DIV_NDEC_SHIFT)CGU_PLL1_STAT_LOCK (1 << CGU_PLL1_STAT_LOCK_SHIFT)__FLT32_DIG__ 6INT_LEAST16_MAXCGU_BASE_M4_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_M4_CLK_CLK_SEL_SHIFT)CGU_PLL0USB_STAT_LOCK (1 << CGU_PLL0USB_STAT_LOCK_SHIFT)CGU_IDIVD_CTRL_PD (1 << CGU_IDIVD_CTRL_PD_SHIFT)BIT15 (1<<15)BACKUP_REG_BASE (0x40041000U)CGU_BASE_UART3_CLK_AUTOBLOCK (1 << CGU_BASE_UART3_CLK_AUTOBLOCK_SHIFT)CGU_IDIVC_CTRL_AUTOBLOCK (1 << CGU_IDIVC_CTRL_AUTOBLOCK_SHIFT)BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1GPIO_GROUP0_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x08000)__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)CGU_PLL0AUDIO_CTRL_DIRECTO (1 << CGU_PLL0AUDIO_CTRL_DIRECTO_SHIFT)__ACCUM_MIN__ (-0X1P15K-0X1P15K)CGU_BASE_SDIO_CLK MMIO32(CGU_BASE + 0x090)__ARM_FEATURE_CRYPTOCGU_IDIVB_CTRL_CLK_SEL(x) ((x) << CGU_IDIVB_CTRL_CLK_SEL_SHIFT)__INT_LEAST32_TYPE__ long intCGU_BASE_LCD_CLK_CLK_SEL(x) ((x) << CGU_BASE_LCD_CLK_CLK_SEL_SHIFT)CGU_PLL1_CTRL_PSEL_MASK (0x3 << CGU_PLL1_CTRL_PSEL_SHIFT)CGU_PLL0AUDIO_MDIV_MDEC_MASK (0x1ffff << CGU_PLL0AUDIO_MDIV_MDEC_SHIFT)SSP_ICR(port) MMIO32((port) + 0x020)CGU_BASE_APB1_CLK_CLK_SEL_SHIFT (24)BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULLCGU_BASE_CGU_OUT0_CLK_PD (1 << CGU_BASE_CGU_OUT0_CLK_PD_SHIFT)__FRACT_IBIT__ 0I2C1_BASE (PERIPH_BASE_APB3 + 0x00000)UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2CGU_SRC_IDIVA 0x0CBIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234__FLT_NORM_MAX__ 3.4028234663852886e+38Flong long unsigned int__FLT_MIN_10_EXP__ (-37)BIT31 (1<<31)CGU_BASE_USB0_CLK MMIO32(CGU_BASE + 0x060)__ULACCUM_IBIT__ 32__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__ULLACCUM_EPSILON__ 0x1P-32ULLK__APCS_32__ 1__DQ_FBIT__ 63CGU_IDIVC_CTRL_IDIV(x) ((x) << CGU_IDIVC_CTRL_IDIV_SHIFT)INT_LEAST64_MAX__SACCUM_IBIT__ 8CGU_BASE_SSP1_CLK_AUTOBLOCK (1 << CGU_BASE_SSP1_CLK_AUTOBLOCK_SHIFT)__UHQ_IBIT__ 0CGU_BASE_SPI_CLK_CLK_SEL(x) ((x) << CGU_BASE_SPI_CLK_CLK_SEL_SHIFT)SSP0_SR SSP_SR(SSP0)SSP1_MIS SSP_MIS(SSP1)CGU_BASE_UART0_CLK MMIO32(CGU_BASE + 0x09C)BIT29 (1<<29)__INT_FAST16_TYPE__ intINT64_C__ULFRACT_MAX__ 0XFFFFFFFFP-32ULR__UINT_LEAST16_TYPE__ short unsigned intCGU_BASE_SPIFI_CLK_AUTOBLOCK_SHIFT (11)__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned int__FLT32X_DIG__ 15CGU_BASE_SSP0_CLK_CLK_SEL(x) ((x) << CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT)SSP0_MIS SSP_MIS(SSP0)__UTQ_FBIT__ 128CGU_PLL0AUDIO_CTRL_MOD_PD_SHIFT (14)__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffffSSP0_ICR SSP_ICR(SSP0)CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT (24)CGU_BASE_UART3_CLK_PD_SHIFT (0)CGU_BASE_UART2_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART2_CLK_CLK_SEL_SHIFT)PTRDIFF_MAX __PTRDIFF_MAX____SIZEOF_SHORT__ 2CGU_BASE_VADC_CLK_PD (1 << CGU_BASE_VADC_CLK_PD_SHIFT)CGU_IDIVA_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVA_CTRL_CLK_SEL_SHIFT)CGU_BASE_SAFE_CLK MMIO32(CGU_BASE + 0x05C)CGU_PLL0USB_CTRL_DIRECTI (1 << CGU_PLL0USB_CTRL_DIRECTI_SHIFT)__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKCGU_BASE_LCD_CLK MMIO32(CGU_BASE + 0x088)CGU_BASE_M4_CLK_AUTOBLOCK (1 << CGU_BASE_M4_CLK_AUTOBLOCK_SHIFT)CGU_PLL1_CTRL_BYPASS_SHIFT (1)SSP0_DR SSP_DR(SSP0)CGU_IDIVE_CTRL_IDIV_SHIFT (2)UINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRssp_num_t__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intCGU_IDIVA_CTRL_IDIV(x) ((x) << CGU_IDIVA_CTRL_IDIV_SHIFT)CGU_PLL0USB_MDIV_SELR_SHIFT (28)SSP0_BASE (PERIPH_BASE_APB0 + 0x03000)CGU_IDIVE_CTRL MMIO32(CGU_BASE + 0x058)QEI_BASE (PERIPH_BASE_APB2 + 0x06000)WCHAR_MINCGU_SRC_ENET_RX 0x02BEGIN_DECLS CGU_FREQ_MON_FCNT_MASK (0x3fff << CGU_FREQ_MON_FCNT_SHIFT)SSP_SR_RNE BIT2CGU_PLL1_CTRL_CLK_SEL_SHIFT (24)CGU_BASE_PHY_RX_CLK_PD (1 << CGU_BASE_PHY_RX_CLK_PD_SHIFT)CGU_BASE_UART1_CLK_PD (1 << CGU_BASE_UART1_CLK_PD_SHIFT)CGU_BASE_UART3_CLK MMIO32(CGU_BASE + 0x0A8)__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__FLT32X_MAX__ 1.7976931348623157e+308F32xclk_prescaleCGU_PLL0USB_STAT_LOCK_SHIFT (0)SSP_DATA_14BITSCGU_PLL0USB_STAT_FR (1 << CGU_PLL0USB_STAT_FR_SHIFT)INT16_MININTPTR_MIN__FLT_IS_IEC_60559__ 2__THUMBEL__ 1CGU_BASE_USB0_CLK_AUTOBLOCK (1 << CGU_BASE_USB0_CLK_AUTOBLOCK_SHIFT)__ARM_FEATURE_DSP 1CGU_SRC_PLL0AUDIO 0x08CGU_BASE_SPIFI_CLK MMIO32(CGU_BASE + 0x070)__QQ_IBIT__ 0CGU_IDIVC_CTRL MMIO32(CGU_BASE + 0x050)CGU_PLL0AUDIO_NP_DIV MMIO32(CGU_BASE + 0x038)CGU_BASE_VADC_CLK_CLK_SEL_SHIFT (24)CGU_SRC_PLL0USB 0x07__LLACCUM_FBIT__ 31INT32_MAXSSP0_IMSC SSP_IMSC(SSP0)__UINTMAX_TYPE__ long long unsigned intCGU_PLL1_CTRL_AUTOBLOCK (1 << CGU_PLL1_CTRL_AUTOBLOCK_SHIFT)CGU_BASE_PHY_TX_CLK_AUTOBLOCK_SHIFT (11)__USQ_IBIT__ 0__UINT_LEAST32_TYPE__ long unsigned int__ARM_FEATURE_NUMERIC_MAXMIN__INTMAX_TYPE__ long long intSSP_DATA_4BITSSSP1_CR1 SSP_CR1(SSP1)CGU_IDIVC_CTRL_CLK_SEL(x) ((x) << CGU_IDIVC_CTRL_CLK_SEL_SHIFT)UINT_FAST8_MAXCGU_BASE_SPI_CLK_AUTOBLOCK_SHIFT (11)INT_LEAST8_MININTMAX_MAXCGU_BASE_CGU_OUT0_CLK_CLK_SEL(x) ((x) << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT)TIMER2_BASE (PERIPH_BASE_APB2 + 0x03000)CGU_PLL0AUDIO_CTRL_DIRECTI_SHIFT (2)SSP_DMACR_RXDMAE 0x1CGU_XTAL_OSC_CTRL_ENABLE_SHIFT (0)__ARM_FEATURE_FP16_SCALAR_ARITHMETIC__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1CGU_PLL1_CTRL_MSEL_SHIFT (16)SSP0_CR1 SSP_CR1(SSP0)__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CCGU_BASE_CGU_OUT1_CLK_PD (1 << CGU_BASE_CGU_OUT1_CLK_PD_SHIFT)CGU_BASE_SSP0_CLK_AUTOBLOCK_SHIFT (11)CGU_PLL0AUDIO_NP_DIV_NDEC_MASK (0x3ff << CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT)INT64_MIN__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intCGU_BASE_APB1_CLK_AUTOBLOCK (1 << CGU_BASE_APB1_CLK_AUTOBLOCK_SHIFT)CGU_IDIVC_CTRL_IDIV_MASK (0xf << CGU_IDIVC_CTRL_IDIV_SHIFT)UINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULR__SIZEOF_SIZE_T__ 4PMC_BASE (0x40042000U)uint16_t__INT64_C(c) c ## LLCGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_SHIFT (11)__LDBL_MIN_10_EXP__ (-307)CGU_BASE_SSP1_CLK_AUTOBLOCK_SHIFT (11)CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ (1 << CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_SHIFT)UART1_BASE (PERIPH_BASE_APB0 + 0x02000)__LDBL_MIN__ 2.2250738585072014e-308LCGU_PLL0AUDIO_NP_DIV_NDEC(x) ((x) << CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT)__ARM_FEATURE_CDE__ACCUM_IBIT__ 16CGU_BASE_SPIFI_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT)CGU_PLL1_CTRL_PD_SHIFT (0)CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT (24)CGU_BASE_USB1_CLK_CLK_SEL_SHIFT (24)CGU_BASE_APB3_CLK_CLK_SEL_SHIFT (24)CGU_PLL0AUDIO_MDIV MMIO32(CGU_BASE + 0x034)CGU_BASE_OUT_CLK_AUTOBLOCK_SHIFT (11)CGU_LPC43XX_CGU_H short intCGU_BASE_APLL_CLK_AUTOBLOCK_SHIFT (11)CGU_BASE_APB1_CLK_PD (1 << CGU_BASE_APB1_CLK_PD_SHIFT)CGU_BASE_USB1_CLK_AUTOBLOCK (1 << CGU_BASE_USB1_CLK_AUTOBLOCK_SHIFT)__UINT16_C(c) cCGU_OUTCLK_23_CTRL MMIO32(CGU_BASE + 0x0B8)CGU_PLL0AUDIO_CTRL_CLK_SEL(x) ((x) << CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT)__UDA_IBIT__ 32modeUINT_LEAST32_MAXssp_disableBIT2 (1<<2)__ATOMIC_RELAXED 0__ARM_FEATURE_COPROCCGU_BASE_VADC_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_VADC_CLK_CLK_SEL_SHIFT)__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53SSP_DR(port) MMIO32((port) + 0x008)LPC43XX_M4 1CGU_PLL0AUDIO_CTRL_DIRECTI (1 << CGU_PLL0AUDIO_CTRL_DIRECTI_SHIFT)BIT5 (1<<5)CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT (24)BIT1 (1<<1)INT8_CSSP_MASTER__USES_INITFINI__ 1I2S1_BASE (PERIPH_BASE_APB1 + 0x03000)ssp_slave_option_tSSP_FRAME_SPI__DBL_DECIMAL_DIG__ 17CGU_BASE_SSP1_CLK_PD_SHIFT (0)BIT8 (1<<8)CGU_BASE_SSP1_CLK_CLK_SEL(x) ((x) << CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT)CGU_BASE_SSP1_CLK MMIO32(CGU_BASE + 0x098)ssp_master_slave_tCGU_BASE_LCD_CLK_AUTOBLOCK (1 << CGU_BASE_LCD_CLK_AUTOBLOCK_SHIFT)SSP_CR1(port) MMIO32((port) + 0x004)CGU_BASE_CGU_OUT1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT)__INT16_MAX__ 0x7fffssp_mode_tCGU_BASE_PERIPH_CLK MMIO32(CGU_BASE + 0x064)CGU_BASE_SAFE_CLK_AUTOBLOCK_SHIFT (11)CGU_IDIVA_CTRL_CLK_SEL_SHIFT (24)CGU_XTAL_OSC_CTRL_ENABLE (1 << CGU_XTAL_OSC_CTRL_ENABLE_SHIFT)__INT_WIDTH__ 32__ARM_FEATURE_SIMD32 1CGU_IDIVA_CTRL_AUTOBLOCK_SHIFT (11)CGU_BASE_UART1_CLK MMIO32(CGU_BASE + 0x0A0)__QQ_FBIT__ 7RITIMER_BASE (PERIPH_BASE_APB2 + 0x00000)CGU_SRC_IDIVD 0x0F__SIG_ATOMIC_WIDTH__ 32CGU_IDIVC_CTRL_CLK_SEL_SHIFT (24)__FLT64_EPSILON__ 2.2204460492503131e-16F64CGU_BASE_UART1_CLK_PD_SHIFT (0)INT16_CCGU_BASE_UART1_CLK_AUTOBLOCK_SHIFT (11)__UTA_IBIT__ 64__ULLACCUM_IBIT__ 32RGU_BASE (0x40053000U)__ULLFRACT_EPSILON__ 0x1P-64ULLRfalse 0__SIZEOF_WINT_T__ 4CGU_BASE_LCD_CLK_PD_SHIFT (0)__ARM_FEATURE_UNALIGNED 1__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17CGU_PLL0AUDIO_CTRL_MOD_PD (1 << CGU_PLL0AUDIO_CTRL_MOD_PD_SHIFT)__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1CGU_PLL1_CTRL_PSEL(x) ((x) << CGU_PLL1_CTRL_PSEL_SHIFT)__FLT32X_HAS_DENORM__ 1CGU_IDIVB_CTRL_IDIV_MASK (0xf << CGU_IDIVB_CTRL_IDIV_SHIFT)__ULLACCUM_MIN__ 0.0ULLKSSP1_RIS SSP_RIS(SSP1)__INT_FAST32_WIDTH__ 32CGU_IDIVE_CTRL_IDIV(x) ((x) << CGU_IDIVE_CTRL_IDIV_SHIFT)CGU_IDIVA_CTRL_CLK_SEL(x) ((x) << CGU_IDIVA_CTRL_CLK_SEL_SHIFT)CGU_PLL0AUDIO_STAT MMIO32(CGU_BASE + 0x02C)CGU_PLL0USB_MDIV_SELI(x) ((x) << CGU_PLL0USB_MDIV_SELI_SHIFT)CGU_IDIVB_CTRL MMIO32(CGU_BASE + 0x04C)__ARM_ASM_SYNTAX_UNIFIED__ 1CGU_PLL0AUDIO_MDIV_MDEC(x) ((x) << CGU_PLL0AUDIO_MDIV_MDEC_SHIFT)__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODSSP_ENABLE BIT1RTC_BASE (0x40046000U)CGU_PLL1_CTRL_NSEL_SHIFT (12)CGU_PLL0USB_CTRL_CLKEN_SHIFT (4)CGU_PLL0AUDIO_CTRL_CLKEN (1 << CGU_PLL0AUDIO_CTRL_CLKEN_SHIFT)__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H CGU_FREQ_MON_MEAS (1 << CGU_FREQ_MON_MEAS_SHIFT)AES_BASE (0x400F1000U)INT_LEAST64_MIN__GCC_CONSTRUCTIVE_SIZE 64CGU_BASE_VADC_CLK_AUTOBLOCK (1 << CGU_BASE_VADC_CLK_AUTOBLOCK_SHIFT)__LLFRACT_IBIT__ 0SSP_CR0(port) MMIO32((port) + 0x000)uint32_tBIT12 (1<<12)LPC43XX_SSP_H SSP0_CPSR SSP_CPSR(SSP0)__SACCUM_EPSILON__ 0x1P-7HK__GCC_ASM_FLAG_OUTPUTS__ 1CGU_BASE_APLL_CLK_CLK_SEL(x) ((x) << CGU_BASE_APLL_CLK_CLK_SEL_SHIFT)__ARM_FP 4__UINT_FAST16_TYPE__ unsigned intCGU_BASE_SAFE_CLK_AUTOBLOCK (1 << CGU_BASE_SAFE_CLK_AUTOBLOCK_SHIFT)SSP_SLAVE_OUT_DISABLECGU_BASE_PERIPH_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT)__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULK__LDBL_DIG__ 15CGU_BASE_SSP1_CLK_PD (1 << CGU_BASE_SSP1_CLK_PD_SHIFT)UINT64_CSSP_DATA_13BITSSIG_ATOMIC_MAXBIT16 (1<<16)ssp_num__WINT_MIN__ 0UINT_LEAST16_MIN__FLT64_DIG__ 15__WINT_MAX__ 0xffffffffUBIT22 (1<<22)__INT_LEAST8_WIDTH__ 8CGU_PLL0USB_CTRL MMIO32(CGU_BASE + 0x020)CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK (1 << CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_SHIFT)CGU_BASE_PHY_TX_CLK_CLK_SEL(x) ((x) << CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT)__INT_LEAST16_TYPE__ short intCGU_PLL0USB_NP_DIV MMIO32(CGU_BASE + 0x028)SSP_MODE_LOOPBACKCGU_IDIVA_CTRL_PD (1 << CGU_IDIVA_CTRL_PD_SHIFT)CGU_PLL0USB_CTRL_DIRECTO_SHIFT (3)__DBL_MAX__ ((double)1.7976931348623157e+308L)CGU_SRC_IDIVC 0x0EINT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1UINTMAX_CCGU_PLL1_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL1_CTRL_CLK_SEL_SHIFT)CGU_PLL0AUDIO_CTRL_FRM_SHIFT (6)CGU_PLL0USB_CTRL_CLK_SEL(x) ((x) << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT)INT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1__UINTPTR_MAX__ 0xffffffffUCGU_FREQ_MON_FCNT(x) ((x) << CGU_FREQ_MON_FCNT_SHIFT)__HQ_FBIT__ 15__bool_true_false_are_defined 1USART2_BASE (PERIPH_BASE_APB2 + 0x01000)CGU_BASE_UART2_CLK MMIO32(CGU_BASE + 0x0A4)BIT26 (1<<26)__SIZE_MAX__ 0xffffffffUssp_datasize_tCGU_BASE_SPIFI_CLK_PD_SHIFT (0)CGU_FREQ_MON_RCNT_MASK (0x1ff << CGU_FREQ_MON_RCNT_SHIFT)CGU_BASE_CGU_OUT0_CLK_PD_SHIFT (0)__ARM_ARCH__LONG_MAX__ 0x7fffffffLMCPWM_BASE (PERIPH_BASE_APB1 + 0x00000)LPC43XX_MEMORYMAP_H __ARM_FEATURE_LDREX 7PTRDIFF_MAXCGU_BASE_APB3_CLK MMIO32(CGU_BASE + 0x084)CGU_PLL0USB_MDIV_SELP_SHIFT (17)SSP_CPOL_0_CPHA_0SSP_CPOL_0_CPHA_1__LLFRACT_EPSILON__ 0x1P-63LLRCGU_PLL0USB_NP_DIV_NDEC(x) ((x) << CGU_PLL0USB_NP_DIV_NDEC_SHIFT)__SFRACT_MAX__ 0X7FP-7HR__FLT32X_MANT_DIG__ 53CGU_BASE_APB1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_APB1_CLK_CLK_SEL_SHIFT)__WCHAR_WIDTH__ 32WINT_MAX__INT16_C(c) cINT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32CGU_BASE_SDIO_CLK_PD_SHIFT (0)__ATOMIC_ACQ_REL 4ADC1_BASE (PERIPH_BASE_APB3 + 0x04000)__HQ_IBIT__ 0__DBL_MIN_10_EXP__ (-307)dataCGU_BASE_PERIPH_CLK_PD_SHIFT (0)CGU_BASE_LCD_CLK_CLK_SEL_SHIFT (24)SSP1_IMSC SSP_IMSC(SSP1)SSP_FRAME_TI__FLT32_NORM_MAX__ 3.4028234663852886e+38F32UINT64_C(c) __UINT64_C(c)CGU_BASE_UART3_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART3_CLK_CLK_SEL_SHIFT)CGU_PLL0AUDIO_CTRL_PD (1 << CGU_PLL0AUDIO_CTRL_PD_SHIFT)CGU_BASE_USB1_CLK_PD (1 << CGU_BASE_USB1_CLK_PD_SHIFT)__UINTMAX_MAX__ 0xffffffffffffffffULLCGU_BASE_SDIO_CLK_AUTOBLOCK (1 << CGU_BASE_SDIO_CLK_AUTOBLOCK_SHIFT)__DBL_MANT_DIG__ 53__ULFRACT_IBIT__ 0INT_FAST16_MAX__INT_MAX__ 0x7fffffff__INT_LEAST64_TYPE__ long long int__ARM_FEATURE_CDE_COPROCCGU_PLL0USB_CTRL_BYPASS (1 << CGU_PLL0USB_CTRL_BYPASS_SHIFT)../ssp.cSSP_DATA_9BITSGCC: (15:12.2.rel1-1) 12.2.1 20221205 | A XD^A3aeabi)7E-M M  "        t  H*, "$&(. 4e-[-0  Xssp.c$t$dwm4.0.ac8f3cbd7733ee78183be95102ca936awm4.common.h.21.c9066c2f6b12c71b40226ea6107829a4wm4.stdint.h.29.6d480f4ba0f60596e88234283d42444fwm4.stdbool.h.29.4a1c88fe569adb8d03217dd16982ca34wm4.common.h.67.5c568a1f62c8e726909b04e29f9e1fc0wm4.memorymap.h.22.395ffb693017d551ed93d11c39ba4361wm4.ssp.h.46.fffaf39f115091980571760c0a31a002wm4.cgu.h.37.c480a83e7590bba775f2472229e8edb0ssp_disablessp_initssp_transfer "&-4;BGUZhm{ '-3:PV\bi  , 1=AFS`lw~   %/38BMT_m ( = Jbz   & $-3<BK #)/5;AGMSY_ekqw} %+17=CIOU[agmsy !'-39?EKQW]ciou{ #)/5;AGMSY_ekqw} %+17=CIOU[agmsy !'-39?EKQW]ciou{ #)/5;AGMSY_ekqw} %+17=CIOU[agmsy !'-39?EKQW]ciou{     # ) / 5 ; A G M S Y _ e k q w }                            % + 1 7 = C I O U [ a g m s y          #)/5;AGMSY_ekqx  '.5<CJQX_fmt{#*18?FMT[bipw~ &-4;BI  #)/5;AGMSY_ekqw} #)/5;AGMSY_ekqw} %+17=CIOU\ #)/5;AGMSY_ekqw} #)/5;AGMSY_ekqw} %,3:AHOV]dkry !(/6=DKRY`gnu|$+29@GNU\cjqx  '.5<CJQX_fmt{#*18?FMT[bipw~ &-4;BIPW^elsz ")07>ELSZahov} %,3:AHOV]dkry    ! ( / 6 = D K R Y ` g n u |                        $ + 2 9 @ G N U \ c j q x             $(@D .symtab.strtab.shstrtab.text.data.bss.text.ssp_disable.text.ssp_init.text.ssp_transfer.rel.debug_info.debug_abbrev.rel.debug_loclists.rel.debug_aranges.rel.debug_rnglists.rel.debug_macro.rel.debug_line.debug_str.comment.rel.debug_frame.ARM.attributes.group4 1@ 1 L 1!X 1"d 1#p 1$| 1% 1&!',>M4Xdx` @LP1p37~ @`10 @ 1H, @ 1tR @<P1  @01n @ 1N @1" @(1  @01"a @ 1$C @@1&8  @p 1($ @1*0&0'ԾX @01.p,4`@21 uart.o/ 0 0 0 644 68664 ` ELF(x4(87 !"#$%&'()*+,-1L`pBNEؤ$BNTB<)L)MP$`$`Di&M h,`@$e@OCC#eC``bCi+`hC`3 C``h`bhC"C`e LBL MPLMPLMP @@ @@i  pGhhpG OQ0h!p]qE!Fh`pG ' ZR 6#HQS i#.Q& 1c 4u&Gr int0\Qr[@'O'[kowQ|Zi9QpDX5,B;(8YhL@ @_w @` @Qps|zWQP.C{ JE* j%\LP.FQ! j n F2&L:V9jE=R! jmea FS jp Hf FL! ja F @4L! j F//LPC/4,&30OIQ901pj1X1%Fp1=F%e3 j!4 j( 4:!; 9 IB:!; 9 IB$ > >! I:!;9!:!;9!I(:!; 9 I :!; 9 I .?:!; 9 'I@z % Uy $ >  4: ; 9 I?.?: ; 9 '@z I.?: ; 9 '@zPP$|l$0P02|lQ$Q$.Q.2QP$|l$0P02|lP 0(2^ P rl P rl PPPPP PPQQQ`R`RRfSfSS..SQP<2(2 ?@MPS;O]co3n !!y" #1$&t(r5a POc$"(=D'M5N*wAk}x& -Wg'rcZa6c8S. ߀vA % oWaGxDpcuXLcCu \ dI&0D`5^-sahiQAH?Q9TjinVj3=ϏFJeO2*[CBCj5 @# JŅ>F=  mUE7:qKڑ_Aw("&jk&UUŜx'3V^3Wp@5SM]\r*'"-QZr0$85WFVd>}>EkM\:[3E$ 4Ă/  6 dv3[\SRg*2OkS;SAsDKlRf/1hK(;}01wљOV%bj NV ]\qYv tE;|eV&Hb(?XYGSqL228;A#q^'IZjcXQWj`dRy{uT , OÕ;s)9:f];tJonFiQj}7`]M<uz sR yĘ`I(BD$ ,s~90s5g{c.@"}B#, .undLy$|96tRU*:`?nF7.Wa}DOohFPDj{GrSb_)D€\eD}WU%eVRsU #+}8Qi@uU—Gf{`@o2Z]wD&}0<abb79~KJz2:/}P*!v{"&)?jdq#eLfvcgjQknSo>p}}q AtVu;xnyQQz{ ~?XYZ 'bvK6t`D-l`/djH2(_b'QsRkq #CCEvMxeej+u)I`|(Hk yea 1YDZS}ZO9%فjrz#Jf=/w$R/ik DrPŠW{=L}o.&{g<`J#suX-QeCL՛cܕ!:=&c'ڐ2 C;DPE%FmfId>LQTR SyTESU8VۋWPTXZYZU[\\j] ^z_F`wmabfcId,qemGfnghCiIjrkl!mLnuoJprghTN # !B?&@( )6m78K9K:;?S&@;AMBHIwCJΆKzLZHMNAOj&PnQlWzXY&@ZC[ab-c;gdej7CCݠwv't [q8 % <RlƌP$%!". Z6vYW[uW{39:&9N:2V9q/\e7HgYTXi#!-ΣCi=%/[2>58-;S>ܚAZDUG[J~MdP?SV2Yc\~_Abʔexhrk,nqTWt~w0z(} T;vzo,܌zXVT|" F0e}^j5(_5.7-\TCj1" n[ 63h} m5}, WM@x9yTE=G8D`V*6b&r:@f)4fSzhRS+v"hEYJ.0) 1O%m(o8 C)2QMvkXx3pG!^6:>O oulчdwyJ3]9|Q%tp\_@N0܂ Jf{'~tXZKV0Hhz4_x) `څPro@BhÄ&EFnSLFm{:MYA8\N2T-.V(yHJ[\*L6T]fV?cY6[D=*@aVj\4}dgn6$ 4=}iwR#<&Yw(RF,CPU6y.il_aϝ )oB t =\-:v_Rt?{XO75 HI1Wb/s:\~qbk%-PY 6N/sO#3ǡ͗0p(xcZ# 4FbtQ*L cBekvZsA,[++$5|UK8IPtL;+ 1wgAl^9<h~]=>M5m<8?3ʈEM|3eqm!?R9I_ykfDa{ ,k;bR)F~:r4_SD ../usr/lib/gcc/arm-none-eabi/12.2.1/include../../../include/libopencm3/lpc43xx../../../include/libopencm3/cm3uart.cstdint.huart.hcommon.hstdbool.hmemorymap.hcgu.h1z&z l L11 g  O1   .1 5y & $.a 1###   =!!" =$ $0 z ##! <Lx Lr L # X# .. . 0" w  -/! . .. < % # u r. / >  /. / 0!CGU_PLL1_CTRL_FBSEL (1 << CGU_PLL1_CTRL_FBSEL_SHIFT)CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT (24)__DECIMAL_DIG__ 17CGU_BASE_SPIFI_CLK_AUTOBLOCK_SHIFT (11)__UHA_FBIT__ 8CGU_BASE_OUT_CLK_PD (1 << CGU_BASE_OUT_CLK_PD_SHIFT)uart_statusUART1_IER_CTSINT_EN (1 << 7)CGU_BASE_UART0_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART0_CLK_CLK_SEL_SHIFT)CGU_BASE_UART2_CLK_PD (1 << CGU_BASE_UART2_CLK_PD_SHIFT)__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64uart_num__GCC_ATOMIC_WCHAR_T_LOCK_FREE 2CGU_BASE_PHY_TX_CLK_PD (1 << CGU_BASE_PHY_TX_CLK_PD_SHIFT)__CHAR_UNSIGNED__ 1ETHERNET_BASE (PERIPH_BASE_AHB + 0x10000)CGU_BASE_PHY_RX_CLK_AUTOBLOCK_SHIFT (11)CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT (24)__FLT64_HAS_INFINITY__ 1CGU_IDIVC_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVC_CTRL_CLK_SEL_SHIFT)CGU_IDIVB_CTRL_CLK_SEL_SHIFT (24)__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GNUC_MINOR__ 2__GCC_DESTRUCTIVE_SIZE 64__LACCUM_EPSILON__ 0x1P-31LK__PTRDIFF_MAX__ 0x7fffffff__ARM_FEATURE_FMA 1CGU_PLL0AUDIO_CTRL_SEL_EXT_SHIFT (13)__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)__INTMAX_MAX__ 0x7fffffffffffffffLLCGU_IDIVD_CTRL_CLK_SEL_SHIFT (24)__TQ_IBIT__ 0__FLT64_DECIMAL_DIG__ 17WINT_MIN __WINT_MIN__I2C0_BASE (PERIPH_BASE_APB1 + 0x01000)data_readyUART0_NUM__ATOMIC_CONSUME 1__LFRACT_MIN__ (-0.5LR-0.5LR)__WCHAR_MAX__ 0xffffffffUCGU_PLL0USB_MDIV_SELR(x) ((x) << CGU_PLL0USB_MDIV_SELR_SHIFT)CGU_IDIVA_CTRL_PD (1 << CGU_IDIVA_CTRL_PD_SHIFT)OTP_BASE (0x40045000U)CGU_BASE_APLL_CLK MMIO32(CGU_BASE + 0x0C0)CGU_BASE_SSP1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT)CGU_BASE_OUT_CLK_CLK_SEL_SHIFT (24)CGU_PLL0USB_CTRL_CLK_SEL_SHIFT (24)INT64_MAX __INT64_MAX__INTMAX_MIN__SIZEOF_LONG_LONG__ 8__DBL_MAX_10_EXP__ 308CGU_BASE_APLL_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_APLL_CLK_CLK_SEL_SHIFT)__FRACT_MIN__ (-0.5R-0.5R)__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLK__USACCUM_MAX__ 0XFFFFP-8UHK__SFRACT_FBIT__ 7__INTMAX_WIDTH__ 64__ARM_FEATURE_BF16_SCALAR_ARITHMETIC__SQ_IBIT__ 0__ORDER_PDP_ENDIAN__ 3412__SIZE_TYPE__ unsigned intC_CCAN1_BASE (PERIPH_BASE_APB1 + 0x04000)__FLT_HAS_DENORM__ 1__INT8_TYPE__ signed char__SHRT_WIDTH__ 16CGU_BASE_SDIO_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT)__USACCUM_MIN__ 0.0UHK__FLT32_DECIMAL_DIG__ 9CGU_BASE_UART1_CLK_AUTOBLOCK (1 << CGU_BASE_UART1_CLK_AUTOBLOCK_SHIFT)UART_FCR(port) MMIO32((port) + 0x008)__LDBL_MIN_EXP__ (-1021)CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_MASK (0x3fffff << CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT)__LDBL_MANT_DIG__ 53UART_SRC_IDIVC 0x0EINT64_MIN (-INT64_MAX - 1)LPC43XX_UART_H __UINT8_C(c) c__INT16_TYPE__ short intCGU_BASE_USB0_CLK_CLK_SEL(x) ((x) << CGU_BASE_USB0_CLK_CLK_SEL_SHIFT)__FLT64_MAX__ 1.7976931348623157e+308F64USB0_BASE (PERIPH_BASE_AHB + 0x06000)UART_LSR_THRE (1 << 5)UINT_FAST32_MAXCGU_BASE_PHY_TX_CLK MMIO32(CGU_BASE + 0x07C)CGU_BASE_SDIO_CLK_PD_SHIFT (0)CGU_PLL0USB_CTRL_PD (1 << CGU_PLL0USB_CTRL_PD_SHIFT)INT_FAST64_MAX __INT_FAST64_MAX__CGU_PLL0AUDIO_CTRL_FRM (1 << CGU_PLL0AUDIO_CTRL_FRM_SHIFT)__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1UART_IIR_ABEO_INT (1 << 8)__UINT_LEAST16_MAX__ 0xffff__STDC_HOSTED__ 1__ULLFRACT_FBIT__ 64__SIG_ATOMIC_TYPE__ intCGU_BASE_APB3_CLK_AUTOBLOCK (1 << CGU_BASE_APB3_CLK_AUTOBLOCK_SHIFT)CGU_BASE_SPIFI_CLK_CLK_SEL(x) ((x) << CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT)__INT_FAST64_TYPE__ long long int__WINT_TYPE__ unsigned intPERIPH_BASE_APB2 (0x400C0000U)CGU_BASE_SPIFI_CLK_AUTOBLOCK (1 << CGU_BASE_SPIFI_CLK_AUTOBLOCK_SHIFT)CGU_XTAL_OSC_CTRL_ENABLE_SHIFT (0)INT32_MIN (-INT32_MAX - 1)UART_ICR(port) MMIO32((port) + 0x024)uart_rx_data_readyCGU_SRC_32K 0x00WWDT_BASE (PERIPH_BASE_APB0 + 0x00000)__USFRACT_MAX__ 0XFFP-8UHRCGU_PLL0USB_MDIV MMIO32(CGU_BASE + 0x024)__FP_FAST_FMAF32 1CGU_PLL1_CTRL MMIO32(CGU_BASE + 0x044)TIMER1_BASE (PERIPH_BASE_APB0 + 0x05000)UART1_IER_BITMASK ((uint32_t)(0x38F))__FLT32_MIN_EXP__ (-125)CGU_BASE_VADC_CLK_PD_SHIFT (0)ATIMER_BASE (0x40040000U)UINT32_MAX __UINT32_MAX__CGU_IDIVB_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVB_CTRL_CLK_SEL_SHIFT)C_CAN0_BASE (PERIPH_BASE_APB3 + 0x02000)__DA_IBIT__ 32__ULFRACT_FBIT__ 32INT8_MIN (-INT8_MAX - 1)__FLT64_MIN_10_EXP__ (-307)__GNUC_EXECUTION_CHARSET_NAME "UTF-8"BIT10 (1<<10)__INT_FAST64_WIDTH__ 64__STDC_VERSION__ 199901LINT_LEAST64_MAX __INT_LEAST64_MAX__CGU_BASE_APB3_CLK_PD (1 << CGU_BASE_APB3_CLK_PD_SHIFT)CGU_BASE_SPI_CLK_AUTOBLOCK (1 << CGU_BASE_SPI_CLK_AUTOBLOCK_SHIFT)UART_ICR_IRDAINV (1 << 1)__SFRACT_EPSILON__ 0x1P-7HRCGU_PLLAUDIO_FRAC_PLLFRACT_CTRL(x) ((x) << CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT)__INT32_C(c) c ## LUINT32_C(c) __UINT32_C(c)__ORDER_BIG_ENDIAN__ 4321SIZE_MAXCGU_PLL0USB_STAT_FR_SHIFT (1)__SQ_FBIT__ 31CGU_BASE_CGU_OUT1_CLK_PD_SHIFT (0)INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)CGU_PLL1_STAT_LOCK_SHIFT (0)UART_RS485CTRL(port) MMIO32((port) + 0x04C)__UHQ_FBIT__ 16CGU_IDIVB_CTRL_IDIV_SHIFT (2)__FLT64_MIN_EXP__ (-1021)__PTRDIFF_WIDTH__ 32__FLT32_MAX_10_EXP__ 38CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT (0)__UINT_FAST8_MAX__ 0xffffffffUuart_num_tCGU_IDIVA_CTRL_AUTOBLOCK (1 << CGU_IDIVA_CTRL_AUTOBLOCK_SHIFT)UINT16_C(c) __UINT16_C(c)CGU_BASE_CGU_OUT0_CLK_CLK_SEL(x) ((x) << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT)__LACCUM_IBIT__ 32CGU_PLL0AUDIO_CTRL_BYPASS (1 << CGU_PLL0AUDIO_CTRL_BYPASS_SHIFT)CGU_BASE_SDIO_CLK_CLK_SEL(x) ((x) << CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT)__INT_FAST16_WIDTH__ 32CGU_BASE_USB1_CLK MMIO32(CGU_BASE + 0x068)INTMAX_C__VERSION__ "12.2.1 20221205"__VFP_FP__ 1CGU_PLL0AUDIO_CTRL_SEL_EXT (1 << CGU_PLL0AUDIO_CTRL_SEL_EXT_SHIFT)__LLFRACT_MIN__ (-0.5LLR-0.5LLR)INT_FAST8_MAXCGU_PLL0USB_MDIV_MDEC_SHIFT (0)__GCC_ATOMIC_POINTER_LOCK_FREE 2__UINT_FAST16_MAX__ 0xffffffffUCGU_PLL0AUDIO_CTRL_PD_SHIFT (0)CGU_IDIVC_CTRL_PD_SHIFT (0)UART_SCICTRL_GUARDTIME(n) ((uint32_t)(((n)&0xFF)<<8))__INTPTR_MAX__ 0x7fffffffINT64_C(c) __INT64_C(c)CGU_IDIVD_CTRL_CLK_SEL(x) ((x) << CGU_IDIVD_CTRL_CLK_SEL_SHIFT)CGU_BASE_CGU_OUT1_CLK MMIO32(CGU_BASE + 0x0C8)__GCC_IEC_559_COMPLEX 0CREG_BASE (0x40043000U)__UFRACT_MIN__ 0.0URCGU_PLL0AUDIO_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT)uart_divaddvalCGU_BASE_M4_CLK_PD (1 << CGU_BASE_M4_CLK_PD_SHIFT)__FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX__CGU_FREQ_MON_CLK_SEL_SHIFT (24)__UINT_LEAST8_TYPE__ unsigned charUART_DLL_MASKBIT ((uint8_t)0xFF)CGU_BASE_UART0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART0_CLK_CLK_SEL_SHIFT)__ACCUM_FBIT__ 15CGU_PLL0USB_CTRL_PD_SHIFT (0)UART_ACR(port) MMIO32((port) + 0x020)long intUINT8_MAXCGU_BASE_SAFE_CLK_CLK_SEL_SHIFT (24)uart_divisorCGU_PLL0USB_STAT MMIO32(CGU_BASE + 0x01C)__INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17CGU_PLL1_CTRL_NSEL_MASK (0x3 << CGU_PLL1_CTRL_NSEL_SHIFT)__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1CGU_BASE_PERIPH_CLK_AUTOBLOCK (1 << CGU_BASE_PERIPH_CLK_AUTOBLOCK_SHIFT)__FLT32X_EPSILON__ 2.2204460492503131e-16F32xUART_SRC_PLL0USB 0x07CGU_IDIVB_CTRL_PD (1 << CGU_IDIVB_CTRL_PD_SHIFT)CGU_BASE_UART2_CLK_AUTOBLOCK_SHIFT (11)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32UART_SYNCCTRL(port) MMIO32((port) + 0x058)uart_init__UINTMAX_C(c) c ## ULL__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed char__GCC_ATOMIC_BOOL_LOCK_FREE 2BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON__UART_TIMEOUT_ERROR__FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX____TA_FBIT__ 63__THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRCGU_BASE_UART3_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART3_CLK_CLK_SEL_SHIFT)CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT (24)UART_LSR_RXFE (1 << 7)short unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)CGU_BASE_PHY_RX_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT)BIT7 (1<<7)BIT17 (1<<17)__FLT32X_MIN_10_EXP__ (-307)CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_SHIFT (11)UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_SHIFT (12)DAC_BASE (PERIPH_BASE_APB3 + 0x01000)error__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4UART_FDR_MULVAL(n) ((uint32_t)(((n)<<4)&0xF0))LCD_BASE (PERIPH_BASE_AHB + 0x08000)CGU_BASE_OUT_CLK MMIO32(CGU_BASE + 0x0AC)CGU_BASE_SSP0_CLK_PD (1 << CGU_BASE_SSP0_CLK_PD_SHIFT)UART_IER_ABEOINT_EN (1 << 8)__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32__FLT32X_MIN_EXP__ (-1021)GPDMA_BASE (PERIPH_BASE_AHB + 0x02000)UART_SRC_IDIVA 0x0CUART_SYNCCTRL_NOSTARTSTOP (1 << 5)UART_IER_BITMASK ((uint32_t)(0x307))UART_FCR_FIFO_EN (1 << 0)uart_portBIT27 (1<<27)UART_IIR_INTID_RLS (3 << 1)UART_LSR_FE (1 << 3)CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT (24)CGU_PLL0AUDIO_NP_DIV_PDEC_MASK (0x7f << CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT)__UTA_FBIT__ 64SDIO_BASE (PERIPH_BASE_AHB + 0x04000)CGU_PLL0USB_NP_DIV_PDEC(x) ((x) << CGU_PLL0USB_NP_DIV_PDEC_SHIFT)__FLT_DECIMAL_DIG__ 9CGU_FREQ_MON_CLK_SEL(x) ((x) << CGU_FREQ_MON_CLK_SEL_SHIFT)__thumb__ 1__INT_LEAST32_MAX__ 0x7fffffffLsigned charGIMA_BASE (PERIPH_BASE_APB2 + 0x07000)uint8_tINT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)CGU_BASE_LCD_CLK_AUTOBLOCK_SHIFT (11)INT32_C(c) __INT32_C(c)__GNUC_STDC_INLINE__ 1__FRACT_FBIT__ 15CGU_BASE_VADC_CLK_CLK_SEL(x) ((x) << CGU_BASE_VADC_CLK_CLK_SEL_SHIFT)__LLACCUM_EPSILON__ 0x1P-31LLK__GNUC_PATCHLEVEL__ 1__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2PTRDIFF_MIN__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)CGU_BASE_UART0_CLK_AUTOBLOCK (1 << CGU_BASE_UART0_CLK_AUTOBLOCK_SHIFT)UART_LSR_PE (1 << 2)UINTPTR_MAX __UINTPTR_MAX____ARM_ARCH_PROFILE 77CGU_BASE_APB3_CLK_PD_SHIFT (0)UART_LCR_BREAK_EN (1 << 6)__FLT64_MAX_10_EXP__ 308CGU_PLL1_CTRL_PSEL_SHIFT (8)MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINUART3 USART3_BASE__INT_FAST32_WIDTH__ 32UART_ICR_IRDAEN (1 << 0)CGU_BASE (0x40050000U)GPIO_PIN_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x07000)__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38UART_DATABIT_6UART_DATABIT_7__FRACT_MAX__ 0X7FFFP-15R__GCC_IEC_559 0GNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -O2 -std=c99 -fno-common -ffunction-sections -fdata-sectionsINT_LEAST32_MAX __INT_LEAST32_MAX__CGU_IDIVE_CTRL_PD (1 << CGU_IDIVE_CTRL_PD_SHIFT)CGU_PLL0AUDIO_CTRL_DIRECTO_SHIFT (3)CGU_BASE_PHY_RX_CLK MMIO32(CGU_BASE + 0x078)__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5CGU_BASE_SPIFI_CLK_PD (1 << CGU_BASE_SPIFI_CLK_PD_SHIFT)CGU_PLL0AUDIO_CTRL_AUTOBLOCK_SHIFT (11)UART_IER_ABTOINT_EN (1 << 9)CGU_IDIVB_CTRL_PD_SHIFT (0)CGU_PLL0USB_MDIV_SELP_MASK (0x1f << CGU_PLL0USB_MDIV_SELP_SHIFT)CGU_PLL0AUDIO_STAT_FR (1 << CGU_PLL0AUDIO_STAT_FR_SHIFT)CGU_BASE_SSP0_CLK_PD_SHIFT (0)CGU_BASE_SAFE_CLK_CLK_SEL(x) ((x) << CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT)CGU_IDIVE_CTRL_AUTOBLOCK (1 << CGU_IDIVE_CTRL_AUTOBLOCK_SHIFT)__UINT16_MAX__ 0xffffCGU_PLL0USB_CTRL_AUTOBLOCK (1 << CGU_PLL0USB_CTRL_AUTOBLOCK_SHIFT)__TQ_FBIT__ 127CGU_BASE_UART0_CLK_AUTOBLOCK_SHIFT (11)CGU_PLL0USB_NP_DIV_PDEC_MASK (0x7f << CGU_PLL0USB_NP_DIV_PDEC_SHIFT)__USQ_FBIT__ 32INT_FAST16_MINCGU_BASE_UART2_CLK_AUTOBLOCK (1 << CGU_BASE_UART2_CLK_AUTOBLOCK_SHIFT)__thumb2__ 1__ULLACCUM_FBIT__ 32CGU_SRC_ENET_TX 0x03UART_PARITY_EVENCGU_BASE_USB1_CLK_CLK_SEL(x) ((x) << CGU_BASE_USB1_CLK_CLK_SEL_SHIFT)CGU_BASE_SSP0_CLK MMIO32(CGU_BASE + 0x094)CGU_BASE_SSP1_CLK_CLK_SEL(x) ((x) << CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT)__STRICT_ANSI__ 1CGU_BASE_SPI_CLK_PD (1 << CGU_BASE_SPI_CLK_PD_SHIFT)UINT_LEAST8_MAXCGU_IDIVD_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVD_CTRL_CLK_SEL_SHIFT)UART_FDR_BITMASK ((uint32_t)(0xFF))UINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8CGU_FREQ_MON_FCNT(x) ((x) << CGU_FREQ_MON_FCNT_SHIFT)UART_LSR_BI (1 << 4)__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__CGU_IDIVE_CTRL_PD_SHIFT (0)CGU_FREQ_MON_FCNT_SHIFT (9)__USA_IBIT__ 16UART_RX_DATA_ERROR__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1CGU_BASE_PHY_TX_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT)PTRDIFF_MIN (-PTRDIFF_MAX - 1)UART_SCICTRL_TXRETRY(n) ((uint32_t)(((n)&0x07)<<5))CGU_BASE_APB3_CLK_CLK_SEL(x) ((x) << CGU_BASE_APB3_CLK_CLK_SEL_SHIFT)__DBL_IS_IEC_60559__ 2__UINT_FAST64_TYPE__ long long unsigned intCGU_PLL0AUDIO_STAT_FR_SHIFT (1)CGU_PLL1_CTRL_NSEL(x) ((x) << CGU_PLL1_CTRL_NSEL_SHIFT)__FLT_MIN__ 1.1754943508222875e-38F__HA_FBIT__ 7__FDPIC__CGU_IDIVA_CTRL_IDIV_SHIFT (2)CGU_BASE_SPI_CLK MMIO32(CGU_BASE + 0x074)CGU_BASE_UART2_CLK_CLK_SEL_SHIFT (24)__FLT32_IS_IEC_60559__ 2CGU_BASE_PHY_TX_CLK_PD_SHIFT (0)CGU_FREQ_MON_CLK_SEL_MASK (0x1f << CGU_FREQ_MON_CLK_SEL_SHIFT)UART_SRC_IDIVD 0x0FCGU_PLL0AUDIO_CTRL_BYPASS_SHIFT (1)INT_FAST64_MINADC0_BASE (PERIPH_BASE_APB3 + 0x03000)__USFRACT_IBIT__ 0__LDBL_EPSILON__ 2.2204460492503131e-16LUART_RS485ADRMATCH(port) MMIO32((port) + 0x050)__USFRACT_MIN__ 0.0UHR__ARM_NEONUART_HDEN_HDEN (1 << 0)CGU_IDIVA_CTRL MMIO32(CGU_BASE + 0x048)__UINT8_MAX__ 0xffCGU_PLL0AUDIO_CTRL_AUTOBLOCK (1 << CGU_PLL0AUDIO_CTRL_AUTOBLOCK_SHIFT)CGU_BASE_APLL_CLK_PD (1 << CGU_BASE_APLL_CLK_PD_SHIFT)__LDBL_MAX_EXP__ 1024UART_ACR_ABTOINT_CLR (1 << 9)CGU_XTAL_OSC_CTRL_HF_SHIFT (2)CGU_PLL0AUDIO_MDIV_MDEC_SHIFT (0)CGU_PLL1_CTRL_FBSEL_SHIFT (6)__DBL_HAS_DENORM__ 1CGU_PLL0USB_MDIV_SELP(x) ((x) << CGU_PLL0USB_MDIV_SELP_SHIFT)CGU_BASE_USB0_CLK_AUTOBLOCK_SHIFT (11)CGU_BASE_PERIPH_CLK_PD (1 << CGU_BASE_PERIPH_CLK_PD_SHIFT)CGU_SRC_IDIVB 0x0DCGU_BASE_SDIO_CLK_PD (1 << CGU_BASE_SDIO_CLK_PD_SHIFT)CGU_FREQ_MON_RCNT(x) ((x) << CGU_FREQ_MON_RCNT_SHIFT)__DA_FBIT__ 31CGU_BASE_OUT_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_OUT_CLK_CLK_SEL_SHIFT)__GXX_ABI_VERSION 1017__INT_LEAST16_MAX__ 0x7fffCGU_FREQ_MON_RCNT_SHIFT (0)__FLT_DENORM_MIN__ 1.4012984643248171e-45FCGU_XTAL_OSC_CTRL_BYPASS (1 << CGU_XTAL_OSC_CTRL_BYPASS_SHIFT)CGU_IDIVE_CTRL_CLK_SEL_SHIFT (24)CGU_BASE_USB0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_USB0_CLK_CLK_SEL_SHIFT)INT_LEAST8_MAX __INT_LEAST8_MAX__CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT (12)UART_IIR_INTSTAT_PEND (1 << 0)__UINT32_C(c) c ## ULUART1_IER_MSINT_EN (1 << 3)CGU_BASE_PHY_RX_CLK_AUTOBLOCK (1 << CGU_BASE_PHY_RX_CLK_AUTOBLOCK_SHIFT)UART_LCR_WLEN7 (2 << 0)__UACCUM_MIN__ 0.0UKCGU_FREQ_MON_FCNT_MASK (0x3fff << CGU_FREQ_MON_FCNT_SHIFT)CGU_IDIVD_CTRL_AUTOBLOCK_SHIFT (11)__FLT_EPSILON__ 1.1920928955078125e-7FCGU_BASE_UART1_CLK_CLK_SEL_SHIFT (24)UART_LCR_PARITY_SP_1 (1 << 5)__PTRDIFF_TYPE__ intUART_FCR_TRG_LEV2 (2 << 6)__ARM_ARCH_ISA_THUMBCGU_PLL0USB_CTRL_FRM_SHIFT (6)CGU_PLL0AUDIO_CTRL_CLKEN_SHIFT (4)UART_SCICTRL_PROTSEL_T1 (1 << 2)__ARM_FEATURE_MATMUL_INT8data_parityCGU_PLL1_CTRL_DIRECT_SHIFT (7)__GCC_ATOMIC_SHORT_LOCK_FREE 2CGU_BASE_UART3_CLK_AUTOBLOCK_SHIFT (11)uart_stopbit_t__HQ_IBIT__ 0UART_ACR_BITMASK ((uint32_t)(0x307))__USACCUM_FBIT__ 8CGU_SRC_PLL1 0x09__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1UART_ICR_BITMASK ((uint32_t)(0x3F))CGU_PLL0USB_MDIV_MDEC_MASK (0x1ffff << CGU_PLL0USB_MDIV_MDEC_SHIFT)CGU_BASE_SPI_CLK_CLK_SEL_SHIFT (24)__ELF__ 1CGU_BASE_APB1_CLK_PD_SHIFT (0)EMC_BASE (PERIPH_BASE_AHB + 0x05000)__FLT32_HAS_QUIET_NAN__ 1UART_PARITY_SP_1__LDBL_HAS_INFINITY__ 1CGU_SRC_GP_CLKIN 0x04__SACCUM_FBIT__ 7UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))CCU1_BASE (0x40051000U)__FLT32X_MAX_10_EXP__ 308UART_LCR_DLAB_EN (1 << 7)CGU_BASE_PERIPH_CLK_CLK_SEL(x) ((x) << CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT)CGU_BASE_OUT_CLK_CLK_SEL(x) ((x) << CGU_BASE_OUT_CLK_CLK_SEL_SHIFT)__ARM_ARCH_EXT_IDIV__ 1CGU_BASE_UART3_CLK_AUTOBLOCK (1 << CGU_BASE_UART3_CLK_AUTOBLOCK_SHIFT)UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F))bool _BoolCGU_PLL0USB_CTRL_CLKEN_SHIFT (4)UINTMAX_MAX __UINTMAX_MAX__CGU_BASE_OUT_CLK_PD_SHIFT (0)__SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffCGU_BASE_PERIPH_CLK_AUTOBLOCK_SHIFT (11)CGU_XTAL_OSC_CTRL MMIO32(CGU_BASE + 0x018)CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT (0)BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)INT16_MAX __INT16_MAX____FP_FAST_FMAF 1CGU_BASE_OUT_CLK_AUTOBLOCK (1 << CGU_BASE_OUT_CLK_AUTOBLOCK_SHIFT)__FLT32X_IS_IEC_60559__ 2PERIPH_BASE_APB3 (0x400E0000U)UART_DLM_MASKBIT ((uint8_t)0xFF)LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))UINT32_MAXCGU_PLL1_STAT MMIO32(CGU_BASE + 0x040)CGU_BASE_PHY_RX_CLK_PD_SHIFT (0)__INT_LEAST16_WIDTH__ 16I2S0_BASE (PERIPH_BASE_APB1 + 0x02000)CGU_PLL0USB_CTRL_DIRECTI_SHIFT (2)__DEC_EVAL_METHOD__ 2SCT_BASE (PERIPH_BASE_AHB + 0x00000)__ARM_FEATURE_FP16_FMLCGU_PLL0USB_MDIV_MDEC(x) ((x) << CGU_PLL0USB_MDIV_MDEC_SHIFT)CGU_BASE_UART3_CLK_PD_SHIFT (0)INT16_MIN (-INT16_MAX - 1)__USFRACT_EPSILON__ 0x1P-8UHRCGU_IDIVD_CTRL_IDIV(x) ((x) << CGU_IDIVD_CTRL_IDIV_SHIFT)CGU_IDIVD_CTRL MMIO32(CGU_BASE + 0x054)__WINT_MAX__ 0xffffffffUCGU_BASE_SSP1_CLK_CLK_SEL_SHIFT (24)SCU_BASE (PERIPH_BASE_APB0 + 0x06000)__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLKUART_IIR_FIFO_EN (3 << 6)CGU_BASE_SSP0_CLK_AUTOBLOCK (1 << CGU_BASE_SSP0_CLK_AUTOBLOCK_SHIFT)CGU_IDIVC_CTRL_PD (1 << CGU_IDIVC_CTRL_PD_SHIFT)__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX__UART_LCR_WLEN8 (3 << 0)__UINT32_MAX__ 0xffffffffULUSART0_BASE (PERIPH_BASE_APB0 + 0x01000)CGU_BASE_M4_CLK_PD_SHIFT (0)__INT_LEAST8_MAX__ 0x7fUART_FIFOLVL_RX(n) ((uint32_t)((n)&0x0F))uart_rx_data_ready_t__ARM_FEATURE_QBIT 1__ARM_FEATURE_CLZ 1__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXCGU_SRC_IRC 0x01__ARM_PCS_VFP 1__UINT64_TYPE__ long long unsigned intCGU_BASE_SAFE_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT)__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024CGU_IDIVC_CTRL_AUTOBLOCK_SHIFT (11)dummy_read__UINT_LEAST32_MAX__ 0xffffffffULUART_FCR_TX_RS (1 << 2)__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)CGU_BASE_APLL_CLK_AUTOBLOCK (1 << CGU_BASE_APLL_CLK_AUTOBLOCK_SHIFT)CGU_SRC_PLL0USB 0x07__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1__ACCUM_MAX__ 0X7FFFFFFFP-15K__INT8_MAX__ 0x7fCGU_OUTCLK_21_CTRL MMIO32(CGU_BASE + 0x0B0)BIT14 (1<<14)__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16USB1_BASE (PERIPH_BASE_AHB + 0x07000)BIT20 (1<<20)__ARM_FEATURE_MVE__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intCGU_PLL0USB_CTRL_CLKEN (1 << CGU_PLL0USB_CTRL_CLKEN_SHIFT)UINT_LEAST16_MAX __UINT_LEAST16_MAX__INT_FAST32_MINUART_SYNCCTRL_CSRC_MASTER (1 << 1)TIMER0_BASE (PERIPH_BASE_APB0 + 0x04000)CGU_IDIVA_CTRL_IDIV_MASK (0x3 << CGU_IDIVA_CTRL_IDIV_SHIFT)__SCHAR_WIDTH__ 8CGU_BASE_PHY_RX_CLK_CLK_SEL(x) ((x) << CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT)BIT18 (1<<18)UINT_FAST16_MAXCGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_SHIFT (11)__UINT_FAST8_TYPE__ unsigned intCGU_BASE_UART1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART1_CLK_CLK_SEL_SHIFT)__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RBIT24 (1<<24)CGU_PLL1_CTRL_MSEL_MASK (0xff << CGU_PLL1_CTRL_MSEL_SHIFT)CGU_IDIVE_CTRL_IDIV_MASK (0xff << CGU_IDIVE_CTRL_IDIV_SHIFT)__INT32_MAX__ 0x7fffffffLCGU_PLL0AUDIO_STAT_LOCK (1 << CGU_PLL0AUDIO_STAT_LOCK_SHIFT)UINTMAX_MAXBIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_BF16_VECTOR_ARITHMETIC__FLT32_MANT_DIG__ 24CGU_IDIVA_CTRL_PD_SHIFT (0)INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32UART_LSR(port) MMIO32((port) + 0x014)EVENTROUTER_BASE (0x40044000U)__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN__UART_IIR_INTID_CTI (6 << 1)__USFRACT_FBIT__ 8INT8_MAX __INT8_MAX__CGU_IDIVD_CTRL_PD_SHIFT (0)BIT28 (1<<28)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2INTMAX_C(c) __INTMAX_C(c)UART_SRC_32K 0x00__DBL_MAX_EXP__ 1024__ATOMIC_RELEASE 3CGU_IDIVD_CTRL_IDIV_MASK (0xf << CGU_IDIVD_CTRL_IDIV_SHIFT)UINT_FAST8_MAX__FLT_MANT_DIG__ 24UART_FCR_TRG_LEV1 (1 << 6)CGU_BASE_APLL_CLK_CLK_SEL_SHIFT (24)__LACCUM_FBIT__ 31CCU2_BASE (0x40052000U)__OPTIMIZE__ 1CGU_BASE_APB3_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_APB3_CLK_CLK_SEL_SHIFT)CGU_IDIVD_CTRL_AUTOBLOCK (1 << CGU_IDIVD_CTRL_AUTOBLOCK_SHIFT)__FLT64_NORM_MAX__ 1.7976931348623157e+308F64PERIPH_BASE_APB1 (0x400A0000U)UART_FCR_TRG_LEV0 (0 << 6)UINTPTR_MAX__LDBL_DENORM_MIN__ 4.9406564584124654e-324LTIMER3_BASE (PERIPH_BASE_APB2 + 0x04000)__INT64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_SAT 1__ULLFRACT_IBIT__ 0SPI_PORT_BASE (0x40100000U)CGU_BASE_LCD_CLK_PD (1 << CGU_BASE_LCD_CLK_PD_SHIFT)MMIO16(addr) (*(volatile uint16_t *)(addr))CGU_BASE_APB3_CLK_AUTOBLOCK_SHIFT (11)UART0 USART0_BASEUART_TX_FIFO_SIZE (16)LPC43XX 1__GNUC__ 12CGU_BASE_UART1_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART1_CLK_CLK_SEL_SHIFT)WCHAR_MAXUART_SRC_IRC 0x01CGU_IDIVB_CTRL_AUTOBLOCK_SHIFT (11)__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16CGU_PLL1_CTRL_DIRECT (1 << CGU_PLL1_CTRL_DIRECT_SHIFT)__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0UUART_IIR_BITMASK ((uint32_t)(0x3CF))__UQQ_IBIT__ 0CGU_BASE_PERIPH_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT)CGU_SRC_XTAL 0x06__GCC_ATOMIC_LONG_LOCK_FREE 2__ULACCUM_MIN__ 0.0ULKCGU_PLL0USB_NP_DIV_PDEC_SHIFT (0)__LDBL_MAX__ 1.7976931348623157e+308L__ARM_ARCH 7/build/libopencm3/lib/lpc43xx/m4UART_SRC_ENET_RX 0x02__FLT_RADIX__ 2BIT3 (1<<3)long long intCGU_SRC_IDIVE 0x10__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAXcounterSGPIO_PORT_BASE (0x40101000U)__LDBL_HAS_QUIET_NAN__ 1CGU_PLL0USB_MDIV_SELI_MASK (0x3f << CGU_PLL0USB_MDIV_SELI_SHIFT)PERIPH_BASE_APB0 (0x40080000U)__LONG_LONG_WIDTH__ 64BIT6 (1<<6)CGU_FREQ_MON_MEAS_SHIFT (23)CGU_PLL0USB_CTRL_DIRECTO (1 << CGU_PLL0USB_CTRL_DIRECTO_SHIFT)CGU_BASE_APB1_CLK MMIO32(CGU_BASE + 0x080)CGU_IDIVE_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVE_CTRL_CLK_SEL_SHIFT)__UINT_FAST64_MAX__ 0xffffffffffffffffULLCGU_BASE_M4_CLK_AUTOBLOCK_SHIFT (11)__ARM_FP__HA_IBIT__ 8__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1CGU_PLL0AUDIO_CTRL MMIO32(CGU_BASE + 0x030)BIT9 (1<<9)UART_FCR_RX_RS (1 << 1)__FLT32X_MIN__ 2.2250738585072014e-308F32xrx_timeout_nb_cycles__FLT64_MAX_EXP__ 1024CGU_BASE_SAFE_CLK_PD_SHIFT (0)UINT16_MAXUART_SCICTRL_SCIEN (1 << 0)__FLT64_MIN__ 2.2250738585072014e-308F64CGU_PLL0USB_CTRL_AUTOBLOCK_SHIFT (11)__INTMAX_C(c) c ## LLCGU_PLL0USB_CTRL_BYPASS_SHIFT (1)__FLT_EVAL_METHOD_TS_18661_3__ 0CGU_BASE_M4_CLK MMIO32(CGU_BASE + 0x06C)__ARM_ARCH_PROFILE__INT64_TYPE__ long long int__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4UART_ACR_MODE (1 << 1)CGU_BASE_PHY_TX_CLK_AUTOBLOCK (1 << CGU_BASE_PHY_TX_CLK_AUTOBLOCK_SHIFT)UART_PARITY_ODDUART_SYNCCTRL_TSBYPASS (1 << 3)CGU_PLL1_CTRL_CLK_SEL(x) ((x) << CGU_PLL1_CTRL_CLK_SEL_SHIFT)__UFRACT_MAX__ 0XFFFFP-16URCGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT (24)__UINT_LEAST32_TYPE__ long unsigned intINT64_MAXCGU_BASE_USB1_CLK_PD_SHIFT (0)CGU_PLL0AUDIO_STAT_LOCK_SHIFT (0)UART_SYNCCTRL_FES (1 << 2)INT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0SSP1_BASE (PERIPH_BASE_APB2 + 0x05000)UART_LSR_ERROR_MASK (UART_LSR_OE | UART_LSR_PE | UART_LSR_FE | UART_LSR_BI | UART_LSR_RXFE)SPIFI_BASE (PERIPH_BASE_AHB + 0x03000)__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__../uart.c__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__UART_LSR_TEMT (1 << 6)__UFRACT_FBIT__ 16UART_LCR_PARITY_ODD (0 << 4)__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)CGU_XTAL_OSC_CTRL_BYPASS_SHIFT (1)CGU_FREQ_MON MMIO32(CGU_BASE + 0x014)__LDBL_MAX_10_EXP__ 308CGU_BASE_UART0_CLK_PD_SHIFT (0)UART_DATABIT_5UART_DATABIT_8__INT_FAST32_TYPE__ intuart_writeunsigned intCGU_BASE_SPI_CLK_PD_SHIFT (0)CGU_IDIVE_CTRL_AUTOBLOCK_SHIFT (11)__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1CGU_PLL1_CTRL_PSEL(x) ((x) << CGU_PLL1_CTRL_PSEL_SHIFT)CGU_BASE_APB1_CLK_AUTOBLOCK_SHIFT (11)CGU_IDIVE_CTRL_CLK_SEL(x) ((x) << CGU_IDIVE_CTRL_CLK_SEL_SHIFT)UART_SRC_GP_CLKIN 0x04__USACCUM_IBIT__ 8UART_IIR(port) MMIO32((port) + 0x008)__ARM_ARCH_7EM__ 1__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UKUART_IER_RBRINT_EN (1 << 0)CGU_PLL0AUDIO_NP_DIV_PDEC(x) ((x) << CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT)__FLT_EVAL_METHOD__ 0CGU_BASE_UART3_CLK_PD (1 << CGU_BASE_UART3_CLK_PD_SHIFT)CGU_OUTCLK_24_CTRL MMIO32(CGU_BASE + 0x0BC)GPIO_PORT_BASE (0x400F4000U)__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32CGU_FREQ_MON_RCNT_MASK (0x1ff << CGU_FREQ_MON_RCNT_SHIFT)__ARM_FEATURE_LDREXCGU_BASE_SPI_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SPI_CLK_CLK_SEL_SHIFT)__UQQ_FBIT__ 8CGU_PLL1_CTRL_AUTOBLOCK_SHIFT (11)CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK (1 << CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_SHIFT)INT16_CCGU_PLL0USB_CTRL_FRM (1 << CGU_PLL0USB_CTRL_FRM_SHIFT)__ARM_FP16_ARGS__UACCUM_MAX__ 0XFFFFFFFFP-16UKUART3_NUMINT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX____LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4__STDC__ 1CGU_BASE_USB0_CLK_PD_SHIFT (0)CGU_BASE_M4_CLK_CLK_SEL(x) ((x) << CGU_BASE_M4_CLK_CLK_SEL_SHIFT)__ARM_FEATURE_IDIV 1__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN____UINT8_TYPE__ unsigned charCGU_BASE_APB1_CLK_CLK_SEL(x) ((x) << CGU_BASE_APB1_CLK_CLK_SEL_SHIFT)CGU_BASE_SDIO_CLK_AUTOBLOCK_SHIFT (11)UART_RS485DLY(port) MMIO32((port) + 0x054)__ARM_FEATURE_COPROC 15CGU_PLL0USB_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT)UINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"CGU_BASE_SAFE_CLK_PD (1 << CGU_BASE_SAFE_CLK_PD_SHIFT)INT8_MINUART_SRC_XTAL 0x06true 1CGU_IDIVB_CTRL MMIO32(CGU_BASE + 0x04C)__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)CGU_BASE_VADC_CLK_AUTOBLOCK_SHIFT (11)__LDBL_MIN_10_EXP__ (-307)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1__GCC_ATOMIC_CHAR_LOCK_FREE 2UART_LOAD_DLL(div) ((div) & 0xFF)CGU_PLL1_CTRL_PD (1 << CGU_PLL1_CTRL_PD_SHIFT)__LFRACT_EPSILON__ 0x1P-31LRCGU_PLLAUDIO_FRAC MMIO32(CGU_BASE + 0x03C)lcr_configCGU_OUTCLK_22_CTRL MMIO32(CGU_BASE + 0x0B4)__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX__UART_SYNCCTRL_SYNC (1 << 0)__FLT32X_NORM_MAX__ 1.7976931348623157e+308F32x__arm__ 1INT_FAST64_MAXCGU_BASE_SSP0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT)uart_read__FLT32_MIN_10_EXP__ (-37)MMIO64(addr) (*(volatile uint64_t *)(addr))CGU_PLL1_CTRL_MSEL(x) ((x) << CGU_PLL1_CTRL_MSEL_SHIFT)CGU_PLL0USB_MDIV_SELI_SHIFT (22)__ARM_FP16_FORMAT_ALTERNATIVE__LDBL_NORM_MAX__ 1.7976931348623157e+308LUSART3_BASE (PERIPH_BASE_APB2 + 0x02000)CGU_BASE_USB0_CLK_CLK_SEL_SHIFT (24)__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)CGU_BASE_UART2_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART2_CLK_CLK_SEL_SHIFT)__TA_IBIT__ 64CGU_PLL0USB_NP_DIV_NDEC_SHIFT (12)__FLT32_MIN__ 1.1754943508222875e-38F32uart_parity_tPERIPH_BASE_AHB (0x40000000U)CGU_IDIVC_CTRL_IDIV_SHIFT (2)CGU_XTAL_OSC_CTRL_HF (1 << CGU_XTAL_OSC_CTRL_HF_SHIFT)__ARM_FEATURE_QRDMXCGU_PLL0USB_MDIV_SELR_MASK (0xf << CGU_PLL0USB_MDIV_SELR_SHIFT)CGU_BASE_M4_CLK_CLK_SEL_SHIFT (24)__ARM_ARCH_ISA_THUMB 2__LONG_LONG_MAX__ 0x7fffffffffffffffLLUART_FIFOLVL_TX(n) ((uint32_t)(((n)>>8)&0x0F))__WINT_WIDTH__ 32UART_SYNCCTRL_CSCEN (1 << 4)SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__CGU_BASE_CGU_OUT0_CLK MMIO32(CGU_BASE + 0x0C4)UART_LCR_WLEN6 (1 << 0)CGU_BASE_USB0_CLK_PD (1 << CGU_BASE_USB0_CLK_PD_SHIFT)BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN__UART_FCR_DMAMODE_SEL (1 << 3)__SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)CGU_BASE_CGU_OUT1_CLK_CLK_SEL(x) ((x) << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT)__DBL_MIN_EXP__ (-1021)__LDBL_HAS_DENORM__ 1INT_FAST32_MIN (-INT_FAST32_MAX - 1)GPIO_GROUP1_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x09000)UART_LCR_BITMASK ((uint8_t)(0xFF))CGU_PLL1_STAT_LOCK (1 << CGU_PLL1_STAT_LOCK_SHIFT)__FLT32_DIG__ 6INT_LEAST16_MAXCGU_BASE_M4_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_M4_CLK_CLK_SEL_SHIFT)CGU_PLL0USB_STAT_LOCK (1 << CGU_PLL0USB_STAT_LOCK_SHIFT)CGU_IDIVD_CTRL_PD (1 << CGU_IDIVD_CTRL_PD_SHIFT)BIT15 (1<<15)BACKUP_REG_BASE (0x40041000U)CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK (1 << CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_SHIFT)CGU_PLL0AUDIO_CTRL_DIRECTI (1 << CGU_PLL0AUDIO_CTRL_DIRECTI_SHIFT)UART_SRC_PLL1 0x09CGU_IDIVC_CTRL_AUTOBLOCK (1 << CGU_IDIVC_CTRL_AUTOBLOCK_SHIFT)BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1GPIO_GROUP0_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x08000)uart_read_timeoutINT32_MAXCGU_PLL0AUDIO_CTRL_DIRECTO (1 << CGU_PLL0AUDIO_CTRL_DIRECTO_SHIFT)__ACCUM_MIN__ (-0X1P15K-0X1P15K)uart_databit_tCGU_BASE_SDIO_CLK MMIO32(CGU_BASE + 0x090)UART_SRC_PLL0AUDIO 0x08__ARM_FEATURE_CRYPTOCGU_IDIVB_CTRL_CLK_SEL(x) ((x) << CGU_IDIVB_CTRL_CLK_SEL_SHIFT)__INT_LEAST32_TYPE__ long intCGU_BASE_LCD_CLK_CLK_SEL(x) ((x) << CGU_BASE_LCD_CLK_CLK_SEL_SHIFT)CGU_PLL1_CTRL_PSEL_MASK (0x3 << CGU_PLL1_CTRL_PSEL_SHIFT)CGU_PLL0AUDIO_MDIV_MDEC_MASK (0x1ffff << CGU_PLL0AUDIO_MDIV_MDEC_SHIFT)UART_PARITY_NONECGU_BASE_APB1_CLK_CLK_SEL_SHIFT (24)BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULLCGU_BASE_CGU_OUT0_CLK_PD (1 << CGU_BASE_CGU_OUT0_CLK_PD_SHIFT)__FRACT_IBIT__ 0I2C1_BASE (PERIPH_BASE_APB3 + 0x00000)UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2CGU_SRC_IDIVA 0x0CBIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234SIZE_MAX __SIZE_MAX____FLT_NORM_MAX__ 3.4028234663852886e+38Flong long unsigned intUART_CGU_BASE_CLK_SEL_SHIFT 24__FLT_MIN_10_EXP__ (-37)BIT31 (1<<31)CGU_BASE_USB0_CLK MMIO32(CGU_BASE + 0x060)__ULACCUM_IBIT__ 32UART_NO_ERROR__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2UART_LOAD_DLM(div) (((div) >> 8) & 0xFF)__ULLACCUM_EPSILON__ 0x1P-32ULLK__APCS_32__ 1__DQ_FBIT__ 63INT_LEAST64_MAX__SACCUM_IBIT__ 8CGU_BASE_SSP1_CLK_AUTOBLOCK (1 << CGU_BASE_SSP1_CLK_AUTOBLOCK_SHIFT)UART_LCR_PARITY_EN (1 << 3)__UHQ_IBIT__ 0CGU_BASE_SPI_CLK_CLK_SEL(x) ((x) << CGU_BASE_SPI_CLK_CLK_SEL_SHIFT)INT_LEAST8_MINCGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT (24)CGU_BASE_SDIO_CLK_AUTOBLOCK (1 << CGU_BASE_SDIO_CLK_AUTOBLOCK_SHIFT)BIT29 (1<<29)__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1__INT_FAST16_TYPE__ intUART_ACR_START (1 << 0)INT64_C__ULFRACT_MAX__ 0XFFFFFFFFP-32ULR__UINT_LEAST16_TYPE__ short unsigned intINT_FAST16_MIN (-INT_FAST16_MAX - 1)__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned intUART_LSR_BITMASK ((uint8_t)(0xFF))__FLT32X_DIG__ 15CGU_BASE_SSP0_CLK_CLK_SEL(x) ((x) << CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT)__UTQ_FBIT__ 128UART_LCR_NO_PARITY (0 << 3)CGU_PLL0AUDIO_CTRL_MOD_PD_SHIFT (14)CGU_BASE_USB1_CLK_AUTOBLOCK_SHIFT (11)__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffffUART2_NUMCGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT (24)UART_LCR_TWO_STOPBIT (1 << 2)CGU_BASE_UART2_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART2_CLK_CLK_SEL_SHIFT)PTRDIFF_MAX __PTRDIFF_MAX____SIZEOF_SHORT__ 2CGU_BASE_VADC_CLK_PD (1 << CGU_BASE_VADC_CLK_PD_SHIFT)CGU_IDIVA_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVA_CTRL_CLK_SEL_SHIFT)CGU_BASE_SAFE_CLK MMIO32(CGU_BASE + 0x05C)CGU_PLL0USB_CTRL_DIRECTI (1 << CGU_PLL0USB_CTRL_DIRECTI_SHIFT)__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKCGU_BASE_M4_CLK_AUTOBLOCK (1 << CGU_BASE_M4_CLK_AUTOBLOCK_SHIFT)CGU_PLL1_CTRL_BYPASS_SHIFT (1)UART_SRC_IDIVB 0x0DCGU_IDIVE_CTRL_IDIV_SHIFT (2)UINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRuart_error_tCGU_BASE_UART0_CLK MMIO32(CGU_BASE + 0x09C)__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVECGU_IDIVA_CTRL_IDIV(x) ((x) << CGU_IDIVA_CTRL_IDIV_SHIFT)CGU_PLL0USB_MDIV_SELR_SHIFT (28)SSP0_BASE (PERIPH_BASE_APB0 + 0x03000)UART_THR_MASKBIT ((uint8_t)0xFF)UART_RBR(port) MMIO32((port) + 0x000)QEI_BASE (PERIPH_BASE_APB2 + 0x06000)WCHAR_MINCGU_SRC_ENET_RX 0x02BEGIN_DECLS CGU_IDIVD_CTRL_IDIV_SHIFT (2)CGU_PLL1_CTRL_CLK_SEL_SHIFT (24)CGU_BASE_PHY_RX_CLK_PD (1 << CGU_BASE_PHY_RX_CLK_PD_SHIFT)UART_ACR_ABEOINT_CLR (1 << 8)CGU_BASE_UART1_CLK_PD (1 << CGU_BASE_UART1_CLK_PD_SHIFT)CGU_BASE_UART3_CLK MMIO32(CGU_BASE + 0x0A8)__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15UART_FCR_TRG_LEV3 (3 << 6)__FLT32X_MAX__ 1.7976931348623157e+308F32xCGU_PLL0USB_STAT_LOCK_SHIFT (0)__ARM_EABI__ 1CGU_PLL0USB_STAT_FR (1 << CGU_PLL0USB_STAT_FR_SHIFT)__UACCUM_IBIT__ 16INT16_MININTPTR_MIN__FLT_IS_IEC_60559__ 2__THUMBEL__ 1CGU_BASE_USB0_CLK_AUTOBLOCK (1 << CGU_BASE_USB0_CLK_AUTOBLOCK_SHIFT)__ARM_FEATURE_DSP 1CGU_SRC_PLL0AUDIO 0x08CGU_PLL1_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL1_CTRL_CLK_SEL_SHIFT)CGU_BASE_UART3_CLK_CLK_SEL_SHIFT (24)CGU_BASE_SPIFI_CLK MMIO32(CGU_BASE + 0x070)__QQ_IBIT__ 0CGU_IDIVC_CTRL MMIO32(CGU_BASE + 0x050)CGU_PLL0AUDIO_NP_DIV MMIO32(CGU_BASE + 0x038)CGU_BASE_VADC_CLK_CLK_SEL_SHIFT (24)data_nb_bitsUART_RX_NO_DATA__LLACCUM_FBIT__ 31CGU_BASE_UART2_CLK_PD_SHIFT (0)UART_RBR_MASKBIT ((uint8_t)0xFF)__UINTMAX_TYPE__ long long unsigned intCGU_PLL1_CTRL_AUTOBLOCK (1 << CGU_PLL1_CTRL_AUTOBLOCK_SHIFT)CGU_BASE_PHY_TX_CLK_AUTOBLOCK_SHIFT (11)__USQ_IBIT__ 0CGU_BASE_USB1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_USB1_CLK_CLK_SEL_SHIFT)UART_HDEN(port) MMIO32((port) + 0x040)__ARM_FEATURE_NUMERIC_MAXMIN__INTMAX_TYPE__ long long intCGU_BASE_UART0_CLK_PD (1 << CGU_BASE_UART0_CLK_PD_SHIFT)__GCC_ATOMIC_INT_LOCK_FREE 2CGU_IDIVC_CTRL_CLK_SEL(x) ((x) << CGU_IDIVC_CTRL_CLK_SEL_SHIFT)CGU_BASE_SPI_CLK_AUTOBLOCK_SHIFT (11)__UINT_FAST32_MAX__ 0xffffffffUINTMAX_MAXUART_LCR_WLEN5 (0 << 0)TIMER2_BASE (PERIPH_BASE_APB2 + 0x03000)CGU_PLL0AUDIO_CTRL_DIRECTI_SHIFT (2)CGU_PLL1_CTRL_BYPASS (1 << CGU_PLL1_CTRL_BYPASS_SHIFT)__ARM_FEATURE_FP16_SCALAR_ARITHMETIC__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1CGU_PLL1_CTRL_MSEL_SHIFT (16)UART_THR(port) MMIO32((port) + 0x000)__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CCGU_BASE_CGU_OUT1_CLK_PD (1 << CGU_BASE_CGU_OUT1_CLK_PD_SHIFT)CGU_BASE_SSP0_CLK_AUTOBLOCK_SHIFT (11)CGU_PLL0AUDIO_NP_DIV_NDEC_MASK (0x3ff << CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT)UART_IER_THREINT_EN (1 << 1)INT64_MIN__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intCGU_BASE_APB1_CLK_AUTOBLOCK (1 << CGU_BASE_APB1_CLK_AUTOBLOCK_SHIFT)CGU_IDIVC_CTRL_IDIV_MASK (0xf << CGU_IDIVC_CTRL_IDIV_SHIFT)UINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRCGU_BASE_LCD_CLK_PD_SHIFT (0)__SIZEOF_SIZE_T__ 4PMC_BASE (0x40042000U)uint16_t__INT64_C(c) c ## LLCGU_IDIVB_CTRL_IDIV(x) ((x) << CGU_IDIVB_CTRL_IDIV_SHIFT)CGU_PLL0USB_NP_DIV_NDEC_MASK (0x3ff << CGU_PLL0USB_NP_DIV_NDEC_SHIFT)CGU_BASE_SSP1_CLK_AUTOBLOCK_SHIFT (11)CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ (1 << CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_SHIFT)UART1_BASE (PERIPH_BASE_APB0 + 0x02000)__LDBL_MIN__ 2.2250738585072014e-308LCGU_PLL0AUDIO_NP_DIV_NDEC(x) ((x) << CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT)__ARM_FEATURE_CDE__ACCUM_IBIT__ 16CGU_BASE_SPIFI_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT)CGU_PLL1_CTRL_PD_SHIFT (0)CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT (24)CGU_BASE_USB1_CLK_CLK_SEL_SHIFT (24)CGU_BASE_APB3_CLK_CLK_SEL_SHIFT (24)CGU_PLL0AUDIO_MDIV MMIO32(CGU_BASE + 0x034)CGU_BASE_OUT_CLK_AUTOBLOCK_SHIFT (11)CGU_LPC43XX_CGU_H short intCGU_BASE_APLL_CLK_AUTOBLOCK_SHIFT (11)CGU_BASE_APB1_CLK_PD (1 << CGU_BASE_APB1_CLK_PD_SHIFT)CGU_BASE_USB1_CLK_AUTOBLOCK (1 << CGU_BASE_USB1_CLK_AUTOBLOCK_SHIFT)__UINT16_C(c) cCGU_OUTCLK_23_CTRL MMIO32(CGU_BASE + 0x0B8)CGU_PLL0AUDIO_CTRL_CLK_SEL(x) ((x) << CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT)__UDA_IBIT__ 32UART_IER(port) MMIO32((port) + 0x004)UINT_LEAST32_MAXCGU_BASE_APLL_CLK_PD_SHIFT (0)UART_SCR_BIMASK ((uint8_t)(0xFF))BIT2 (1<<2)__ATOMIC_RELAXED 0__ARM_FEATURE_COPROCCGU_BASE_VADC_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_VADC_CLK_CLK_SEL_SHIFT)__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53UART_LCR_PARITY_EVEN (1 << 4)LPC43XX_M4 1UART_FCR_BITMASK ((uint8_t)(0xCF))BIT5 (1<<5)CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT (24)BIT1 (1<<1)INT8_CINT_LEAST32_MAX__USES_INITFINI__ 1I2S1_BASE (PERIPH_BASE_APB1 + 0x03000)INTMAX_MAX __INTMAX_MAX____DBL_DECIMAL_DIG__ 17CGU_BASE_SSP1_CLK_PD_SHIFT (0)BIT8 (1<<8)UART_LSR_RDR (1 << 0)CGU_BASE_SSP1_CLK MMIO32(CGU_BASE + 0x098)__ULACCUM_FBIT__ 32INT16_C(c) __INT16_C(c)CGU_BASE_LCD_CLK_AUTOBLOCK (1 << CGU_BASE_LCD_CLK_AUTOBLOCK_SHIFT)CGU_BASE_LCD_CLK MMIO32(CGU_BASE + 0x088)CGU_BASE_CGU_OUT1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT)__INT16_MAX__ 0x7fffUART_FDR(port) MMIO32((port) + 0x028)CGU_BASE_PERIPH_CLK MMIO32(CGU_BASE + 0x064)CGU_BASE_SAFE_CLK_AUTOBLOCK_SHIFT (11)CGU_IDIVA_CTRL_CLK_SEL_SHIFT (24)CGU_XTAL_OSC_CTRL_ENABLE (1 << CGU_XTAL_OSC_CTRL_ENABLE_SHIFT)__INT_WIDTH__ 32__ARM_FEATURE_SIMD32 1UART_LCR_PARITY_SP_0 ((1 << 5) | (1 << 4))CGU_IDIVA_CTRL_AUTOBLOCK_SHIFT (11)CGU_BASE_UART1_CLK MMIO32(CGU_BASE + 0x0A0)__QQ_FBIT__ 7RITIMER_BASE (PERIPH_BASE_APB2 + 0x00000)CGU_SRC_IDIVD 0x0F__SIG_ATOMIC_WIDTH__ 32CGU_IDIVC_CTRL_CLK_SEL_SHIFT (24)__FLT64_EPSILON__ 2.2204460492503131e-16F64CGU_BASE_UART1_CLK_PD_SHIFT (0)CGU_BASE_UART1_CLK_AUTOBLOCK_SHIFT (11)__UTA_IBIT__ 64__ULLACCUM_IBIT__ 32RGU_BASE (0x40053000U)__ULLFRACT_EPSILON__ 0x1P-64ULLRfalse 0UART2 USART2_BASE__SIZEOF_WINT_T__ 4INT_LEAST64_MIN__ARM_FEATURE_UNALIGNED 1__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17CGU_PLL0AUDIO_CTRL_MOD_PD (1 << CGU_PLL0AUDIO_CTRL_MOD_PD_SHIFT)UART1_NUM__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1CGU_IDIVC_CTRL_IDIV(x) ((x) << CGU_IDIVC_CTRL_IDIV_SHIFT)__FLT32X_HAS_DENORM__ 1CGU_IDIVB_CTRL_IDIV_MASK (0xf << CGU_IDIVB_CTRL_IDIV_SHIFT)__ULLACCUM_MIN__ 0.0ULLK__FLT32_EPSILON__ 1.1920928955078125e-7F32CGU_IDIVE_CTRL_IDIV(x) ((x) << CGU_IDIVE_CTRL_IDIV_SHIFT)CGU_IDIVA_CTRL_CLK_SEL(x) ((x) << CGU_IDIVA_CTRL_CLK_SEL_SHIFT)CGU_PLL0AUDIO_STAT MMIO32(CGU_BASE + 0x02C)CGU_PLL0USB_MDIV_SELI(x) ((x) << CGU_PLL0USB_MDIV_SELI_SHIFT)UART_IIR_ABTO_INT (1 << 9)UART_IIR_INTID_RDA (2 << 1)__ARM_ASM_SYNTAX_UNIFIED__ 1CGU_PLL0AUDIO_MDIV_MDEC(x) ((x) << CGU_PLL0AUDIO_MDIV_MDEC_SHIFT)UART_STOPBIT_1UART_STOPBIT_2__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODCGU_IDIVE_CTRL MMIO32(CGU_BASE + 0x058)RTC_BASE (0x40046000U)UART_SCICTRL(port) MMIO32((port) + 0x048)data_nb_stopCGU_PLL1_CTRL_NSEL_SHIFT (12)UART_OSR(port) MMIO32((port) + 0x02C)CGU_PLL0AUDIO_CTRL_CLKEN (1 << CGU_PLL0AUDIO_CTRL_CLKEN_SHIFT)__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H CGU_FREQ_MON_MEAS (1 << CGU_FREQ_MON_MEAS_SHIFT)AES_BASE (0x400F1000U)__UDQ_IBIT__ 0__GCC_CONSTRUCTIVE_SIZE 64CGU_BASE_VADC_CLK_AUTOBLOCK (1 << CGU_BASE_VADC_CLK_AUTOBLOCK_SHIFT)__LLFRACT_IBIT__ 0CGU_IDIVB_CTRL_AUTOBLOCK (1 << CGU_IDIVB_CTRL_AUTOBLOCK_SHIFT)UART_RX_DATA_READYuint32_tBIT12 (1<<12)UART_SCICTRL_NACKDIS (1 << 1)__SACCUM_EPSILON__ 0x1P-7HK__GCC_ASM_FLAG_OUTPUTS__ 1uart_mulvalCGU_BASE_APLL_CLK_CLK_SEL(x) ((x) << CGU_BASE_APLL_CLK_CLK_SEL_SHIFT)__ARM_FP 4CGU_BASE_LCD_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_LCD_CLK_CLK_SEL_SHIFT)__UINT_FAST16_TYPE__ unsigned intCGU_BASE_SAFE_CLK_AUTOBLOCK (1 << CGU_BASE_SAFE_CLK_AUTOBLOCK_SHIFT)__UHA_IBIT__ 8UART_ACR_AUTO_RESTART (1 << 2)__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULKUART_TER(port) MMIO32((port) + 0x05C)__LDBL_DIG__ 15CGU_BASE_SSP1_CLK_PD (1 << CGU_BASE_SSP1_CLK_PD_SHIFT)UART_LSR_OE (1 << 1)UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXBIT16 (1<<16)__WINT_MIN__ 0UINT_LEAST16_MINUART_SRC_IDIVE 0x10__FLT64_DIG__ 15UART_LCR(port) MMIO32((port) + 0x00C)BIT22 (1<<22)__INT_LEAST8_WIDTH__ 8CGU_PLL0USB_CTRL MMIO32(CGU_BASE + 0x020)UART_IER_RLSINT_EN (1 << 2)CGU_BASE_PHY_TX_CLK_CLK_SEL(x) ((x) << CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT)__INT_LEAST16_TYPE__ short intCGU_PLL0USB_NP_DIV MMIO32(CGU_BASE + 0x028)UART_ICR_PULSEDIV(n) ((uint32_t)(((n)&0x07)<<3))CGU_PLL0USB_CTRL_DIRECTO_SHIFT (3)__DBL_MAX__ ((double)1.7976931348623157e+308L)CGU_SRC_IDIVC 0x0EINT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1UINTMAX_CUART_DLM(port) MMIO32((port) + 0x004)CGU_PLL0AUDIO_CTRL_FRM_SHIFT (6)CGU_PLL0USB_CTRL_CLK_SEL(x) ((x) << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT)INT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1UART_FDR_DIVADDVAL(n) ((uint32_t)((n)&0x0F))__UINTPTR_MAX__ 0xffffffffUUART_SYNCCTRL_CCCLR (1 << 6)__HQ_FBIT__ 15__bool_true_false_are_defined 1USART2_BASE (PERIPH_BASE_APB2 + 0x01000)CGU_BASE_UART2_CLK MMIO32(CGU_BASE + 0x0A4)BIT26 (1<<26)__SIZE_MAX__ 0xffffffffUCGU_BASE_UART0_CLK_CLK_SEL_SHIFT (24)CGU_BASE_SPIFI_CLK_PD_SHIFT (0)UART_DLL(port) MMIO32((port) + 0x000)UART_ICR_FIXPULSE_EN (1 << 2)CGU_BASE_CGU_OUT0_CLK_PD_SHIFT (0)__ARM_ARCH__LONG_MAX__ 0x7fffffffLMCPWM_BASE (PERIPH_BASE_APB1 + 0x00000)CGU_BASE_CGU_OUT0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT)LPC43XX_MEMORYMAP_H __ARM_FEATURE_LDREX 7UART_PARITY_SP_0PTRDIFF_MAXCGU_BASE_APB3_CLK MMIO32(CGU_BASE + 0x084)CGU_PLL0USB_MDIV_SELP_SHIFT (17)__LLFRACT_EPSILON__ 0x1P-63LLRCGU_PLL0USB_NP_DIV_NDEC(x) ((x) << CGU_PLL0USB_NP_DIV_NDEC_SHIFT)__SFRACT_MAX__ 0X7FP-7HR__FLT32X_MANT_DIG__ 53CGU_BASE_APB1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_APB1_CLK_CLK_SEL_SHIFT)uart_val__WCHAR_WIDTH__ 32WINT_MAX__INT16_C(c) cUART1_IIR_INTID_MODEM (0 << 1)UART1 UART1_BASEWCHAR_MAX __WCHAR_MAX__UART_LCR_ONE_STOPBIT (0 << 2)UART_IIR_INTID_THRE (1 << 1)UART_IIR_INTID_MASK (7 << 1)__ATOMIC_ACQ_REL 4ADC1_BASE (PERIPH_BASE_APB3 + 0x04000)__INT32_TYPE__ long int__DBL_MIN_10_EXP__ (-307)dataCGU_BASE_PERIPH_CLK_PD_SHIFT (0)CGU_BASE_LCD_CLK_CLK_SEL_SHIFT (24)CGU_BASE_VADC_CLK MMIO32(CGU_BASE + 0x08C)__FLT32_NORM_MAX__ 3.4028234663852886e+38F32UINT64_C(c) __UINT64_C(c)CGU_BASE_UART3_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART3_CLK_CLK_SEL_SHIFT)CGU_PLL0AUDIO_CTRL_PD (1 << CGU_PLL0AUDIO_CTRL_PD_SHIFT)CGU_BASE_USB1_CLK_PD (1 << CGU_BASE_USB1_CLK_PD_SHIFT)__UINTMAX_MAX__ 0xffffffffffffffffULL__DBL_MANT_DIG__ 53__ULFRACT_IBIT__ 0INT_FAST16_MAXUART_CGU_AUTOBLOCK_CLOCK_BIT 11__INT_MAX__ 0x7fffffff__INT_LEAST64_TYPE__ long long intUART_TER_TXEN (1 << 0)__ARM_FEATURE_CDE_COPROCCGU_PLL0USB_CTRL_BYPASS (1 << CGU_PLL0USB_CTRL_BYPASS_SHIFT)UART_SRC_ENET_TX 0x03UINT32_CGCC: (15:12.2.rel1-1) 12.2.1 20221205 | A  2A A3aeabi)7E-M M  "      .0 "$&(*,25f.]14 2uart.c$t$dwm4.0.ac8f3cbd7733ee78183be95102ca936awm4.common.h.21.c9066c2f6b12c71b40226ea6107829a4wm4.stdint.h.29.6d480f4ba0f60596e88234283d42444fwm4.stdbool.h.29.4a1c88fe569adb8d03217dd16982ca34wm4.common.h.67.5c568a1f62c8e726909b04e29f9e1fc0wm4.memorymap.h.22.395ffb693017d551ed93d11c39ba4361wm4.uart.h.29.91cd6c3f394a9fd992df7cfff7c074edwm4.cgu.h.37.c480a83e7590bba775f2472229e8edb0uart_initdummy_readuart_rx_data_readyuart_readuart_read_timeoutuart_write6 "&-4;BGTYfkx (1:CMdjq6 #(26;HRV[einx| $(-7;AHS`jns}  F n      -Pq  ( 0   &$-3<B K!RX^djpv| #)/5;AGMSY_ekqw} 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__UINTPTR_MAX____ARM_ARCH_PROFILE 77TIMER1_CCR TIMER_CCR(TIMER1)__FLT64_MAX_10_EXP__ 308MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINTIMER_CTCR_CINSEL_CAPN_3 (0x3 << 2)__INT_FAST32_WIDTH__ 32CGU_BASE (0x40050000U)__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38__FRACT_MAX__ 0X7FFFP-15RTIMER3_PR TIMER_PR(TIMER3)GNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -O2 -std=c99 -fno-common -ffunction-sections -fdata-sectionsINT_LEAST32_MAX __INT_LEAST32_MAX__TIMER_EMR_EM2 (1 << 2)__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5TIMER_CTCR_MODE_MASK (0x3 << 0)__UINT16_MAX__ 0xffff__TQ_FBIT__ 127TIMER1_MR2 TIMER_MR2(TIMER1)__USQ_FBIT__ 32TIMER_EMR(timer) MMIO32((timer) + 0x03C)__USES_INITFINI__ 1__thumb2__ 1__ULLACCUM_FBIT__ 32TIMER3_IR TIMER_IR(TIMER3)TIMER_CCR_CAP0I (1 << 2)INT_FAST32_MIN (-INT_FAST32_MAX - 1)__STRICT_ANSI__ 1TIMER1_MCR TIMER_MCR(TIMER1)TIMER0_MR2 TIMER_MR2(TIMER0)TIMER_CTCR_CINSEL_CAPN_1 (0x1 << 2)UINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8TIMER_EMR_EMC_TOGGLE 0x3__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX____USA_IBIT__ 16__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1PTRDIFF_MIN (-PTRDIFF_MAX - 1)TIMER_MCR_MR3S (1 << 11)__UINT_FAST64_TYPE__ long long unsigned int__FLT_MIN__ 1.1754943508222875e-38F__HA_FBIT__ 7BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)__FDPIC____FLT32_IS_IEC_60559__ 2TIMER3_CR2 TIMER_CR2(TIMER3)INT_FAST64_MINADC0_BASE (PERIPH_BASE_APB3 + 0x03000)__USFRACT_IBIT__ 0__LDBL_EPSILON__ 2.2204460492503131e-16LTIMER0_MR1 TIMER_MR1(TIMER0)__USFRACT_MIN__ 0.0UHR__ARM_NEONTIMER_CCR_CAP3I (1 << 11)__UINT8_MAX__ 0xffTIMER_IR_MR1INT (1 << 1)__LDBL_MAX_EXP__ 1024__DBL_HAS_DENORM__ 1TIMER2_PC TIMER_PC(TIMER2)__DA_FBIT__ 31__GXX_ABI_VERSION 1017__INT_LEAST16_MAX__ 0x7fff__FLT_DENORM_MIN__ 1.4012984643248171e-45FTIMER0_CR1 TIMER_CR1(TIMER0)INT_LEAST8_MAX __INT_LEAST8_MAX__DAC_BASE (PERIPH_BASE_APB3 + 0x01000)__UINT32_C(c) c ## UL__UACCUM_MIN__ 0.0UK__FLT_EPSILON__ 1.1920928955078125e-7FTIMER2_CR1 TIMER_CR1(TIMER2)TIMER_MCR_MR0I (1 << 0)__PTRDIFF_TYPE__ int__ARM_ARCH_ISA_THUMBTIMER_TC(timer) MMIO32((timer) + 0x008)TIMER_CCR_CAP0FE (1 << 1)__GCC_ATOMIC_SHORT_LOCK_FREE 2input__USACCUM_FBIT__ 8__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1__LACCUM_FBIT__ 31TIMER_CCR(timer) MMIO32((timer) + 0x028)__FLT32_HAS_QUIET_NAN__ 1__ARM_FEATURE_MATMUL_INT8TIMER_IR_CR3INT (1 << 7)__LDBL_HAS_INFINITY__ 1__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))CCU1_BASE (0x40051000U)TIMER_CCR_CAP0RE (1 << 0)__FLT32X_MAX_10_EXP__ 308TIMER_EMR_EMC2_MASK (0x3 << TIMER_EMR_EMC2_SHIFT)__ARM_ARCH_EXT_IDIV__ 1bool _BoolUINTMAX_MAX __UINTMAX_MAX____SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffTIMER3_PC TIMER_PC(TIMER3)INT16_MAX __INT16_MAX____FP_FAST_FMAF 1__FLT32X_IS_IEC_60559__ 2PERIPH_BASE_APB3 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(0x40044000U)__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN____USFRACT_FBIT__ 8LPC43XX_TIMER_H BIT28 (1<<28)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2INTMAX_C(c) __INTMAX_C(c)__DBL_MAX_EXP__ 1024__ATOMIC_RELEASE 3UINT_FAST8_MAX__FLT_MANT_DIG__ 24__UDQ_IBIT__ 0TIMER3_MR0 TIMER_MR0(TIMER3)TIMER3_CR3 TIMER_CR3(TIMER3)CCU2_BASE (0x40052000U)__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UK__FLT64_NORM_MAX__ 1.7976931348623157e+308F64PERIPH_BASE_APB1 (0x400A0000U)__FINITE_MATH_ONLY__ 0TIMER2_CR0 TIMER_CR0(TIMER2)__LDBL_DENORM_MIN__ 4.9406564584124654e-324LTIMER3_BASE (PERIPH_BASE_APB2 + 0x04000)__INT64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_SAT 1__ULLFRACT_IBIT__ 0SPI_PORT_BASE (0x40100000U)MMIO16(addr) (*(volatile uint16_t *)(addr))TIMER_CTCR_MODE_COUNTER_BOTH (0x3 << 0)TIMER2 TIMER2_BASELPC43XX 1__GNUC__ 12TIMER_MCR_MR3R (1 << 10)WCHAR_MAX__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16__UFRACT_EPSILON__ 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0XFFFFP-16URTIMER0_IR TIMER_IR(TIMER0)INT64_MAXINT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0SSP1_BASE (PERIPH_BASE_APB2 + 0x05000)SPIFI_BASE (PERIPH_BASE_AHB + 0x03000)TIMER1_CR1 TIMER_CR1(TIMER1)__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__TIMER_MR0(timer) MMIO32((timer) + 0x018)count__UFRACT_FBIT__ 16__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)__LDBL_MAX_10_EXP__ 308TIMER_CTCR_MODE_TIMER (0x0 << 0)__INT_FAST32_TYPE__ intunsigned int__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1__USACCUM_IBIT__ 8__ARM_ARCH_7EM__ 1__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UK__FLT_EVAL_METHOD__ 0GPIO_PORT_BASE (0x400F4000U)__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32__ARM_FEATURE_LDREX__UQQ_FBIT__ 8INT16_CTIMER_CCR_CAP1I (1 << 5)__ARM_FP16_ARGS__GCC_IEC_559 0INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX__TIMER3_CR1 TIMER_CR1(TIMER3)__LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4__STDC__ 1TIMER_MCR_MR0S (1 << 2)__ARM_FEATURE_IDIV 1__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN____UINT8_TYPE__ unsigned char__ARM_FEATURE_COPROC 15UINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"INT8_MINTIMER_PR(timer) MMIO32((timer) + 0x00C)true 1__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)TIMER_TCR_CEN (1 << 0)__LDBL_MIN_10_EXP__ (-307)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1__GCC_ATOMIC_CHAR_LOCK_FREE 2TIMER0_CCR TIMER_CCR(TIMER0)__LFRACT_EPSILON__ 0x1P-31LRTIMER0_TCR TIMER_TCR(TIMER0)__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX__TIMER_CCR_CAP3RE (1 << 9)__FLT32X_NORM_MAX__ 1.7976931348623157e+308F32x__arm__ 1INT_FAST64_MAX__FLT32_MIN_10_EXP__ (-37)MMIO64(addr) (*(volatile uint64_t *)(addr))INT8_MAX __INT8_MAX____ARM_FP16_FORMAT_ALTERNATIVE__LDBL_NORM_MAX__ 1.7976931348623157e+308LINTPTR_MIN__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)__TA_IBIT__ 64__FLT32_MIN__ 1.1754943508222875e-38F32TIMER3_MR1 TIMER_MR1(TIMER3)TIMER0_PC TIMER_PC(TIMER0)PERIPH_BASE_AHB (0x40000000U)TIMER0_PR TIMER_PR(TIMER0)__ARM_FEATURE_QRDMXTIMER0_MR3 TIMER_MR3(TIMER0)__LONG_LONG_MAX__ 0x7fffffffffffffffLLTIMER_MCR_MR1I (1 << 3)__WINT_WIDTH__ 32SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__TIMER0_MCR TIMER_MCR(TIMER0)BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN____SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__DBL_MIN_EXP__ (-1021)__LDBL_HAS_DENORM__ 1TIMER1_TC TIMER_TC(TIMER1)INT8_MIN (-INT8_MAX - 1)GPIO_GROUP1_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x09000)__FLT32_DIG__ 6INT_LEAST16_MAXBIT15 (1<<15)BACKUP_REG_BASE (0x40041000U)TIMER_IR_CR0INT (1 << 4)BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1GPIO_GROUP0_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x08000)__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1INT32_MAX__ACCUM_MIN__ (-0X1P15K-0X1P15K)TIMER2_MR0 TIMER_MR0(TIMER2)__ARM_FEATURE_CRYPTO__INT_LEAST32_TYPE__ long inttimer_resetBIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULLTIMER_IR(timer) MMIO32((timer) + 0x000)__FRACT_IBIT__ 0I2C1_BASE (PERIPH_BASE_APB3 + 0x00000)TIMER1_CR0 TIMER_CR0(TIMER1)UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234__FLT_NORM_MAX__ 3.4028234663852886e+38Flong long unsigned int__FLT_MIN_10_EXP__ (-37)BIT31 (1<<31)__ULACCUM_IBIT__ 32__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__ULLACCUM_EPSILON__ 0x1P-32ULLK__APCS_32__ 1__DQ_FBIT__ 63INT_LEAST64_MAX__SACCUM_IBIT__ 8__UHQ_IBIT__ 0INT_LEAST8_MINBIT29 (1<<29)__INT_FAST16_TYPE__ intINT64_C__ULFRACT_MAX__ 0XFFFFFFFFP-32ULRtimer_set_prescaler__UINT_LEAST16_TYPE__ short unsigned int__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned int__FLT32X_DIG__ 15__UTQ_FBIT__ 128TIMER_MR3(timer) MMIO32((timer) + 0x024)TIMER_CR2(timer) MMIO32((timer) + 0x034)timer_peripheralTIMER1_CR2 TIMER_CR2(TIMER1)__INT_FAST16_MAX__ 0x7fffffffTIMER_EMR_EMC0_MASK (0x3 << TIMER_EMR_EMC0_SHIFT)PTRDIFF_MAX __PTRDIFF_MAX____SIZEOF_SHORT__ 2TIMER_PC(timer) MMIO32((timer) + 0x010)TIMER_IR_MR0INT (1 << 0)__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKUINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRTIMER_IR_MR3INT (1 << 3)__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intSSP0_BASE (PERIPH_BASE_APB0 + 0x03000)TIMER1_CTCR TIMER_CTCR(TIMER1)TIMER0_TC TIMER_TC(TIMER0)QEI_BASE (PERIPH_BASE_APB2 + 0x06000)WCHAR_MINBEGIN_DECLS TIMER_CTCR_CINSEL_CAPN_2 (0x2 << 2)TIMER2_TCR TIMER_TCR(TIMER2)__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__FLT32X_MAX__ 1.7976931348623157e+308F32x__ARM_EABI__ 1INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1__ARM_FEATURE_DSP 1USART3_BASE (PERIPH_BASE_APB2 + 0x02000)__QQ_IBIT__ 0__LLACCUM_FBIT__ 31__UINTMAX_TYPE__ long long unsigned int__USQ_IBIT__ 0__UINT_LEAST32_TYPE__ long unsigned int__ARM_FEATURE_NUMERIC_MAXMINTIMER1_IR TIMER_IR(TIMER1)__INTMAX_TYPE__ long long intUINTPTR_MAX__GCC_ATOMIC_INT_LOCK_FREE 2INTMAX_MAXTIMER_CTCR_CINSEL_CAPN_0 (0x0 << 2)TIMER2_BASE (PERIPH_BASE_APB2 + 0x03000)__ARM_FEATURE_FP16_SCALAR_ARITHMETICTIMER_EMR_EM1 (1 << 1)__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1__FLT64_HAS_INFINITY__ 1TIMER3_CCR TIMER_CCR(TIMER3)__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CINT64_MINTIMER_EMR_EMC3_SHIFT 10__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intUINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRTIMER2_CR3 TIMER_CR3(TIMER2)__SIZEOF_SIZE_T__ 4PMC_BASE (0x40042000U)TIMER_CCR_CAP3FE (1 << 10)__INT64_C(c) c ## LLUART1_BASE (PERIPH_BASE_APB0 + 0x02000)__LDBL_MIN__ 2.2250738585072014e-308L__ARM_FEATURE_CDE__ACCUM_IBIT__ 16TIMER3_MR2 TIMER_MR2(TIMER3)timer_disable_countershort int__UINT16_C(c) cTIMER_EMR_EMC1_SHIFT 6__UDA_IBIT__ 32modeUINT_LEAST32_MAXTIMER_EMR_EMC3_MASK (0x3 << TIMER_EMR_EMC3_SHIFT)BIT2 (1<<2)__ATOMIC_RELAXED 0__ARM_FEATURE_COPROC__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53TIMER3 TIMER3_BASE__ARM_FEATURE_FMA 1LPC43XX_M4 1BIT5 (1<<5)__GNUC_PATCHLEVEL__ 1BIT1 (1<<1)INT8_CINT_LEAST32_MAX__SIZEOF_FLOAT__ 4I2S1_BASE (PERIPH_BASE_APB1 + 0x03000)timer_set_count_input__DBL_DECIMAL_DIG__ 17BIT8 (1<<8)INT16_C(c) __INT16_C(c)__INT16_MAX__ 0x7fff__INT_WIDTH__ 32__ARM_FEATURE_SIMD32 1TIMER2_MR1 TIMER_MR1(TIMER2)__QQ_FBIT__ 7RITIMER_BASE (PERIPH_BASE_APB2 + 0x00000)UINT_LEAST8_MAX__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64TIMER3_MR3 TIMER_MR3(TIMER3)TIMER_CCR_CAP1FE (1 << 4)timer_get_prescaler__UTA_IBIT__ 64__ULLACCUM_IBIT__ 32RGU_BASE (0x40053000U)__ULLFRACT_EPSILON__ 0x1P-64ULLRfalse 0__SIZEOF_WINT_T__ 4__ARM_FEATURE_UNALIGNED 1__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)TIMER_EMR_EMC1_MASK (0x3 << TIMER_EMR_EMC1_SHIFT)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1__FLT32X_HAS_DENORM__ 1TIMER1_PC TIMER_PC(TIMER1)__ULLACCUM_MIN__ 0.0ULLKTIMER_CCR_CAP1RE (1 << 3)GPIO_PIN_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x07000)TIMER1_PR TIMER_PR(TIMER1)timer_get_counter__ARM_ASM_SYNTAX_UNIFIED__ 1__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODTIMER0_CR2 TIMER_CR2(TIMER0)TIMER_IR_CR2INT (1 << 6)RTC_BASE (0x40046000U)TIMER1_MR0 TIMER_MR0(TIMER1)TIMER1_CR3 TIMER_CR3(TIMER1)__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H AES_BASE (0x400F1000U)INT_LEAST64_MINTIMER2_TC TIMER_TC(TIMER2)__GCC_CONSTRUCTIVE_SIZE 64__LLFRACT_IBIT__ 0TIMER0_CR0 TIMER_CR0(TIMER0)uint32_tBIT12 (1<<12)TIMER_MCR(timer) MMIO32((timer) + 0x014)__SACCUM_EPSILON__ 0x1P-7HK__ARM_ARCH_ISA_THUMB 2__ARM_FP 4__UINT_FAST16_TYPE__ unsigned int__UHA_IBIT__ 8__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULK__LDBL_DIG__ 15UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXBIT16 (1<<16)__WINT_MIN__ 0UINT_LEAST16_MIN__FLT64_DIG__ 15__WINT_MAX__ 0xffffffffUBIT22 (1<<22)__INT_LEAST8_WIDTH__ 8__INT_LEAST16_TYPE__ short intTIMER3_CR0 TIMER_CR0(TIMER3)TIMER_EMR_EMC_SET 0x2__DBL_MAX__ ((double)1.7976931348623157e+308L)timer_set_counterINT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1UINTMAX_CTIMER2_CTCR TIMER_CTCR(TIMER2)INT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1__UINTPTR_MAX__ 0xffffffffU__HQ_FBIT__ 15__bool_true_false_are_defined 1USART2_BASE (PERIPH_BASE_APB2 + 0x01000)BIT26 (1<<26)TIMER2_EMR TIMER_EMR(TIMER2)__SIZE_MAX__ 0xffffffffU__ARM_ARCHTIMER_CCR_CAP2I (1 << 8)TIMER_IR_MR2INT (1 << 2)__LONG_MAX__ 0x7fffffffLMCPWM_BASE (PERIPH_BASE_APB1 + 0x00000)LPC43XX_MEMORYMAP_H __ARM_FEATURE_LDREX 7PTRDIFF_MAXTIMER_EMR_EMC2_SHIFT 8TIMER3_TCR TIMER_TCR(TIMER3)__LLFRACT_EPSILON__ 0x1P-63LLR__SFRACT_MAX__ 0X7FP-7HR__FLT32X_MANT_DIG__ 53TIMER_CTCR(timer) MMIO32((timer) + 0x070)__WCHAR_WIDTH__ 32WINT_MAX__INT16_C(c) cINT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32__ATOMIC_ACQ_REL 4ADC1_BASE (PERIPH_BASE_APB3 + 0x04000)__HQ_IBIT__ 0__DBL_MIN_10_EXP__ (-307)__ULLFRACT_FBIT__ 64__FLT32_NORM_MAX__ 3.4028234663852886e+38F32UINT64_C(c) __UINT64_C(c)TIMER_CR0(timer) MMIO32((timer) + 0x02C)__UINTMAX_MAX__ 0xffffffffffffffffULL__DBL_MANT_DIG__ 53__ULFRACT_IBIT__ 0TIMER_CR3(timer) MMIO32((timer) + 0x038)INT_FAST16_MAXTIMER_CTCR_CINSEL_MASK (0x3 << 2)__INT_MAX__ 0x7fffffff__INT_LEAST64_TYPE__ long long intTIMER3_MCR TIMER_MCR(TIMER3)__ARM_FEATURE_CDE_COPROCUINT32_CGCC: (15:12.2.rel1-1) 12.2.1 20221205 |      A3aeabi)7E-M M  "           -/!#%')+1 3d,03\ h  }    timer.c$twm4.0.ac8f3cbd7733ee78183be95102ca936awm4.common.h.21.c9066c2f6b12c71b40226ea6107829a4wm4.stdint.h.29.6d480f4ba0f60596e88234283d42444fwm4.stdbool.h.29.4a1c88fe569adb8d03217dd16982ca34wm4.common.h.67.5c568a1f62c8e726909b04e29f9e1fc0wm4.memorymap.h.22.395ffb693017d551ed93d11c39ba4361wm4.timer.h.45.f974f2d0aadff31f08efbc4412bbe219timer_resettimer_enable_countertimer_disable_countertimer_set_countertimer_get_countertimer_get_prescalertimer_set_prescalertimer_set_modetimer_set_count_input "&-4;BIPUcjx} ",06? NX\bg v (   ( 0 8@HP   % +17= $!-"3#<$B% #)/5;AGMSY_ekqw} %+17=CIOU[agmsy !'-39?EKQW]ciou{ #)/5;AGMSY_ekqw} %+17=CIOU[agmsy !'-39?EKQW]ciou{ #)/5;AGMSY_ekqw} %+17=CIOU[agmsy !'-39?EKQW]ciou{     # ) / 5 ; A G M S Y _ e k q w }                            % + 1 7 = C I O U [ a g m s y          #)/5;AGMSY_ekqx  '.5<CJQX_fmt{#*18?FMT[bipw~ &-4;BI  #)/5;AGMSY_ekqw} #)/5;AGMSY_ekqw} %+17=CIOU\ #)/5;AGMSY_ekqw} %+17=CIOU[bipw~ &-4;BIPW^elsz ")07>ELSZahov} 6 Q l&$&(4&8 D&H T&X d&ht&x&&.symtab.strtab.shstrtab.text.data.bss.text.timer_reset.text.timer_enable_counter.text.timer_disable_counter.text.timer_set_counter.text.timer_get_counter.text.timer_get_prescaler.text.timer_set_prescaler.text.timer_set_mode.text.timer_set_count_input.rel.debug_info.debug_abbrev.rel.debug_loclists.rel.debug_aranges.rel.debug_rnglists.rel.debug_macro.rel.debug_line.debug_str.comment.rel.debug_frame.ARM.attributes.group4 4'@ 4(L 4)X 4*d 4+p 4,| 4-!',> Y u    @ x4,:( @y4@`< @yP4S"CO @ zH4geIc @hzH4g c @z04gVc @ 4!grNc @4#g"c @،(4%gc @04'gac @04)g+c @4+xt @H4-03V0!q'Hq @41pq4r57 vipc.o/ 0 0 0 644 73860 ` ELF(4(10 !"#$%&JCCs1T1pG0@ K JC#s1T1pG0@0@y- \d (d,"4eTT?intq6'03'TP)`| PX(`|$ > 4:!; 9!I% Uy: ; 9 I5I$ > .?: ; 9 '@z: ; 9 I .?: ; 9 '@z$(0(0?@=wma.*.TP[}]i$y,%3hE~_ zmw Tnx %V4i'ǘ=#| hxUtQ ֆtY ɋqGWw,5u<tω 7%6]W nbe /ho  zGOBTڧ\XP_9W0-ONOL =|Kt(1%XSG ,RG?uYƬu~.H,?W$fwfu*?t Q LG $Tb?*]sD^#}cɐ̳XM)1{% >>ӨG im08u(cz41<!p#\ 6f>U<мE~hy4@ f'kN&) 34)[!#zZD*BEcfdC PхT:45iv+PϫTgPEUdnu@Pޙ{Qhi|=Od[h(1CAZfUO}u $.L!g9mU"~sk6FwmUva3"zvyV#.tF z"TINN!S[{8k1Wb!W2 |7Tl!mdծ~m5^*qcgn(?6(f* 5A##y4aגZhr4,$U]~u)q3ٝE&Zy!G&x'2CED`E+F|I^HL"Q!RISTdUy!VWeXg#YZf[z\]?^2 _TT`aqbs#cWdge7UfÅg>hG$iBXj}kRl 'mZnoXpo2e] !0J& L(%)Sm*'+xD, -U.$0*57678B9Y:;$?`,@!FA\BHIIIOJKLlMNMO`PQރWXYKZ[l ab)cdOe'_fylgh(nӇo!?pq8rwï{t`d$K1c47K:S@=@C/FHI*LRO.U1Xq[U^!aXdwgsl/<mpbqQtuYxnyQ|}1Y.'Q=`~+4 e UhIxdBGAzƗj̺b&qYMZ4QSFp s_@(رAnޭ2Q;;_1žҵYrO3Nk WQic=h5V$m J^K` NoQ_TKWZE]`cľfXix@l&uorubx{~!-0V[vn[ HfLwWr7H=#<02S*w>:%{bSWN2gr NS5tU$/UWݡ7c',;Bo]}2)'&?JzIGb35"[+ 7M=)x%7;4+4dn`J+V9q/K}}0{"&=l48P l'%~й6G.-ofks~&qFf`{EL5(5Tگ{(LϚk3^6UmyTjvhvXiq:xbT0CRASNepPrΖJi9!/_fb>nv\oRy\HVۀ{k|.6 P92FyaM+qv17kYEu]?FNp#i/yLq:0 _@3)_)&+]i[ГP;O[MaŽ ?RJQ*HAJKHw%VEn6N3!}PrA7$66dfHD1G=Fn}d2\Utzt :;`%G߼4_>g5H/zu: h <AI`&tZD&*[{-}0m}V:Le'<eCZ i+h7%?x Y{?QPDөEEc8J]2?8Br=0@"kqxOJ?rCr9%*%nEt =<r8Bz1o<|Yjp~t.=E/~0L9l|v$D¶qa&AطA A^H^ o߻ M K<   WU ! [ l V   7c   T RG| ../usr/lib/gcc/arm-none-eabi/12.2.1/include../../../include/libopencm3/lpc43xx../../../include/libopencm3/cm3ipc.cstdint.hipc.hcommon.hstdbool.hmemorymap.hcreg.hrgu.h6(../ .#  2'%*.(../z.$  2RESET_CTRL0_ETHERNET_RST (1 << RESET_CTRL0_ETHERNET_RST_SHIFT)RESET_ACTIVE_STATUS1_M0APP_RST (1 << RESET_ACTIVE_STATUS1_M0APP_RST_SHIFT)RESET_EXT_STAT17 MMIO32(RGU_BASE + 0x444)__DECIMAL_DIG__ 17CREG_M0TXEVENT_TXEVCLR_SHIFT (0)__UHA_FBIT__ 8RESET_EXT_STAT14 MMIO32(RGU_BASE + 0x438)RESET_EXT_STAT19 MMIO32(RGU_BASE + 0x44C)RESET_STATUS2 MMIO32(RGU_BASE + 0x118)__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64__WCHAR_MIN__ 0UCREG_DMAMUX_DMAMUXPER12(x) ((x) << CREG_DMAMUX_DMAMUXPER12_SHIFT)__GCC_ATOMIC_WCHAR_T_LOCK_FREE 2__CHAR_UNSIGNED__ 1ETHERNET_BASE (PERIPH_BASE_AHB + 0x10000)RESET_STATUS0_SCU_RST_MASK (0x3 << RESET_STATUS0_SCU_RST_SHIFT)RESET_ACTIVE_STATUS1_CAN0_RST (1 << RESET_ACTIVE_STATUS1_CAN0_RST_SHIFT)RESET_ACTIVE_STATUS0_PERIPH_RST_SHIFT (1)RESET_EXT_STAT25 MMIO32(RGU_BASE + 0x464)CREG_CREG0_USB0PHY (1 << CREG_CREG0_USB0PHY_SHIFT)__FLT64_HAS_INFINITY__ 1RESET_CTRL1_UART0_RST_SHIFT (12)RESET_ACTIVE_STATUS1_SSP1_RST_SHIFT (19)__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GNUC_MINOR__ 2__GCC_DESTRUCTIVE_SIZE 64__LACCUM_EPSILON__ 0x1P-31LK__PTRDIFF_MAX__ 0x7fffffffRESET_ACTIVE_STATUS1_SGPIO_RST (1 << RESET_ACTIVE_STATUS1_SGPIO_RST_SHIFT)__SACCUM_FBIT__ 7__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)RESET_STATUS2_TIMER2_RST(x) ((x) << RESET_STATUS2_TIMER2_RST_SHIFT)__INTMAX_MAX__ 0x7fffffffffffffffLL__TQ_IBIT__ 0CREG_USB1FLADJ_FLTV(x) ((x) << CREG_USB1FLADJ_FLTV_SHIFT)__FLT64_DECIMAL_DIG__ 17RESET_EXT_STAT57 MMIO32(RGU_BASE + 0x4E4)__LDBL_MIN__ 2.2250738585072014e-308LI2C0_BASE (PERIPH_BASE_APB1 + 0x01000)__ATOMIC_CONSUME 1__ULACCUM_FBIT__ 32__WCHAR_MAX__ 0xffffffffUCREG_DMAMUX_DMAMUXPER12_SHIFT (24)RESET_ACTIVE_STATUS0_USB1_RST_SHIFT (18)__ACCUM_MIN__ (-0X1P15K-0X1P15K)OTP_BASE (0x40045000U)RESET_EXT_STAT50_PERIPHERAL_RESET (1 << RESET_EXT_STAT50_PERIPHERAL_RESET_SHIFT)RESET_CTRL0_BUS_RST (1 << RESET_CTRL0_BUS_RST_SHIFT)RESET_EXT_STAT23 MMIO32(RGU_BASE + 0x45C)RESET_STATUS3_SSP1_RST_MASK (0x3 << RESET_STATUS3_SSP1_RST_SHIFT)CREG_CREG6_I2S1_RX_SCK_IN_SEL (1 << CREG_CREG6_I2S1_RX_SCK_IN_SEL_SHIFT)RESET_STATUS0_MASTER_RST_SHIFT (4)CREG_DMAMUX_DMAMUXPER10_SHIFT (20)INT64_MAX __INT64_MAX__INTMAX_MIN__SIZEOF_LONG_LONG__ 8__DBL_MAX_10_EXP__ 308RESET_STATUS3_I2C0_RST(x) ((x) << RESET_STATUS3_I2C0_RST_SHIFT)__FRACT_MIN__ (-0.5R-0.5R)RESET_STATUS3_SPIFI_RST_SHIFT (10)__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLK__USACCUM_MAX__ 0XFFFFP-8UHK__SFRACT_FBIT__ 7__INTMAX_WIDTH__ 64CREG_CREG6_ETHMODE(x) ((x) << CREG_CREG6_ETHMODE_SHIFT)__ARM_FEATURE_BF16_SCALAR_ARITHMETIC__SQ_IBIT__ 0__ORDER_PDP_ENDIAN__ 3412__SIZE_TYPE__ unsigned intCREG_CREG0_BODLVL1(x) ((x) << CREG_CREG0_BODLVL1_SHIFT)C_CCAN1_BASE (PERIPH_BASE_APB1 + 0x04000)__FLT_HAS_DENORM__ 1CREG_CREG0_BODLVL2(x) ((x) << CREG_CREG0_BODLVL2_SHIFT)__SHRT_WIDTH__ 16RESET_ACTIVE_STATUS1_SSP1_RST (1 << RESET_ACTIVE_STATUS1_SSP1_RST_SHIFT)__USACCUM_MIN__ 0.0UHK__FLT32_DECIMAL_DIG__ 9CREG_DMAMUX_DMAMUXPER15_MASK (0x3 << CREG_DMAMUX_DMAMUXPER15_SHIFT)RESET_ACTIVE_STATUS1_RITIMER_RST_SHIFT (4)__LDBL_MIN_EXP__ (-1021)RESET_EXT_STAT46_PERIPHERAL_RESET_SHIFT (2)__LDBL_MANT_DIG__ 53RESET_STATUS2_TIMER3_RST_SHIFT (6)INT64_MIN (-INT64_MAX - 1)RESET_EXT_STAT25_PERIPHERAL_RESET_SHIFT (2)RESET_EXT_STAT52_PERIPHERAL_RESET (1 << RESET_EXT_STAT52_PERIPHERAL_RESET_SHIFT)__UINT8_C(c) c__INT16_TYPE__ short intCREG_FLASHCFGA_POW_SHIFT (31)__FLT64_MAX__ 1.7976931348623157e+308F64RESET_EXT_STAT2 MMIO32(RGU_BASE + 0x408)USB0_BASE (PERIPH_BASE_AHB + 0x06000)RESET_CTRL0_EMC_RST (1 << RESET_CTRL0_EMC_RST_SHIFT)UINT_FAST32_MAXRESET_ACTIVE_STATUS1_TIMER3_RST_SHIFT (3)RESET_EXT_STAT49_PERIPHERAL_RESET (1 << RESET_EXT_STAT49_PERIPHERAL_RESET_SHIFT)RESET_STATUS1_FLASHB_RST(x) ((x) << RESET_STATUS1_FLASHB_RST_SHIFT)RESET_EXT_STAT22 MMIO32(RGU_BASE + 0x458)INT_FAST64_MAX __INT_FAST64_MAX____GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1RESET_ACTIVE_STATUS0_MASTER_RST (1 << RESET_ACTIVE_STATUS0_MASTER_RST_SHIFT)RESET_STATUS2_UART0_RST_MASK (0x3 << RESET_STATUS2_UART0_RST_SHIFT)RESET_ACTIVE_STATUS1_TIMER1_RST (1 << RESET_ACTIVE_STATUS1_TIMER1_RST_SHIFT)__UINT_LEAST16_MAX__ 0xffff__STDC_HOSTED__ 1__ULLFRACT_FBIT__ 64RESET_EXT_STAT22_MASTER_RESET (1 << RESET_EXT_STAT22_MASTER_RESET_SHIFT)__SIG_ATOMIC_TYPE__ intRESET_STATUS1_LCD_RST(x) ((x) << RESET_STATUS1_LCD_RST_SHIFT)RESET_STATUS1_SDIO_RST(x) ((x) << RESET_STATUS1_SDIO_RST_SHIFT)CREG_DMAMUX_DMAMUXPER15_SHIFT (30)__INT_FAST64_TYPE__ long long int__WINT_TYPE__ unsigned intPERIPH_BASE_APB2 (0x400C0000U)INT32_MIN (-INT32_MAX - 1)RESET_EXT_STAT8_PERIPHERAL_RESET_SHIFT (2)__FLT32_MAX_10_EXP__ 38CREG_M4MEMMAP_M4MAP_SHIFT (12)RESET_ACTIVE_STATUS1_CAN0_RST_SHIFT (23)WWDT_BASE (PERIPH_BASE_APB0 + 0x00000)__USFRACT_MAX__ 0XFFP-8UHRRESET_EXT_STAT6 MMIO32(RGU_BASE + 0x418)__FP_FAST_FMAF32 1TIMER1_BASE (PERIPH_BASE_APB0 + 0x05000)RESET_CTRL0_FLASHB_RST_SHIFT (29)RESET_CTRL1_TIMER3_RST_SHIFT (3)__FLT32_MIN_EXP__ (-125)RESET_EXT_STAT37_PERIPHERAL_RESET (1 << RESET_EXT_STAT37_PERIPHERAL_RESET_SHIFT)RESET_CTRL1_I2C0_RST (1 << RESET_CTRL1_I2C0_RST_SHIFT)RESET_CTRL1_DAC_RST_SHIFT (10)RESET_STATUS0_PERIPH_RST(x) ((x) << RESET_STATUS0_PERIPH_RST_SHIFT)ATIMER_BASE (0x40040000U)CREG_CREG0_PD32KHZ (1 << CREG_CREG0_PD32KHZ_SHIFT)CREG_CREG4 MMIO32(CREG_BASE + 0x114)C_CAN0_BASE (PERIPH_BASE_APB3 + 0x02000)__ULFRACT_FBIT__ 32RESET_EXT_STAT45_PERIPHERAL_RESET_SHIFT (2)__FLT64_MIN_10_EXP__ (-307)CREG_ETBCFG MMIO32(CREG_BASE + 0x128)__GNUC_EXECUTION_CHARSET_NAME "UTF-8"BIT10 (1<<10)__INT_FAST64_WIDTH__ 64__STDC_VERSION__ 199901LINT_LEAST64_MAX __INT_LEAST64_MAX__RESET_STATUS0_MASTER_RST(x) ((x) << RESET_STATUS0_MASTER_RST_SHIFT)CREG_M0TXEVENT MMIO32(CREG_BASE + 0x400)RESET_STATUS3_CAN1_RST_SHIFT (12)TIMER0_BASE (PERIPH_BASE_APB0 + 0x04000)__SFRACT_EPSILON__ 0x1P-7HRRESET_STATUS1_LCD_RST_MASK (0x3 << RESET_STATUS1_LCD_RST_SHIFT)RESET_STATUS2_ADC1_RST(x) ((x) << RESET_STATUS2_ADC1_RST_SHIFT)__INT32_C(c) c ## LUINT32_C(c) __UINT32_C(c)__ORDER_BIG_ENDIAN__ 4321SIZE_MAX__SQ_FBIT__ 31RESET_CTRL0_M4_RST_SHIFT (13)RESET_EXT_STAT57_PERIPHERAL_RESET_SHIFT (2)INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)CREG_CREG6_EMC_CLK_SEL (1 << CREG_CREG6_EMC_CLK_SEL_SHIFT)RESET_EXT_STAT25_PERIPHERAL_RESET (1 << RESET_EXT_STAT25_PERIPHERAL_RESET_SHIFT)__UHQ_FBIT__ 16CREG_DMAMUX_DMAMUXPER2_SHIFT (4)RESET_EXT_STAT8 MMIO32(RGU_BASE + 0x420)__FLT64_MIN_EXP__ (-1021)__PTRDIFF_WIDTH__ 32RESET_EXT_STAT20_MASTER_RESET_SHIFT (3)__UINT_FAST8_MAX__ 0xffffffffURESET_EXT_STAT47_PERIPHERAL_RESET (1 << RESET_EXT_STAT47_PERIPHERAL_RESET_SHIFT)UINT16_C(c) __UINT16_C(c)__LACCUM_IBIT__ 32__INT_FAST16_WIDTH__ 32INTMAX_C__VERSION__ "12.2.1 20221205"__VFP_FP__ 1__LLFRACT_MIN__ (-0.5LLR-0.5LLR)INT_FAST8_MAX__UINT_FAST16_MAX__ 0xffffffffU__INTPTR_MAX__ 0x7fffffffINT64_C(c) __INT64_C(c)false 0RESET_STATUS0_CREG_RST(x) ((x) << RESET_STATUS0_CREG_RST_SHIFT)RESET_CTRL1_SGPIO_RST (1 << RESET_CTRL1_SGPIO_RST_SHIFT)__GCC_IEC_559_COMPLEX 0CREG_BASE (0x40043000U)__UFRACT_MIN__ 0.0URCREG_USB1FLADJ_FLTV_MASK (0x3f << CREG_USB1FLADJ_FLTV_SHIFT)CREG_DMAMUX_DMAMUXPER2_MASK (0x3 << CREG_DMAMUX_DMAMUXPER2_SHIFT)WCHAR_MAX __WCHAR_MAX__CREG_DMAMUX_DMAMUXPER6_MASK (0x3 << CREG_DMAMUX_DMAMUXPER6_SHIFT)__FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX__CREG_CREG0_EN1KHZ (1 << CREG_CREG0_EN1KHZ_SHIFT)RESET_CTRL1_TIMER0_RST_SHIFT (0)__UINT_LEAST8_TYPE__ unsigned charRESET_ACTIVE_STATUS0_FLASHB_RST_SHIFT (29)CREG_M4TXEVENT_TXEVCLR_SHIFT (0)__ACCUM_FBIT__ 15CREG_CREG0_ALARMCTRL_SHIFT (6)RESET_ACTIVE_STATUS1_CAN1_RST (1 << RESET_ACTIVE_STATUS1_CAN1_RST_SHIFT)__UACCUM_IBIT__ 16long intUINT8_MAXRESET_ACTIVE_STATUS1_TIMER0_RST (1 << RESET_ACTIVE_STATUS1_TIMER0_RST_SHIFT)SIZE_MAX __SIZE_MAX__CREG_DMAMUX_DMAMUXPER15(x) ((x) << CREG_DMAMUX_DMAMUXPER15_SHIFT)__INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17RESET_EXT_STAT55_PERIPHERAL_RESET (1 << RESET_EXT_STAT55_PERIPHERAL_RESET_SHIFT)__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1RESET_STATUS2_DAC_RST_MASK (0x3 << RESET_STATUS2_DAC_RST_SHIFT)__FLT32X_EPSILON__ 2.2204460492503131e-16F32xRESET_STATUS3_SGPIO_RST_MASK (0x3 << RESET_STATUS3_SGPIO_RST_SHIFT)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32RESET_CTRL1_I2C0_RST_SHIFT (16)CREG_DMAMUX_DMAMUXPER3_SHIFT (6)__UINTMAX_C(c) c ## ULL__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed charRESET_EXT_STAT48_PERIPHERAL_RESET_SHIFT (2)RESET_EXT_STAT53_PERIPHERAL_RESET (1 << RESET_EXT_STAT53_PERIPHERAL_RESET_SHIFT)__GCC_ATOMIC_BOOL_LOCK_FREE 2BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON__RESET_STATUS3_SPI_RST(x) ((x) << RESET_STATUS3_SPI_RST_SHIFT)__FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX__RESET_CTRL0_SDIO_RST_SHIFT (20)__THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRRESET_CTRL1_UART1_RST (1 << RESET_CTRL1_UART1_RST_SHIFT)short unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)RESET_EXT_STAT39 MMIO32(RGU_BASE + 0x49C)BIT7 (1<<7)BIT17 (1<<17)__FLT32X_MIN_10_EXP__ (-307)RESET_STATUS2_ADC1_RST_SHIFT (18)UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)RESET_EXT_STAT59 MMIO32(RGU_BASE + 0x4EC)__DBL_IS_IEC_60559__ 2__UINT_FAST32_MAX__ 0xffffffffU__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4WINT_MIN __WINT_MIN__LCD_BASE (PERIPH_BASE_AHB + 0x08000)RESET_CTRL0_GPIO_RST_SHIFT (28)RESET_ACTIVE_STATUS1_SPIFI_RST (1 << RESET_ACTIVE_STATUS1_SPIFI_RST_SHIFT)__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32RESET_EXT_STAT48 MMIO32(RGU_BASE + 0x4C0)__FLT32X_MIN_EXP__ (-1021)GPDMA_BASE (PERIPH_BASE_AHB + 0x02000)RESET_ACTIVE_STATUS1_DAC_RST (1 << RESET_ACTIVE_STATUS1_DAC_RST_SHIFT)CREG_CREG5_M4TAPSEL (1 << CREG_CREG5_M4TAPSEL_SHIFT)RESET_ACTIVE_STATUS1_QEI_RST_SHIFT (7)RESET_CTRL1_CAN0_RST_SHIFT (23)RESET_STATUS2_UART3_RST(x) ((x) << RESET_STATUS2_UART3_RST_SHIFT)BIT27 (1<<27)CREG_CREG0_ALARMCTRL_MASK (0x3 << CREG_CREG0_ALARMCTRL_SHIFT)RESET_CTRL1_I2C1_RST_SHIFT (17)RESET_ACTIVE_STATUS1_I2C0_RST_SHIFT (16)__UTA_FBIT__ 64SDIO_BASE (PERIPH_BASE_AHB + 0x04000)RESET_CTRL0_BUS_RST_SHIFT (8)__FLT_DECIMAL_DIG__ 9CREG_CREG6_I2S0_TX_SCK_IN_SEL (1 << CREG_CREG6_I2S0_TX_SCK_IN_SEL_SHIFT)__thumb__ 1__INT_LEAST32_MAX__ 0x7fffffffLsigned charGIMA_BASE (PERIPH_BASE_APB2 + 0x07000)CREG_DMAMUX_DMAMUXPER4_SHIFT (8)INT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)INT32_C(c) __INT32_C(c)__GNUC_STDC_INLINE__ 1RESET_CTRL0_FLASHA_RST_SHIFT (25)RESET_STATUS2_UART3_RST_MASK (0x3 << RESET_STATUS2_UART3_RST_SHIFT)RESET_STATUS2_UART3_RST_SHIFT (30)__FRACT_FBIT__ 15__LLACCUM_EPSILON__ 0x1P-31LLKRESET_CTRL0_CREG_RST (1 << RESET_CTRL0_CREG_RST_SHIFT)__GNUC_PATCHLEVEL__ 1__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2PTRDIFF_MIN__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)RESET_EXT_STAT19_MASTER_RESET_SHIFT (3)UINTPTR_MAX __UINTPTR_MAX__CREG_FLASHCFGA MMIO32(CREG_BASE + 0x120)RESET_CTRL0_EMC_RST_SHIFT (21)RESET_CTRL1_TIMER1_RST_SHIFT (1)CREG_CREG6_I2S1_RX_SCK_IN_SEL_SHIFT (15)CREG_CREG0_BODLVL1_MASK (0x3 << CREG_CREG0_BODLVL1_SHIFT)__FLT64_MAX_10_EXP__ 308RESET_STATUS3_I2C0_RST_SHIFT (0)MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINRESET_CTRL0_MASTER_RST_SHIFT (2)__INT_FAST32_WIDTH__ 32CGU_BASE (0x40050000U)__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38RESET_ACTIVE_STATUS1_UART1_RST_SHIFT (13)__FRACT_MAX__ 0X7FFFP-15RCREG_CREG6_ETHMODE_SHIFT (0)GNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -O2 -std=c99 -fno-common -ffunction-sections -fdata-sectionsINT_LEAST32_MAX __INT_LEAST32_MAX__RESET_CTRL1_SSP1_RST (1 << RESET_CTRL1_SSP1_RST_SHIFT)__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5RESET_EXT_STAT35_PERIPHERAL_RESET_SHIFT (2)RESET_STATUS2_TIMER2_RST_MASK (0x3 << RESET_STATUS2_TIMER2_RST_SHIFT)RESET_STATUS1_FLASHA_RST_SHIFT (18)RESET_EXT_STAT36_PERIPHERAL_RESET_SHIFT (2)RESET_CTRL1_QEI_RST_SHIFT (7)CREG_CREG5 MMIO32(CREG_BASE + 0x118)RESET_ACTIVE_STATUS0_FLASHB_RST (1 << RESET_ACTIVE_STATUS0_FLASHB_RST_SHIFT)RESET_EXT_STAT37_PERIPHERAL_RESET_SHIFT (2)RESET_EXT_STAT20 MMIO32(RGU_BASE + 0x450)__UINT16_MAX__ 0xffff__TQ_FBIT__ 127RESET_ACTIVE_STATUS1_UART1_RST (1 << RESET_ACTIVE_STATUS1_UART1_RST_SHIFT)RESET_EXT_STAT41 MMIO32(RGU_BASE + 0x4A4)RESET_STATUS1_USB1_RST_MASK (0x3 << RESET_STATUS1_USB1_RST_SHIFT)__USQ_FBIT__ 32RESET_ACTIVE_STATUS0_SCU_RST_SHIFT (9)INT_FAST16_MINRESET_EXT_STAT29_PERIPHERAL_RESET (1 << RESET_EXT_STAT29_PERIPHERAL_RESET_SHIFT)CREG_DMAMUX_DMAMUXPER8_SHIFT (16)__thumb2__ 1__ULLACCUM_FBIT__ 32RESET_EXT_STAT42 MMIO32(RGU_BASE + 0x4A8)RESET_STATUS2_TIMER3_RST(x) ((x) << RESET_STATUS2_TIMER3_RST_SHIFT)RESET_CTRL0_CREG_RST_SHIFT (5)RESET_EXT_STAT52 MMIO32(RGU_BASE + 0x4D0)INT_FAST32_MIN (-INT_FAST32_MAX - 1)CREG_DMAMUX_DMAMUXPER6_SHIFT (12)__STRICT_ANSI__ 1RESET_STATUS2_UART2_RST(x) ((x) << RESET_STATUS2_UART2_RST_SHIFT)UINT_LEAST8_MAXUINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8RESET_CTRL0_USB1_RST (1 << RESET_CTRL0_USB1_RST_SHIFT)RESET_STATUS0_BUS_RST_SHIFT (16)RESET_STATUS3_SPI_RST_MASK (0x3 << RESET_STATUS3_SPI_RST_SHIFT)__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__RESET_CTRL1_UART3_RST_SHIFT (15)__USA_IBIT__ 16__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1RESET_ACTIVE_STATUS0_FLASHA_RST_SHIFT (25)PTRDIFF_MIN (-PTRDIFF_MAX - 1)RESET_STATUS0_CORE_RST(x) ((x) << RESET_STATUS0_CORE_RST_SHIFT)CREG_DMAMUX_DMAMUXPER14_MASK (0x3 << CREG_DMAMUX_DMAMUXPER14_SHIFT)RESET_STATUS0_CORE_RST_MASK (0x3 << RESET_STATUS0_CORE_RST_SHIFT)__UINT_FAST64_TYPE__ long long unsigned intUINTMAX_MAX __UINTMAX_MAX__RESET_ACTIVE_STATUS0_WWDT_RST_SHIFT (4)RESET_STATUS0_BUS_RST_MASK (0x3 << RESET_STATUS0_BUS_RST_SHIFT)__FLT_MIN__ 1.1754943508222875e-38Fipc_start_m0__HA_FBIT__ 7RESET_CTRL1_SSP1_RST_SHIFT (19)__FDPIC__RESET_ACTIVE_STATUS0_MASTER_RST_SHIFT (2)RESET_STATUS2_MOTOCONPWM_RST_SHIFT (12)__FLT32_IS_IEC_60559__ 2RESET_EXT_STAT34 MMIO32(RGU_BASE + 0x488)RESET_CTRL0_FLASHB_RST (1 << RESET_CTRL0_FLASHB_RST_SHIFT)RESET_CTRL0_CORE_RST_SHIFT (0)INT_FAST64_MINADC0_BASE (PERIPH_BASE_APB3 + 0x03000)__USFRACT_IBIT__ 0RESET_EXT_STAT1_CORE_RESET_SHIFT (1)__LDBL_EPSILON__ 2.2204460492503131e-16LCREG_CREG6_ETHMODE_MASK (0x7 << CREG_CREG6_ETHMODE_SHIFT)__USFRACT_MIN__ 0.0UHRRESET_EXT_STAT0_BOD_RESET (1 << RESET_EXT_STAT0_BOD_RESET_SHIFT)RESET_STATUS1_ETHERNET_RST(x) ((x) << RESET_STATUS1_ETHERNET_RST_SHIFT)__ARM_NEONRESET_EXT_STAT18_MASTER_RESET_SHIFT (3)__UINT8_MAX__ 0xffRESET_EXT_STAT38_PERIPHERAL_RESET (1 << RESET_EXT_STAT38_PERIPHERAL_RESET_SHIFT)__LDBL_MAX_EXP__ 1024RESET_STATUS2_UART0_RST(x) ((x) << RESET_STATUS2_UART0_RST_SHIFT)RESET_ACTIVE_STATUS1_UART3_RST_SHIFT (15)RESET_ACTIVE_STATUS0_SDIO_RST (1 << RESET_ACTIVE_STATUS0_SDIO_RST_SHIFT)RESET_ACTIVE_STATUS1_TIMER2_RST (1 << RESET_ACTIVE_STATUS1_TIMER2_RST_SHIFT)RESET_CTRL1_TIMER0_RST (1 << RESET_CTRL1_TIMER0_RST_SHIFT)CREG_DMAMUX_DMAMUXPER6(x) ((x) << CREG_DMAMUX_DMAMUXPER6_SHIFT)__DBL_HAS_DENORM__ 1CREG_DMAMUX_DMAMUXPER7_SHIFT (14)RESET_CTRL0_MASTER_RST (1 << RESET_CTRL0_MASTER_RST_SHIFT)RESET_EXT_STAT27_PERIPHERAL_RESET_SHIFT (2)CREG_CREG0_EN1KHZ_SHIFT (0)RESET_EXT_STAT51_PERIPHERAL_RESET (1 << RESET_EXT_STAT51_PERIPHERAL_RESET_SHIFT)__DA_FBIT__ 31RESET_ACTIVE_STATUS1_I2C0_RST (1 << RESET_ACTIVE_STATUS1_I2C0_RST_SHIFT)__GXX_ABI_VERSION 1017__INT_LEAST16_MAX__ 0x7fffRESET_CTRL1_UART2_RST_SHIFT (14)RESET_ACTIVE_STATUS0_SCU_RST (1 << RESET_ACTIVE_STATUS0_SCU_RST_SHIFT)__FLT_DENORM_MIN__ 1.4012984643248171e-45FRESET_EXT_STAT4_CORE_RESET (1 << RESET_EXT_STAT4_CORE_RESET_SHIFT)CREG_DMAMUX_DMAMUXPER13(x) ((x) << CREG_DMAMUX_DMAMUXPER13_SHIFT)__ULLACCUM_EPSILON__ 0x1P-32ULLKRESET_ACTIVE_STATUS0_FLASHA_RST (1 << RESET_ACTIVE_STATUS0_FLASHA_RST_SHIFT)RESET_EXT_STAT1 MMIO32(RGU_BASE + 0x404)RESET_EXT_STAT46 MMIO32(RGU_BASE + 0x4B8)INT_LEAST8_MAX __INT_LEAST8_MAX__DAC_BASE (PERIPH_BASE_APB3 + 0x01000)__UINT32_C(c) c ## ULRESET_STATUS2_QEI_RST(x) ((x) << RESET_STATUS2_QEI_RST_SHIFT)RESET_CTRL0_SCU_RST_SHIFT (9)UINTMAX_MAX__UACCUM_MIN__ 0.0UKRESET_ACTIVE_STATUS1_CAN1_RST_SHIFT (22)__FLT_EPSILON__ 1.1920928955078125e-7FCREG_CREG6_I2S1_TX_SCK_IN_SEL_SHIFT (14)CREG_CREG2 MMIO32(CREG_BASE + 0x10C)RESET_EXT_STAT12 MMIO32(RGU_BASE + 0x430)RESET_STATUS2_UART2_RST_MASK (0x3 << RESET_STATUS2_UART2_RST_SHIFT)RESET_EXT_STAT9_PERIPHERAL_RESET_SHIFT (2)__ARM_ARCH_ISA_THUMBRESET_EXT_STAT44_PERIPHERAL_RESET_SHIFT (2)RESET_STATUS1_DMA_RST_SHIFT (6)RESET_ACTIVE_STATUS0_PERIPH_RST (1 << RESET_ACTIVE_STATUS0_PERIPH_RST_SHIFT)__ARM_FEATURE_MATMUL_INT8RESET_STATUS3_CAN0_RST(x) ((x) << RESET_STATUS3_CAN0_RST_SHIFT)__GCC_ATOMIC_SHORT_LOCK_FREE 2RESET_EXT_STAT29_PERIPHERAL_RESET_SHIFT (2)CREG_CREG0_WAKEUP0CTRL_MASK (0x3 << CREG_CREG0_WAKEUP0CTRL_SHIFT)RESET_EXT_STAT1_CORE_RESET (1 << RESET_EXT_STAT1_CORE_RESET_SHIFT)RESET_CTRL0_WWDT_RST_SHIFT (4)__USACCUM_FBIT__ 8RESET_EXT_STAT17_MASTER_RESET (1 << RESET_EXT_STAT17_MASTER_RESET_SHIFT)__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1RESET_STATUS1_USB1_RST(x) ((x) << RESET_STATUS1_USB1_RST_SHIFT)RESET_ACTIVE_STATUS1_I2C1_RST (1 << RESET_ACTIVE_STATUS1_I2C1_RST_SHIFT)__LACCUM_FBIT__ 31RESET_EXT_STAT41_PERIPHERAL_RESET_SHIFT (2)RESET_ACTIVE_STATUS1_SPI_RST_SHIFT (26)EMC_BASE (PERIPH_BASE_AHB + 0x05000)__FLT32_HAS_QUIET_NAN__ 1RESET_ACTIVE_STATUS1_ADC1_RST (1 << RESET_ACTIVE_STATUS1_ADC1_RST_SHIFT)RESET_EXT_STAT0_EXT_RESET (1 << RESET_EXT_STAT0_EXT_RESET_SHIFT)__LDBL_HAS_INFINITY__ 1RESET_STATUS2_MOTOCONPWM_RST(x) ((x) << RESET_STATUS2_MOTOCONPWM_RST_SHIFT)RESET_EXT_STAT7 MMIO32(RGU_BASE + 0x41C)__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))CCU1_BASE (0x40051000U)__FLT32X_MAX_10_EXP__ 308CREG_DMAMUX_DMAMUXPER2(x) ((x) << CREG_DMAMUX_DMAMUXPER2_SHIFT)__ARM_ARCH_EXT_IDIV__ 1RESET_ACTIVE_STATUS0_M4_RST_SHIFT (13)RESET_STATUS2_RITIMER_RST_MASK (0x3 << RESET_STATUS2_RITIMER_RST_SHIFT)bool _BoolRESET_ACTIVE_STATUS0_ETHERNET_RST_SHIFT (22)RESET_EXT_STAT58_PERIPHERAL_RESET (1 << RESET_EXT_STAT58_PERIPHERAL_RESET_SHIFT)CREG_CREG0_WAKEUP1CTRL_SHIFT (16)__SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffRESET_EXT_STAT29 MMIO32(RGU_BASE + 0x474)RESET_ACTIVE_STATUS0_GPIO_RST_SHIFT (28)BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)RESET_ACTIVE_STATUS0_BUS_RST (1 << RESET_ACTIVE_STATUS0_BUS_RST_SHIFT)RESET_EXT_STAT47_PERIPHERAL_RESET_SHIFT (2)INT16_MAX __INT16_MAX__RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_SHIFT (6)__FP_FAST_FMAF 1RESET_CTRL0_LCD_RST (1 << RESET_CTRL0_LCD_RST_SHIFT)CREG_CREG0_SAMPLECTRL_MASK (0x3 << CREG_CREG0_SAMPLECTRL_SHIFT)__FLT32X_IS_IEC_60559__ 2RESET_CTRL1_RTIMER_RST_SHIFT (4)PERIPH_BASE_APB3 (0x400E0000U)RESET_EXT_STAT16_MASTER_RESET (1 << RESET_EXT_STAT16_MASTER_RESET_SHIFT)RESET_CTRL0_M4_RST (1 << RESET_CTRL0_M4_RST_SHIFT)LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))LPC43XX_CREG_H CREG_CREG6_CTOUTCTRL (1 << CREG_CREG6_CTOUTCTRL_SHIFT)RESET_STATUS3_M0APP_RST_MASK (0x3 << RESET_STATUS3_M0APP_RST_SHIFT)__INT_LEAST16_WIDTH__ 16I2S0_BASE (PERIPH_BASE_APB1 + 0x02000)CREG_CREG1 MMIO32(CREG_BASE + 0x108)__DEC_EVAL_METHOD__ 2SCT_BASE (PERIPH_BASE_AHB + 0x00000)__ARM_FEATURE_FP16_FMLRESET_STATUS0_CORE_RST_SHIFT (0)RESET_EXT_STAT30 MMIO32(RGU_BASE + 0x478)INT16_MIN (-INT16_MAX - 1)RESET_STATUS0_WWDT_RST_MASK (0x3 << RESET_STATUS0_WWDT_RST_SHIFT)__USFRACT_EPSILON__ 0x1P-8UHRRESET_EXT_STAT50_PERIPHERAL_RESET_SHIFT (2)RESET_CTRL0_ETHERNET_RST_SHIFT (22)RESET_STATUS3_SSP1_RST(x) ((x) << RESET_STATUS3_SSP1_RST_SHIFT)SCU_BASE (PERIPH_BASE_APB0 + 0x06000)RESET_STATUS2_SCT_RST_SHIFT (10)__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLKRESET_EXT_STAT54 MMIO32(RGU_BASE + 0x4D8)RESET_STATUS3_SPI_RST_SHIFT (20)RESET_EXT_STAT51 MMIO32(RGU_BASE + 0x4CC)__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX__RESET_STATUS2_ADC0_RST_MASK (0x3 << RESET_STATUS2_ADC0_RST_SHIFT)__UINT32_MAX__ 0xffffffffULUSART0_BASE (PERIPH_BASE_APB0 + 0x01000)CREG_DMAMUX_DMAMUXPER9(x) ((x) << CREG_DMAMUX_DMAMUXPER9_SHIFT)RESET_STATUS3_SSP0_RST(x) ((x) << RESET_STATUS3_SSP0_RST_SHIFT)__INT_LEAST8_MAX__ 0x7f__GCC_ATOMIC_POINTER_LOCK_FREE 2__ARM_FEATURE_QBIT 1__ARM_FEATURE_CLZ 1__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXRESET_ACTIVE_STATUS0_CORE_RST (1 << RESET_ACTIVE_STATUS0_CORE_RST_SHIFT)RESET_ACTIVE_STATUS0 MMIO32(RGU_BASE + 0x150)RESET_STATUS1_EMC_RST_MASK (0x3 << RESET_STATUS1_EMC_RST_SHIFT)CREG_DMAMUX_DMAMUXPER1(x) ((x) << CREG_DMAMUX_DMAMUXPER1_SHIFT)__UINT64_TYPE__ long long unsigned int__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024CREG_CREG0_EN32KHZ (1 << CREG_CREG0_EN32KHZ_SHIFT)RESET_STATUS3_CAN1_RST_MASK (0x3 << RESET_STATUS3_CAN1_RST_SHIFT)RESET_STATUS3_SPIFI_RST(x) ((x) << RESET_STATUS3_SPIFI_RST_SHIFT)CREG_FLASHCFGB MMIO32(CREG_BASE + 0x124)__UINT_LEAST32_MAX__ 0xffffffffULRESET_STATUS2_TIMER0_RST_SHIFT (0)__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)RESET_EXT_STAT50 MMIO32(RGU_BASE + 0x4C8)RESET_EXT_STAT55 MMIO32(RGU_BASE + 0x4DC)__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1RESET_STATUS1_DMA_RST(x) ((x) << RESET_STATUS1_DMA_RST_SHIFT)__ACCUM_MAX__ 0X7FFFFFFFP-15K__INT8_MAX__ 0x7fBIT14 (1<<14)RESET_STATUS1_USB0_RST(x) ((x) << RESET_STATUS1_USB0_RST_SHIFT)__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16USB1_BASE (PERIPH_BASE_AHB + 0x07000)BIT20 (1<<20)__ARM_FEATURE_MVERESET_EXT_STAT53_PERIPHERAL_RESET_SHIFT (2)RESET_STATUS0_BUS_RST(x) ((x) << RESET_STATUS0_BUS_RST_SHIFT)__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intRESET_EXT_STAT61 MMIO32(RGU_BASE + 0x4F4)RESET_STATUS3_SGPIO_RST_SHIFT (18)RESET_STATUS2_TIMER0_RST(x) ((x) << RESET_STATUS2_TIMER0_RST_SHIFT)UINT_LEAST16_MAX __UINT_LEAST16_MAX__RESET_EXT_STAT55_PERIPHERAL_RESET_SHIFT (2)RESET_CTRL1_MOTOCONPWM_RST_SHIFT (6)INT_FAST32_MINRESET_EXT_STAT33 MMIO32(RGU_BASE + 0x484)__FLT_EVAL_METHOD_TS_18661_3__ 0__SCHAR_WIDTH__ 8CREG_M0TXEVENT_TXEVCLR (1 << CREG_M0TXEVENT_TXEVCLR_SHIFT)BIT18 (1<<18)UINT_FAST16_MAXRESET_EXT_STAT62 MMIO32(RGU_BASE + 0x4F8)__UINT_FAST8_TYPE__ unsigned int__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RBIT24 (1<<24)ipc_halt_m0__INT32_MAX__ 0x7fffffffLRESET_STATUS0_M4_RST_MASK (0x3 << RESET_STATUS0_M4_RST_SHIFT)CREG_M0APPMEMMAP MMIO32(CREG_BASE + 0x404)BIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLLCREG_CREG0_RESET32KHZ (1 << CREG_CREG0_RESET32KHZ_SHIFT)__FLT32_MANT_DIG__ 24INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32EVENTROUTER_BASE (0x40044000U)__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN__CREG_DMAMUX_DMAMUXPER0(x) ((x) << CREG_DMAMUX_DMAMUXPER0_SHIFT)INT8_MAX __INT8_MAX__RESET_ACTIVE_STATUS1_ADC1_RST_SHIFT (9)BIT28 (1<<28)UINT32_MAX __UINT32_MAX____GCC_ATOMIC_CHAR16_T_LOCK_FREE 2INTMAX_C(c) __INTMAX_C(c)RESET_EXT_STAT28 MMIO32(RGU_BASE + 0x470)RESET_ACTIVE_STATUS1_UART0_RST_SHIFT (12)__DBL_MAX_EXP__ 1024RESET_STATUS3_I2C1_RST_SHIFT (2)__ATOMIC_RELEASE 3RESET_CTRL0_SDIO_RST (1 << RESET_CTRL0_SDIO_RST_SHIFT)UINT_FAST8_MAX__FLT_MANT_DIG__ 24RESET_EXT_STAT54_PERIPHERAL_RESET_SHIFT (2)__UDQ_IBIT__ 0RESET_ACTIVE_STATUS0_LCD_RST (1 << RESET_ACTIVE_STATUS0_LCD_RST_SHIFT)RESET_STATUS2_TIMER0_RST_MASK (0x3 << RESET_STATUS2_TIMER0_RST_SHIFT)CCU2_BASE (0x40052000U)CREG_FLASHCFGB_FLASHTIM_MASK (0xf << CREG_FLASHCFGB_FLASHTIM_SHIFT)__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UKRESET_EXT_STAT0_WWDT_RESET_SHIFT (5)RESET_CTRL0_WWDT_RST (1 << RESET_CTRL0_WWDT_RST_SHIFT)__FLT64_NORM_MAX__ 1.7976931348623157e+308F64PERIPH_BASE_APB1 (0x400A0000U)RESET_STATUS3_I2C0_RST_MASK (0x3 << RESET_STATUS3_I2C0_RST_SHIFT)UINTPTR_MAXRESET_EXT_STAT46_PERIPHERAL_RESET (1 << RESET_EXT_STAT46_PERIPHERAL_RESET_SHIFT)CREG_FLASHCFGA_FLASHTIM_MASK (0xf << CREG_FLASHCFGA_FLASHTIM_SHIFT)__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__LDBL_DENORM_MIN__ 4.9406564584124654e-324LTIMER3_BASE (PERIPH_BASE_APB2 + 0x04000)__INT64_MAX__ 0x7fffffffffffffffLLCREG_DMAMUX_DMAMUXPER3_MASK (0x3 << CREG_DMAMUX_DMAMUXPER3_SHIFT)RESET_STATUS1_FLASHA_RST_MASK (0x3 << RESET_STATUS1_FLASHA_RST_SHIFT)CREG_DMAMUX_DMAMUXPER7_MASK (0x3 << CREG_DMAMUX_DMAMUXPER7_SHIFT)CREG_CREG0_BODLVL1_SHIFT (8)__ULLFRACT_IBIT__ 0RESET_CTRL1_TIMER3_RST (1 << RESET_CTRL1_TIMER3_RST_SHIFT)SPI_PORT_BASE (0x40100000U)MMIO16(addr) (*(volatile uint16_t *)(addr))RESET_CTRL1_SGPIO_RST_SHIFT (25)LPC43XX 1RESET_EXT_STAT42_PERIPHERAL_RESET (1 << RESET_EXT_STAT42_PERIPHERAL_RESET_SHIFT)__GNUC__ 12RESET_STATUS2_RITIMER_RST(x) ((x) << RESET_STATUS2_RITIMER_RST_SHIFT)WCHAR_MAXCREG_FLASHCFGB_POW_SHIFT (31)RESET_STATUS3_I2S_RST_SHIFT (8)__LONG_WIDTH__ 32RESET_CTRL0_USB0_RST (1 << RESET_CTRL0_USB0_RST_SHIFT)__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16RESET_EXT_STAT16 MMIO32(RGU_BASE + 0x440)CREG_CREG0_EN32KHZ_SHIFT (1)__UFRACT_EPSILON__ 0x1P-16URCREG_CREG0 MMIO32(CREG_BASE + 0x004)__UQQ_IBIT__ 0RESET_EXT_STAT56_PERIPHERAL_RESET (1 << RESET_EXT_STAT56_PERIPHERAL_RESET_SHIFT)__GCC_ATOMIC_LONG_LOCK_FREE 2__ULACCUM_MIN__ 0.0ULKCREG_DMAMUX_DMAMUXPER13_MASK (0x3 << CREG_DMAMUX_DMAMUXPER13_SHIFT)RESET_ACTIVE_STATUS0_CREG_RST_SHIFT (5)__LDBL_MAX__ 1.7976931348623157e+308L__ARM_ARCH 7/build/libopencm3/lib/lpc43xx/m4RESET_ACTIVE_STATUS0_LCD_RST_SHIFT (16)__FLT_RADIX__ 2BIT3 (1<<3)long long int__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAXSGPIO_PORT_BASE (0x40101000U)CREG_CREG0_BODLVL2_SHIFT (10)__LDBL_HAS_QUIET_NAN__ 1RESET_ACTIVE_STATUS1_UART3_RST (1 << RESET_ACTIVE_STATUS1_UART3_RST_SHIFT)PERIPH_BASE_APB0 (0x40080000U)__LONG_LONG_WIDTH__ 64BIT6 (1<<6)RESET_ACTIVE_STATUS1_I2C1_RST_SHIFT (17)RESET_STATUS1_FLASHA_RST(x) ((x) << RESET_STATUS1_FLASHA_RST_SHIFT)RESET_CTRL1_M0APP_RST (1 << RESET_CTRL1_M0APP_RST_SHIFT)__UINT_FAST64_MAX__ 0xffffffffffffffffULL__ARM_FP__HA_IBIT__ 8__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1BIT9 (1<<9)RESET_CTRL1_SPIFI_RST (1 << RESET_CTRL1_SPIFI_RST_SHIFT)__FLT32X_MIN__ 2.2250738585072014e-308F32xINTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024RESET_ACTIVE_STATUS0_EEPROM_RST (1 << RESET_ACTIVE_STATUS0_EEPROM_RST_SHIFT)UINT16_MAX__FLT64_MIN__ 2.2250738585072014e-308F64__INTMAX_C(c) c ## LLRESET_ACTIVE_STATUS1_SPIFI_RST_SHIFT (21)CREG_CREG0_SAMPLECTRL_SHIFT (12)RESET_STATUS0_M4_RST_SHIFT (26)__ARM_ARCH_PROFILE__INT64_TYPE__ long long int__LFRACT_FBIT__ 31__CHAR_BIT__ 8RESET_ACTIVE_STATUS1_TIMER3_RST (1 << RESET_ACTIVE_STATUS1_TIMER3_RST_SHIFT)__SIZEOF_WCHAR_T__ 4RESET_STATUS1_ETHERNET_RST_MASK (0x3 << RESET_STATUS1_ETHERNET_RST_SHIFT)RESET_ACTIVE_STATUS1_I2S_RST_SHIFT (20)CREG_DMAMUX_DMAMUXPER13_SHIFT (26)RESET_STATUS0_M4_RST(x) ((x) << RESET_STATUS0_M4_RST_SHIFT)RESET_STATUS0_SCU_RST(x) ((x) << RESET_STATUS0_SCU_RST_SHIFT)RESET_EXT_STAT33_PERIPHERAL_RESET (1 << RESET_EXT_STAT33_PERIPHERAL_RESET_SHIFT)CREG_M4MEMMAP_M4MAP(x) ((x) << CREG_M4MEMMAP_M4MAP_SHIFT)__UFRACT_MAX__ 0XFFFFP-16URRESET_STATUS2_MOTOCONPWM_RST_MASK (0x3 << RESET_STATUS2_MOTOCONPWM_RST_SHIFT)CREG_DMAMUX_DMAMUXPER11_SHIFT (22)INT64_MAXRESET_STATUS2_TIMER1_RST_MASK (0x3 << RESET_STATUS2_TIMER1_RST_SHIFT)RESET_STATUS0_CREG_RST_SHIFT (10)RESET_CTRL1_CAN1_RST_SHIFT (22)RESET_EXT_STAT54_PERIPHERAL_RESET (1 << RESET_EXT_STAT54_PERIPHERAL_RESET_SHIFT)INT_FAST64_MIN (-INT_FAST64_MAX - 1)SSP1_BASE (PERIPH_BASE_APB2 + 0x05000)RESET_EXT_STAT39_PERIPHERAL_RESET (1 << RESET_EXT_STAT39_PERIPHERAL_RESET_SHIFT)RESET_CTRL1_UART2_RST (1 << RESET_CTRL1_UART2_RST_SHIFT)CREG_CREG6_I2S0_RX_SCK_IN_SEL_SHIFT (13)SPIFI_BASE (PERIPH_BASE_AHB + 0x03000)__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__RESET_EXT_STAT27 MMIO32(RGU_BASE + 0x46C)RESET_STATUS3_SGPIO_RST(x) ((x) << RESET_STATUS3_SGPIO_RST_SHIFT)RESET_ACTIVE_STATUS0_M4_RST (1 << RESET_ACTIVE_STATUS0_M4_RST_SHIFT)CREG_CREG0_PD32KHZ_SHIFT (3)RESET_STATUS1_GPIO_RST_MASK (0x3 << RESET_STATUS1_GPIO_RST_SHIFT)CREG_FLASHCFGA_POW (1 << CREG_FLASHCFGA_POW_SHIFT)CREG_FLASHCFGB_POW (1 << CREG_FLASHCFGB_POW_SHIFT)RESET_EXT_STAT32_PERIPHERAL_RESET_SHIFT (2)__UFRACT_FBIT__ 16RESET_EXT_STAT48_PERIPHERAL_RESET (1 << RESET_EXT_STAT48_PERIPHERAL_RESET_SHIFT)__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)RESET_STATUS1_SDIO_RST_MASK (0x3 << RESET_STATUS1_SDIO_RST_SHIFT)__LDBL_MAX_10_EXP__ 308RESET_STATUS2_ADC0_RST(x) ((x) << RESET_STATUS2_ADC0_RST_SHIFT)RESET_EXT_STAT34_PERIPHERAL_RESET_SHIFT (2)RESET_STATUS2_SCT_RST_MASK (0x3 << RESET_STATUS2_SCT_RST_SHIFT)RESET_EXT_STAT13_MASTER_RESET_SHIFT (3)__INT_FAST32_TYPE__ intRESET_STATUS1_LCD_RST_SHIFT (0)RESET_CTRL1_M0APP_RST_SHIFT (24)unsigned intCREG_CREG5_M0APPTAPSEL_SHIFT (9)RESET_EXT_STAT4_CORE_RESET_SHIFT (1)RESET_EXT_STAT17_MASTER_RESET_SHIFT (3)RESET_EXT_STAT53 MMIO32(RGU_BASE + 0x4D4)__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1RESET_STATUS1_EMC_RST(x) ((x) << RESET_STATUS1_EMC_RST_SHIFT)CREG_USB1FLADJ MMIO32(CREG_BASE + 0x600)__USACCUM_IBIT__ 8CREG_FLASHCFGA_FLASHTIM(x) ((x) << CREG_FLASHCFGA_FLASHTIM_SHIFT)__ARM_ARCH_7EM__ 1CREG_FLASHCFGB_FLASHTIM(x) ((x) << CREG_FLASHCFGB_FLASHTIM_SHIFT)__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UKRESET_EXT_STAT58 MMIO32(RGU_BASE + 0x4E8)__FLT_EVAL_METHOD__ 0RESET_ACTIVE_STATUS0_USB0_RST_SHIFT (17)RESET_EXT_STAT34_PERIPHERAL_RESET (1 << RESET_EXT_STAT34_PERIPHERAL_RESET_SHIFT)GPIO_PORT_BASE (0x400F4000U)__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32RESET_EXT_STAT13 MMIO32(RGU_BASE + 0x434)CREG_USB0FLADJ_FLTV_SHIFT (0)__ARM_FEATURE_LDREXRESET_STATUS2_QEI_RST_SHIFT (14)__UQQ_FBIT__ 8RESET_ACTIVE_STATUS1_TIMER2_RST_SHIFT (2)INT16_C__ARM_FP16_ARGS__GCC_IEC_559 0RESET_EXT_STAT40_PERIPHERAL_RESET (1 << RESET_EXT_STAT40_PERIPHERAL_RESET_SHIFT)INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX__RESET_EXT_STAT24 MMIO32(RGU_BASE + 0x460)__LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4RESET_STATUS2_SCT_RST(x) ((x) << RESET_STATUS2_SCT_RST_SHIFT)__STDC__ 1RESET_STATUS3_M0APP_RST(x) ((x) << RESET_STATUS3_M0APP_RST_SHIFT)__ARM_FEATURE_IDIV 1RESET_EXT_STAT45 MMIO32(RGU_BASE + 0x4B4)__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__CREG_USB0FLADJ MMIO32(CREG_BASE + 0x500)__UINT8_TYPE__ unsigned char__ARM_FEATURE_COPROC 15UINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"INT8_MIN__FLT64_IS_IEC_60559__ 2CREG_CREG0_SAMPLECTRL(x) ((x) << CREG_CREG0_SAMPLECTRL_SHIFT)true 1__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)RESET_STATUS2_DAC_RST(x) ((x) << RESET_STATUS2_DAC_RST_SHIFT)RESET_STATUS0_SCU_RST_SHIFT (18)__LDBL_MIN_10_EXP__ (-307)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1CREG_M4TXEVENT_TXEVCLR (1 << CREG_M4TXEVENT_TXEVCLR_SHIFT)__GCC_ATOMIC_CHAR_LOCK_FREE 2CREG_CREG0_WAKEUP1CTRL_MASK (0x3 << CREG_CREG0_WAKEUP1CTRL_SHIFT)RESET_ACTIVE_STATUS1_TIMER0_RST_SHIFT (0)RESET_ACTIVE_STATUS0_USB0_RST (1 << RESET_ACTIVE_STATUS0_USB0_RST_SHIFT)__LFRACT_EPSILON__ 0x1P-31LRRESET_STATUS0_MASTER_RST_MASK (0x3 << RESET_STATUS0_MASTER_RST_SHIFT)RESET_ACTIVE_STATUS1_M0APP_RST_SHIFT (24)RESET_EXT_STAT49 MMIO32(RGU_BASE + 0x4C4)__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX__RESET_CTRL1_UART1_RST_SHIFT (13)__FLT32X_NORM_MAX__ 1.7976931348623157e+308F32xRESET_EXT_STAT32_PERIPHERAL_RESET (1 << RESET_EXT_STAT32_PERIPHERAL_RESET_SHIFT)__arm__ 1INT_FAST64_MAX__INT8_TYPE__ signed char__FLT32_MIN_10_EXP__ (-37)RESET_STATUS2_TIMER2_RST_SHIFT (4)MMIO64(addr) (*(volatile uint64_t *)(addr))__ARM_FEATURE_BF16_VECTOR_ARITHMETIC__ARM_FP16_FORMAT_ALTERNATIVERESET_ACTIVE_STATUS1_UART2_RST (1 << RESET_ACTIVE_STATUS1_UART2_RST_SHIFT)__LDBL_NORM_MAX__ 1.7976931348623157e+308LRESET_CTRL1_ADC1_RST (1 << RESET_CTRL1_ADC1_RST_SHIFT)INTPTR_MINRESET_CTRL1_SSP0_RST_SHIFT (18)__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)RESET_CTRL1_CAN1_RST (1 << RESET_CTRL1_CAN1_RST_SHIFT)RESET_EXT_STAT36_PERIPHERAL_RESET (1 << RESET_EXT_STAT36_PERIPHERAL_RESET_SHIFT)__TA_IBIT__ 64__FLT32_MIN__ 1.1754943508222875e-38F32PERIPH_BASE_AHB (0x40000000U)RESET_STATUS2_TIMER3_RST_MASK (0x3 << RESET_STATUS2_TIMER3_RST_SHIFT)CREG_FLASHCFGA_FLASHTIM_SHIFT (12)CREG_CREG6_I2S0_TX_SCK_IN_SEL_SHIFT (12)__ARM_FEATURE_QRDMXCREG_DMAMUX_DMAMUXPER10(x) ((x) << CREG_DMAMUX_DMAMUXPER10_SHIFT)RESET_CTRL1_UART3_RST (1 << RESET_CTRL1_UART3_RST_SHIFT)RESET_EXT_STAT42_PERIPHERAL_RESET_SHIFT (2)__ARM_ARCH_ISA_THUMB 2__LONG_LONG_MAX__ 0x7fffffffffffffffLLRESET_STATUS2_TIMER1_RST_SHIFT (2)__WINT_WIDTH__ 32SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__RESET_EXT_STAT0_WWDT_RESET (1 << RESET_EXT_STAT0_WWDT_RESET_SHIFT)RESET_STATUS3 MMIO32(RGU_BASE + 0x11C)__USFRACT_FBIT__ 8BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN__RESET_EXT_STAT0_EXT_RESET_SHIFT (0)__SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)CREG_DMAMUX_DMAMUXPER1_MASK (0x3 << CREG_DMAMUX_DMAMUXPER1_SHIFT)__DBL_MIN_EXP__ (-1021)RESET_EXT_STAT52_PERIPHERAL_RESET_SHIFT (2)__LDBL_HAS_DENORM__ 1RESET_EXT_STAT35_PERIPHERAL_RESET (1 << RESET_EXT_STAT35_PERIPHERAL_RESET_SHIFT)INT8_MIN (-INT8_MAX - 1)RESET_CTRL0_GPIO_RST (1 << RESET_CTRL0_GPIO_RST_SHIFT)GPIO_GROUP1_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x09000)RESET_EXT_STAT20_MASTER_RESET (1 << RESET_EXT_STAT20_MASTER_RESET_SHIFT)RESET_STATUS2_UART1_RST(x) ((x) << RESET_STATUS2_UART1_RST_SHIFT)__FLT32_DIG__ 6INT_LEAST16_MAXRESET_STATUS2_ADC1_RST_MASK (0x3 << RESET_STATUS2_ADC1_RST_SHIFT)BIT15 (1<<15)BACKUP_REG_BASE (0x40041000U)RESET_EXT_STAT60 MMIO32(RGU_BASE + 0x4F0)CREG_DMAMUX_DMAMUXPER9_MASK (0x3 << CREG_DMAMUX_DMAMUXPER9_SHIFT)RESET_ACTIVE_STATUS0_DMA_RST_SHIFT (19)BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1GPIO_GROUP0_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x08000)__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1INT32_MAXRESET_EXT_STAT11 MMIO32(RGU_BASE + 0x42C)RESET_STATUS1_USB1_RST_SHIFT (4)LPC43XX_RGU_H LPC43XX_IPC_H __ARM_FEATURE_CRYPTO__INT_LEAST32_TYPE__ long intRESET_EXT_STAT18 MMIO32(RGU_BASE + 0x448)RESET_EXT_STAT9 MMIO32(RGU_BASE + 0x424)RESET_CTRL0_USB0_RST_SHIFT (17)BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULLCREG_DMAMUX_DMAMUXPER5_SHIFT (10)__FRACT_IBIT__ 0I2C1_BASE (PERIPH_BASE_APB3 + 0x00000)RESET_EXT_STAT21_MASTER_RESET_SHIFT (3)UINT_LEAST64_MAXcm0_baseaddrCREG_USB0FLADJ_FLTV_MASK (0x3f << CREG_USB0FLADJ_FLTV_SHIFT)BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234RESET_ACTIVE_STATUS1_DAC_RST_SHIFT (10)__FLT_NORM_MAX__ 3.4028234663852886e+38FCREG_M0APPMEMMAP_M0APPMAP(x) ((x) << CREG_M0APPMEMMAP_M0APPMAP_SHIFT)long long unsigned int__FLT_MIN_10_EXP__ (-37)BIT31 (1<<31)__ULACCUM_IBIT__ 32RESET_STATUS3_I2S_RST(x) ((x) << RESET_STATUS3_I2S_RST_SHIFT)__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2RESET_EXT_STAT38 MMIO32(RGU_BASE + 0x498)__PTRDIFF_TYPE__ intRESET_STATUS1_USB0_RST_SHIFT (2)__APCS_32__ 1__DQ_FBIT__ 63RESET_CTRL0_EEPROM_RST (1 << RESET_CTRL0_EEPROM_RST_SHIFT)RESET_STATUS3_I2C1_RST(x) ((x) << RESET_STATUS3_I2C1_RST_SHIFT)INT_LEAST64_MAX__SACCUM_IBIT__ 8RESET_STATUS2_TIMER1_RST(x) ((x) << RESET_STATUS2_TIMER1_RST_SHIFT)CREG_DMAMUX_DMAMUXPER0_SHIFT (0)__UHQ_IBIT__ 0INT_LEAST8_MINBIT29 (1<<29)CREG_DMAMUX_DMAMUXPER14_SHIFT (28)__INT_FAST16_TYPE__ intRESET_CTRL1_DAC_RST (1 << RESET_CTRL1_DAC_RST_SHIFT)INT64_CCREG_CREG0_RESET32KHZ_SHIFT (2)RESET_STATUS1_EEPROM_RST_MASK (0x3 << RESET_STATUS1_EEPROM_RST_SHIFT)__UINT_LEAST16_TYPE__ short unsigned intRESET_EXT_STAT5_CORE_RESET (1 << RESET_EXT_STAT5_CORE_RESET_SHIFT)INT_FAST16_MIN (-INT_FAST16_MAX - 1)__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned intRESET_ACTIVE_STATUS1_MOTOCONPWM_RST (1 << RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_SHIFT)CREG_DMAMUX_DMAMUXPER12_MASK (0x3 << CREG_DMAMUX_DMAMUXPER12_SHIFT)__FLT32X_DIG__ 15RESET_ACTIVE_STATUS0_DMA_RST (1 << RESET_ACTIVE_STATUS0_DMA_RST_SHIFT)CREG_CREG6_I2S1_TX_SCK_IN_SEL (1 << CREG_CREG6_I2S1_TX_SCK_IN_SEL_SHIFT)__UTQ_FBIT__ 128RESET_STATUS1_DMA_RST_MASK (0x3 << RESET_STATUS1_DMA_RST_SHIFT)CREG_M4MEMMAP MMIO32(CREG_BASE + 0x100)CREG_CREG0_BODLVL2_MASK (0x3 << CREG_CREG0_BODLVL2_SHIFT)RESET_STATUS1_SDIO_RST_SHIFT (8)RESET_EXT_STAT3 MMIO32(RGU_BASE + 0x40C)__FINITE_MATH_ONLY__ 0RESET_CTRL1_I2S_RST (1 << RESET_CTRL1_I2S_RST_SHIFT)__INT_FAST16_MAX__ 0x7fffffffPTRDIFF_MAX __PTRDIFF_MAX____SIZEOF_SHORT__ 2CREG_CREG6 MMIO32(CREG_BASE + 0x12C)RESET_EXT_STAT21 MMIO32(RGU_BASE + 0x454)RESET_ACTIVE_STATUS1_ADC0_RST (1 << RESET_ACTIVE_STATUS1_ADC0_RST_SHIFT)__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKRESET_EXT_STAT22_MASTER_RESET_SHIFT (3)UINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRCREG_DMAMUX_DMAMUXPER14(x) ((x) << CREG_DMAMUX_DMAMUXPER14_SHIFT)__DQ_IBIT__ 0RESET_EXT_STAT51_PERIPHERAL_RESET_SHIFT (2)__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intCREG_M4MEMMAP_M4MAP_MASK (0xfffff << CREG_M4MEMMAP_M4MAP_SHIFT)RESET_STATUS3_CAN0_RST_MASK (0x3 << RESET_STATUS3_CAN0_RST_SHIFT)SSP0_BASE (PERIPH_BASE_APB0 + 0x03000)QEI_BASE (PERIPH_BASE_APB2 + 0x06000)WCHAR_MINRESET_STATUS1 MMIO32(RGU_BASE + 0x114)RESET_STATUS2_QEI_RST_MASK (0x3 << RESET_STATUS2_QEI_RST_SHIFT)RESET_EXT_STAT36 MMIO32(RGU_BASE + 0x490)RESET_EXT_STAT28_PERIPHERAL_RESET (1 << RESET_EXT_STAT28_PERIPHERAL_RESET_SHIFT)BEGIN_DECLS RESET_STATUS3_I2C1_RST_MASK (0x3 << RESET_STATUS3_I2C1_RST_SHIFT)RESET_ACTIVE_STATUS1_TIMER1_RST_SHIFT (1)RESET_ACTIVE_STATUS1_SCT_RST (1 << RESET_ACTIVE_STATUS1_SCT_RST_SHIFT)CREG_DMAMUX_DMAMUXPER1_SHIFT (2)RESET_ACTIVE_STATUS1_QEI_RST (1 << RESET_ACTIVE_STATUS1_QEI_RST_SHIFT)CREG_DMAMUX_DMAMUXPER9_SHIFT (18)__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__FLT32X_MAX__ 1.7976931348623157e+308F32xRESET_STATUS1_USB0_RST_MASK (0x3 << RESET_STATUS1_USB0_RST_SHIFT)RESET_EXT_STAT35 MMIO32(RGU_BASE + 0x48C)__ARM_EABI__ 1RESET_CTRL0 MMIO32(RGU_BASE + 0x100)INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1CREG_CREG0_ALARMCTRL(x) ((x) << CREG_CREG0_ALARMCTRL_SHIFT)CREG_ETBCFG_ETB (1 << CREG_ETBCFG_ETB_SHIFT)__ARM_FEATURE_DSP 1RESET_STATUS1_ETHERNET_RST_SHIFT (12)USART3_BASE (PERIPH_BASE_APB2 + 0x02000)RESET_EXT_STAT26 MMIO32(RGU_BASE + 0x468)__QQ_IBIT__ 0CREG_CHIPID MMIO32(CREG_BASE + 0x200)RESET_ACTIVE_STATUS1_UART0_RST (1 << RESET_ACTIVE_STATUS1_UART0_RST_SHIFT)CREG_CREG0_WAKEUP1CTRL(x) ((x) << CREG_CREG0_WAKEUP1CTRL_SHIFT)RESET_CTRL0_PERIPH_RST (1 << RESET_CTRL0_PERIPH_RST_SHIFT)RESET_EXT_STAT45_PERIPHERAL_RESET (1 << RESET_EXT_STAT45_PERIPHERAL_RESET_SHIFT)__LLACCUM_FBIT__ 31RESET_STATUS3_SSP1_RST_SHIFT (6)__UINTMAX_TYPE__ long long unsigned intRESET_STATUS2_UART2_RST_SHIFT (28)RESET_EXT_STAT37 MMIO32(RGU_BASE + 0x494)__USQ_IBIT__ 0RESET_EXT_STAT5 MMIO32(RGU_BASE + 0x414)__UINT_LEAST32_TYPE__ long unsigned intRESET_STATUS0_CREG_RST_MASK (0x3 << RESET_STATUS0_CREG_RST_SHIFT)__ARM_FEATURE_NUMERIC_MAXMINRESET_EXT_STAT28_PERIPHERAL_RESET_SHIFT (2)__INTMAX_TYPE__ long long int__GCC_ATOMIC_INT_LOCK_FREE 2RESET_STATUS1_EEPROM_RST_SHIFT (22)RESET_ACTIVE_STATUS0_USB1_RST (1 << RESET_ACTIVE_STATUS0_USB1_RST_SHIFT)RESET_STATUS0_WWDT_RST(x) ((x) << RESET_STATUS0_WWDT_RST_SHIFT)CREG_CREG0_WAKEUP0CTRL(x) ((x) << CREG_CREG0_WAKEUP0CTRL_SHIFT)TIMER2_BASE (PERIPH_BASE_APB2 + 0x03000)RESET_EXT_STAT13_MASTER_RESET (1 << RESET_EXT_STAT13_MASTER_RESET_SHIFT)RESET_STATUS3_SPIFI_RST_MASK (0x3 << RESET_STATUS3_SPIFI_RST_SHIFT)__ARM_FEATURE_FP16_SCALAR_ARITHMETICRESET_STATUS3_CAN0_RST_SHIFT (14)__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1RESET_CTRL1_SPI_RST (1 << RESET_CTRL1_SPI_RST_SHIFT)__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CCREG_FLASHCFGB_FLASHTIM_SHIFT (12)CREG_DMAMUX_DMAMUXPER11_MASK (0x3 << CREG_DMAMUX_DMAMUXPER11_SHIFT)INT64_MIN__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intRESET_ACTIVE_STATUS1_UART2_RST_SHIFT (14)UINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRCREG_DMAMUX_DMAMUXPER0_MASK (0x3 << CREG_DMAMUX_DMAMUXPER0_SHIFT)__SIZEOF_SIZE_T__ 4RESET_CTRL1_ADC1_RST_SHIFT (9)CREG_DMAMUX_DMAMUXPER8_MASK (0x3 << CREG_DMAMUX_DMAMUXPER8_SHIFT)PMC_BASE (0x40042000U)__INT64_C(c) c ## LLRESET_CTRL1_UART0_RST (1 << RESET_CTRL1_UART0_RST_SHIFT)__ARM_ARCH_PROFILE 77RESET_CTRL1_RTIMER_RST (1 << RESET_CTRL1_RTIMER_RST_SHIFT)RESET_EXT_STAT31 MMIO32(RGU_BASE + 0x47C)UART1_BASE (PERIPH_BASE_APB0 + 0x02000)__LONG_MAX__ 0x7fffffffLRESET_EXT_STAT18_MASTER_RESET (1 << RESET_EXT_STAT18_MASTER_RESET_SHIFT)CREG_DMAMUX_DMAMUXPER5_MASK (0x3 << CREG_DMAMUX_DMAMUXPER5_SHIFT)__ARM_FEATURE_CDE__ACCUM_IBIT__ 16CREG_CREG6_CTOUTCTRL_SHIFT (4)RESET_STATUS3_M0APP_RST_SHIFT (16)RESET_CTRL1_QEI_RST (1 << RESET_CTRL1_QEI_RST_SHIFT)RESET_CTRL1_ADC0_RST_SHIFT (8)RESET_ACTIVE_STATUS1 MMIO32(RGU_BASE + 0x154)short intCREG_CREG5_M0APPTAPSEL (1 << CREG_CREG5_M0APPTAPSEL_SHIFT)RESET_EXT_STAT63 MMIO32(RGU_BASE + 0x4FC)CREG_CREG3 MMIO32(CREG_BASE + 0x110)__UINT16_C(c) cRESET_EXT_STAT40 MMIO32(RGU_BASE + 0x4A0)__UDA_IBIT__ 32RESET_STATUS1_GPIO_RST(x) ((x) << RESET_STATUS1_GPIO_RST_SHIFT)RESET_ACTIVE_STATUS1_I2S_RST (1 << RESET_ACTIVE_STATUS1_I2S_RST_SHIFT)RESET_ACTIVE_STATUS0_WWDT_RST (1 << RESET_ACTIVE_STATUS0_WWDT_RST_SHIFT)UINT_LEAST32_MAXCREG_DMAMUX_DMAMUXPER11(x) ((x) << CREG_DMAMUX_DMAMUXPER11_SHIFT)BIT2 (1<<2)__ATOMIC_RELAXED 0RESET_EXT_STAT33_PERIPHERAL_RESET_SHIFT (2)__ARM_FEATURE_COPROCCREG_DMAMUX_DMAMUXPER10_MASK (0x3 << CREG_DMAMUX_DMAMUXPER10_SHIFT)__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53RESET_STATUS0 MMIO32(RGU_BASE + 0x110)__ARM_FEATURE_FMA 1LPC43XX_M4 1BIT5 (1<<5)RESET_STATUS0_WWDT_RST_SHIFT (8)BIT1 (1<<1)INT8_CRESET_STATUS1_FLASHB_RST_MASK (0x3 << RESET_STATUS1_FLASHB_RST_SHIFT)INT_LEAST32_MAXCREG_M0APPMEMMAP_M0APPMAP_MASK (0xfffff << CREG_M0APPMEMMAP_M0APPMAP_SHIFT)__USES_INITFINI__ 1I2S1_BASE (PERIPH_BASE_APB1 + 0x03000)RESET_CTRL1_MOTOCONPWM_RST (1 << RESET_CTRL1_MOTOCONPWM_RST_SHIFT)RESET_EXT_STAT40_PERIPHERAL_RESET_SHIFT (2)__ULFRACT_MAX__ 0XFFFFFFFFP-32ULR__DBL_DECIMAL_DIG__ 17__ARM_FEATURE_SAT 1BIT8 (1<<8)RESET_ACTIVE_STATUS0_SDIO_RST_SHIFT (20)RESET_EXT_STAT44 MMIO32(RGU_BASE + 0x4B0)RESET_EXT_STAT58_PERIPHERAL_RESET_SHIFT (2)INT16_C(c) __INT16_C(c)UINT32_MAXRESET_CTRL1_ADC0_RST (1 << RESET_CTRL1_ADC0_RST_SHIFT)__INT16_MAX__ 0x7fffCREG_CREG6_EMC_CLK_SEL_SHIFT (16)RESET_CTRL1_CAN0_RST (1 << RESET_CTRL1_CAN0_RST_SHIFT)CREG_DMAMUX MMIO32(CREG_BASE + 0x11C)__INT_WIDTH__ 32__ARM_FEATURE_SIMD32 1RESET_ACTIVE_STATUS1_SGPIO_RST_SHIFT (25)rst_active_status1__QQ_FBIT__ 7RITIMER_BASE (PERIPH_BASE_APB2 + 0x00000)RESET_STATUS2_UART1_RST_MASK (0x3 << RESET_STATUS2_UART1_RST_SHIFT)__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64CREG_DMAMUX_DMAMUXPER7(x) ((x) << CREG_DMAMUX_DMAMUXPER7_SHIFT)RESET_ACTIVE_STATUS1_SPI_RST (1 << RESET_ACTIVE_STATUS1_SPI_RST_SHIFT)RESET_EXT_STAT57_PERIPHERAL_RESET (1 << RESET_EXT_STAT57_PERIPHERAL_RESET_SHIFT)__UTA_IBIT__ 64__ULLACCUM_IBIT__ 32RESET_EXT_STAT27_PERIPHERAL_RESET (1 << RESET_EXT_STAT27_PERIPHERAL_RESET_SHIFT)RGU_BASE (0x40053000U)__ULLFRACT_EPSILON__ 0x1P-64ULLRCREG_CREG0_WAKEUP0CTRL_SHIFT (14)RESET_ACTIVE_STATUS0_EMC_RST_SHIFT (21)RESET_CTRL0_PERIPH_RST_SHIFT (1)__SIZEOF_WINT_T__ 4RESET_CTRL1_I2C1_RST (1 << RESET_CTRL1_I2C1_RST_SHIFT)__ARM_FEATURE_UNALIGNED 1__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17RESET_EXT_STAT9_PERIPHERAL_RESET (1 << RESET_EXT_STAT9_PERIPHERAL_RESET_SHIFT)CREG_M4TXEVENT MMIO32(CREG_BASE + 0x130)RESET_EXT_STAT56_PERIPHERAL_RESET_SHIFT (2)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1__FLT32X_HAS_DENORM__ 1__ULLACCUM_MIN__ 0.0ULLKRESET_CTRL1_SCT_RST (1 << RESET_CTRL1_SCT_RST_SHIFT)GPIO_PIN_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x07000)RESET_ACTIVE_STATUS1_SSP0_RST (1 << RESET_ACTIVE_STATUS1_SSP0_RST_SHIFT)CREG_DMAMUX_DMAMUXPER5(x) ((x) << CREG_DMAMUX_DMAMUXPER5_SHIFT)RESET_ACTIVE_STATUS1_RITIMER_RST (1 << RESET_ACTIVE_STATUS1_RITIMER_RST_SHIFT)__ARM_ASM_SYNTAX_UNIFIED__ 1RESET_EXT_STAT0 MMIO32(RGU_BASE + 0x400)__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODRESET_CTRL0_DMA_RST_SHIFT (19)RTC_BASE (0x40046000U)RESET_STATUS3_SSP0_RST_MASK (0x3 << RESET_STATUS3_SSP0_RST_SHIFT)__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H RESET_STATUS2_DAC_RST_SHIFT (20)AES_BASE (0x400F1000U)RESET_STATUS0_PERIPH_RST_MASK (0x3 << RESET_STATUS0_PERIPH_RST_SHIFT)INT_LEAST64_MINRESET_EXT_STAT8_PERIPHERAL_RESET (1 << RESET_EXT_STAT8_PERIPHERAL_RESET_SHIFT)__GCC_CONSTRUCTIVE_SIZE 64CREG_ETBCFG_ETB_SHIFT (0)RESET_STATUS2_RITIMER_RST_SHIFT (8)__LLFRACT_IBIT__ 0RESET_STATUS1_FLASHB_RST_SHIFT (26)uint32_tRESET_ACTIVE_STATUS1_SCT_RST_SHIFT (5)BIT12 (1<<12)CREG_USB1FLADJ_FLTV_SHIFT (0)__ARM_PCS_VFP 1RESET_CTRL1_SPI_RST_SHIFT (26)RESET_STATUS1_GPIO_RST_SHIFT (24)__SACCUM_EPSILON__ 0x1P-7HKCREG_DMAMUX_DMAMUXPER4_MASK (0x3 << CREG_DMAMUX_DMAMUXPER4_SHIFT)__GCC_ASM_FLAG_OUTPUTS__ 1RESET_EXT_STAT56 MMIO32(RGU_BASE + 0x4E0)RESET_EXT_STAT4 MMIO32(RGU_BASE + 0x410)__ARM_FP 4RESET_CTRL1_TIMER2_RST_SHIFT (2)RESET_ACTIVE_STATUS0_GPIO_RST (1 << RESET_ACTIVE_STATUS0_GPIO_RST_SHIFT)__UINT_FAST16_TYPE__ unsigned intRESET_ACTIVE_STATUS0_CREG_RST (1 << RESET_ACTIVE_STATUS0_CREG_RST_SHIFT)__UHA_IBIT__ 8CREG_USB0FLADJ_FLTV(x) ((x) << CREG_USB0FLADJ_FLTV_SHIFT)__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULKRESET_ACTIVE_STATUS0_EEPROM_RST_SHIFT (27)__LDBL_DIG__ 15UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXRESET_STATUS3_SSP0_RST_SHIFT (4)BIT16 (1<<16)__WINT_MIN__ 0UINT_LEAST16_MIN__FLT64_DIG__ 15CREG_CREG6_I2S0_RX_SCK_IN_SEL (1 << CREG_CREG6_I2S0_RX_SCK_IN_SEL_SHIFT)RESET_EXT_STAT38_PERIPHERAL_RESET_SHIFT (2)__WINT_MAX__ 0xffffffffUBIT22 (1<<22)__INT_LEAST8_WIDTH__ 8RESET_EXT_STAT0_BOD_RESET_SHIFT (4)RESET_EXT_STAT39_PERIPHERAL_RESET_SHIFT (2)__INT_LEAST16_TYPE__ short intCREG_DMAMUX_DMAMUXPER8(x) ((x) << CREG_DMAMUX_DMAMUXPER8_SHIFT)__DBL_MAX__ ((double)1.7976931348623157e+308L)CREG_DMAMUX_DMAMUXPER4(x) ((x) << CREG_DMAMUX_DMAMUXPER4_SHIFT)INT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1UINTMAX_CRESET_EXT_STAT41_PERIPHERAL_RESET (1 << RESET_EXT_STAT41_PERIPHERAL_RESET_SHIFT)RESET_EXT_STAT5_CORE_RESET_SHIFT (1)INT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1RESET_ACTIVE_STATUS0_BUS_RST_SHIFT (8)__UINTPTR_MAX__ 0xffffffffU__HQ_FBIT__ 15__bool_true_false_are_defined 1RESET_EXT_STAT44_PERIPHERAL_RESET (1 << RESET_EXT_STAT44_PERIPHERAL_RESET_SHIFT)USART2_BASE (PERIPH_BASE_APB2 + 0x01000)BIT26 (1<<26)RESET_ACTIVE_STATUS0_EMC_RST (1 << RESET_ACTIVE_STATUS0_EMC_RST_SHIFT)__SIZE_MAX__ 0xffffffffURESET_CTRL0_FLASHA_RST (1 << RESET_CTRL0_FLASHA_RST_SHIFT)RESET_CTRL0_USB1_RST_SHIFT (18)RESET_CTRL0_EEPROM_RST_SHIFT (27)__ARM_ARCH__SFRACT_IBIT__ 0RESET_ACTIVE_STATUS1_SSP0_RST_SHIFT (18)RESET_CTRL1 MMIO32(RGU_BASE + 0x104)MCPWM_BASE (PERIPH_BASE_APB1 + 0x00000)RESET_CTRL1_SSP0_RST (1 << RESET_CTRL1_SSP0_RST_SHIFT)RESET_CTRL1_SCT_RST_SHIFT (5)RESET_EXT_STAT19_MASTER_RESET (1 << RESET_EXT_STAT19_MASTER_RESET_SHIFT)RESET_EXT_STAT21_MASTER_RESET (1 << RESET_EXT_STAT21_MASTER_RESET_SHIFT)LPC43XX_MEMORYMAP_H CREG_CREG5_M4TAPSEL_SHIFT (6)__ARM_FEATURE_LDREX 7RESET_ACTIVE_STATUS0_CORE_RST_SHIFT (0)PTRDIFF_MAXRESET_CTRL1_TIMER1_RST (1 << RESET_CTRL1_TIMER1_RST_SHIFT)RESET_CTRL1_SPIFI_RST_SHIFT (21)__LLFRACT_EPSILON__ 0x1P-63LLR__SFRACT_MAX__ 0X7FP-7HR__FLT32X_MANT_DIG__ 53RESET_EXT_STAT49_PERIPHERAL_RESET_SHIFT (2)__WCHAR_WIDTH__ 32RESET_EXT_STAT16_MASTER_RESET_SHIFT (3)RESET_STATUS2_ADC0_RST_SHIFT (16)WINT_MAXINTMAX_MAX__INT16_C(c) cRESET_ACTIVE_STATUS1_ADC0_RST_SHIFT (8)CREG_CREG0_USB0PHY_SHIFT (5)__DA_IBIT__ 32RESET_ACTIVE_STATUS0_ETHERNET_RST (1 << RESET_ACTIVE_STATUS0_ETHERNET_RST_SHIFT)RESET_STATUS2_UART1_RST_SHIFT (26)RESET_EXT_STAT43 MMIO32(RGU_BASE + 0x4AC)__ATOMIC_ACQ_REL 4ADC1_BASE (PERIPH_BASE_APB3 + 0x04000)__HQ_IBIT__ 0RESET_STATUS3_I2S_RST_MASK (0x3 << RESET_STATUS3_I2S_RST_SHIFT)__DBL_MIN_10_EXP__ (-307)RESET_STATUS1_EMC_RST_SHIFT (10)CREG_DMAMUX_DMAMUXPER3(x) ((x) << CREG_DMAMUX_DMAMUXPER3_SHIFT)RESET_STATUS1_EEPROM_RST(x) ((x) << RESET_STATUS1_EEPROM_RST_SHIFT)RESET_EXT_STAT10 MMIO32(RGU_BASE + 0x428)RESET_EXT_STAT15 MMIO32(RGU_BASE + 0x43C)RESET_CTRL0_DMA_RST (1 << RESET_CTRL0_DMA_RST_SHIFT)__FLT32_NORM_MAX__ 3.4028234663852886e+38F32RESET_CTRL0_LCD_RST_SHIFT (16)RESET_EXT_STAT2_PERIPHERAL_RESET (1 << RESET_EXT_STAT2_PERIPHERAL_RESET_SHIFT)UINT64_C(c) __UINT64_C(c)RESET_EXT_STAT2_PERIPHERAL_RESET_SHIFT (2)RESET_CTRL1_I2S_RST_SHIFT (20)RESET_STATUS2_UART0_RST_SHIFT (24)__UINTMAX_MAX__ 0xffffffffffffffffULL__DBL_MANT_DIG__ 53RESET_CTRL0_SCU_RST (1 << RESET_CTRL0_SCU_RST_SHIFT)__ULFRACT_IBIT__ 0INT_FAST16_MAX__INT_MAX__ 0x7fffffff__INT_LEAST64_TYPE__ long long intRESET_EXT_STAT47 MMIO32(RGU_BASE + 0x4BC)RESET_CTRL1_TIMER2_RST (1 << RESET_CTRL1_TIMER2_RST_SHIFT)CREG_M0APPMEMMAP_M0APPMAP_SHIFT (12)RESET_STATUS3_CAN1_RST(x) ((x) << RESET_STATUS3_CAN1_RST_SHIFT)__ARM_FEATURE_CDE_COPROCRESET_CTRL0_CORE_RST (1 << RESET_CTRL0_CORE_RST_SHIFT)RESET_STATUS0_PERIPH_RST_SHIFT (2)RESET_EXT_STAT32 MMIO32(RGU_BASE + 0x480)UINT32_C../ipc.cGCC: (15:12.2.rel1-1) 12.2.1 20221205 | (BN0ENA3aeabi)7E-M M  "     $   ( ')!#%+ 4e-\*-( 0 ipc.c$t$dwm4.0.ac8f3cbd7733ee78183be95102ca936awm4.common.h.21.c9066c2f6b12c71b40226ea6107829a4wm4.stdint.h.29.6d480f4ba0f60596e88234283d42444fwm4.stdbool.h.29.4a1c88fe569adb8d03217dd16982ca34wm4.common.h.67.5c568a1f62c8e726909b04e29f9e1fc0wm4.memorymap.h.22.395ffb693017d551ed93d11c39ba4361wm4.creg.h.36.6becb3aedddf02e82cc32e255e0e64efwm4.rgu.h.35.fb70e7ab2eda27dc3b52363603206e72ipc_halt_m0ipc_start_m0 "&-4;BIPUho}  $-3<FO #)/5;AGMSY_ekqw} %+17=CIOU[agmsy !'-39?EKQW]ciou{ #)/5;AGMSY_ekqw} %+17=CIOU[agmsy !'-39?EKQW]ciou{ #)/5;AGMSY_ekqw} %+17=CIOU[agmsy !'-39?EKQW]ciou{     # ) / 5 ; A G M S Y _ e k q w }                            % + 1 7 = C I O U [ a g m s y          #)/5;AGMSY_ekqx  '.5<CJQX_fmt{#*18?FMT[bipw~ &-4;BI  #)/5;AGMSY_ekqw} #)/5;AGMSY_ekqw} %+17=CIOU\ #)/5;AGMSY_ekqw}$+29@GNU\cjqx  '.5<CJQX_fmt{#*18?FMT[bipw~ #)/5;AGMSY_ekqw}$+29@GNU\cjqx  '.5<CJQX_fmt{#*18?FMT[bipw~ &-4;BIPW^elsz ")07>ELSZahov} %,3:AHOV]dkry !(/6=DKRY`gnu|$+29@GNU\cjqx     ' . 5 < C J Q X _ f m t {                        # * 1 8 ? F M T [ b i p w ~                        & - 4 ; B I P W ^ e l s z                        " ) 0 7 > E L S Z a h o v }                      2,0.symtab.strtab.shstrtab.text.data.bss.text.ipc_halt_m0.text.ipc_start_m0.rel.debug_info.debug_abbrev.rel.debug_aranges.rel.debug_rnglists.rel.debug_macro.rel.debug_line.debug_str.comment.rel.debug_frame.ARM.attributes.group4 .@ .L .X .d .p . | .! ."!',(>0UQ @.asZ(o @p. @.V @P.  @0.  @ . N @8." @(.% @80. a @h.!n @8p.#7  @.%L$ @.'0%0'@ @ .+p4/-  vector.o/ 0 0 0 644 47984 ` ELF(`4(:9 !"#$%&'()*+,-./pG82K2LB<1J$4FR A B#D+JB :"2D F3B`O!$J$M=PCs(= K!IB1 QI!1D*Fh`3BKQLMBT;GBLMBT;GBMLBT;GB80@5 G I!K0HZRt0;?Y4`(YG int{5u_-/ RM0R]51nmi2l3 00456O7W S8,90S:4f?;8DQ<<irq=g@ ?uguwu4@1ICuMC!u` C(u+C0uD0C7uDwvuu(uDy' 5 $w^!!$(#n k 83f\>  src@  L@ 1) fpA _M^ R  +Q| src L 4: ; 9 I?< :!; 9 I8 $ > : ; 9 I !I :!; 9!I8 I!I/ .?:!; 9!'@z 4:!; 9 IB 41B % Uy $ > 5I' : ; 9  : ; 9 I84G: ; 9 .?: ; 9 'I<.?: ; 9 '@|4: ; 9 IB1RB UX Y W  UH}.: ; 9 ' 4: ; 9 I4: ; 9 IRr|RQq|Q8STt| TTt|T(,T,.t|.2Tf&S|R,.J FI"#?@&)  5 N  < 1F6>J A. R,%L,<^,ICM3J$OP2AF 837> >RG _NMhI h K2>p(WP#A[E`)Nn+Hc5_)ZgMOO<G_\RBw/[Zr\)'(T.91]yB Z<2A_NS!Uv'\T)-$$6%JC*[]R#( /g*P('!%Ri&AFW+V6`I_ UW2   y 1' w=g 6(k#l0n,65pG /G0mA'?t"L_^PC]^7,d!T`[4&+aSYOZT)Q05AvV/LAQ@-C 1G+DC @FJ6P^3(+V[^  SZ  :2nL0-\21Un695F]I?Q& L[@1K$W 0"3'] +-i#lF{-)4C 3Z/2XC&=@ _JHmP[Y qOi]S.XUEQHOY(6;O2Q`EX'9ZG/a,6 ' V@IG/^JTZM)|K:|UWR>QM`x *JUV|L T.SqzP6"5 %I3*0aQ8_<4?BIEYP3Rz4[/\R_a/$c0a!K")#;CdTe+f*?g j}kn0o\"prLq#tQ2u xEEy//z[{P~G#\ ?*H$^->+wH=BD=Z?C(S<S RlSAHc XCF(S $$&_,_\^.) K(DJg3940WwA4-mNB]g!B]J.ZB-jC . K+] SA_=DTOzH. O7P f` Z_w [J?X!\!&3?'U2D\C D1.EF@I!LNQRSSRT|0UyVSWP1XY8TZ1[$ \B]HY^_'`DaZbc )d3Fe9(fDg[hzi)jFkd\lm+nHoY*pG+-.61U4'7:DuHK>)PQSVVY\"_y-b*e hMk(nCq\t.w]zh}53Xy1?9"HR$6*IDB:  , 5<uK\1P?G+ VVYsZM$E*g_]4$ELA%EE2%/],ONd>RkG^B MW[*cH1>@dR RJ\S(Wh!.DLQ^F FQY0}F\a*L&3<"E!KN].WXXezk@xPyF}C~&a'OXDo`u]U&&  .lUT'._A" W!*"&`#v $ %OE&6'R(U)P*#+T,N%-R./`K0#12;63n?45mW6^7 89 F:L;<(==>>@,E ../../cm3../../cm3/../dispatch/../lpc43xx/m4/usr/lib/gcc/arm-none-eabi/12.2.1/include../../../include/libopencm3/cm3../../../include/libopencm3/dispatch../../../include/libopencm3/lpc43xx/m4../../cm3/../dispatchvector.cvector_chipset.cstdint.hvector.hscb.hmemorymap.hcommon.hstdbool.hnvic.hnvic.hnvic.hvector_chipset.cvector_nvic.cvector_nvic.c> %##  .-/$    !&Q./.Q. / Q. / 1 I!$$ 0  t!    ! -% .')K.A'$1K.;$3$+1$/.;$2_etext_romSCB_DCCSW MMIO32(SCB_BASE + 0x26C)SCB_SHPR_PRI_4_MEMMANAGE 0SCB_BASE (SCS_BASE + 0x0D00)__UHA_FBIT__ 8NVIC_M0CORE_IRQ 1__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64CORESIGHT_LSR_SLK (1<<1)__GCC_ATOMIC_WCHAR_T_LOCK_FREE 2__CHAR_UNSIGNED__ 1pre_mainbus_faultNVIC_RTC_IRQ 47NVIC_WWDT_IRQ 49__FLT64_HAS_INFINITY__ 1SCB_AIRCR_PRIGROUP_GROUP4_SUB4 (0x5 << 8)__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GNUC_MINOR__ 2__GCC_DESTRUCTIVE_SIZE 64__LACCUM_EPSILON__ 0x1P-31LK__PTRDIFF_MAX__ 0x7fffffff__ARM_FEATURE_FMA 1__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)__INTMAX_MAX__ 0x7fffffffffffffffLL__TQ_IBIT__ 0__FLT64_DECIMAL_DIG__ 17SCB_CFSR_INVSTATE (1 << 17)WINT_MIN __WINT_MIN__INT_FAST64_MAX__ATOMIC_CONSUME 1__ULACCUM_FBIT__ 32__WCHAR_MAX__ 0xffffffffUSCB_SHCSR_SVCALLPENDED (1 << 15)INT64_MAX __INT64_MAX__INTMAX_MIN__SIZEOF_LONG_LONG__ 8__DBL_MAX_10_EXP__ 308__FRACT_MIN__ (-0.5R-0.5R)__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLK__USACCUM_MAX__ 0XFFFFP-8UHK__SFRACT_FBIT__ 7__INTMAX_WIDTH__ 64__ARM_FEATURE_BF16_SCALAR_ARITHMETIC__SQ_IBIT__ 0__ORDER_PDP_ENDIAN__ 3412__SIZE_TYPE__ unsigned int__FLT_HAS_DENORM__ 1__INT8_TYPE__ signed char__FLT32_MIN__ 1.1754943508222875e-38F32SCB_SCR MMIO32(SCB_BASE + 0x10)__USACCUM_MIN__ 0.0UHKNVIC_PIN_INT3_IRQ 35SCB_CCR MMIO32(SCB_BASE + 0x14)SCB_CPACR_NONE 0__DECIMAL_DIG__ 17__LDBL_MIN_EXP__ (-1021)UINTPTR_MAX __UINTPTR_MAX____LDBL_MANT_DIG__ 53__fini_array_endSCB_HFSR_FORCED (1 << 30)NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + ((iser_id) * 4))__UINT8_C(c) c__INT16_TYPE__ short intSCB_AIRCR_VECTRESET (1 << 0)__FLT64_MAX__ 1.7976931348623157e+308F64SCB_SHPR(ipr_id) MMIO8(SCS_BASE + 0xD18 + (ipr_id))UINT_FAST32_MAXLIBOPENCM3_NVIC_H INT_FAST64_MAX __INT_FAST64_MAX____GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1NVIC_MCPWM_IRQ 16__UINT_LEAST16_MAX__ 0xffff__STDC_HOSTED__ 1__ULLFRACT_FBIT__ 64__SIG_ATOMIC_TYPE__ intSCB_AIRCR_PRIGROUP_GROUP2_SUB8 (0x6 << 8)SCB_CFSR_STKERR (1 << 12)SCB_DCISW MMIO32(SCB_BASE + 0x260)__INT_FAST64_TYPE__ long long int__WINT_TYPE__ unsigned intSCB_CPUID_REVISION_LSB 0NVIC_C_CAN0_IRQ 51INT32_MIN (-INT32_MAX - 1)SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 (0x7 << 8)__FLT32_MAX_10_EXP__ 38vector_table_tNVIC_PENDSV_IRQ -2_text_ramSCB_AIRCR_ENDIANESS (1 << 15)__USFRACT_MAX__ 0XFFP-8UHR__FP_FAST_FMAF32 1__UINTPTR_MAX__ 0xffffffffU__FLT32_MIN_EXP__ (-125)UINT32_MAX __UINT32_MAX__NVIC_ADC1_IRQ 21SCB_SHCSR_BUSFAULTACT (1 << 1)__ULFRACT_FBIT__ 32INT8_MIN (-INT8_MAX - 1)__FLT64_MIN_10_EXP__ (-307)NVIC_LCD_IRQ 7__GNUC_EXECUTION_CHARSET_NAME "UTF-8"BIT10 (1<<10)__INT_FAST64_WIDTH__ 64__STDC_VERSION__ 199901LINT_LEAST64_MAX __INT_LEAST64_MAX__openblt_signature__SFRACT_EPSILON__ 0x1P-7HRSCB_CCR_NONBASETHRDENA (1 << 0)__INT32_C(c) c ## LUINT32_C(c) __UINT32_C(c)__ORDER_BIG_ENDIAN__ 4321SIZE_MAX__SQ_FBIT__ 31DWT_BASE (PPBI_BASE + 0x1000)INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)__UHQ_FBIT__ 16NVIC_SSP0_IRQ 22__FLT64_MIN_EXP__ (-1021)__PTRDIFF_WIDTH__ 32__UINT_FAST8_MAX__ 0xffffffffUSCB_ID_DFR0 MMIO32(SCB_BASE + 0x48)UINT16_C(c) __UINT16_C(c)__LACCUM_IBIT__ 32SCB_DCIMVAC MMIO32(SCB_BASE + 0x25C)__INT_FAST16_WIDTH__ 32INTMAX_C__VERSION__ "12.2.1 20221205"__VFP_FP__ 1__LLFRACT_MIN__ (-0.5LLR-0.5LLR)INT_FAST8_MAXSCB_SHPR_PRI_9_RESERVED 5__UINT_FAST16_MAX__ 0xffffffffU__INTPTR_MAX__ 0x7fffffffINT64_C(c) __INT64_C(c)SCB_CTR_DMINLINE_SHIFT 16_edata__GCC_IEC_559_COMPLEX 0__UFRACT_MIN__ 0.0URSCB_DCCMVAU MMIO32(SCB_BASE + 0x264)WCHAR_MAX __WCHAR_MAX____FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX____UINT_LEAST8_TYPE__ unsigned char__ACCUM_FBIT__ 15SCB_SCR_SLEEPONEXIT (1 << 1)__UACCUM_IBIT__ 16long intUINT8_MAXSCB_MMFAR MMIO32(SCB_BASE + 0x34)SIZE_MAX __SIZE_MAX____INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1__FLT32X_EPSILON__ 2.2204460492503131e-16F32x__UINT_FAST64_MAX__ 0xffffffffffffffffULLNVIC_BASE (SCS_BASE + 0x0100)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32__UINTMAX_C(c) c ## ULL__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed charNVIC_MEM_MANAGE_IRQ -12__GCC_ATOMIC_BOOL_LOCK_FREE 2BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON____FLT32_MAX_EXP__ 128SCB_BFAR MMIO32(SCB_BASE + 0x38)main__THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRshort unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)BIT7 (1<<7)UINT_FAST8_MAX __UINT_FAST8_MAX____FLT32X_MIN_10_EXP__ (-307)UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)__DBL_IS_IEC_60559__ 2__UINT_FAST32_MAX__ 0xffffffffU__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4SCB_SCR_SLEEPDEEP (1 << 2)LIBOPENCM3_VECTOR_H INTMAX_MAX __INTMAX_MAX____INT_LEAST32_WIDTH__ 32SCB_SHCSR_MEMFAULTENA (1 << 16)SCB_HFSR_VECTTBL (1 << 1)BIT27 (1<<27)SCB_SHPR_PRI_13_RESERVED 9__UTA_FBIT__ 64INTMAX_C(c) __INTMAX_C(c)__FLT_DECIMAL_DIG__ 9SCB_CPUID_VARIANT (0xF << SCB_CPUID_VARIANT_LSB)__thumb__ 1__INT_LEAST32_MAX__ 0x7fffffffLsigned charINT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)INT32_C(c) __INT32_C(c)__GNUC_STDC_INLINE__ 1__FRACT_FBIT__ 15__LLACCUM_EPSILON__ 0x1P-31LLK__GNUC_PATCHLEVEL__ 1__preinit_array_startPTRDIFF_MINSCB_CPUID_VARIANT_LSB 20__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)SCB_CPACR_CP10 (1 << 20)PPBI_BASE (0xE0000000U)__ARM_ARCH_PROFILE 77NVIC_SDIO_IRQ 6null_handler__FLT64_MAX_10_EXP__ 308MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINNVIC_PIN_INT0_IRQ 32SCB_CFSR_MUNSTKERR (1 << 3)SCB_CCSIDR MMIO32(SCB_BASE + 0x80)__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38SCB_ICIALLU MMIO32(SCB_BASE + 0x250)__FRACT_MAX__ 0X7FFFP-15RGNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -O2 -std=c99 -fno-common -ffunction-sections -fdata-sectionsSCB_ICSR_PENDSVSET (1 << 28)__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5SCB_CPACR MMIO32(SCB_BASE + 0x88)NVIC_USAGE_FAULT_IRQ -10NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + (ipr_id))NVIC_EVENTROUTER_IRQ 42NVIC_PIN_INT6_IRQ 38__UINT16_MAX__ 0xffff__TQ_FBIT__ 127usage_fault__USQ_FBIT__ 32INT_FAST16_MIN__thumb2__ 1__ULLACCUM_FBIT__ 32SCB_AIRCR_VECTKEY (0x05FA << SCB_AIRCR_VECTKEYSTAT_LSB)SCB_SHCSR MMIO32(SCB_BASE + 0x24)__TA_IBIT__ 64NVIC_USB1_IRQ 9__STRICT_ANSI__ 1SCB_CFSR_DACCVIOL (1 << 1)UINT_LEAST8_MAXSCB_VTOR_TBLOFF (0x7FFFFF << SCB_VTOR_TBLOFF_LSB)UINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8SCB_ID_ISAR1 MMIO32(SCB_BASE + 0x64)__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__SCB_SHCSR_PENDSVACT (1 << 10)__USA_IBIT__ 16__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1PTRDIFF_MIN (-PTRDIFF_MAX - 1)__UINT_FAST64_TYPE__ long long unsigned int__preinit_array_enddebug_monitor__FLT_MIN__ 1.1754943508222875e-38F__HA_FBIT__ 7__FDPIC____FLT32_IS_IEC_60559__ 2NVIC_TIMER0_IRQ 12INT_FAST64_MINSCB_CFSR_IACCVIOL (1 << 0)__USFRACT_IBIT__ 0__LDBL_EPSILON__ 2.2204460492503131e-16L__USFRACT_MIN__ 0.0UHRSCB_CFSR_PRECISERR (1 << 9)SCB_SHCSR_BUSFAULTENA (1 << 17)__ARM_NEON__UINT8_MAX__ 0xffSCB_CTR_ERG_MASK 0xf__LDBL_MAX_EXP__ 1024SCB_CTR MMIO32(SCB_BASE + 0x7C)SCB_SHCSR_USGFAULTENA (1 << 18)SCB_ICSR_RETOBASE (1 << 11)__DBL_HAS_DENORM__ 1_etext_ram__DA_FBIT__ 31BIT17 (1<<17)__GXX_ABI_VERSION 1017__INT_LEAST16_MAX__ 0x7fff__FLT_DENORM_MIN__ 1.4012984643248171e-45Fvector_tableINT_LEAST32_MAX __INT_LEAST32_MAX____ULLACCUM_EPSILON__ 0x1P-32ULLKSCB_SHCSR_MEMFAULTACT (1 << 0)hard_faultINT_LEAST8_MAX __INT_LEAST8_MAX____UINT32_C(c) c ## ULUINTMAX_MAX__UACCUM_MIN__ 0.0UKSCS_BASE (PPBI_BASE + 0xE000)__init_array_startSCB_CCSELR MMIO32(SCB_BASE + 0x84)__SIZEOF_DOUBLE__ 8__ARM_ARCH_ISA_THUMBSCB_ID_AFR0 MMIO32(SCB_BASE + 0x4C)LIBOPENCM3_CM3_MEMORYMAP_H __GCC_ATOMIC_SHORT_LOCK_FREE 2SCB_FPCAR MMIO32(SCB_BASE + 0x238)__USACCUM_FBIT__ 8__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1NVIC_GINT1_IRQ 41__LACCUM_FBIT__ 31SCB_CPUID_CONSTANT (0xF << SCB_CPUID_CONSTANT_LSB)__FLT32_HAS_QUIET_NAN__ 1__ARM_FEATURE_MATMUL_INT8__LDBL_HAS_INFINITY__ 1__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))__FLT32X_MAX_10_EXP__ 308SCB_SHPR_PRI_5_BUSFAULT 1__ARM_ARCH_EXT_IDIV__ 1../../cm3/vector.cbool _BoolUINTMAX_MAX __UINTMAX_MAX____SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffSCB_CTR_FORMAT_SHIFT 29BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)SCB_FPCCR MMIO32(SCB_BASE + 0x234)INT16_MAX __INT16_MAX____FP_FAST_FMAF 1__FLT32X_IS_IEC_60559__ 2SCB_AFSR MMIO32(SCB_BASE + 0x3C)NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + ((icer_id) * 4))NVIC_ADC0_IRQ 17LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))UINT32_MAX__INT_LEAST16_WIDTH__ 16__DEC_EVAL_METHOD__ 2__ARM_FEATURE_FP16_FMLNVIC_I2S0_IRQ 28NVIC_PIN_INT2_IRQ 34INT16_MIN (-INT16_MAX - 1)__USFRACT_EPSILON__ 0x1P-8UHRSCB_SCR_SEVONPEND (1 << 4)SCB_ICSR_PENDSTCLR (1 << 25)CORESIGHT_LSR_SLI (1<<0)INT64_MINSCB_MVFR0 MMIO32(SCB_BASE + 0x240)__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX____UINT32_MAX__ 0xffffffffULSCB_CCR_UNALIGN_TRP (1 << 3)SCB_CCR_USERSETMPEND (1 << 1)__INT_LEAST8_MAX__ 0x7fNVIC_SPIFI_IRQ 30__GCC_ATOMIC_POINTER_LOCK_FREE 2__ARM_FEATURE_QBIT 1__ARM_FEATURE_CLZ 1__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXSCB_ICSR_VECTPENDING_LSB 12SCB_ICSR_VECTACTIVE (0x1FF << SCB_ICSR_VECTACTIVE_LSB)NVIC_ETHERNET_IRQ 5__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024__UINT_LEAST32_MAX__ 0xffffffffULNVIC_BUS_FAULT_IRQ -11__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)NVIC_TIMER1_IRQ 13__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1__ACCUM_MAX__ 0X7FFFFFFFP-15K__INT8_MAX__ 0x7fSCB_AIRCR MMIO32(SCB_BASE + 0x0C)BIT14 (1<<14)__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16__SHRT_WIDTH__ 16BIT20 (1<<20)__ARM_FEATURE_MVE__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intSCB_ID_MMFR0 MMIO32(SCB_BASE + 0x50)UINT_LEAST16_MAX __UINT_LEAST16_MAX__INT_FAST32_MIN__FLT_EVAL_METHOD_TS_18661_3__ 0__SCHAR_WIDTH__ 8BIT18 (1<<18)UINT_FAST16_MAXSCB_DFSR MMIO32(SCB_BASE + 0x30)__UINT_FAST8_TYPE__ unsigned int__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RBIT24 (1<<24)__UINT_LEAST16_TYPE__ short unsigned int__INT32_MAX__ 0x7fffffffLSCB_CFSR_NOCP (1 << 19)SCB_ICSR_NMIPENDSET (1 << 31)SCB_MVFR1 MMIO32(SCB_BASE + 0x244)BIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLLNVIC_I2C1_IRQ 19__ARM_FEATURE_BF16_VECTOR_ARITHMETICSCB_ID_PFR1 MMIO32(SCB_BASE + 0x44)SCB_CPACR_CP11 (1 << 22)__FLT32_MANT_DIG__ 24INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN____USFRACT_FBIT__ 8INT8_MAX __INT8_MAX__BIT28 (1<<28)_ebss__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2SCB_DCCMVAC MMIO32(SCB_BASE + 0x268)__DBL_MAX_EXP__ 1024__ATOMIC_RELEASE 3UINT_FAST8_MAX__FLT_MANT_DIG__ 24__UDQ_IBIT__ 0NVIC_IRQ_COUNT 53SCB_AIRCR_VECTKEYSTAT (0xFFFF << SCB_AIRCR_VECTKEYSTAT_LSB)__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UKSCB_CPUID MMIO32(SCB_BASE + 0x00)__FLT64_NORM_MAX__ 1.7976931348623157e+308F64INT64_MIN (-INT64_MAX - 1)SCB_ID_PFR0 MMIO32(SCB_BASE + 0x40)UINTPTR_MAX__LDBL_DENORM_MIN__ 4.9406564584124654e-324L__INT64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_SAT 1NVIC_USB0_IRQ 8__ULLFRACT_IBIT__ 0MMIO16(addr) (*(volatile uint16_t *)(addr))NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + ((icpr_id) * 4))LPC43XX 1SCB_CTR_FORMAT_MASK 0x7__GNUC__ 12SCB_ID_MMFR3 MMIO32(SCB_BASE + 0x5C)WCHAR_MAX__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0U__UQQ_IBIT__ 0CORESIGHT_LSR_OFFSET 0xfb4__GCC_ATOMIC_LONG_LOCK_FREE 2__ULACCUM_MIN__ 0.0ULKSCB_VTOR_TBLOFF_LSB 9__LDBL_MAX__ 1.7976931348623157e+308L__ARM_ARCH 7memory_manage_fault_stack/build/libopencm3/lib/lpc43xx/m4__FLT_RADIX__ 2BIT3 (1<<3)long long intCORESIGHT_LAR_KEY 0xC5ACCE55__FLT_EPSILON__ 1.1920928955078125e-7F__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAX__LDBL_HAS_QUIET_NAN__ 1SCB_CFSR_UNDEFINSTR (1 << 16)__LONG_LONG_WIDTH__ 64BIT6 (1<<6)SCB_CPUID_IMPLEMENTER_LSB 24SCB_ID_ISAR4 MMIO32(SCB_BASE + 0x70)__ARM_FP__HA_IBIT__ 8__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1BIT9 (1<<9)__FLT32X_MIN__ 2.2250738585072014e-308F32xSCB_CCR_DIV_0_TRP (1 << 4)__FLT64_MAX_EXP__ 1024UINT16_MAX__FLT64_MIN__ 2.2250738585072014e-308F64__INTMAX_C(c) c ## LL__ARM_ARCH_PROFILE__INT64_TYPE__ long long intSCB_ICSR_VECTACTIVE_LSB 0__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4__UFRACT_MAX__ 0XFFFFP-16URblocking_handlerFPB_BASE (PPBI_BASE + 0x2000)INT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0STIR_BASE (SCS_BASE + 0x0F00)__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__SCB_ICSR_PENDSTSET (1 << 26)ID_BASE (SCS_BASE + 0x0FD0)SYS_TICK_BASE (SCS_BASE + 0x0010)SCB_AIRCR_VECTCLRACTIVE (1 << 1)__UFRACT_FBIT__ 16__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)__LDBL_MAX_10_EXP__ 308SCB_CCR_DC (1 << 16)reset__INT_FAST32_TYPE__ intunsigned intSCB_ID_ISAR2 MMIO32(SCB_BASE + 0x68)SCB_DCCIMVAC MMIO32(SCB_BASE + 0x270)__init_array_end__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1NVIC_USART0_IRQ 24__USACCUM_IBIT__ 8NVIC_PIN_INT4_IRQ 36ITM_BASE (PPBI_BASE + 0x0000)__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UKSCB_ICSR MMIO32(SCB_BASE + 0x04)__UTA_IBIT__ 64__FLT_EVAL_METHOD__ 0IRQ_HANDLERS [NVIC_DAC_IRQ] = dac_isr, [NVIC_M0CORE_IRQ] = m0core_isr, [NVIC_DMA_IRQ] = dma_isr, [NVIC_ETHERNET_IRQ] = ethernet_isr, [NVIC_SDIO_IRQ] = sdio_isr, [NVIC_LCD_IRQ] = lcd_isr, [NVIC_USB0_IRQ] = usb0_isr, [NVIC_USB1_IRQ] = usb1_isr, [NVIC_SCT_IRQ] = sct_isr, [NVIC_RITIMER_IRQ] = ritimer_isr, [NVIC_TIMER0_IRQ] = timer0_isr, [NVIC_TIMER1_IRQ] = timer1_isr, [NVIC_TIMER2_IRQ] = timer2_isr, [NVIC_TIMER3_IRQ] = timer3_isr, [NVIC_MCPWM_IRQ] = mcpwm_isr, [NVIC_ADC0_IRQ] = adc0_isr, [NVIC_I2C0_IRQ] = i2c0_isr, [NVIC_I2C1_IRQ] = i2c1_isr, [NVIC_SPI_IRQ] = spi_isr, [NVIC_ADC1_IRQ] = adc1_isr, [NVIC_SSP0_IRQ] = ssp0_isr, [NVIC_SSP1_IRQ] = ssp1_isr, [NVIC_USART0_IRQ] = usart0_isr, [NVIC_UART1_IRQ] = uart1_isr, [NVIC_USART2_IRQ] = usart2_isr, [NVIC_USART3_IRQ] = usart3_isr, [NVIC_I2S0_IRQ] = i2s0_isr, [NVIC_I2S1_IRQ] = i2s1_isr, [NVIC_SPIFI_IRQ] = spifi_isr, [NVIC_SGPIO_IRQ] = sgpio_isr, [NVIC_PIN_INT0_IRQ] = pin_int0_isr, [NVIC_PIN_INT1_IRQ] = pin_int1_isr, [NVIC_PIN_INT2_IRQ] = pin_int2_isr, [NVIC_PIN_INT3_IRQ] = pin_int3_isr, [NVIC_PIN_INT4_IRQ] = pin_int4_isr, [NVIC_PIN_INT5_IRQ] = pin_int5_isr, [NVIC_PIN_INT6_IRQ] = pin_int6_isr, [NVIC_PIN_INT7_IRQ] = pin_int7_isr, [NVIC_GINT0_IRQ] = gint0_isr, [NVIC_GINT1_IRQ] = gint1_isr, [NVIC_EVENTROUTER_IRQ] = eventrouter_isr, [NVIC_C_CAN1_IRQ] = c_can1_isr, [NVIC_ATIMER_IRQ] = atimer_isr, [NVIC_RTC_IRQ] = rtc_isr, [NVIC_WWDT_IRQ] = wwdt_isr, [NVIC_C_CAN0_IRQ] = c_can0_isr, [NVIC_QEI_IRQ] = qei_isrCREG_M4MEMMAP MMIO32((0x40043000U + 0x100))__SCHAR_MAX__ 0x7fINT_LEAST32_MINSCB_DCCISW MMIO32(SCB_BASE + 0x274)SCB_SHPR_PRI_6_USAGEFAULT 2__ARM_FEATURE_LDREX__UQQ_FBIT__ 8INT16_C__ARM_FP16_ARGS__GCC_IEC_559 0INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX____LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4NVIC_QEI_IRQ 52__STDC__ 1__ARM_FEATURE_IDIV 1__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8)__UINT8_TYPE__ unsigned charSCB_SHCSR_SYSTICKACT (1 << 11)__ARM_FEATURE_COPROC 15UINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"INT8_MINtrue 1__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)pend_svNVIC_PIN_INT5_IRQ 37__FLT32X_MIN_EXP__ (-1021)INT64_MAXINT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1__GCC_ATOMIC_CHAR_LOCK_FREE 2__LFRACT_EPSILON__ 0x1P-31LR__ARM_SIZEOF_MINIMAL_ENUM 1SCB_CFSR_BFARVALID (1 << 15)__FLT32X_NORM_MAX__ 1.7976931348623157e+308F32x__arm__ 1__FLT32_MIN_10_EXP__ (-37)SCB_SHCSR_USGFAULTPENDED (1 << 12)MMIO64(addr) (*(volatile uint64_t *)(addr))NVIC_STIR MMIO32(STIR_BASE)NVIC_TIMER3_IRQ 15__ARM_FP16_FORMAT_ALTERNATIVE__LDBL_NORM_MAX__ 1.7976931348623157e+308LINTPTR_MIN__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)SCB_AIRCR_SYSRESETREQ (1 << 2)SCB_ICSR_ISRPENDING (1 << 22)SCB_AIRCR_PRIGROUP_SHIFT 8__ARM_FEATURE_QRDMXSCB_SHCSR_USGFAULTACT (1 << 3)__ARM_ARCH_ISA_THUMB 2__LONG_LONG_MAX__ 0x7fffffffffffffffLL__WINT_WIDTH__ 32SCB_ICIMVAU MMIO32(SCB_BASE + 0x258)SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__UINT_LEAST8_MAX __UINT_LEAST8_MAX__BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN____SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__DBL_MIN_EXP__ (-1021)__LDBL_HAS_DENORM__ 1SCB_ID_MMFR1 MMIO32(SCB_BASE + 0x54)INT_FAST32_MIN (-INT_FAST32_MAX - 1)SCB_AIRCR_PRIGROUP_MASK (0x7 << 8)__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2SCB_CTR_CWG_SHIFT 24__FLT32_DIG__ 6INT_LEAST16_MAXfuncp_tBIT15 (1<<15)NVIC_SYSTICK_IRQ -1BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1INT32_MAXNVIC_SSP1_IRQ 23__ACCUM_MIN__ (-0X1P15K-0X1P15K)SCB_ICSR_VECTPENDING (0x1FF << SCB_ICSR_VECTPENDING_LSB)__ARM_FEATURE_CRYPTO__INT_LEAST32_TYPE__ long intSCB_CPUID_REVISION (0xF << SCB_CPUID_REVISION_LSB)NVIC_C_CAN1_IRQ 43BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__FRACT_IBIT__ 0SCB_CPACR_PRIV 1UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234NVIC_HARD_FAULT_IRQ -13SCB_CTR_DMINLINE_MASK 0x1f__FLT_NORM_MAX__ 3.4028234663852886e+38FSCB_CPUID_CONSTANT_LSB 16long long unsigned int__FLT_MIN_10_EXP__ (-37)BIT31 (1<<31)SCB_SHCSR_MONITORACT (1 << 8)__ULACCUM_IBIT__ 32__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__PTRDIFF_TYPE__ int__APCS_32__ 1__DQ_FBIT__ 63SCB_SHPR_PRI_8_RESERVED 4INT_LEAST64_MAX__SACCUM_IBIT__ 8SCB_CFSR_INVPC (1 << 18)__UHQ_IBIT__ 0INT_LEAST8_MINSCB_FPDSCR MMIO32(SCB_BASE + 0x23C)BIT29 (1<<29)__INT_FAST16_TYPE__ intINT64_C__ULFRACT_MAX__ 0XFFFFFFFFP-32ULRSCB_SHCSR_BUSFAULTPENDED (1 << 14)_data_loadaddr__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned int__FLT32X_DIG__ 15__UTQ_FBIT__ 128LIBOPENCM3_SCB_H SCB_CLIDR MMIO32(SCB_BASE + 0x78)__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffffPTRDIFF_MAX __PTRDIFF_MAX____SIZEOF_SHORT__ 2__FLT32_DECIMAL_DIG__ 9__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKUINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRSCB_CFSR_IBUSERR (1 << 8)__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intNVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + ((ispr_id) * 4))NVIC_PIN_INT1_IRQ 33SCB_BPIALL MMIO32(SCB_BASE + 0x278)WCHAR_MINBEGIN_DECLS __LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__FLT32X_MAX__ 1.7976931348623157e+308F32xSCB_ICSR_ISRPREEMPT (1 << 23)__ARM_EABI__ 1INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1NVIC_ATIMER_IRQ 46__ARM_FEATURE_DSP 1destSCB_GET_EXCEPTION_STACK_FRAME(f) do { asm volatile ("mov %[frameptr], sp" : [frameptr]"=r" (f)); } while (0)__QQ_IBIT__ 0SCB_SHPR_PRI_14_PENDSV 10SCB_SHPR_PRI_12_RESERVED 8__LLACCUM_FBIT__ 31_datainitial_sp_value__UINTMAX_TYPE__ long long unsigned int__USQ_IBIT__ 0SCB_CPUID_PARTNO (0xFFF << SCB_CPUID_PARTNO_LSB)__UINT_LEAST32_TYPE__ long unsigned int__ARM_FEATURE_NUMERIC_MAXMIN__INTMAX_TYPE__ long long int__GCC_ATOMIC_INT_LOCK_FREE 2SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8)INTMAX_MAXLIBOPENCM3_LPC43xx_M4_NVIC_H __ARM_ARCH_7EM__ 1__ARM_FEATURE_FP16_SCALAR_ARITHMETICNVIC_SV_CALL_IRQ -5__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_Creserved_x001c__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intNVIC_NMI_IRQ -14UINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRNVIC_USART3_IRQ 27__SIZEOF_SIZE_T__ 4__UINT64_TYPE__ long long unsigned int__INT64_C(c) c ## LLSCB_CPUID_IMPLEMENTER (0xFF << SCB_CPUID_IMPLEMENTER_LSB)__LDBL_MIN_10_EXP__ (-307)systickSCB_CTR_CWG_MASK 0xfTPIU_BASE (PPBI_BASE + 0x40000)SCB_CTR_IMINLINE_SHIFT 0__LDBL_MIN__ 2.2250738585072014e-308LSCB_CFSR MMIO32(SCB_BASE + 0x28)__ARM_FEATURE_CDE__ACCUM_IBIT__ 16CORESIGHT_LAR_OFFSET 0xfb0SCB_CFSR_IMPRECISERR (1 << 10)SCB_SHPR_PRI_15_SYSTICK 11short intSCB_CFSR_UNSTKERR (1 << 11)__UINT16_C(c) c__UDA_IBIT__ 32NVIC_UART1_IRQ 25UINT_LEAST32_MAXNVIC_SGPIO_IRQ 31BIT2 (1<<2)__ATOMIC_RELAXED 0__ARM_FEATURE_COPROCsv_call__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53LPC43XX_M4 1reserved_x0034BIT5 (1<<5)BIT1 (1<<1)INT8_CINT_LEAST32_MAXSCB_CFSR_MSTKERR (1 << 4)__USES_INITFINI__ 1__DBL_DECIMAL_DIG__ 17BIT8 (1<<8)INT16_C(c) __INT16_C(c)__INT16_MAX__ 0x7fffSCB_SHCSR_MEMFAULTPENDED (1 << 13)NVIC_RITIMER_IRQ 11__INT_WIDTH__ 32__ARM_FEATURE_SIMD32 1SCB_CCR_BP (1 << 18)__QQ_FBIT__ 7NVIC_I2S1_IRQ 29SCB_CCR_IC (1 << 17)__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64NVIC_DMA_IRQ 2NVIC_SCT_IRQ 10__ULLACCUM_IBIT__ 32SCB_VTOR MMIO32(SCB_BASE + 0x08)__ULLFRACT_EPSILON__ 0x1P-64ULLRfalse 0NVIC_USART2_IRQ 26__SIZEOF_WINT_T__ 4SCB_CPUID_CONSTANT_ARMV6 (0xC << SCB_CPUID_CONSTANT_LSB)__ARM_FEATURE_UNALIGNED 1__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17SCB_HFSR MMIO32(SCB_BASE + 0x2C)__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1SCB_CFSR_DIVBYZERO (1 << 25)__FLT32X_HAS_DENORM__ 1__ULLACCUM_MIN__ 0.0ULLK__INT_FAST32_WIDTH__ 32NVIC_PIN_INT7_IRQ 39NVIC_I2C0_IRQ 18SCB_HFSR_DEBUG_VT (1 << 31)__ARM_ASM_SYNTAX_UNIFIED__ 1__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODDEBUG_MONITOR_IRQ -4SCB_ID_ISAR3 MMIO32(SCB_BASE + 0x6C)NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + ((iabr_id) * 4))__ARM_PCS_VFP 1SCB_CCR_STKALIGN (1 << 9)__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H 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MMIO32(SCB_BASE + 0x58)SCB_AIRCR_VECTKEYSTAT_LSB 16__ARM_FEATURE_LDREX 7PTRDIFF_MAXSCB_CCR_BFHFNMIGN (1 << 8)__LLFRACT_EPSILON__ 0x1P-63LLR__SFRACT_MAX__ 0X7FP-7HR__FLT32X_MANT_DIG__ 53__WCHAR_WIDTH__ 32WINT_MAX__INT16_C(c) cSCB_ID_ISAR0 MMIO32(SCB_BASE + 0x60)INT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32__ATOMIC_ACQ_REL 4__HQ_IBIT__ 0__DBL_MIN_10_EXP__ (-307)__fini_array_startSCB_CTR_ERG_SHIFT 20SCB_SHCSR_SVCALLACT (1 << 7)NVIC_GINT0_IRQ 40SCB_SHPR_PRI_11_SVCALL 7__FLT32_NORM_MAX__ 3.4028234663852886e+38F32UINT64_C(c) __UINT64_C(c)NVIC_TIMER2_IRQ 14__UINTMAX_MAX__ 0xffffffffffffffffULLSCB_ICSR_PENDSVCLR (1 << 27)__DBL_MANT_DIG__ 53__ULFRACT_IBIT__ 0vector_table_entry_tINT_FAST16_MAXITR_BASE (SCS_BASE + 0x0000)__INT_MAX__ 0x7fffffff__INT_LEAST64_TYPE__ long long intNVIC_SPI_IRQ 20__INT_FAST8_WIDTH__ 32__ARM_FEATURE_CDE_COPROCUINT32_CNVIC_DAC_IRQ 0GCC: (15:12.2.rel1-1) 12.2.1 20221205 |  AA3aeabi)7E-M M  "        02 "$&(*,.47k0^ 36  " " " " " !" ," 5" =" H" S" c" m" w" " " " " " " " " " " " " " " %" 0" 9" B" K" S" \" e" n" x" " " " " " " " " " " " " " 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@ԩ7*"n @ܮ7,$ @d7.I @700!~`0{' L  @074p4$84 >,1systick.o/ 0 0 0 644 34800 ` ELF(~4(:9"#$%&'()*+,-./O# @XapGO#Xi @pGKBoCBO" iCaO#9!AYa pGi#a pGO#i @pGO"i#CapGO"iCapGO"i#apGO"iCapGO"i#apGO#i@pGO#"apGO#i @pGX-! w/' B,0- .Qp6<k 4j4 int^] _ L" 9 F != Mzz&F m _  (RD "R%_ ahbR4_84 T _QK6 ^ jh` vtc';&C _ 8+8"_ > $ > .?:!; 9!'@z1B.?:!; 9 'I@z:!; 9 I.?:!; 9!' !:!; 9 I% Uy $ >  .?: ; 9 'I@z : ; 9 IB : ; 9 IB 4: ; 9 IB1RB UX Y W 1RB X Y W 1RB UX Y W .1@z.1@z,P,.P.<PQ604q QP PPPt D  l$&*   D    )8?/:;?@#Y44T%a #?6Z"a :#~3-7%+- g+'1>78$:~65)?. ,0@1{;71 <)C : 7,'6 i,Y#*p$]Z0-.%2c %02(+L2&(:?\%t(u*$+>k~X' # Dm " y?=7/, @?.Z32<*I$ QAH/i/4o @>%$:#7^ 9=9+6s+8% 0)>: !Qt'b1->=. @&6@'.| eV>pF+=8[ a2  &" 192- 95 "C vL9,&>j36;9Wg<;F (%)3/l7-l#{9&b%46o&L,  -"?$ 2@@ (' j@K2 i)AF97*D%(^1 1#a3% fb?N8&R  AY<@7)-8+) 8/"+3//'3y*  >2 4 'J< "/[p 9P`)=U/O h6J,<74?}..a.2"J5'] w:8(F =>t * ; @C*I C0"< > ;{.20 =*L V@ N&YB?7 9-A#P= -*a$%"7544"5%'*R60j=8N-<? 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16__DEC_EVAL_METHOD__ 2__ARM_FEATURE_FP16_FMLINT16_MIN (-INT16_MAX - 1)__USFRACT_EPSILON__ 0x1P-8UHRNULL ((void *)0)SCB_SCR_SEVONPEND (1 << 4)_Thread_local __thread___int_least32_t_defined 1__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLKSCB_CTR MMIO32(SCB_BASE + 0x7C)__need_NULLUINT64_C__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX____UINT32_MAX__ 0xffffffffUL_REENT_MBTOWC_STATE(ptr) ((ptr)->_new._reent._mbtowc_state)SCB_CCR_UNALIGN_TRP (1 << 3)_REENT_MBLEN_STATE(ptr) ((ptr)->_new._reent._mblen_state)__trylocks_shared(...) __lock_annotate(shared_trylock_function(__VA_ARGS__))__INT_LEAST8_MAX__ 0x7f__GCC_ATOMIC_POINTER_LOCK_FREE 2__ARM_FEATURE_QBIT 1__ARM_FEATURE_CLZ 1__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEX__locks_shared(...) __lock_annotate(shared_lock_function(__VA_ARGS__))unsigned signedSCB_ICSR_VECTACTIVE (0x1FF << SCB_ICSR_VECTACTIVE_LSB)__UINT64_TYPE__ long long unsigned int__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024SCB_ICSR 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(0xabcd)__UDQ_IBIT__ 0SCB_AIRCR_VECTKEYSTAT (0xFFFF << SCB_AIRCR_VECTKEYSTAT_LSB)___int_ptrdiff_t_h __OPTIMIZE__ 1SCB_CTR_ERG_MASK 0xf__UACCUM_MAX__ 0XFFFFFFFFP-16UK__CC_SUPPORTS___FUNC__ 1__FLT64_NORM_MAX__ 1.7976931348623157e+308F64__GNUCLIKE_MATH_BUILTIN_CONSTANTS SCB_ID_PFR0 MMIO32(SCB_BASE + 0x40)UINTPTR_MAX_T_PTRDIFF_ __LDBL_DENORM_MIN__ 4.9406564584124654e-324L__INT64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_SAT 1__ULLFRACT_IBIT__ 0SCB_DCCMVAC MMIO32(SCB_BASE + 0x268)_ANSI_STDDEF_H _REENT_CHECK_SIGNAL_BUF(ptr) MMIO16(addr) (*(volatile uint16_t *)(addr))UINT16_C(c) __UINT16_C(c)LPC43XX 1_REENT_SMALL_CHECK_INIT(ptr) __GNUC__ 12SCB_ID_MMFR3 MMIO32(SCB_BASE + 0x5C)WCHAR_MAX__LONG_WIDTH__ 32_T_WCHAR_ INT32_MAX __INT32_MAX____UACCUM_FBIT__ 16__warn_references(sym,msg) __asm__(".section .gnu.warning." #sym); __asm__(".asciz \"" msg "\""); __asm__(".previous")__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0U__UQQ_IBIT__ 0CORESIGHT_LSR_OFFSET 0xfb4_NEWLIB_VERSION_H__ 1__GCC_ATOMIC_LONG_LOCK_FREE 2__ULACCUM_MIN__ 0.0ULK_ATEXIT_DYNAMIC_ALLOC 1__need_size_t__LDBL_MAX__ 1.7976931348623157e+308L__ARM_ARCH 7SCB_CCR_NONBASETHRDENA (1 << 0)_SIZE_T_ /build/libopencm3/lib/lpc43xx/m4__FLT_RADIX__ 2BIT3 (1<<3)__lock_acquire_recursive(lock) ((void) 0)_REENT_RAND48_MULT(ptr) ((ptr)->_new._reent._r48._mult)SCB_SHPR_PRI_13_RESERVED 9__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAX__wchar_t__ __LDBL_HAS_QUIET_NAN__ 1SCB_CFSR_UNDEFINSTR (1 << 16)__LONG_LONG_WIDTH__ 64BIT6 (1<<6)__DEFINED_wchar_t SCB_CPUID_IMPLEMENTER_LSB 24__UINT_FAST64_MAX__ 0xffffffffffffffffULLSCB_ID_DFR0 MMIO32(SCB_BASE + 0x48)__ARM_FPSCB_ICSR_PENDSTCLR (1 << 25)_REENT_CHECK_ASCTIME_BUF(ptr) __INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1BIT9 (1<<9)__FLT32X_MIN__ 2.2250738585072014e-308F32xINT_FAST8_MIN (-INT_FAST8_MAX - 1)__strftimelike(fmtarg,firstvararg) __attribute__((__format__ (__strftime__, fmtarg, firstvararg)))__FLT64_MAX_EXP__ 1024__WCHAR_T BIT20 (1<<20)MB_CUR_MAX __locale_mb_cur_max()__FLT64_MIN__ 2.2250738585072014e-308F64___int32_t_defined 1__INT_WIDTH__ 32_HAVE_CC_INHIBIT_LOOP_TO_LIBCALL 1__FLT_MIN_EXP__ (-125)__ARM_ARCH_PROFILE__INT64_TYPE__ long long intSCB_ICSR_VECTACTIVE_LSB 0__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4_PTRDIFF_T __BSD_VISIBLE 0__predict_false(exp) __builtin_expect((exp), 0)__unused __attribute__((__unused__))_REENT_MBSRTOWCS_STATE(ptr) ((ptr)->_new._reent._mbsrtowcs_state)SCB_ICSR_VECTPENDING_LSB 12SCB_ICIALLU MMIO32(SCB_BASE + 0x250)SCB_CTR_IMINLINE_SHIFT 0__UFRACT_MAX__ 0XFFFFP-16UR___int_least64_t_defined 1_Alignof(x) __alignof(x)FPB_BASE (PPBI_BASE + 0x2000)__THROW SCB_SHCSR_BUSFAULTACT (1 << 1)INT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0_REENT_L64A_BUF(ptr) ((ptr)->_new._reent._l64a_buf)__EXP(x) __ ##x ##____BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX___NOTHROW _ANSIDECL_H_ SYS_TICK_BASE (SCS_BASE + 0x0010)SCB_AIRCR_VECTCLRACTIVE (1 << 1)__SIG_ATOMIC_TYPE__ int__UFRACT_FBIT__ 16__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)__GNUCLIKE_BUILTIN_MEMCPY 1__APCS_32__ 1SCB_CCR_DC (1 << 16)__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)__INT_FAST32_TYPE__ int__ARM_ARCH_PROFILE 77unsigned int_SIZE_T_DEFINED_ SCB_ID_ISAR2 MMIO32(SCB_BASE + 0x68)SCB_DCCIMVAC MMIO32(SCB_BASE + 0x270)__NEWLIB_MINOR__ 3_SIZET_ __FLT64_HAS_QUIET_NAN__ 1__USACCUM_IBIT__ 8__ARM_ARCH_7EM__ 1__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UK_FVWRITE_IN_STREAMIO 1_WCHAR_T_DECLARED INT_LEAST8_MAX __INT_LEAST8_MAX___SYS_REENT_H_ __FLT_EVAL_METHOD__ 0SCB_ICSR_ISRPENDING (1 << 22)__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32SCB_SHPR_PRI_6_USAGEFAULT 2_RAND48_MULT_2 (0x0005)__ARM_FEATURE_LDREX_T_PTRDIFF __UQQ_FBIT__ 8INT16_C__ARM_FP16_ARGS__GCC_IEC_559 0__requires_unlocked(...) __lock_annotate(locks_excluded(__VA_ARGS__))INT_LEAST16_MAX __INT_LEAST16_MAX____LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4_PTRDIFF_T_DECLARED ___int_least8_t_defined 1__ARM_FEATURE_IDIV 1__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8)_GCC_WCHAR_T SCB_SHCSR_SYSTICKACT (1 << 11)__unlocks(...) __lock_annotate(unlock_function(__VA_ARGS__))__EXPORT __ARM_FEATURE_COPROC 15__OBSOLETE_MATH_DEFAULT 1_Noreturn __dead2UINT64_MAX __UINT64_MAX__false 0__SHRT_WIDTH__ 16_UNBUF_STREAM_OPT 1__IMPORT true 1_ATEXIT_SIZE 32__USA_FBIT__ 16__volatile volatile_MACHINE__TYPES_H __IEEE_LITTLE_ENDIAN __LDBL_MIN_10_EXP__ (-307)INT64_MAX_WANT_REGISTER_FINI 1__FLT_HAS_QUIET_NAN__ 1__ATFILE_VISIBLE 0__GCC_ATOMIC_CHAR_LOCK_FREE 2__LFRACT_EPSILON__ 0x1P-31LR_BEGIN_STD_C __malloc_like __attribute__((__malloc__))__ARM_SIZEOF_MINIMAL_ENUM 1bool _Bool_POINTER_INT long__FLT32X_NORM_MAX__ 1.7976931348623157e+308F32x__arm__ 1INT_FAST64_MAX__FLT32_MIN_10_EXP__ (-37)SCB_SHCSR_USGFAULTPENDED (1 << 12)__RAND_MAX 0x7fffffff__lock_try_acquire(lock) ((void) 0)__STRING(x) #x_WCHAR_T ../../cm3/scb.cINT8_MAX __INT8_MAX____ARM_FP16_FORMAT_ALTERNATIVE__FBSDID(s) struct __hack__LDBL_NORM_MAX__ 1.7976931348623157e+308LINTPTR_MIN_MACHINE__DEFAULT_TYPES_H __BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)_GCC_PTRDIFF_T __GNUCLIKE_BUILTIN_NEXT_ARG 1__TA_IBIT__ 64SCB_SHCSR_PENDSVACT (1 << 10)__LOCK_INIT(class,lock) static int lock = 0;_SIZE_T _WCHAR_T_H SCB_AIRCR_PRIGROUP_SHIFT 8__ARM_FEATURE_QRDMXSCB_DCCISW MMIO32(SCB_BASE + 0x274)__ARM_ARCH_ISA_THUMB 2__LONG_LONG_MAX__ 0x7fffffffffffffffLL_FSEEK_OPTIMIZATION 1SCB_CFSR_MUNSTKERR (1 << 3)__WINT_WIDTH__ 32SCB_ICIMVAU MMIO32(SCB_BASE + 0x258)__arg_type_tag(arg_kind,arg_idx,type_tag_idx) __USQ_IBIT__ 0_REENT_INIT_PTR(var) { memset((var), 0, sizeof(*(var))); _REENT_INIT_PTR_ZEROED(var); }STIR_BASE (SCS_BASE + 0x0F00)__COPYRIGHT(s) struct __hack__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1_REENT_MBRLEN_STATE(ptr) ((ptr)->_new._reent._mbrlen_state)_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)_STDDEF_H_ INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__DBL_MIN_EXP__ (-1021)__SIZE_T SCB_CPUID MMIO32(SCB_BASE + 0x00)SCB_ID_MMFR1 MMIO32(SCB_BASE + 0x54)INT8_MIN (-INT8_MAX - 1)__printf0like(fmtarg,firstvararg) SCB_AIRCR_PRIGROUP_MASK (0x7 << 8)SCB_CTR_CWG_SHIFT 24__FLT32_DIG__ 6INT_LEAST16_MAX__dead2 __attribute__((__noreturn__))BIT15 (1<<15)__compar_fn_t_defined __EXP___int64_t_defined 1__LDBL_HAS_DENORM__ 1__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1INT32_MAX__BEGIN_DECLS __ACCUM_MIN__ (-0X1P15K-0X1P15K)_REENT_CHECK_MISC(ptr) __GNUC_VA_LIST_COMPATIBILITY 1__ARM_FEATURE_CRYPTO__INT_LEAST32_TYPE__ long intSCB_SHCSR_MEMFAULTPENDED (1 << 13)SCB_CPUID_REVISION (0xF << SCB_CPUID_REVISION_LSB)UINT_LEAST16_MAXBIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__FRACT_IBIT__ 0SCB_CFSR_DACCVIOL (1 << 1)SCB_CPACR_PRIV 1UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2__NEWLIB_PATCHLEVEL__ 0BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234__size_tSCB_CTR_DMINLINE_MASK 0x1f__CC_SUPPORTS_INLINE 1__DOTS , ...long long unsigned int__alloc_size(x) __attribute__((__alloc_size__(x)))BIT31 (1<<31)SCB_SHCSR_MONITORACT (1 << 8)__ULACCUM_IBIT__ 32__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__PTRDIFF_TYPE__ int_SIZE_T_DEFINED __DQ_FBIT__ 63SCB_SHPR_PRI_8_RESERVED 4__GNU_VISIBLE 0INT_LEAST64_MAX__SACCUM_IBIT__ 8SCB_CFSR_INVPC (1 << 18)__PTRDIFF_T __UHQ_IBIT__ 0INT_LEAST8_MIN_REENT_WCTOMB_STATE(ptr) ((ptr)->_new._reent._wctomb_state)SCB_FPDSCR MMIO32(SCB_BASE + 0x23C)BIT29 (1<<29)__INT_FAST16_TYPE__ int__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)__ULFRACT_MAX__ 0XFFFFFFFFP-32ULRSCB_SHCSR_BUSFAULTPENDED (1 << 14)__UINT_LEAST16_TYPE__ short unsigned intUINT16_MAX__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned intSCB_ID_MMFR2 MMIO32(SCB_BASE + 0x58)__FLT32X_DIG__ 15__signed signedSCB_BFAR MMIO32(SCB_BASE + 0x38)__UTQ_FBIT__ 128LIBOPENCM3_SCB_H _REENT_ASCTIME_BUF(ptr) ((ptr)->_new._reent._asctime_buf)SCB_CLIDR MMIO32(SCB_BASE + 0x78)__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffff__have_longlong64 1PTRDIFF_MAX __PTRDIFF_MAX____SIZEOF_SHORT__ 2_REENT_MP_P5S(ptr) ((ptr)->_p5s)INT8_MINUINTPTR_MAX __UINTPTR_MAX___WCHAR_T_DEFINED __ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULK__trylocks_exclusive(...) __lock_annotate(exclusive_trylock_function(__VA_ARGS__))SCB_ICSR_VECTPENDING (0x1FF << SCB_ICSR_VECTPENDING_LSB)UINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRSCB_CFSR_IBUSERR (1 << 8)BIT26 (1<<26)__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long int__always_inline __inline__ __attribute__((__always_inline__))INT32_MIN__containerof(x,s,m) ({ const volatile __typeof(((s *)0)->m) *__x = (x); __DEQUALIFY(s *, (const volatile char *)__x - __offsetof(s, m));})SCB_ID_AFR0 MMIO32(SCB_BASE + 0x4C)SCB_BPIALL MMIO32(SCB_BASE + 0x278)_BSD_SIZE_T_ __HA_IBIT__ 8SCB_CPUID_REVISION_LSB 0__no_lock_analysis __lock_annotate(no_thread_safety_analysis)_WCHAR_T_ _REENT_STDIO_STREAM(var,index) &(var)->__sf[index]_T_WCHAR _CLOCKID_T_ unsigned long_REENT_CHECK_TM(ptr) SCB_VTOR MMIO32(SCB_BASE + 0x08)__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__INT_WCHAR_T_H __FLT32X_MAX__ 1.7976931348623157e+308F32xSCB_ICSR_ISRPREEMPT (1 << 23)__ARM_EABI__ 1INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1__ARM_FEATURE_DSP 1SCB_GET_EXCEPTION_STACK_FRAME(f) do { asm volatile ("mov %[frameptr], sp" : [frameptr]"=r" (f)); } while (0)__QQ_IBIT__ 0__ARMEL__ 1SCB_SHPR_PRI_12_RESERVED 8__LLACCUM_FBIT__ 31scb_reset_system__UINTMAX_TYPE__ long long unsigned int__FLT32X_MIN_10_EXP__ (-307)__GNUC_MINOR__ 2__lock_release_recursive(lock) ((void) 0)__UINT_LEAST32_TYPE__ long unsigned int__ARM_FEATURE_NUMERIC_MAXMIN_RAND48_MULT_1 (0xdeec)__INTMAX_TYPE__ long long int__GCC_ATOMIC_INT_LOCK_FREE 2SCB_HFSR_DEBUG_VT (1 << 31)_RAND48_SEED_0 (0x330e)SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8)INTMAX_MAXID_BASE (SCS_BASE + 0x0FD0)__Long long__ARM_FEATURE_FP16_SCALAR_ARITHMETIC__FLT_NORM_MAX__ 3.4028234663852886e+38F_STDLIB_H_ __DBL_HAS_QUIET_NAN__ 1UINT_LEAST32_MAXSCB_CCR_USERSETMPEND (1 << 1)__ptrvalue _NOINLINE_STATIC _NOINLINE staticSCB_SHCSR_USGFAULTACT (1 << 3)__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_C_PTRDIFF_T_ INT64_MINSCB_CFSR_NOCP (1 << 19)__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intUINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULR__RCSID(s) struct __hackWCHAR_MAX __WCHAR_MAX__WCHAR_MIN__SIZEOF_SIZE_T__ 4__lock_close_recursive(lock) ((void) 0)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__GNUCLIKE___OFFSETOF 1__INT64_C(c) c ## LL__GNUCLIKE_CTOR_SECTION_HANDLING 1__lockable __lock_annotate(lockable)__END_DECLS TPIU_BASE (PPBI_BASE + 0x40000)__generic(expr,t,yes,no) __builtin_choose_expr( __builtin_types_compatible_p(__typeof(expr), t), yes, no)__LONG_MAX__ 0x7fffffffLSCB_CFSR MMIO32(SCB_BASE + 0x28)__ARM_FEATURE_CDE__ACCUM_IBIT__ 16unsignedCORESIGHT_LAR_OFFSET 0xfb0SCB_CFSR_IMPRECISERR (1 << 10)__GCC_DESTRUCTIVE_SIZE 64INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)SCB_SHPR_PRI_15_SYSTICK 11short int_STDDEF_H __pt_guarded_by(x) __lock_annotate(pt_guarded_by(x))__guarded_by(x) __lock_annotate(guarded_by(x))__UINT16_C(c) c__FLT64_MIN_EXP__ (-1021)_REENT_INIT_ATEXIT _NULL, _ATEXIT_INIT,__CC_SUPPORTS___INLINE__ 1__UDA_IBIT__ 32__printflike(fmtarg,firstvararg) __attribute__((__format__ (__printf__, fmtarg, firstvararg)))__fastcall __attribute__((__fastcall__))__lock_annotate(x) BIT2 (1<<2)_REENT_SIGNAL_BUF(ptr) ((ptr)->_new._reent._signal_buf)__ATOMIC_RELAXED 0_ATTRIBUTE(attrs) __attribute__ (attrs)__ARM_FEATURE_COPROC__ATTRIBUTE_IMPURE_PTR__ __DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX___RAND48_MULT_0 (0xe66d)LPC43XX_M4 1BIT5 (1<<5)BIT1 (1<<1)__rangeof(type,start,end) (__offsetof(type, end) - __offsetof(type, start))INT8_CINT_LEAST32_MAXSCB_CFSR_MSTKERR (1 << 4)__USES_INITFINI__ 1__lock_init(lock) ((void) 0)__need_ptrdiff_tINTMAX_MAX __INTMAX_MAX____DBL_DECIMAL_DIG__ 17__have_long32 1_GLOBAL_REENT _global_impure_ptr_NULL 0__flexarr [0]INT16_C(c) __INT16_C(c)INT32_C(c) __INT32_C(c)__INT16_MAX__ 0x7fff__SYS_CONFIG_H__ __DEVOLATILE(type,var) ((type)(__uintptr_t)(volatile void *)(var))__WCHAR_T__ __SSP_FORTIFY_LEVEL 0__ARM_FEATURE_SIMD32 1__XSI_VISIBLE 0INT_FAST32_MIN (-INT_FAST32_MAX - 1)__QQ_FBIT__ 7SCB_ID_ISAR4 MMIO32(SCB_BASE + 0x70)SCB_CCR_IC (1 << 17)__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64__GNUC_PREREQ__(ma,mi) __GNUC_PREREQ(ma, mi)__UTA_IBIT__ 64__ULLACCUM_IBIT__ 32__ARM_FEATURE_CRC32__strong_reference(sym,aliassym) extern __typeof (sym) aliassym __attribute__ ((__alias__ (#sym)))__ULLFRACT_EPSILON__ 0x1P-64ULLR__unreachable() __builtin_unreachable()__LOCK_INIT_RECURSIVE(class,lock) static int lock = 0;__SIZEOF_WINT_T__ 4SCB_CPUID_CONSTANT_ARMV6 (0xC << SCB_CPUID_CONSTANT_LSB)__ARM_FEATURE_UNALIGNED 1__STDC__ 1__LDBL_DECIMAL_DIG__ 17SCB_CCSIDR MMIO32(SCB_BASE + 0x80)__GNUCLIKE_ASM 3__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1__scanflike(fmtarg,firstvararg) __attribute__((__format__ (__scanf__, fmtarg, firstvararg)))SCB_CFSR_DIVBYZERO (1 << 25)_WIDE_ORIENT 1__ULLACCUM_MIN__ 0.0ULLK_SYS__TYPES_H __INT_FAST32_WIDTH__ 32_SYS_CDEFS_H_ __GNUCLIKE_BUILTIN_VAALIST 1__sym_compat(sym,impl,verid) __asm__(".symver " #impl ", " #sym "@" #verid)SCB_SHCSR_MEMFAULTACT (1 << 0)__ARM_ASM_SYNTAX_UNIFIED__ 1__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPROD_NEWLIB_VERSION "3.3.0"SCB_ID_ISAR3 MMIO32(SCB_BASE + 0x6C)__pure __attribute__((__pure__))__ARM_PCS_VFP 1_GCC_SIZE_T SCB_CCR_STKALIGN (1 << 9)__CC_SUPPORTS_WARNING 1__ULLFRACT_MIN__ 0.0ULLRUINT_FAST8_MAX_REENT_CHECK_RAND48(ptr) INT_LEAST64_MIN__lock_release(lock) ((void) 0)__GCC_CONSTRUCTIVE_SIZE 64_BSD_WCHAR_T___LLFRACT_IBIT__ 0__CC_SUPPORTS_VARADIC_XXX 1SCB_SHPR_PRI_10_RESERVED 6uint32_tBIT12 (1<<12)SCB_CPUID_CONSTANT_ARMV7 (0xF << SCB_CPUID_CONSTANT_LSB)SCB_ICSR_RETOBASE (1 << 11)MPU_BASE (SCS_BASE + 0x0D90)__SACCUM_EPSILON__ 0x1P-7HK__GCC_ASM_FLAG_OUTPUTS__ 1_REENT_CHECK_VERIFY 1__ARM_FP 4SCB_CTR_IMINLINE_MASK 0xf_REENT_RAND_NEXT(ptr) ((ptr)->_new._reent._rand_next)__UHA_IBIT__ 8__GNUC_STDC_INLINE__ 1__need_wint_t __ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULKSCB_CPUID_PARTNO_LSB 4__LDBL_DIG__ 15_Atomic(T) struct { T volatile __val; }__SIZE_WIDTH__ 32SIG_ATOMIC_MAXBIT16 (1<<16)__WINT_MIN__ 0UINT_LEAST16_MINSCB_ICSR_PENDSTSET (1 << 26)__FLT64_DIG__ 15__WINT_MAX__ 0xffffffffUBIT22 (1<<22)__INT_LEAST8_WIDTH__ 8__long_double_t long double__INT_LEAST16_TYPE__ short int__DBL_MAX__ ((double)1.7976931348623157e+308L)_REENT_WCRTOMB_STATE(ptr) ((ptr)->_new._reent._wcrtomb_state)short unsigned int__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1SCB_CFSR_UNALIGNED (1 << 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1)__UHQ_FBIT__ 16__FLT64_MIN_EXP__ (-1021)__PTRDIFF_WIDTH__ 32__UINT_FAST8_MAX__ 0xffffffffUSCB_ID_DFR0 MMIO32(SCB_BASE + 0x48)UINT16_C(c) __UINT16_C(c)__LACCUM_IBIT__ 32SCB_DCIMVAC MMIO32(SCB_BASE + 0x25C)__INT_FAST16_WIDTH__ 32INTMAX_C__VERSION__ "12.2.1 20221205"__VFP_FP__ 1__LLFRACT_MIN__ (-0.5LLR-0.5LLR)INT_FAST8_MAXSCB_SHPR_PRI_9_RESERVED 5__UINT_FAST16_MAX__ 0xffffffffU__INTPTR_MAX__ 0x7fffffffINT64_C(c) __INT64_C(c)SCB_CTR_DMINLINE_SHIFT 16__GCC_IEC_559_COMPLEX 0__UFRACT_MIN__ 0.0URSCB_DCCMVAU MMIO32(SCB_BASE + 0x264)WCHAR_MAX __WCHAR_MAX____FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX____UINT_LEAST8_TYPE__ unsigned char__ACCUM_FBIT__ 15SCB_SCR_SLEEPONEXIT (1 << 1)__UACCUM_IBIT__ 16long intUINT8_MAXSCB_MMFAR MMIO32(SCB_BASE + 0x34)SIZE_MAX __SIZE_MAX____INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1__FLT32X_EPSILON__ 2.2204460492503131e-16F32x__UINT_FAST64_MAX__ 0xffffffffffffffffULLSCB_CPACR_FULL 3NVIC_BASE (SCS_BASE + 0x0100)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32__UINTMAX_C(c) c ## ULL__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed charNVIC_MEM_MANAGE_IRQ -12__GCC_ATOMIC_BOOL_LOCK_FREE 2BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON____FLT32_MAX_EXP__ 128SCB_BFAR MMIO32(SCB_BASE + 0x38)__THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLR__ARM_FEATURE_QBIT 1__FLT64_DECIMAL_DIG__ 17short unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)BIT7 (1<<7)BIT17 (1<<17)__FLT32X_MIN_10_EXP__ (-307)UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)__DBL_IS_IEC_60559__ 2__UINT_FAST32_MAX__ 0xffffffffU__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4SCB_SCR_SLEEPDEEP (1 << 2)SCB_CFSR_DIVBYZERO (1 << 25)__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32SCB_CFSR_STKERR (1 << 12)SCB_SHCSR_MEMFAULTENA (1 << 16)SCB_HFSR_VECTTBL (1 << 1)BIT27 (1<<27)SCB_SHPR_PRI_13_RESERVED 9__UTA_FBIT__ 64INTMAX_C(c) __INTMAX_C(c)__FLT_DECIMAL_DIG__ 9SCB_CPUID_VARIANT (0xF << SCB_CPUID_VARIANT_LSB)__thumb__ 1__INT_LEAST32_MAX__ 0x7fffffffLsigned charuint8_tINT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)INT32_C(c) __INT32_C(c)__GNUC_STDC_INLINE__ 1__FRACT_FBIT__ 15__LLACCUM_EPSILON__ 0x1P-31LLK__GNUC_PATCHLEVEL__ 1__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2SCB_CCR_BFHFNMIGN (1 << 8)PTRDIFF_MINSCB_CPUID_VARIANT_LSB 20__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)SCB_CPACR_CP10 (1 << 20)UINTPTR_MAX __UINTPTR_MAX____ARM_ARCH_PROFILE 77NVIC_SDIO_IRQ 6__FLT64_MAX_10_EXP__ 308MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINSCB_CFSR_MUNSTKERR (1 << 3)SCB_CCSIDR MMIO32(SCB_BASE + 0x80)__UINT_FAST32_TYPE__ unsigned intunsigned charNVIC_ETHERNET_IRQ 5__SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38SCB_SCR MMIO32(SCB_BASE + 0x10)__FRACT_MAX__ 0X7FFFP-15Rnvic_set_priorityINT_LEAST32_MAX __INT_LEAST32_MAX__SCB_FPCAR MMIO32(SCB_BASE + 0x238)__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5SCB_CPACR MMIO32(SCB_BASE + 0x88)NVIC_USAGE_FAULT_IRQ -10NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + (ipr_id))NVIC_EVENTROUTER_IRQ 42NVIC_PIN_INT6_IRQ 38__UINT16_MAX__ 0xffff__TQ_FBIT__ 127__USQ_FBIT__ 32uint16_t__thumb2__ 1__ULLACCUM_FBIT__ 32SCB_AIRCR_VECTKEY (0x05FA << SCB_AIRCR_VECTKEYSTAT_LSB)SCB_SHCSR MMIO32(SCB_BASE + 0x24)NVIC_USB1_IRQ 9__STRICT_ANSI__ 1NVIC_SYSTICK_IRQ -1UINT_LEAST8_MAXINT_LEAST8_MAXSCB_VTOR_TBLOFF (0x7FFFFF << SCB_VTOR_TBLOFF_LSB)UINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8SCB_ID_ISAR1 MMIO32(SCB_BASE + 0x64)__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__SCB_SHCSR_PENDSVACT (1 << 10)__USA_IBIT__ 16__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1PTRDIFF_MIN (-PTRDIFF_MAX - 1)__UINT_FAST64_TYPE__ long long unsigned intSCB_CPACR_PRIV 1__FLT_MIN__ 1.1754943508222875e-38F__HA_FBIT__ 7__FDPIC____FLT32_IS_IEC_60559__ 2INT_FAST64_MINSCB_CFSR_IACCVIOL (1 << 0)__USFRACT_IBIT__ 0__LDBL_EPSILON__ 2.2204460492503131e-16L__USFRACT_MIN__ 0.0UHRSCB_CFSR_PRECISERR (1 << 9)SCB_SHCSR_BUSFAULTENA (1 << 17)__ARM_NEON__UINT8_MAX__ 0xffSCB_CTR_ERG_MASK 0xf__LDBL_MAX_EXP__ 1024SCB_CTR MMIO32(SCB_BASE + 0x7C)SCB_SHCSR_USGFAULTENA (1 << 18)SCB_ICSR_RETOBASE (1 << 11)__DBL_HAS_DENORM__ 1SCB_ICSR_PENDSVSET (1 << 28)__DA_FBIT__ 31__GXX_ABI_VERSION 1017__INT_LEAST16_MAX__ 0x7fff__FLT_DENORM_MIN__ 1.4012984643248171e-45FNVIC_RTC_IRQ 47__ULLACCUM_EPSILON__ 0x1P-32ULLKSCB_SHCSR_MEMFAULTACT (1 << 0)INT_LEAST8_MAX __INT_LEAST8_MAX____UINT32_C(c) c ## UL__UACCUM_MIN__ 0.0UK__FLT_EPSILON__ 1.1920928955078125e-7FSCB_CCSELR MMIO32(SCB_BASE + 0x84)__DBL_MAX_10_EXP__ 308__ARM_ARCH_ISA_THUMBSCB_ID_AFR0 MMIO32(SCB_BASE + 0x4C)LIBOPENCM3_CM3_MEMORYMAP_H __GCC_ATOMIC_SHORT_LOCK_FREE 2NVIC_PIN_INT3_IRQ 35__USACCUM_FBIT__ 8__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1NVIC_GINT1_IRQ 41__LACCUM_FBIT__ 31SCS_BASE (PPBI_BASE + 0xE000)__FLT32_MIN__ 1.1754943508222875e-38F32__FLT32_HAS_QUIET_NAN__ 1__ARM_FEATURE_MATMUL_INT8__LDBL_HAS_INFINITY__ 1__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))__FLT32X_MAX_10_EXP__ 308SCB_SHPR_PRI_5_BUSFAULT 1__ARM_ARCH_EXT_IDIV__ 1NVIC_TIMER1_IRQ 13bool _BoolUINTMAX_MAX __UINTMAX_MAX____SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffSCB_CTR_FORMAT_SHIFT 29BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)SCB_FPCCR MMIO32(SCB_BASE + 0x234)INT16_MAX __INT16_MAX____FP_FAST_FMAF 1__FLT32X_IS_IEC_60559__ 2SCB_AFSR MMIO32(SCB_BASE + 0x3C)LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))UINT32_MAX__INT_LEAST16_WIDTH__ 16__DEC_EVAL_METHOD__ 2__ARM_FEATURE_FP16_FMLNVIC_I2S0_IRQ 28NVIC_PIN_INT2_IRQ 34INT16_MIN (-INT16_MAX - 1)__USFRACT_EPSILON__ 0x1P-8UHRSCB_SCR_SEVONPEND (1 << 4)__USFRACT_FBIT__ 8CORESIGHT_LSR_SLI (1<<0)SCB_MVFR0 MMIO32(SCB_BASE + 0x240)__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX__NVIC_IRQ_COUNT 53SCB_CCR_UNALIGN_TRP (1 << 3)SCB_CCR_USERSETMPEND (1 << 1)__INT_LEAST8_MAX__ 0x7fNVIC_SPIFI_IRQ 30__GCC_ATOMIC_POINTER_LOCK_FREE 2nvic_get_irq_enabled__ARM_FEATURE_CLZ 1__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXSCB_ICSR_VECTPENDING_LSB 12NVIC_HARD_FAULT_IRQ -13__UINT64_TYPE__ long long unsigned int__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024__UINT_LEAST32_MAX__ 0xffffffffULNVIC_BUS_FAULT_IRQ -11__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1__ACCUM_MAX__ 0X7FFFFFFFP-15K__INT8_MAX__ 0x7fSCB_AIRCR MMIO32(SCB_BASE + 0x0C)BIT14 (1<<14)__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16__GCC_DESTRUCTIVE_SIZE 64BIT20 (1<<20)__ARM_FEATURE_MVE__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intSCB_ID_MMFR0 MMIO32(SCB_BASE + 0x50)UINT_LEAST16_MAX __UINT_LEAST16_MAX__NVIC_ADC0_IRQ 17__FLT_EVAL_METHOD_TS_18661_3__ 0__SCHAR_WIDTH__ 8BIT18 (1<<18)UINT_FAST16_MAXSCB_DFSR MMIO32(SCB_BASE + 0x30)__UINT_FAST8_TYPE__ unsigned int__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RBIT24 (1<<24)__UTQ_FBIT__ 128__INT32_MAX__ 0x7fffffffLSCB_CFSR_NOCP (1 << 19)SCB_ICSR_NMIPENDSET (1 << 31)UINTMAX_MAXBIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLLNVIC_I2C1_IRQ 19__ARM_FEATURE_BF16_VECTOR_ARITHMETICSCB_ID_PFR1 MMIO32(SCB_BASE + 0x44)PPBI_BASE (0xE0000000U)SCB_CPACR_CP11 (1 << 22)__FLT32_MANT_DIG__ 24LIBOPENCM3_NVIC_H __FLT32_DENORM_MIN__ 1.4012984643248171e-45F32__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN__INT8_MAX __INT8_MAX__BIT28 (1<<28)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2SCB_DCCMVAC MMIO32(SCB_BASE + 0x268)__DBL_MAX_EXP__ 1024__ATOMIC_RELEASE 3UINT_FAST8_MAX__FLT_MANT_DIG__ 24__UINT32_MAX__ 0xffffffffUL__UDQ_IBIT__ 0SCB_AIRCR_VECTKEYSTAT (0xFFFF << SCB_AIRCR_VECTKEYSTAT_LSB)__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UKSCB_CPUID MMIO32(SCB_BASE + 0x00)__FLT64_NORM_MAX__ 1.7976931348623157e+308F64SCB_ID_PFR0 MMIO32(SCB_BASE + 0x40)SCB_ICSR_VECTACTIVE (0x1FF << SCB_ICSR_VECTACTIVE_LSB)UINTPTR_MAX__LDBL_DENORM_MIN__ 4.9406564584124654e-324L__INT64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_SAT 1NVIC_USB0_IRQ 8__ULLFRACT_IBIT__ 0MMIO16(addr) (*(volatile uint16_t *)(addr))NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + ((icpr_id) * 4))LPC43XX 1SCB_CTR_FORMAT_MASK 0x7__GNUC__ 12SCB_ID_MMFR3 MMIO32(SCB_BASE + 0x5C)WCHAR_MAX__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0U__UQQ_IBIT__ 0CORESIGHT_LSR_OFFSET 0xfb4__GCC_ATOMIC_LONG_LOCK_FREE 2__ULACCUM_MIN__ 0.0ULKSCB_VTOR_TBLOFF_LSB 9__LDBL_MAX__ 1.7976931348623157e+308L__ARM_ARCH 7/build/libopencm3/lib/lpc43xx/m4__FLT_RADIX__ 2BIT3 (1<<3)long long intCORESIGHT_LAR_KEY 0xC5ACCE55__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAX__LDBL_HAS_QUIET_NAN__ 1SCB_CFSR_UNDEFINSTR (1 << 16)__LONG_LONG_WIDTH__ 64BIT6 (1<<6)SCB_CPUID_IMPLEMENTER_LSB 24SCB_ID_ISAR4 MMIO32(SCB_BASE + 0x70)__ARM_FPSCB_ICSR_PENDSTCLR (1 << 25)__HA_IBIT__ 8__INTPTR_WIDTH__ 32NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + ((icer_id) * 4))BIT9 (1<<9)__FLT32X_MIN__ 2.2250738585072014e-308F32xINTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024UINT16_MAX__FLT64_MIN__ 2.2250738585072014e-308F64__INTMAX_C(c) c ## LL__ARM_ARCH_PROFILE__INT64_TYPE__ long long intSCB_ICSR_VECTACTIVE_LSB 0__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4SCB_ICIALLU MMIO32(SCB_BASE + 0x250)__UFRACT_MAX__ 0XFFFFP-16URINT64_MAXFPB_BASE (PPBI_BASE + 0x2000)INT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0STIR_BASE (SCS_BASE + 0x0F00)__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__SCB_ICSR_PENDSTSET (1 << 26)nvic_get_active_irqID_BASE (SCS_BASE + 0x0FD0)SYS_TICK_BASE (SCS_BASE + 0x0010)SCB_AIRCR_VECTCLRACTIVE (1 << 1)__UFRACT_FBIT__ 16__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)__LDBL_MAX_10_EXP__ 308SCB_CCR_DC (1 << 16)../../cm3/nvic.c__INT_FAST32_TYPE__ intunsigned intSCB_ID_ISAR2 MMIO32(SCB_BASE + 0x68)SCB_DCCIMVAC MMIO32(SCB_BASE + 0x270)__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1NVIC_USART0_IRQ 24__USACCUM_IBIT__ 8ITM_BASE (PPBI_BASE + 0x0000)__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UKSCB_ICSR MMIO32(SCB_BASE + 0x04)__FLT_EVAL_METHOD__ 0SCB_ICSR_ISRPENDING (1 << 22)__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32SCB_SHPR_PRI_6_USAGEFAULT 2__ARM_FEATURE_LDREX__UQQ_FBIT__ 8INT16_C__ARM_FP16_ARGS__GCC_IEC_559 0INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX____LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4__STDC__ 1__ARM_FEATURE_IDIV 1__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8)__UINT8_TYPE__ unsigned charSCB_SHCSR_SYSTICKACT (1 << 11)__ARM_FEATURE_COPROC 15UINT64_MAX __UINT64_MAX__GNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -O2 -std=c99 -fno-common -ffunction-sections -fdata-sectionsINT8_MINnvic_generate_software_interrupttrue 1__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)NVIC_PIN_INT5_IRQ 37__LDBL_MIN_10_EXP__ (-307)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1SCB_DCCISW MMIO32(SCB_BASE + 0x274)__GCC_ATOMIC_CHAR_LOCK_FREE 2__LFRACT_EPSILON__ 0x1P-31LR__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX__SCB_CFSR_BFARVALID (1 << 15)__FLT32X_NORM_MAX__ 1.7976931348623157e+308F32x__arm__ 1__FLT32_MIN_10_EXP__ (-37)SCB_SHCSR_USGFAULTPENDED (1 << 12)MMIO64(addr) (*(volatile uint64_t *)(addr))NVIC_TIMER3_IRQ 15__ARM_FP16_FORMAT_ALTERNATIVE__LDBL_NORM_MAX__ 1.7976931348623157e+308LINTPTR_MIN__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)SCB_AIRCR_SYSRESETREQ (1 << 2)__TA_IBIT__ 64SCB_AIRCR_PRIGROUP_SHIFT 8__ARM_FEATURE_QRDMXSCB_SHCSR_USGFAULTACT (1 << 3)__ARM_ARCH_ISA_THUMB 2__LONG_LONG_MAX__ 0x7fffffffffffffffLL__WINT_WIDTH__ 32SCB_ICIMVAU MMIO32(SCB_BASE + 0x258)SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__UINT_LEAST8_MAX __UINT_LEAST8_MAX__BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN____SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__DBL_MIN_EXP__ (-1021)__LDBL_HAS_DENORM__ 1SCB_ID_MMFR1 MMIO32(SCB_BASE + 0x54)INT8_MIN (-INT8_MAX - 1)SCB_AIRCR_PRIGROUP_MASK (0x7 << 8)SCB_CTR_CWG_SHIFT 24__FLT32_DIG__ 6INT_LEAST16_MAXSCB_ICSR_VECTPENDING (0x1FF << SCB_ICSR_VECTPENDING_LSB)BIT15 (1<<15)BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1INT32_MAXNVIC_SSP1_IRQ 23__ACCUM_MIN__ (-0X1P15K-0X1P15K)END_DECLS __ARM_FEATURE_CRYPTO__INT_LEAST32_TYPE__ long intSCB_CPUID_REVISION (0xF << SCB_CPUID_REVISION_LSB)NVIC_C_CAN1_IRQ 43BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__FRACT_IBIT__ 0UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234SCB_CTR_DMINLINE_MASK 0x1f__FLT_NORM_MAX__ 3.4028234663852886e+38FSCB_CPUID_CONSTANT_LSB 16long long unsigned int__FLT_MIN_10_EXP__ (-37)BIT31 (1<<31)SCB_SHCSR_MONITORACT (1 << 8)__ULACCUM_IBIT__ 32__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__PTRDIFF_TYPE__ int__APCS_32__ 1__DQ_FBIT__ 63SCB_SHPR_PRI_8_RESERVED 4INT_LEAST64_MAX__SACCUM_IBIT__ 8NVIC_GINT0_IRQ 40__UHQ_IBIT__ 0INT_LEAST8_MINSCB_FPDSCR MMIO32(SCB_BASE + 0x23C)BIT29 (1<<29)__INT_FAST16_TYPE__ intINT64_C__ULFRACT_MAX__ 0XFFFFFFFFP-32ULRSCB_SHCSR_BUSFAULTPENDED (1 << 14)__UINT_LEAST16_TYPE__ short unsigned int__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned int__FLT32X_DIG__ 15NVIC_TIMER0_IRQ 12LIBOPENCM3_SCB_H SCB_CLIDR MMIO32(SCB_BASE + 0x78)__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffffPTRDIFF_MAX __PTRDIFF_MAX____SIZEOF_SHORT__ 2__FLT32_DECIMAL_DIG__ 9__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKUINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRSCB_CFSR_IBUSERR (1 << 8)NVIC_SCT_IRQ 10__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intNVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + ((ispr_id) * 4))NVIC_PIN_INT1_IRQ 33SCB_BPIALL MMIO32(SCB_BASE + 0x278)WCHAR_MINBEGIN_DECLS nvic_get_pending_irq__DQ_IBIT__ 0__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__FLT32X_MAX__ 1.7976931348623157e+308F32xSCB_ICSR_ISRPREEMPT (1 << 23)__ARM_EABI__ 1INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1NVIC_ATIMER_IRQ 46__ARM_FEATURE_DSP 1SCB_GET_EXCEPTION_STACK_FRAME(f) do { asm volatile ("mov %[frameptr], sp" : [frameptr]"=r" (f)); } while (0)__QQ_IBIT__ 0SCB_SHPR_PRI_14_PENDSV 10SCB_SHPR_PRI_12_RESERVED 8__LLACCUM_FBIT__ 31__UINTMAX_TYPE__ long long unsigned int__USQ_IBIT__ 0SCB_CPUID_PARTNO (0xFFF << SCB_CPUID_PARTNO_LSB)__UINT_LEAST32_TYPE__ long unsigned int__ARM_FEATURE_NUMERIC_MAXMIN__INTMAX_TYPE__ long long int__GCC_ATOMIC_INT_LOCK_FREE 2SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8)INTMAX_MAXLIBOPENCM3_LPC43xx_M4_NVIC_H __ARM_ARCH_7EM__ 1__ARM_FEATURE_FP16_SCALAR_ARITHMETIC__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1INT_FAST32_MIN__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CINT64_MIN__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intNVIC_NMI_IRQ -14UINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRNVIC_USART3_IRQ 27__SIZEOF_SIZE_T__ 4NVIC_I2C0_IRQ 18__INT64_C(c) c ## LLSCB_CPUID_IMPLEMENTER (0xFF << SCB_CPUID_IMPLEMENTER_LSB)SCB_CTR_CWG_MASK 0xfTPIU_BASE (PPBI_BASE + 0x40000)SCB_CTR_IMINLINE_SHIFT 0__LDBL_MIN__ 2.2250738585072014e-308LSCB_CFSR MMIO32(SCB_BASE + 0x28)__ARM_FEATURE_CDE__ACCUM_IBIT__ 16SCB_CFSR_MSTKERR (1 << 4)__GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"CORESIGHT_LAR_OFFSET 0xfb0SCB_CFSR_IMPRECISERR (1 << 10)SCB_SHPR_PRI_15_SYSTICK 11short intSCB_CFSR_UNSTKERR (1 << 11)__UINT16_C(c) c__UDA_IBIT__ 32NVIC_UART1_IRQ 25priorityUINT_LEAST32_MAXNVIC_SGPIO_IRQ 31BIT2 (1<<2)__ATOMIC_RELAXED 0__ARM_FEATURE_COPROC__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53LPC43XX_M4 1BIT5 (1<<5)BIT1 (1<<1)INT8_CINT_LEAST32_MAXirqn__USES_INITFINI__ 1__DBL_DECIMAL_DIG__ 17BIT8 (1<<8)INT16_C(c) __INT16_C(c)__INT16_MAX__ 0x7fffSCB_SHCSR_MEMFAULTPENDED (1 << 13)NVIC_RITIMER_IRQ 11__INT_WIDTH__ 32__ARM_FEATURE_SIMD32 1SCB_CCR_BP (1 << 18)INT_FAST32_MIN (-INT_FAST32_MAX - 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