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434 ` adc_common_v2_multi.o/ crc_common_all.o/ crs_common_all.o/ dac_common_all.o/ dma_common_l1f013.o/ dma_common_csel.o/ exti_common_all.o/ flash_common_all.o/ flash_common_f.o/ flash_common_idcache.o/ gpio_common_all.o/ gpio_common_f0234.o/ iwdg_common_all.o/ lptimer_common_all.o/ rcc_common_all.o/ rtc_common_l1f024.o/ spi_common_all.o/ timer_common_all.o/ usart_common_all.o/ usart_common_v2.o/ quadspi_common_v1.o/ usb_dwc_common.o/ adc.o/ 0 0 0 644 41436 ` ELF(D™4(76 !"#$%&'()*+,hCđ€S`pGh#đ€S`pG˝©¶7řKÍMŁN2~Ł®T4`[*ÖBint©7C92 ś adc2%TP˙' śadc'$TP$>:!;9I%Uy:;9I$>.?:;9'@z.?:;9'@z$ ?@ó(i & "Y9$ %b:X +’0ĘÄU hN˝l(W.CZŃ.ĺ.>EČ?›žĘE—#L˙4o>BDź÷5‚:u =;ąsC€ŰiI°HÂD…R$~FĎ4˝"Ĺ*1S+LŠ/Wł.Ŕ[qDçH”-/D‘7ąé+TU\’K4K!â8GC©[ńL×>EO1?'6VĄXš+|*WPŃ03ĚYţ>Vc…4ŰZ]XÜN%ÝPí)'Pa,˘/ äî'›' (†?ňVZ!Z°&Óa7«,RLź)5%řMÝ(˙!B}-KR9UE4 źĚR@ ĹŻ QC3Ď „3öŇ9@Ě8y+q22.‹8ć7íB‡ç±ă0B*"‘!÷¸)N<Č%˙G[K@dZB.µĘONWE7j˙(© źNWJ:ÎżUµă;< y7˘ěQ˙1ď=ÂuN/@D$Ä2[C)-]@6 Š='oŠpK~Z&6N-hR›W$ă· O¬VDđ 4ą©D/I4őP{t8Šý7iBµYýDPPĹ(Ż$-NGP=Ă3´Ş›R®™Ů%FY=*śYÎ X'N¸ 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{%>|ľ}ÖI€H8U‚#$_*S,¦%.›40‰#26O4 6X8óR<Ý2F¶8HľWJW6Kę MsEO=HQ˘@Z‘\6^R _č*aQ"c;eć1nţpO r&t‡QvůF~•AÍmX„[†ĺśŠÔ:Śr)Ž1Ii“„<” •ţ;–e ™ Eś…ťĐ žđźYŁ&T¦$Hşň»ÇCĽ{/ľlVŔ•ÁÂÄz9Í‡Đ®Óů$Ă135I7QA8Ô9«:ÉF=« @ AëABĆKC#Fý-Gˇ2HRIGL&NNNQ^TW–FXoM_maAcc+e‡,gÓWl)3nßYp‡rĺDt40yž{(}X‚j…R„‹zŽŮ/ŹnT”r4•#5–j.—äX™¦ šČJ›' śŢJť«ZžŰLź.@ • ˇ˘áOŁ}@¤jĄVV¦?+N,äR-éK4µS5‹)6Đ<•(?K#DĐGěH¦GIR–&SG,TYu!˘fű /usr/lib/gcc/arm-none-eabi/12.2.1/include../../../include/libopencm3/stm32../../../include/libopencm3/cm3../../../include/libopencm3/stm32/l4../../../include/libopencm3/stm32/commonadc.cstdint.hadc.hcommon.hstdbool.hmemorymap.hmemorymap.hmemorymap.hadc.hadc_common_v2.hadc_common_v2_multi.h' =2 =ADC_TR1_HT (0xFFF << ADC_TR1_HT_SHIFT)SCB_BASE (SCS_BASE + 0x0D00)__UHA_FBIT__ 8USB_OTG_FS_BASE (0x50000000U + 0x00000)__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64ADC_SQR3(adc) MMIO32((adc) + 0x38)CORESIGHT_LSR_SLK (1<<1)__GCC_ATOMIC_WCHAR_T_LOCK_FREE 2LCD_BASE (PERIPH_BASE_APB1 + 0x2400)__CHAR_UNSIGNED__ 1USART3_BASE (PERIPH_BASE_APB1 + 0x4800)ADC_CFGR1_EXTEN_MASK (0x3 << 10)__FLT64_HAS_INFINITY__ 1__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GNUC_MINOR__ 2__GCC_DESTRUCTIVE_SIZE 64__LACCUM_EPSILON__ 0x1P-31LK__PTRDIFF_MAX__ 0x7fffffff__ARM_FEATURE_FMA 1__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)__INTMAX_MAX__ 0x7fffffffffffffffLLADC1_BASE (0x50000000U + 0x40000)__FLT64_DECIMAL_DIG__ 17__LDBL_MIN__ 2.2250738585072014e-308LINT_FAST64_MAXOPAMP_BASE (PERIPH_BASE_APB1 + 0x7800)__ATOMIC_CONSUME 1__ULACCUM_FBIT__ 32__WCHAR_MAX__ 0xffffffffULIBOPENCM3_ADC_COMMON_V2_H INT64_MAX __INT64_MAX__INTMAX_MIN__SIZEOF_LONG_LONG__ 8__DBL_MAX_10_EXP__ 308__FRACT_MIN__ (-0.5R-0.5R)__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLKADC_TR1_HT_MASK 0xFFF__USACCUM_MAX__ 0XFFFFP-8UHK__SFRACT_FBIT__ 7__INTMAX_WIDTH__ 64__ARM_FEATURE_BF16_SCALAR_ARITHMETIC__SQ_IBIT__ 0__ORDER_PDP_ENDIAN__ 3412__SIZE_TYPE__ unsigned intADC_SQR2(adc) MMIO32((adc) + 0x34)__FLT_HAS_DENORM__ 1__INT8_TYPE__ signed char__FLT32_MIN__ 1.1754943508222875e-38F32ADC_AWD3CR(adc) MMIO32((adc) + 0xA4)__USACCUM_MIN__ 0.0UHK__FLT32_DECIMAL_DIG__ 9__DECIMAL_DIG__ 17__LDBL_MIN_EXP__ (-1021)__LDBL_MANT_DIG__ 53INT64_MIN (-INT64_MAX - 1)ADC_CR_ADCAL (1 << 31)__UINT8_C(c) c__INT16_TYPE__ short inttrue 1__FLT64_MAX__ 1.7976931348623157e+308F64ADC_ISR_JQOVF (1 << 10)UINT_FAST32_MAXADC_TR1_HT_SHIFT 16INT_FAST64_MAX __INT_FAST64_MAX____GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1ADC_CFGR1_RES_8_BIT (0x2 << 3)__UINT_LEAST16_MAX__ 0xffff__STDC_HOSTED__ 1__ULLFRACT_FBIT__ 64__SIG_ATOMIC_TYPE__ intADC_SQR3_SQ14_SHIFT 24ADC_CFGR1_DISCNUM_MASK (0x7 << ADC_CFGR1_DISCNUM_SHIFT)__INT_FAST64_TYPE__ long long int__WINT_TYPE__ unsigned intGPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800)ST_TSENSE_CAL2_110C MMIO16((INFO_BASE + 0x75ca))INT32_MIN (-INT32_MAX - 1)__FLT32_MAX_10_EXP__ 38ADC_CCR_VBATEN (1 << 24)__USFRACT_MAX__ 0XFFP-8UHRLPTIM1_BASE (PERIPH_BASE_APB1 + 0x7c00)__FP_FAST_FMAF32 1__UINTPTR_MAX__ 0xffffffffUADC_SMPR1(adc) MMIO32((adc) + 0x14)__FLT32_MIN_EXP__ (-125)ADC_CR_ADSTP (1 << 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20221205"__VFP_FP__ 1__LLFRACT_MIN__ (-0.5LLR-0.5LLR)INT_FAST8_MAX__UINT_FAST16_MAX__ 0xffffffffU__INTPTR_MAX__ 0x7fffffffINT64_C(c) __INT64_C(c)ADC_SMPR_SMP_24DOT5CYC 0x3ADC_SMPR2(adc) MMIO32((adc) + 0x18)__GCC_IEC_559_COMPLEX 0ADC_TR1(adc) MMIO32((adc) + 0x20)ADC_CFGR1_JDISCEN (1 << 20)WCHAR_MAX __WCHAR_MAX____FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX__ADC_CFGR1_EXTSEL_SHIFT 6__UINT_LEAST8_TYPE__ unsigned charADC_CR_JADSTP (1 << 5)ADC_SQR4_SQ16_SHIFT 6__ACCUM_FBIT__ 15PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)__UACCUM_IBIT__ 16long intUINT8_MAXIWDG_BASE (PERIPH_BASE_APB1 + 0x3000)SIZE_MAX __SIZE_MAX__ADC_TR1_LT_SHIFT 0__INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17ADC_JDR4(adc) MMIO32((adc) + 0x8C)__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1__FLT32X_EPSILON__ 2.2204460492503131e-16F32xNVIC_BASE (SCS_BASE + 0x0100)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32USART2_BASE (PERIPH_BASE_APB1 + 0x4400)__UINTMAX_C(c) c ## ULL__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed char__GCC_ATOMIC_BOOL_LOCK_FREE 2BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON__ADC_SMPR_SMP_92DOT5CYC 0x5__FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX____THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRshort unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)BIT7 (1<<7)BIT17 (1<<17)__FLT32X_MIN_10_EXP__ (-307)UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)ADC_CFGR1_EXTSEL_VAL(x) ((x) << ADC_CFGR1_EXTSEL_SHIFT)__DBL_IS_IEC_60559__ 2__UINT_FAST32_MAX__ 0xffffffffU__DEC_EVAL_METHOD__ 2__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4WINT_MIN __WINT_MIN__LIBOPENCM3_ADC_COMMON_V2_MULTI_H ADC_CFGR1_AWD1SGL (1 << 22)ADC_TR2(adc) MMIO32((adc) + 0x24)__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32__FLT32X_MIN_EXP__ (-1021)DMA1_BASE (PERIPH_BASE_AHB1 + 0x0000)ADC_IER_AWD1IE (1 << 7)GNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsBIT27 (1<<27)TIM1_BASE (PERIPH_BASE_APB2 + 0x2C00)__UTA_FBIT__ 64INTMAX_C(c) __INTMAX_C(c)__FLT_DECIMAL_DIG__ 9__thumb__ 1__INT_LEAST32_MAX__ 0x7fffffffLLIBOPENCM3_MEMORYMAP_COMMON_H signed charINT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)INT32_C(c) __INT32_C(c)__GNUC_STDC_INLINE__ 1__FRACT_FBIT__ 15ADC_CFGR1_RES_12_BIT (0x0 << 3)__LLACCUM_EPSILON__ 0x1P-31LLK__GNUC_PATCHLEVEL__ 1__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2PTRDIFF_MIN__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)ADC_SMPR_SMP_247DOT5CYC 0x6UINTPTR_MAX __UINTPTR_MAX____ARM_ARCH_PROFILE 77GPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000)__FLT64_MAX_10_EXP__ 308GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400)MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINSDMMC1_BASE (PERIPH_BASE_APB2 + 0x2800)__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)__FRACT_MAX__ 0X7FFFP-15RTIM3_BASE (PERIPH_BASE_APB1 + 0x0400)INT_LEAST32_MAX __INT_LEAST32_MAX__ADC_IER_AWD2IE (1 << 8)__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5ADC_CHANNEL_VBAT 18__UINT16_MAX__ 0xffff__TQ_FBIT__ 127__USQ_FBIT__ 32INT_FAST16_MIN__thumb2__ 1__ULLACCUM_FBIT__ 32FMC_QUADSPI_BASE (0xA0000000U)ADC_CFGR1_JAUTO (1 << 25)INT_FAST32_MIN (-INT_FAST32_MAX - 1)__STRICT_ANSI__ 1FMC3_BANK_BASE (0x80000000U)UINT_LEAST8_MAXUINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)TIM8_BASE (PERIPH_BASE_APB2 + 0x3400)__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__ADC_SMPR_SMP_47DOT5CYC 0x4ADC_CFGR1_AWD1CH (0x1F << ADC_CFGR1_AWD1CH_SHIFT)__USA_IBIT__ 16ADC_SQR3_SQ11_SHIFT 6__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1PTRDIFF_MIN (-PTRDIFF_MAX - 1)USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6c00)__UINT_FAST64_TYPE__ long long unsigned intDESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 0x14)DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7590)__FLT_MIN__ 1.1754943508222875e-38FADC_ISR_AWD3 (1 << 9)__HA_FBIT__ 7__FDPIC____UFRACT_MIN__ 0.0URADC_CFGR1_JQM (1 << 21)ADC_CFGR1_DISCEN (1 << 16)__FLT32_IS_IEC_60559__ 2ADC_CFGR1_ALIGN (1 << 5)__UTA_IBIT__ 64ADC_CCR_VREFEN (1 << 22)GPIO_PORT_G_BASE (PERIPH_BASE_AHB2 + 0x1800)INT_FAST64_MIN__USFRACT_IBIT__ 0__INT32_C(c) c ## L__LDBL_EPSILON__ 2.2204460492503131e-16LADC_CR_ADCALDIF (1 << 30)__USFRACT_MIN__ 0.0UHRTSC_BASE (PERIPH_BASE_AHB1 + 0x4000)__ARM_NEONadc_enable_regulator__UINT8_MAX__ 0xffADC_SQR2_SQ5_SHIFT 0__LDBL_MAX_EXP__ 1024ADC_IER_EOSIE (1 << 3)LIBOPENCM3_MEMORYMAP_H ADC_CFGR1_EXTEN_RISING_EDGE (0x1 << 10)__DBL_HAS_DENORM__ 1DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)QUADSPI_BASE (0xa0001000U)__DA_FBIT__ 31__GXX_ABI_VERSION 1017GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0c00)__INT_LEAST16_MAX__ 0x7fffADC_SMPR_SMP_640DOT5CYC 0x7__FLT_DENORM_MIN__ 1.4012984643248171e-45F__ULLACCUM_EPSILON__ 0x1P-32ULLKINT_LEAST8_MAX __INT_LEAST8_MAX____UINT32_C(c) c ## UL__UACCUM_MIN__ 0.0UK__FLT_EPSILON__ 1.1920928955078125e-7FADC_IER_EOCIE (1 << 2)TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)__ARM_ARCH_ISA_THUMB__ARM_FEATURE_MATMUL_INT8__UINT8_TYPE__ unsigned charLIBOPENCM3_CM3_MEMORYMAP_H __GCC_ATOMIC_SHORT_LOCK_FREE 2ADC_OFR4(adc) MMIO32((adc) + 0x6C)__USACCUM_FBIT__ 8ADC_CR_ADVREGEN (1 << 28)__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1ADC_CFGR1(adc) MMIO32((adc) + 0x0C)__LACCUM_FBIT__ 31SCS_BASE (PPBI_BASE + 0xE000)SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)__FLT32_HAS_QUIET_NAN__ 1I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)__LDBL_HAS_INFINITY__ 1__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))__FLT32X_MAX_10_EXP__ 308__ARM_ARCH_EXT_IDIV__ 1bool _BoolUINTMAX_MAX __UINTMAX_MAX____SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffBBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)ADC_IER(adc) MMIO32((adc) + 0x04)__FP_FAST_FMAF 1__FLT32X_IS_IEC_60559__ 2PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)ADC_CR_ADSTART (1 << 2)LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))FIREWALL_BASE (PERIPH_BASE_APB2 + 0x1C00)ADC_SMPR_SMP_2DOT5CYC 0x0__INT_LEAST16_WIDTH__ 16SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)__ARM_FEATURE_FP16_FMLINT16_MIN (-INT16_MAX - 1)__USFRACT_EPSILON__ 0x1P-8UHR__WINT_MAX__ 0xffffffffU__USFRACT_FBIT__ 8CORESIGHT_LSR_SLI (1<<0)__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX____UINT32_MAX__ 0xffffffffUL__INT_LEAST8_MAX__ 0x7f__GCC_ATOMIC_POINTER_LOCK_FREE 2__ARM_FEATURE_QBIT 1__ARM_FEATURE_CLZ 1__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXADC_CR_DEEPPWD (1 << 29)__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024__UINT_LEAST32_MAX__ 0xffffffffUL__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)ADC_CFGR1_CONT (1 << 13)ADC_CHANNEL_TEMP 17__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1__ACCUM_MAX__ 0X7FFFFFFFP-15K__INT8_MAX__ 0x7fBIT14 (1<<14)__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16__SHRT_WIDTH__ 16BIT20 (1<<20)__ARM_FEATURE_MVE__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intADC_IER_EOSEQIE ADC_IER_EOSIESWPMI1_BASE (PERIPH_BASE_APB1 + 0x8800)SAI1_BASE (PERIPH_BASE_APB2 + 0x5400)INT_FAST32_MINADC_ISR_AWD2 (1 << 8)__FLT_EVAL_METHOD_TS_18661_3__ 0__SCHAR_WIDTH__ 8BIT18 (1<<18)COMP_BASE (PERIPH_BASE_APB2 + 0x0200)SIZE_MAX__UINT_FAST8_TYPE__ unsigned int__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RBIT24 (1<<24)ADC_SMPR_SMP_6DOT5CYC 0x1__INT32_MAX__ 0x7fffffffLUINTMAX_MAXADC_ISR_JEOS (1 << 6)BIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_BF16_VECTOR_ARITHMETICINFO_BASE (0x1fff0000U)PPBI_BASE (0xE0000000U)__FLT32_MANT_DIG__ 24INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN__INT8_MAX __INT8_MAX__BIT28 (1<<28)ADC_JDR1(adc) MMIO32((adc) + 0x80)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2__DBL_MAX_EXP__ 1024__ATOMIC_RELEASE 3ADC_SQRx_SQx_MASK 0x1fUINT_FAST8_MAX__FLT_MANT_DIG__ 24__UDQ_IBIT__ 0__INT_LEAST32_TYPE__ long int__OPTIMIZE_SIZE__ 1__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UK__FLT64_NORM_MAX__ 1.7976931348623157e+308F64UINTPTR_MAX__LDBL_DENORM_MIN__ 4.9406564584124654e-324LADC_TR1_LT (0xFFF << ADC_TR1_LT_SHIFT)__INT64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_SAT 1ADC_CFGR1_DISCNUM_SHIFT 17__ULLFRACT_IBIT__ 0MMIO16(addr) (*(volatile uint16_t *)(addr))ADC_IER_JEOCIE (1 << 5)AES_BASE (0x50000000U + 0x60000)DAC_BASE (PERIPH_BASE_APB1 + 0x7400)__GNUC__ 12BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)WCHAR_MAX__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0UUART5_BASE (PERIPH_BASE_APB1 + 0x5000)__UQQ_IBIT__ 0CORESIGHT_LSR_OFFSET 0xfb4__GCC_ATOMIC_LONG_LOCK_FREE 2__ULACCUM_MIN__ 0.0ULKADC_IER_ADRDYIE (1 << 0)__LDBL_MAX__ 1.7976931348623157e+308L__ARM_ARCH 7__FLT_RADIX__ 2BIT3 (1<<3)long long intCORESIGHT_LAR_KEY 0xC5ACCE55__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAXADC_JDR2(adc) MMIO32((adc) + 0x84)__LDBL_HAS_QUIET_NAN__ 1ADC_CCR(adc) MMIO32((adc) + 0x300 + 0x8)__LONG_LONG_WIDTH__ 64BIT6 (1<<6)ADC_IER_JQOVFIE (1 << 10)__UINT_FAST64_MAX__ 0xffffffffffffffffULL__ARM_FP__HA_IBIT__ 8__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1BIT9 (1<<9)__FLT32X_MIN__ 2.2250738585072014e-308F32xINTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024UINT16_MAXPERIPH_BASE_AHB2 (0x48000000U)__FLT64_MIN__ 2.2250738585072014e-308F64ADC_SQR1_L_SHIFT 0__INTMAX_C(c) c ## LLADC_CR(adc) MMIO32((adc) + 0x08)__ARM_ARCH_PROFILE__INT64_TYPE__ long long int__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4ADC_SQR1_L_MASK 0xfCRS_BASE (PERIPH_BASE_APB1 + 0x6000)__UFRACT_MAX__ 0XFFFFP-16UR__ARM_FEATURE_LDREXINT64_MAXFPB_BASE (PPBI_BASE + 0x2000)INT_FAST64_MIN (-INT_FAST64_MAX - 1)STIR_BASE (SCS_BASE + 0x0F00)__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPADC_ISR_EOS (1 << 3)UINT_FAST64_MAX __UINT_FAST64_MAX__ADC_IER_OVRIE (1 << 4)TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)ID_BASE (SCS_BASE + 0x0FD0)SYS_TICK_BASE (SCS_BASE + 0x0010)__UFRACT_FBIT__ 16FMC_BASE (0xa0000000U)__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)__LDBL_MAX_10_EXP__ 308__INT_FAST32_TYPE__ intunsigned intadc.c__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1__USACCUM_IBIT__ 8ITM_BASE (PPBI_BASE + 0x0000)ST_VREFINT_CAL MMIO16((INFO_BASE + 0x75aa))__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UKADC_ISR_AWD1 (1 << 7)__FLT_EVAL_METHOD__ 0__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32DFSDM_BASE (PERIPH_BASE_APB2 + 0x6000)adc_disable_regulatorLIBOPENCM3_ADC_H __UQQ_FBIT__ 8ADC_TR1_HT_VAL(x) (((x) & ADC_TR1_HT_MASK) << ADC_TR1_HT_SHIFT)INT16_C__ARM_FP16_ARGS__GCC_IEC_559 0INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX____LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4__STDC__ 1__ARM_FEATURE_IDIV 1__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__DBGMCU_BASE (PPBI_BASE + 0x00042000)ADC_CFGR1_AUTDLY (1 << 14)__ARM_FEATURE_COPROC 15ADC_IER_EOSMPIE (1 << 1)INTPTR_MIN (-INTPTR_MAX - 1)__GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"INT8_MINPERIPH_BASE (0x40000000U)PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)__LDBL_MIN_10_EXP__ (-307)ADC_CFGR1_EXTEN_FALLING_EDGE (0x2 << 10)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1__GCC_ATOMIC_CHAR_LOCK_FREE 2ADC_CFGR1_EXTEN_DISABLED (0x0 << 10)RCC_BASE (PERIPH_BASE_AHB1 + 0x1000)__LFRACT_EPSILON__ 0x1P-31LRFMC1_BANK_BASE (0x60000000U)STM32L4 1__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX____FLT32X_NORM_MAX__ 1.7976931348623157e+308F32x__arm__ 1__FLT32_MIN_10_EXP__ (-37)MMIO64(addr) (*(volatile uint64_t *)(addr))__ARM_FP16_FORMAT_ALTERNATIVE__LDBL_NORM_MAX__ 1.7976931348623157e+308LINTPTR_MINDESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)INT16_MAX __INT16_MAX____BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)__TA_IBIT__ 64__ARM_FEATURE_QRDMX__ARM_ARCH_ISA_THUMB 2__LONG_LONG_MAX__ 0x7fffffffffffffffLL__WINT_WIDTH__ 32SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN____SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__DBL_MIN_EXP__ (-1021)__LDBL_HAS_DENORM__ 1ADC_SQR2_SQ9_SHIFT 24INT8_MIN (-INT8_MAX - 1)__FLT32_DIG__ 6INT_LEAST16_MAXADC_SQR3_SQ13_SHIFT 18BIT15 (1<<15)ADC_ISR_ADRDY (1 << 0)VREFBUF_BASE (PERIPH_BASE_APB2 + 0x0030)BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1INT32_MAXADC_SQR1(adc) MMIO32((adc) + 0x30)__ACCUM_MIN__ (-0X1P15K-0X1P15K)ADC_CFGR1_AWD1CH_SHIFT 26__ARM_FEATURE_CRYPTOUART4_BASE (PERIPH_BASE_APB1 + 0x4c00)ADC_OFR2(adc) MMIO32((adc) + 0x64)BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__FRACT_IBIT__ 0UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234__FLT_NORM_MAX__ 3.4028234663852886e+38Flong long unsigned int__FLT_MIN_10_EXP__ (-37)GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000)__ULACCUM_IBIT__ 32__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__PTRDIFF_TYPE__ int__APCS_32__ 1__DQ_FBIT__ 63INT_LEAST64_MAX__SACCUM_IBIT__ 8ADC_TR1_LT_MASK 0xFFF__UHQ_IBIT__ 0TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)INT_LEAST8_MINBIT29 (1<<29)__INT_FAST16_TYPE__ intINT64_C__ULFRACT_MAX__ 0XFFFFFFFFP-32ULR__UINT_LEAST16_TYPE__ short unsigned int__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned intADC_IER_JEOSIE (1 << 6)__FLT32X_DIG__ 15__UTQ_FBIT__ 128ADC_CFGR1_RES_MASK (0x3 << 3)__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffffADC_ISR_EOC (1 << 2)DMA2_BASE (PERIPH_BASE_AHB1 + 0x0400)PTRDIFF_MAX __PTRDIFF_MAX____SIZEOF_SHORT__ 2UINT_FAST16_MAX__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKUINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULR__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intADC_CSR(adc) MMIO32((adc) + 0x300 + 0x0)WCHAR_MINADC_SQR4(adc) MMIO32((adc) + 0x3C)BEGIN_DECLS ADC_CR_ADEN (1 << 0)__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__FLT32X_MAX__ 1.7976931348623157e+308F32xGPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400)ADC_CFGR1_EXTSEL_MASK (0xf << ADC_CFGR1_EXTSEL_SHIFT)__ARM_EABI__ 1INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1ADC_CFGR1_DMAEN (1 << 0)ADC_ISR_EOSMP (1 << 1)__ARM_FEATURE_DSP 1TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)__QQ_IBIT__ 0__LLACCUM_FBIT__ 31__UINTMAX_TYPE__ long long unsigned int__USQ_IBIT__ 0__UINT_LEAST32_TYPE__ long unsigned intADC_TR3(adc) MMIO32((adc) + 0x28)ADC_CFGR1_OVRMOD (1 << 12)__ARM_FEATURE_NUMERIC_MAXMIN__INTMAX_TYPE__ long long int__GCC_ATOMIC_INT_LOCK_FREE 2TIM16_BASE (PERIPH_BASE_APB2 + 0x4400)INTMAX_MAXDESIG_PACKAGE MMIO16((INFO_BASE + 0x7500))__ARM_ARCH_7EM__ 1__ARM_FEATURE_FP16_SCALAR_ARITHMETIC__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1TIM17_BASE (PERIPH_BASE_APB2 + 0x4800)__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CADC_SQR1_SQ4_SHIFT 24ADC_SQR2_SQ6_SHIFT 6INT64_MIN__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intUINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRADC_OFR3(adc) MMIO32((adc) + 0x68)ADC3 ADC3_BASE/build/libopencm3/lib/stm32/l4__SIZEOF_SIZE_T__ 4__UINT64_TYPE__ long long unsigned int__INT64_C(c) c ## LLUSART1_BASE (PERIPH_BASE_APB2 + 0x3800)USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x6800)TPIU_BASE (PPBI_BASE + 0x40000)ADC_SQR2_SQ8_SHIFT 18__LONG_MAX__ 0x7fffffffL__ARM_FEATURE_CDE__ACCUM_IBIT__ 16CORESIGHT_LAR_OFFSET 0xfb0EXTI_BASE (PERIPH_BASE_APB2 + 0x0400)ADC_CDR(adc) MMIO32((adc) + 0x300 + 0xc)FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000)short intRNG_BASE (0x50000000U + 0x60800)__UINT16_C(c) cBIT31 (1<<31)__UDA_IBIT__ 32ADC_AWD2CR(adc) MMIO32((adc) + 0xA0)UINT_LEAST32_MAXBIT2 (1<<2)__ATOMIC_RELAXED 0__ARM_FEATURE_COPROCADC1 ADC1_BASE__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53ADC_CFGR2(adc) MMIO32((adc) + 0x10)BIT5 (1<<5)BIT1 (1<<1)INT8_CGPIO_PORT_H_BASE (PERIPH_BASE_AHB2 + 0x1c00)INT_LEAST32_MAX__USES_INITFINI__ 1__DBL_DECIMAL_DIG__ 17ADC_SQR3_SQ12_SHIFT 12BIT8 (1<<8)INT16_C(c) __INT16_C(c)UINT32_MAX__INT16_MAX__ 0x7fffADC_SMPR_SMP_12DOT5CYC 0x2__INT_WIDTH__ 32__ARM_FEATURE_SIMD32 1DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x75e0)__QQ_FBIT__ 7RTC_BASE (PERIPH_BASE_APB1 + 0x2800)__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64LPTIM2_BASE (PERIPH_BASE_APB1 + 0x9400)__ULLACCUM_IBIT__ 32__ULLFRACT_EPSILON__ 0x1P-64ULLRfalse 0ADC_CR_ADDIS (1 << 1)__SIZEOF_WINT_T__ 4__ARM_FEATURE_UNALIGNED 1__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17ADC_JDR3(adc) MMIO32((adc) + 0x88)__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1ADC_CFGR1_JAWD1EN (1 << 24)__FLT32X_HAS_DENORM__ 1__ULLACCUM_MIN__ 0.0ULLK__INT_FAST32_WIDTH__ 32ADC2 ADC2_BASEADC_DR(adc) MMIO32((adc) + 0x40)__ARM_ASM_SYNTAX_UNIFIED__ 1__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODADC_ISR(adc) MMIO32((adc) + 0x00)__ARM_PCS_VFP 1ADC_CHANNEL_VREF 0__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H LPUART1_BASE (PERIPH_BASE_APB1 + 0x8000)INT_LEAST64_MINADC_CFGR1_DMACFG (1 << 1)__GCC_CONSTRUCTIVE_SIZE 64__LLFRACT_IBIT__ 0ADC_CFGR1_DISCNUM_VAL(x) (((x) - 1) << ADC_CFGR1_DISCNUM_SHIFT)uint32_tBIT12 (1<<12)MPU_BASE (SCS_BASE + 0x0D90)__SACCUM_EPSILON__ 0x1P-7HK__GCC_ASM_FLAG_OUTPUTS__ 1ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0x75a8))__ARM_FP 4__UINT_FAST16_TYPE__ unsigned int__UHA_IBIT__ 8__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULK__LDBL_DIG__ 15POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXBIT16 (1<<16)__WINT_MIN__ 0UINT_LEAST16_MINADC_SQR4_SQ15_SHIFT 0ADC_TR1_LT_VAL(x) (((x) & ADC_TR1_LT_MASK) << ADC_TR1_LT_SHIFT)__FLT64_DIG__ 15TIM15_BASE (PERIPH_BASE_APB2 + 0x4000)BIT22 (1<<22)__INT_LEAST8_WIDTH__ 8WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)__INT_LEAST16_TYPE__ short int__DBL_MAX__ ((double)1.7976931348623157e+308L)INT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1UINTMAX_CADC_ISR_OVR (1 << 4)ADC_ISR_JEOC (1 << 5)INT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1ADC_CR_JADSTART (1 << 3)__HQ_FBIT__ 15__bool_true_false_are_defined 1BIT26 (1<<26)ADC_CFGR1_AWD1CH_VAL(x) ((x) << ADC_CFGR1_AWD1CH_SHIFT)__SIZE_MAX__ 0xffffffffUSPI2_BASE (PERIPH_BASE_APB1 + 0x3800)ADC_SQR1_SQ1_SHIFT 6__ARM_ARCH__SFRACT_IBIT__ 0ADC_CFGR1_RES_6_BIT (0x3 << 3)SAI2_BASE (PERIPH_BASE_APB2 + 0x5800)__ARM_FEATURE_LDREX 7PTRDIFF_MAX__LLFRACT_EPSILON__ 0x1P-63LLR__SFRACT_MAX__ 0X7FP-7HR__FLT32X_MANT_DIG__ 53__WCHAR_WIDTH__ 32ADC_IER_AWD3IE (1 << 9)WINT_MAX__INT16_C(c) cINT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32__ATOMIC_ACQ_REL 4__HQ_IBIT__ 0__DBL_MIN_10_EXP__ (-307)__FLT32_NORM_MAX__ 3.4028234663852886e+38F32ADC_SQR2_SQ7_SHIFT 12UINT64_C(c) __UINT64_C(c)__UINTMAX_MAX__ 0xffffffffffffffffULL__DBL_MANT_DIG__ 53ADC_CFGR1_AWD1EN (1 << 23)__ULFRACT_IBIT__ 0UINT64_MAX __UINT64_MAX__INT_FAST16_MAXITR_BASE (SCS_BASE + 0x0000)QUADSPI_BANK_BASE (0x90000000U)__INT_MAX__ 0x7fffffff__INT_LEAST64_TYPE__ long long int__ARM_FEATURE_CDE_COPROCUINT32_CGCC: (15:12.2.rel1-1) 12.2.1 20221205˙˙˙˙| A3aeabi)7E-M M "ń˙ -/!#%')+1 1b“Ĺö*^– Ô 03 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(PERIPH_BASE_AHB2 + 0x0800)ST_TSENSE_CAL2_110C MMIO16((INFO_BASE + 0x75ca))INT32_MIN (-INT32_MAX - 1)ADC_ISR_EOS (1 << 3)__FLT32_MAX_10_EXP__ 38adc_disable_overrun_interrupt__USFRACT_MAX__ 0XFFP-8UHRLPTIM1_BASE (PERIPH_BASE_APB1 + 0x7c00)__FP_FAST_FMAF32 1adc_disable_temperature_sensorADC_SMPR1(adc) MMIO32((adc) + 0x14)__FLT32_MIN_EXP__ (-125)ADC_CR_ADSTP (1 << 4)ADC_CFGR1_EXTEN_BOTH_EDGES (0x3 << 10)UINT32_MAX __UINT32_MAX__ADC_SQR1_SQ3_SHIFT 18__ULFRACT_FBIT__ 32INT8_MIN (-INT8_MAX - 1)__FLT64_MIN_10_EXP__ (-307)__GNUC_EXECUTION_CHARSET_NAME "UTF-8"BIT10 (1<<10)__INT_FAST64_WIDTH__ 64__STDC_VERSION__ 199901LINT_LEAST64_MAX __INT_LEAST64_MAX__ADC_SQR3_SQ10_SHIFT 0ADC_JSQR(adc) MMIO32((adc) + 0x30)__SFRACT_EPSILON__ 0x1P-7HRADC_ISR_EOSEQ ADC_ISR_EOS__INT32_C(c) c ## LUINT32_C(c) __UINT32_C(c)__ORDER_BIG_ENDIAN__ 4321I2C3_BASE (PERIPH_BASE_APB1 + 0x5c00)SYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000)__SQ_FBIT__ 31DWT_BASE (PPBI_BASE + 0x1000)adc_is_power_offadc_set_left_aligned__UHQ_FBIT__ 16ADC_CALFACT(adc) MMIO32((adc) + 0xB4)__FLT64_MIN_EXP__ (-1021)ADC_DIFSEL(adc) MMIO32((adc) + 0xB0)__PTRDIFF_WIDTH__ 32ADC_SQR1_SQ2_SHIFT 12ADC_CCR_TSEN (1 << 23)__UINT_FAST8_MAX__ 0xffffffffULIBOPENCM3_ADC_H UINT16_C(c) __UINT16_C(c)__LACCUM_IBIT__ 32ADC_OFR1(adc) MMIO32((adc) + 0x60)__INT_FAST16_WIDTH__ 32INTMAX_C__VERSION__ "12.2.1 20221205"__VFP_FP__ 1__LLFRACT_MIN__ (-0.5LLR-0.5LLR)INT_FAST8_MAX__UINT_FAST16_MAX__ 0xffffffffU__INTPTR_MAX__ 0x7fffffffINT64_C(c) __INT64_C(c)ADC_SMPR_SMP_24DOT5CYC 0x3ADC_SMPR2(adc) MMIO32((adc) + 0x18)__GCC_IEC_559_COMPLEX 0PERIPH_BASE (0x40000000U)ADC_CFGR1_JDISCEN (1 << 20)WCHAR_MAX __WCHAR_MAX____FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX__ADC_CFGR1_EXTSEL_SHIFT 6__UINT_LEAST8_TYPE__ unsigned charADC_CR_JADSTP (1 << 5)ADC_SQR4_SQ16_SHIFT 6__ACCUM_FBIT__ 15PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)__UACCUM_IBIT__ 16long intUINT8_MAXIWDG_BASE (PERIPH_BASE_APB1 + 0x3000)SIZE_MAX __SIZE_MAX__ADC_TR1_LT_SHIFT 0__INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17ADC_JDR4(adc) MMIO32((adc) + 0x8C)__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1__FLT32X_EPSILON__ 2.2204460492503131e-16F32xDESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7590)NVIC_BASE (SCS_BASE + 0x0100)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32USART2_BASE (PERIPH_BASE_APB1 + 0x4400)__UINTMAX_C(c) c ## ULL__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed char__GCC_ATOMIC_BOOL_LOCK_FREE 2BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON__ADC_SMPR_SMP_92DOT5CYC 0x5__FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX____THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRshort unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)BIT7 (1<<7)BIT17 (1<<17)__FLT32X_MIN_10_EXP__ (-307)UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)ADC_CFGR1_EXTSEL_VAL(x) ((x) << ADC_CFGR1_EXTSEL_SHIFT)__DBL_IS_IEC_60559__ 2__UINT_FAST32_MAX__ 0xffffffffU__DEC_EVAL_METHOD__ 2__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4WINT_MIN __WINT_MIN__LIBOPENCM3_ADC_COMMON_V2_MULTI_H ADC_CFGR1_AWD1SGL (1 << 22)ADC_CFGR1_DISCNUM_SHIFT 17ADC_TR2(adc) MMIO32((adc) + 0x24)__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32DMA1_BASE (PERIPH_BASE_AHB1 + 0x0000)ADC_IER_AWD1IE (1 << 7)GNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsBIT27 (1<<27)SAI1_BASE (PERIPH_BASE_APB2 + 0x5400)__UTA_FBIT__ 64INTMAX_C(c) __INTMAX_C(c)__FLT_DECIMAL_DIG__ 9__thumb__ 1__INT_LEAST32_MAX__ 0x7fffffffLLIBOPENCM3_MEMORYMAP_COMMON_H signed charINT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)INT32_C(c) __INT32_C(c)__GNUC_STDC_INLINE__ 1__FRACT_FBIT__ 15ADC_CFGR1_RES_12_BIT (0x0 << 3)__FLT_HAS_QUIET_NAN__ 1__GNUC_PATCHLEVEL__ 1__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2PTRDIFF_MIN__UINT_LEAST16_MAX__ 0xffffUINTPTR_MAX __UINTPTR_MAX____ARM_ARCH_PROFILE 77GPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000)__FLT64_MAX_10_EXP__ 308GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400)MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINSDMMC1_BASE (PERIPH_BASE_APB2 + 0x2800)__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)__FRACT_MAX__ 0X7FFFP-15RTIM3_BASE (PERIPH_BASE_APB1 + 0x0400)INT_LEAST32_MAX __INT_LEAST32_MAX__ADC_IER_AWD2IE (1 << 8)__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5ADC_CHANNEL_VBAT 18__UINT16_MAX__ 0xffff__TQ_FBIT__ 127adc_disable_vrefint__USQ_FBIT__ 32INT_FAST16_MIN__thumb2__ 1__ULLACCUM_FBIT__ 32FMC_QUADSPI_BASE (0xA0000000U)adc_set_resolution_BoolADC_CFGR1_JAUTO (1 << 25)__FLT_DENORM_MIN__ 1.4012984643248171e-45F__STRICT_ANSI__ 1FMC3_BANK_BASE (0x80000000U)UINT_LEAST8_MAXUINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)TIM8_BASE (PERIPH_BASE_APB2 + 0x3400)ADC_CR_JADSTART (1 << 3)__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__ADC_SMPR_SMP_47DOT5CYC 0x4ADC_CFGR1_AWD1CH (0x1F << ADC_CFGR1_AWD1CH_SHIFT)__USA_IBIT__ 16ADC_SQR3_SQ11_SHIFT 6__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1DBGMCU_BASE (PPBI_BASE + 0x00042000)PTRDIFF_MIN (-PTRDIFF_MAX - 1)USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6c00)__UINT_FAST64_TYPE__ long long unsigned intPERIPH_BASE_AHB2 (0x48000000U)adc_enable_vrefint__FLT_MIN__ 1.1754943508222875e-38FADC_ISR_AWD3 (1 << 9)__HA_FBIT__ 7__FDPIC____UFRACT_MIN__ 0.0URADC_CFGR1_JQM (1 << 21)__UINT32_C(c) c ## UL__FLT32_IS_IEC_60559__ 2ADC_CFGR1_ALIGN (1 << 5)ADC_CCR_VREFEN (1 << 22)GPIO_PORT_G_BASE (PERIPH_BASE_AHB2 + 0x1800)INT_FAST64_MIN__USFRACT_IBIT__ 0__LDBL_EPSILON__ 2.2204460492503131e-16LADC_CR_ADCALDIF (1 << 30)WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)__USFRACT_MIN__ 0.0UHRTSC_BASE (PERIPH_BASE_AHB1 + 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1I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)__LDBL_HAS_INFINITY__ 1__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))__FLT32X_MAX_10_EXP__ 308__ARM_ARCH_EXT_IDIV__ 1bool _BoolUINTMAX_MAX __UINTMAX_MAX____SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffBBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)INT16_MAX __INT16_MAX____FP_FAST_FMAF 1__FLT32X_IS_IEC_60559__ 2PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)ADC_CR_ADSTART (1 << 2)LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))FIREWALL_BASE (PERIPH_BASE_APB2 + 0x1C00)ADC_SMPR_SMP_2DOT5CYC 0x0ADC_CR_ADCAL (1 << 31)__INT_LEAST16_WIDTH__ 16SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)__ARM_FEATURE_FP16_FMLINT16_MIN (-INT16_MAX - 1)__USFRACT_EPSILON__ 0x1P-8UHR__WINT_MAX__ 0xffffffffU__USFRACT_FBIT__ 8CORESIGHT_LSR_SLI (1<<0)__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX____UINT32_MAX__ 0xffffffffULadc_power_off__INT_LEAST8_MAX__ 0x7f__GCC_ATOMIC_POINTER_LOCK_FREE 2__ARM_FEATURE_QBIT 1__ARM_FEATURE_CLZ 1__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXadc_calibrate_asyncADC_CR_DEEPPWD (1 << 29)__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024__UINT_LEAST32_MAX__ 0xffffffffUL__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)ADC_CFGR1_CONT (1 << 13)adc_disable_eoc_interrupt__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1__ACCUM_MAX__ 0X7FFFFFFFP-15K__INT8_MAX__ 0x7fBIT14 (1<<14)__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16__SHRT_WIDTH__ 16BIT20 (1<<20)__ARM_FEATURE_MVE__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intADC_IER_EOSEQIE ADC_IER_EOSIESWPMI1_BASE (PERIPH_BASE_APB1 + 0x8800)UINT_LEAST16_MAX __UINT_LEAST16_MAX__INT_FAST32_MINADC_ISR_AWD2 (1 << 8)__FLT_EVAL_METHOD_TS_18661_3__ 0__SCHAR_WIDTH__ 8BIT18 (1<<18)COMP_BASE (PERIPH_BASE_APB2 + 0x0200)SIZE_MAX__UINT_FAST8_TYPE__ unsigned int__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RBIT24 (1<<24)ADC_SMPR_SMP_6DOT5CYC 0x1__INT32_MAX__ 0x7fffffffLUINTMAX_MAXADC_ISR_JEOS (1 << 6)BIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_BF16_VECTOR_ARITHMETICINFO_BASE (0x1fff0000U)PPBI_BASE (0xE0000000U)__FLT32_MANT_DIG__ 24INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32adc_enable_dma__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN__INT8_MAX __INT8_MAX__BIT28 (1<<28)ADC_JDR1(adc) MMIO32((adc) + 0x80)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2adc_enable_dma_circular_mode__DBL_MAX_EXP__ 1024__ATOMIC_RELEASE 3ADC_SQRx_SQx_MASK 0x1fUINT_FAST8_MAX__FLT_MANT_DIG__ 24ADC_IER(adc) MMIO32((adc) + 0x04)__UDQ_IBIT__ 0TIM1_BASE (PERIPH_BASE_APB2 + 0x2C00)ADC_SMPR_SMP_12DOT5CYC 0x2__OPTIMIZE_SIZE__ 1__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UKadc_enable_temperature_sensor__FLT64_NORM_MAX__ 1.7976931348623157e+308F64UINTPTR_MAX__LDBL_DENORM_MIN__ 4.9406564584124654e-324LADC_TR1_LT (0xFFF << ADC_TR1_LT_SHIFT)__INT64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_SAT 1adc_power_on_async__ULLFRACT_IBIT__ 0MMIO16(addr) (*(volatile uint16_t *)(addr))ADC_IER_JEOCIE (1 << 5)AES_BASE (0x50000000U + 0x60000)DAC_BASE (PERIPH_BASE_APB1 + 0x7400)__GNUC__ 12BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)ADC_ISR_AWD1 (1 << 7)WCHAR_MAX__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0UUART5_BASE (PERIPH_BASE_APB1 + 0x5000)__UQQ_IBIT__ 0CORESIGHT_LSR_OFFSET 0xfb4__GCC_ATOMIC_LONG_LOCK_FREE 2__ULACCUM_MIN__ 0.0ULKADC_IER_ADRDYIE (1 << 0)__LDBL_MAX__ 1.7976931348623157e+308L__ARM_ARCH 7UART4_BASE (PERIPH_BASE_APB1 + 0x4c00)ADC_CFGR1_DMAEN (1 << 0)__FLT_RADIX__ 2BIT3 (1<<3)long long intCORESIGHT_LAR_KEY 0xC5ACCE55__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAXINTPTR_MIN__LDBL_HAS_QUIET_NAN__ 1ADC_CCR(adc) MMIO32((adc) + 0x300 + 0x8)__LONG_LONG_WIDTH__ 64BIT6 (1<<6)ADC_IER_JQOVFIE (1 << 10)__UINT_FAST64_MAX__ 0xffffffffffffffffULL__ARM_FP__HA_IBIT__ 8__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1BIT9 (1<<9)__FLT32X_MIN__ 2.2250738585072014e-308F32xINTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024UINT16_MAX__FLT64_MIN__ 2.2250738585072014e-308F64ADC_SQR1_L_SHIFT 0__INTMAX_C(c) c ## LLADC_CR(adc) MMIO32((adc) + 0x08)__ARM_ARCH_PROFILE__INT64_TYPE__ long long int__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4ADC_SQR1_L_MASK 0xfCRS_BASE (PERIPH_BASE_APB1 + 0x6000)__UFRACT_MAX__ 0XFFFFP-16URINT64_MAXFPB_BASE (PPBI_BASE + 0x2000)INT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0STIR_BASE (SCS_BASE + 0x0F00)__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)adc_get_overrun_flagADC_IER_OVRIE (1 << 4)TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)SYS_TICK_BASE (SCS_BASE + 0x0010)__UFRACT_FBIT__ 16FMC_BASE (0xa0000000U)__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)__LDBL_MAX_10_EXP__ 308__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)__INT_FAST32_TYPE__ intunsigned int__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1__USACCUM_IBIT__ 8ITM_BASE (PPBI_BASE + 0x0000)ST_VREFINT_CAL MMIO16((INFO_BASE + 0x75aa))__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UK__UTA_IBIT__ 64__FLT_EVAL_METHOD__ 0__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32RCC_BASE (PERIPH_BASE_AHB1 + 0x1000)__ARM_FEATURE_LDREX__UQQ_FBIT__ 8ADC_TR1_HT_VAL(x) (((x) & ADC_TR1_HT_MASK) << ADC_TR1_HT_SHIFT)INT16_C__ARM_FP16_ARGS__GCC_IEC_559 0INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX____LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4__STDC__ 1__ARM_FEATURE_IDIV 1__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN____UINT8_TYPE__ unsigned charADC_CFGR1_AUTDLY (1 << 14)__ARM_FEATURE_COPROC 15ADC_IER_EOSMPIE (1 << 1)UINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"INT8_MINPERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)__FLT32X_MIN_EXP__ (-1021)ADC_CFGR1_EXTEN_FALLING_EDGE (0x2 << 10)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__GCC_ATOMIC_CHAR_LOCK_FREE 2ADC_CFGR1_EXTEN_DISABLED (0x0 << 10)__LFRACT_EPSILON__ 0x1P-31LRFMC1_BANK_BASE (0x60000000U)STM32L4 1ADC_TR1_LT_MASK 0xFFF__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX____FLT32X_NORM_MAX__ 1.7976931348623157e+308F32x__arm__ 1__FLT32_MIN_10_EXP__ (-37)MMIO64(addr) (*(volatile uint64_t *)(addr))__ARM_FP16_FORMAT_ALTERNATIVE__LDBL_NORM_MAX__ 1.7976931348623157e+308Ladc_clear_overrun_flagDESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)__TA_IBIT__ 64__ARM_FEATURE_QRDMX__ARM_ARCH_ISA_THUMB 2adc_set_right_aligned__LONG_LONG_MAX__ 0x7fffffffffffffffLL__WINT_WIDTH__ 32SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN____SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__DBL_MIN_EXP__ (-1021)__LDBL_HAS_DENORM__ 1ADC_SQR2_SQ9_SHIFT 24INT_FAST32_MIN (-INT_FAST32_MAX - 1)__FLT32_DIG__ 6INT_LEAST16_MAXADC_SQR3_SQ13_SHIFT 18BIT15 (1<<15)ADC_ISR_ADRDY (1 << 0)VREFBUF_BASE (PERIPH_BASE_APB2 + 0x0030)BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1INT32_MAXADC_SQR1(adc) MMIO32((adc) + 0x30)__ACCUM_MIN__ (-0X1P15K-0X1P15K)ADC_CFGR1_AWD1CH_SHIFT 26__ARM_FEATURE_CRYPTO__INT_LEAST32_TYPE__ long intADC_OFR2(adc) MMIO32((adc) + 0x64)BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__FRACT_IBIT__ 0UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234ADC1_BASE (0x50000000U + 0x40000)__FLT_NORM_MAX__ 3.4028234663852886e+38Flong long unsigned int__FLT_MIN_10_EXP__ (-37)GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000)__ULACCUM_IBIT__ 32__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__PTRDIFF_TYPE__ int__APCS_32__ 1__DQ_FBIT__ 63ADC1 ADC1_BASEINT_LEAST64_MAX__SACCUM_IBIT__ 8adc_disable_dma_circular_mode__UHQ_IBIT__ 0TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)INT_LEAST8_MINBIT29 (1<<29)__INT_FAST16_TYPE__ intINT64_C__ULFRACT_MAX__ 0XFFFFFFFFP-32ULR__UINT_LEAST16_TYPE__ short unsigned intADC_CHANNEL_TEMP 17__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned intADC_IER_JEOSIE (1 << 6)__FLT32X_DIG__ 15__UTQ_FBIT__ 128ADC_CFGR1_RES_MASK (0x3 << 3)adc_set_continuous_conversion_mode__LLACCUM_EPSILON__ 0x1P-31LLK__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffffADC_ISR_EOC (1 << 2)DMA2_BASE (PERIPH_BASE_AHB1 + 0x0400)PTRDIFF_MAX __PTRDIFF_MAX____SIZEOF_SHORT__ 2UINT_FAST16_MAX__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKUINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULR__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intADC_CSR(adc) MMIO32((adc) + 0x300 + 0x0)WCHAR_MINADC_SQR4(adc) MMIO32((adc) + 0x3C)BEGIN_DECLS ADC_CR_ADEN (1 << 0)adc_power_on__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15ADC_CCR_VBATEN (1 << 24)__FLT32X_MAX__ 1.7976931348623157e+308F32xGPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400)ADC_CFGR1_EXTSEL_MASK (0xf << ADC_CFGR1_EXTSEL_SHIFT)__ARM_EABI__ 1INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1adc_power_off_asyncADC_ISR_EOSMP (1 << 1)__ARM_FEATURE_DSP 1TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)__QQ_IBIT__ 0__LLACCUM_FBIT__ 31__UINTMAX_TYPE__ long long unsigned intDESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 0x14)__USQ_IBIT__ 0adc_is_calibratingstops__UINT_LEAST32_TYPE__ long unsigned intADC_TR3(adc) MMIO32((adc) + 0x28)ADC_CFGR1_OVRMOD (1 << 12)__ARM_FEATURE_NUMERIC_MAXMIN__INTMAX_TYPE__ long long int__GCC_ATOMIC_INT_LOCK_FREE 2TIM16_BASE (PERIPH_BASE_APB2 + 0x4400)INTMAX_MAXDESIG_PACKAGE MMIO16((INFO_BASE + 0x7500))__ARM_ARCH_7EM__ 1__ARM_FEATURE_FP16_SCALAR_ARITHMETIC__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1UINT_FAST64_MAX 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@K!/..010/91+#+0ADC_TR1_HT (0xFFF << ADC_TR1_HT_SHIFT)SCB_BASE (SCS_BASE + 0x0D00)__UHA_FBIT__ 8USB_OTG_FS_BASE (0x50000000U + 0x00000)__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64ADC_SQR3(adc) MMIO32((adc) + 0x38)CORESIGHT_LSR_SLK (1<<1)__GCC_ATOMIC_WCHAR_T_LOCK_FREE 2LCD_BASE (PERIPH_BASE_APB1 + 0x2400)__CHAR_UNSIGNED__ 1USART3_BASE (PERIPH_BASE_APB1 + 0x4800)ADC_CFGR1_EXTEN_MASK (0x3 << 10)__FLT64_HAS_INFINITY__ 1__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GNUC_MINOR__ 2__GCC_DESTRUCTIVE_SIZE 64__LACCUM_EPSILON__ 0x1P-31LK__PTRDIFF_MAX__ 0x7fffffff__ARM_FEATURE_FMA 1__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)__INTMAX_MAX__ 0x7fffffffffffffffLLADC1_BASE (0x50000000U + 0x40000)__FLT64_DECIMAL_DIG__ 17WINT_MIN __WINT_MIN__INT_FAST64_MAXOPAMP_BASE (PERIPH_BASE_APB1 + 0x7800)__ATOMIC_CONSUME 1__ULACCUM_FBIT__ 32__WCHAR_MAX__ 0xffffffffUADC_CFGR1_EXTSEL_VAL(x) ((x) << ADC_CFGR1_EXTSEL_SHIFT)LIBOPENCM3_ADC_COMMON_V2_H INT64_MAX __INT64_MAX__INTMAX_MIN__SIZEOF_LONG_LONG__ 8__DBL_MAX_10_EXP__ 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4321I2C3_BASE (PERIPH_BASE_APB1 + 0x5c00)SYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000)__SQ_FBIT__ 31DWT_BASE (PPBI_BASE + 0x1000)INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)__TQ_IBIT__ 0__UHQ_FBIT__ 16ADC_CALFACT(adc) MMIO32((adc) + 0xB4)__FLT64_MIN_EXP__ (-1021)ADC_DIFSEL(adc) MMIO32((adc) + 0xB0)__PTRDIFF_WIDTH__ 32ADC_SQR1_SQ2_SHIFT 12ADC_CCR_TSEN (1 << 23)adc_set_sample_time__UINT_FAST8_MAX__ 0xffffffffUUINT16_C(c) __UINT16_C(c)__LACCUM_IBIT__ 32ADC_OFR1(adc) MMIO32((adc) + 0x60)__INT_FAST16_WIDTH__ 32INTMAX_C__VERSION__ "12.2.1 20221205"__VFP_FP__ 1__LLFRACT_MIN__ (-0.5LLR-0.5LLR)INT_FAST8_MAX__UINT_FAST16_MAX__ 0xffffffffU__INTPTR_MAX__ 0x7fffffffINT64_C(c) __INT64_C(c)ADC_SMPR_SMP_24DOT5CYC 0x3ADC_SMPR2(adc) MMIO32((adc) + 0x18)__GCC_IEC_559_COMPLEX 0PERIPH_BASE (0x40000000U)ADC_CFGR1_JDISCEN (1 << 20)WCHAR_MAX __WCHAR_MAX____FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX__ADC_CFGR1_EXTSEL_SHIFT 6__UINT_LEAST8_TYPE__ unsigned charADC_CR_JADSTP (1 << 5)ADC_SQR4_SQ16_SHIFT 6__ACCUM_FBIT__ 15PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)__UACCUM_IBIT__ 16long intUINT8_MAXIWDG_BASE (PERIPH_BASE_APB1 + 0x3000)SIZE_MAX __SIZE_MAX__ADC_TR1_LT_SHIFT 0__INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17ADC_JDR4(adc) MMIO32((adc) + 0x8C)__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1__FLT32X_EPSILON__ 2.2204460492503131e-16F32xADC_CR_JADSTART (1 << 3)NVIC_BASE (SCS_BASE + 0x0100)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32USART2_BASE (PERIPH_BASE_APB1 + 0x4400)__UINTMAX_C(c) c ## ULL__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed char__GCC_ATOMIC_BOOL_LOCK_FREE 2BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON__ADC_SMPR_SMP_92DOT5CYC 0x5__FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX____THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRshort unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)BIT7 (1<<7)BIT17 (1<<17)__FLT32X_MIN_10_EXP__ (-307)UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)length__DBL_IS_IEC_60559__ 2__UINT_FAST32_MAX__ 0xffffffffU__DEC_EVAL_METHOD__ 2__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4LIBOPENCM3_ADC_COMMON_V2_MULTI_H ADC_CFGR1_AWD1SGL (1 << 22)ADC_TR2(adc) MMIO32((adc) + 0x24)__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32__FLT32X_MIN_EXP__ (-1021)DMA1_BASE (PERIPH_BASE_AHB1 + 0x0000)ADC_IER_AWD1IE (1 << 7)GNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsBIT27 (1<<27)TIM1_BASE (PERIPH_BASE_APB2 + 0x2C00)__UTA_FBIT__ 64INTMAX_C(c) __INTMAX_C(c)__FLT_DECIMAL_DIG__ 9__thumb__ 1__INT_LEAST32_MAX__ 0x7fffffffLLIBOPENCM3_MEMORYMAP_COMMON_H signed charuint8_tINT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)INT32_C(c) __INT32_C(c)__GNUC_STDC_INLINE__ 1__FRACT_FBIT__ 15ADC_CFGR1_RES_12_BIT (0x0 << 3)__LLACCUM_EPSILON__ 0x1P-31LLK__GNUC_PATCHLEVEL__ 1__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2PTRDIFF_MIN__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)ADC_SMPR_SMP_247DOT5CYC 0x6UINTPTR_MAX __UINTPTR_MAX____ARM_ARCH_PROFILE 77GPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000)__FLT64_MAX_10_EXP__ 308GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400)MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINSDMMC1_BASE (PERIPH_BASE_APB2 + 0x2800)__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)__FRACT_MAX__ 0X7FFFP-15RTIM3_BASE (PERIPH_BASE_APB1 + 0x0400)INT_LEAST32_MAX __INT_LEAST32_MAX__ADC_IER_AWD2IE (1 << 8)__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5ADC_CHANNEL_VBAT 18__UINT16_MAX__ 0xffff__TQ_FBIT__ 127__USQ_FBIT__ 32INT_FAST16_MIN__thumb2__ 1__ULLACCUM_FBIT__ 32FMC_QUADSPI_BASE (0xA0000000U)ADC_CFGR1_JAUTO (1 << 25)INT_FAST32_MIN (-INT_FAST32_MAX - 1)__STRICT_ANSI__ 1FMC3_BANK_BASE (0x80000000U)UINT_LEAST8_MAXUINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)TIM8_BASE (PERIPH_BASE_APB2 + 0x3400)__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__ADC_SMPR_SMP_47DOT5CYC 0x4ADC_CFGR1_AWD1CH (0x1F << ADC_CFGR1_AWD1CH_SHIFT)__USA_IBIT__ 16ADC_SQR3_SQ11_SHIFT 6__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1PTRDIFF_MIN (-PTRDIFF_MAX - 1)USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6c00)__UINT_FAST64_TYPE__ long long unsigned intDESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 0x14)DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7590)__FLT_MIN__ 1.1754943508222875e-38Freg32_3__HA_FBIT__ 7__FDPIC____UFRACT_MIN__ 0.0URADC_CFGR1_JQM (1 << 21)__UINT32_C(c) c ## UL__FLT32_IS_IEC_60559__ 2ADC_CFGR1_ALIGN (1 << 5)ADC_CCR_VREFEN (1 << 22)GPIO_PORT_G_BASE (PERIPH_BASE_AHB2 + 0x1800)INT_FAST64_MIN__USFRACT_IBIT__ 0__INT32_C(c) c ## L__LDBL_EPSILON__ 2.2204460492503131e-16LADC_CR_ADCALDIF (1 << 30)__USFRACT_MIN__ 0.0UHRTSC_BASE (PERIPH_BASE_AHB1 + 0x4000)__ARM_NEON__UINT8_MAX__ 0xffADC_SQR2_SQ5_SHIFT 0__LDBL_MAX_EXP__ 1024ADC_IER_EOSIE (1 << 3)LIBOPENCM3_MEMORYMAP_H ADC_CFGR1_EXTEN_RISING_EDGE (0x1 << 10)__DBL_HAS_DENORM__ 1DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)QUADSPI_BASE (0xa0001000U)__DA_FBIT__ 31__GXX_ABI_VERSION 1017GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0c00)__INT_LEAST16_MAX__ 0x7fffADC_SMPR_SMP_640DOT5CYC 0x7__FLT_DENORM_MIN__ 1.4012984643248171e-45F__ULLACCUM_EPSILON__ 0x1P-32ULLKINT_LEAST8_MAX __INT_LEAST8_MAX__TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)__UACCUM_MIN__ 0.0UK__FLT_EPSILON__ 1.1920928955078125e-7FADC_IER_EOCIE (1 << 2)__ARM_ARCH_ISA_THUMB__ARM_FEATURE_MATMUL_INT8__UINT8_TYPE__ unsigned charLIBOPENCM3_CM3_MEMORYMAP_H __GCC_ATOMIC_SHORT_LOCK_FREE 2ADC_OFR4(adc) MMIO32((adc) + 0x6C)__USACCUM_FBIT__ 8ADC_CR_ADVREGEN (1 << 28)__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1ADC_CFGR1(adc) MMIO32((adc) + 0x0C)__LACCUM_FBIT__ 31SCS_BASE (PPBI_BASE + 0xE000)SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)__FLT32_HAS_QUIET_NAN__ 1I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)__LDBL_HAS_INFINITY__ 1__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))__FLT32X_MAX_10_EXP__ 308__ARM_ARCH_EXT_IDIV__ 1bool _BoolUINTMAX_MAX __UINTMAX_MAX____SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffBBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)ADC_IER(adc) MMIO32((adc) + 0x04)__FP_FAST_FMAF 1__FLT32X_IS_IEC_60559__ 2PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)ADC_CR_ADSTART (1 << 2)LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))FIREWALL_BASE (PERIPH_BASE_APB2 + 0x1C00)ADC_SMPR_SMP_2DOT5CYC 0x0ADC_CR_ADCAL (1 << 31)__INT_LEAST16_WIDTH__ 16SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)__ARM_FEATURE_FP16_FMLINT16_MIN (-INT16_MAX - 1)__USFRACT_EPSILON__ 0x1P-8UHR__WINT_MAX__ 0xffffffffU__USFRACT_FBIT__ 8CORESIGHT_LSR_SLI (1<<0)__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX 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(PERIPH_BASE_APB2 + 0x0200)SIZE_MAX__UINT_FAST8_TYPE__ unsigned int__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RBIT24 (1<<24)ADC_SMPR_SMP_6DOT5CYC 0x1__INT32_MAX__ 0x7fffffffLUINTMAX_MAXADC_ISR_JEOS (1 << 6)BIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_BF16_VECTOR_ARITHMETICINFO_BASE (0x1fff0000U)PPBI_BASE (0xE0000000U)__FLT32_MANT_DIG__ 24INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN__INT8_MAX __INT8_MAX__BIT28 (1<<28)ADC_JDR1(adc) MMIO32((adc) + 0x80)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2__DBL_MAX_EXP__ 1024__ATOMIC_RELEASE 3ADC_SQRx_SQx_MASK 0x1fUINT_FAST8_MAX__FLT_MANT_DIG__ 24__UDQ_IBIT__ 0__INT_LEAST32_TYPE__ long int__OPTIMIZE_SIZE__ 1__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UK__FLT64_NORM_MAX__ 1.7976931348623157e+308F64UINTPTR_MAX__LDBL_DENORM_MIN__ 4.9406564584124654e-324LADC_TR1_LT (0xFFF << ADC_TR1_LT_SHIFT)__INT64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_SAT 1ADC_CFGR1_DISCNUM_SHIFT 17__ULLFRACT_IBIT__ 0MMIO16(addr) (*(volatile uint16_t *)(addr))ADC_IER_JEOCIE (1 << 5)AES_BASE (0x50000000U + 0x60000)DAC_BASE (PERIPH_BASE_APB1 + 0x7400)__GNUC__ 12BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)ADC_ISR_AWD1 (1 << 7)WCHAR_MAX__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0UUART5_BASE (PERIPH_BASE_APB1 + 0x5000)__UQQ_IBIT__ 0CORESIGHT_LSR_OFFSET 0xfb4__GCC_ATOMIC_LONG_LOCK_FREE 2__ULACCUM_MIN__ 0.0ULKADC_IER_ADRDYIE (1 << 0)__LDBL_MAX__ 1.7976931348623157e+308L__ARM_ARCH 7__FLT_RADIX__ 2BIT3 (1<<3)long long intCORESIGHT_LAR_KEY 0xC5ACCE55__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAXchannel__LDBL_HAS_QUIET_NAN__ 1ADC_CCR(adc) MMIO32((adc) + 0x300 + 0x8)__LONG_LONG_WIDTH__ 64BIT6 (1<<6)ADC_IER_JQOVFIE (1 << 10)__UINT_FAST64_MAX__ 0xffffffffffffffffULL__ARM_FP__HA_IBIT__ 8__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1BIT9 (1<<9)__FLT32X_MIN__ 2.2250738585072014e-308F32xINTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024UINT16_MAXPERIPH_BASE_AHB2 (0x48000000U)__FLT64_MIN__ 2.2250738585072014e-308F64ADC_SQR1_L_SHIFT 0__INTMAX_C(c) c ## LLADC_CR(adc) MMIO32((adc) + 0x08)__ARM_ARCH_PROFILE__INT64_TYPE__ long long int__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4ADC_SQR1_L_MASK 0xfCRS_BASE (PERIPH_BASE_APB1 + 0x6000)__UFRACT_MAX__ 0XFFFFP-16UR__ARM_FEATURE_LDREXINT64_MAXFPB_BASE (PPBI_BASE + 0x2000)INT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0STIR_BASE (SCS_BASE + 0x0F00)__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__ADC_IER_OVRIE (1 << 4)TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)ADC_ISR_AWD3 (1 << 9)ID_BASE (SCS_BASE + 0x0FD0)SYS_TICK_BASE (SCS_BASE + 0x0010)__UFRACT_FBIT__ 16FMC_BASE (0xa0000000U)__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)__LDBL_MAX_10_EXP__ 308__INT_FAST32_TYPE__ intunsigned int__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1__USACCUM_IBIT__ 8ITM_BASE (PPBI_BASE + 0x0000)ST_VREFINT_CAL MMIO16((INFO_BASE + 0x75aa))__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UK__UTA_IBIT__ 64__FLT_EVAL_METHOD__ 0__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32DFSDM_BASE (PERIPH_BASE_APB2 + 0x6000)RCC_BASE (PERIPH_BASE_AHB1 + 0x1000)LIBOPENCM3_ADC_H __UQQ_FBIT__ 8ADC_TR1_HT_VAL(x) (((x) & ADC_TR1_HT_MASK) << ADC_TR1_HT_SHIFT)INT16_C__ARM_FP16_ARGS__GCC_IEC_559 0INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX____LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4__STDC__ 1__ARM_FEATURE_IDIV 1__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__DBGMCU_BASE (PPBI_BASE + 0x00042000)ADC_CFGR1_AUTDLY (1 << 14)__ARM_FEATURE_COPROC 15ADC_IER_EOSMPIE (1 << 1)UINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"INT8_MINPERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)__LDBL_MIN_10_EXP__ (-307)ADC_CFGR1_EXTEN_FALLING_EDGE (0x2 << 10)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1__GCC_ATOMIC_CHAR_LOCK_FREE 2ADC_CFGR1_EXTEN_DISABLED (0x0 << 10)__LFRACT_EPSILON__ 0x1P-31LRFMC1_BANK_BASE (0x60000000U)STM32L4 1ADC_TR1_LT_MASK 0xFFF__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX____FLT32X_NORM_MAX__ 1.7976931348623157e+308F32x__arm__ 1__FLT32_MIN_10_EXP__ (-37)MMIO64(addr) (*(volatile uint64_t *)(addr))__ARM_FP16_FORMAT_ALTERNATIVE__LDBL_NORM_MAX__ 1.7976931348623157e+308LINTPTR_MINDESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)INT16_MAX __INT16_MAX____BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)__TA_IBIT__ 64__ARM_FEATURE_QRDMX__ARM_ARCH_ISA_THUMB 2__LONG_LONG_MAX__ 0x7fffffffffffffffLL__WINT_WIDTH__ 32SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN____SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__DBL_MIN_EXP__ (-1021)__LDBL_HAS_DENORM__ 1ADC_SQR2_SQ9_SHIFT 24INT8_MIN (-INT8_MAX - 1)__FLT32_DIG__ 6INT_LEAST16_MAXADC_CFGR1_AWD1CH_SHIFT 26ADC_SQR3_SQ13_SHIFT 18BIT15 (1<<15)ADC_ISR_ADRDY (1 << 0)VREFBUF_BASE (PERIPH_BASE_APB2 + 0x0030)BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1INT32_MAXADC_SQR1(adc) MMIO32((adc) + 0x30)__ACCUM_MIN__ (-0X1P15K-0X1P15K)__ARM_FEATURE_CRYPTOUART4_BASE (PERIPH_BASE_APB1 + 0x4c00)ADC_OFR2(adc) MMIO32((adc) + 0x64)BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__FRACT_IBIT__ 0UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234__FLT_NORM_MAX__ 3.4028234663852886e+38Flong long unsigned int__FLT_MIN_10_EXP__ (-37)GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000)__ULACCUM_IBIT__ 32__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__PTRDIFF_TYPE__ int__APCS_32__ 1__DQ_FBIT__ 63INT_LEAST64_MAX__SACCUM_IBIT__ 8reg32__UHQ_IBIT__ 0TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)INT_LEAST8_MINBIT29 (1<<29)__INT_FAST16_TYPE__ intINT64_C__ULFRACT_MAX__ 0XFFFFFFFFP-32ULR__UINT_LEAST16_TYPE__ short unsigned int__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned intADC_IER_JEOSIE (1 << 6)__FLT32X_DIG__ 15__UTQ_FBIT__ 128ADC_CFGR1_RES_MASK (0x3 << 3)__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffffADC_ISR_EOC (1 << 2)DMA2_BASE (PERIPH_BASE_AHB1 + 0x0400)PTRDIFF_MAX __PTRDIFF_MAX____SIZEOF_SHORT__ 2UINT_FAST16_MAX__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKUINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULR__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intADC_CSR(adc) MMIO32((adc) + 0x300 + 0x0)WCHAR_MINADC_SQR4(adc) MMIO32((adc) + 0x3C)BEGIN_DECLS ADC_CR_ADEN (1 << 0)__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15../common/adc_common_v2_multi.c__FLT32X_MAX__ 1.7976931348623157e+308F32xGPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400)ADC_CFGR1_EXTSEL_MASK (0xf << ADC_CFGR1_EXTSEL_SHIFT)__ARM_EABI__ 1INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1ADC_CFGR1_DMAEN (1 << 0)ADC_ISR_EOSMP (1 << 1)__ARM_FEATURE_DSP 1TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)__QQ_IBIT__ 0time__LLACCUM_FBIT__ 31__UINTMAX_TYPE__ long long unsigned int__USQ_IBIT__ 0__UINT_LEAST32_TYPE__ long unsigned intADC_TR3(adc) MMIO32((adc) + 0x28)ADC_CFGR1_OVRMOD (1 << 12)__ARM_FEATURE_NUMERIC_MAXMIN__INTMAX_TYPE__ long long int__GCC_ATOMIC_INT_LOCK_FREE 2TIM16_BASE (PERIPH_BASE_APB2 + 0x4400)INTMAX_MAXDESIG_PACKAGE MMIO16((INFO_BASE + 0x7500))__ARM_ARCH_7EM__ 1__ARM_FEATURE_FP16_SCALAR_ARITHMETIC__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1TIM17_BASE (PERIPH_BASE_APB2 + 0x4800)__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CADC_SQR1_SQ4_SHIFT 24ADC_SQR2_SQ6_SHIFT 6INT64_MIN__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intUINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRADC_OFR3(adc) MMIO32((adc) + 0x68)ADC3 ADC3_BASE/build/libopencm3/lib/stm32/l4__SIZEOF_SIZE_T__ 4__UINT64_TYPE__ long long unsigned int__INT64_C(c) c ## LLUSART1_BASE (PERIPH_BASE_APB2 + 0x3800)USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x6800)TPIU_BASE (PPBI_BASE + 0x40000)ADC_SQR2_SQ8_SHIFT 18__LDBL_MIN__ 2.2250738585072014e-308L__ARM_FEATURE_CDE__ACCUM_IBIT__ 16CORESIGHT_LAR_OFFSET 0xfb0EXTI_BASE (PERIPH_BASE_APB2 + 0x0400)ADC_CDR(adc) MMIO32((adc) + 0x300 + 0xc)FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000)short intRNG_BASE (0x50000000U + 0x60800)__UINT16_C(c) cBIT31 (1<<31)__UDA_IBIT__ 32ADC_AWD2CR(adc) MMIO32((adc) + 0xA0)UINT_LEAST32_MAXBIT2 (1<<2)__ATOMIC_RELAXED 0__ARM_FEATURE_COPROCADC1 ADC1_BASE__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53ADC_CFGR2(adc) MMIO32((adc) + 0x10)BIT5 (1<<5)BIT1 (1<<1)INT8_CGPIO_PORT_H_BASE (PERIPH_BASE_AHB2 + 0x1c00)INT_LEAST32_MAX__USES_INITFINI__ 1__DBL_DECIMAL_DIG__ 17ADC_SQR3_SQ12_SHIFT 12BIT8 (1<<8)INT16_C(c) __INT16_C(c)UINT32_MAX__INT16_MAX__ 0x7fffADC_SMPR_SMP_12DOT5CYC 0x2__INT_WIDTH__ 32__ARM_FEATURE_SIMD32 1DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x75e0)__QQ_FBIT__ 7RTC_BASE (PERIPH_BASE_APB1 + 0x2800)__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64LPTIM2_BASE (PERIPH_BASE_APB1 + 0x9400)__ULLACCUM_IBIT__ 32__ULLFRACT_EPSILON__ 0x1P-64ULLRfalse 0ADC_CR_ADDIS (1 << 1)__SIZEOF_WINT_T__ 4__ARM_FEATURE_UNALIGNED 1__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17ADC_JDR3(adc) MMIO32((adc) + 0x88)__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1ADC_CFGR1_JAWD1EN (1 << 24)__FLT32X_HAS_DENORM__ 1__ULLACCUM_MIN__ 0.0ULLK__INT_FAST32_WIDTH__ 32ADC2 ADC2_BASEADC_DR(adc) MMIO32((adc) + 0x40)__ARM_ASM_SYNTAX_UNIFIED__ 1__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODADC_ISR(adc) MMIO32((adc) + 0x00)__ARM_PCS_VFP 1ADC_CHANNEL_VREF 0__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H LPUART1_BASE (PERIPH_BASE_APB1 + 0x8000)INT_LEAST64_MINADC_CFGR1_DMACFG (1 << 1)__GCC_CONSTRUCTIVE_SIZE 64__LLFRACT_IBIT__ 0ADC_CFGR1_DISCNUM_VAL(x) (((x) - 1) << ADC_CFGR1_DISCNUM_SHIFT)uint32_tBIT12 (1<<12)MPU_BASE (SCS_BASE + 0x0D90)__SACCUM_EPSILON__ 0x1P-7HK__GCC_ASM_FLAG_OUTPUTS__ 1ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0x75a8))__ARM_FP 4__UINT_FAST16_TYPE__ unsigned int__UHA_IBIT__ 8__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULK__LDBL_DIG__ 15POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXBIT16 (1<<16)__WINT_MIN__ 0UINT_LEAST16_MINADC_SQR4_SQ15_SHIFT 0ADC_TR1_LT_VAL(x) (((x) & ADC_TR1_LT_MASK) << ADC_TR1_LT_SHIFT)__FLT64_DIG__ 15TIM15_BASE (PERIPH_BASE_APB2 + 0x4000)BIT22 (1<<22)__INT_LEAST8_WIDTH__ 8WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)__INT_LEAST16_TYPE__ short int__DBL_MAX__ ((double)1.7976931348623157e+308L)INT32_MIN__LLFRACT_FBIT__ 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#!:0<Ł /.CAN_IER_ERRIE (1 << 15)CAN_BTR_TS2_6TQ (0x5 << 20)__LACCUM_EPSILON__ 0x1P-31LK__thumb__ 1UINT16_C(c) __UINT16_C(c)__UACCUM_FBIT__ 16__APCS_32__ 1__LFRACT_EPSILON__ 0x1P-31LR__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__RCC_APB1RSTR1_TIM2RST (1 << 0)CAN_RDTxR(can_base,fifo) MMIO32((can_base) + (fifo) + 0x4)CAN_BTR_TS1_SHIFT 16__FLT_NORM_MAX__ 3.4028234663852886e+38FRCC_APB1ENR2 MMIO32(RCC_BASE + RCC_APB1ENR2_OFFSET)__USACCUM_MIN__ 0.0UHK__ARM_FEATURE_MATMUL_INT8RCC_APB1SMENR2_OFFSET 0x7c__FLT32_DIG__ 6__DBL_EPSILON__ ((double)2.2204460492503131e-16L)__FLT32X_MAX__ 1.7976931348623157e+308F32x__UACCUM_IBIT__ 16RCC_APB2ENR_TIM15EN (1 << 16)CAN_RI1R(can_base) CAN_RIxR((can_base), CAN_FIFO1)INTPTR_MIN (-INTPTR_MAX - 1)RCC_CFGR_SWS_MASK 0x3RCC_APB2SMENR_SPI1SMEN (1 << 12)RCC_CCIPR_UARTxSEL_LSE RCC_CCIPR_USARTxSEL_LSE__INT_FAST16_MAX__ 0x7fffffffRCC_AHB2ENR_OTGFSEN (1 << 12)__SIZEOF_SHORT__ 2__FLT64_MANT_DIG__ 53UINT_LEAST16_MAXUINT_LEAST8_MAX __UINT_LEAST8_MAX__UINT_FAST16_MAX __UINT_FAST16_MAX____SIG_ATOMIC_MAX__ 0x7fffffffINT_LEAST16_MIN (-INT_LEAST16_MAX - 1)filter_select_bitCAN_TSR_TERR0 (1 << 3)RCC_CICR MMIO32(RCC_BASE + 0x20)RCC_APB1ENR1_DAC1EN (1 << 29)RCC_APB2ENR MMIO32(RCC_BASE + RCC_APB2ENR_OFFSET)RST_DAC1RCC_APB1SMENR1_PWRSMEN (1 << 28)__ARM_FEATURE_UNALIGNED 1RCC_AHB1SMENR MMIO32(RCC_BASE + RCC_AHB1SMENR_OFFSET)CAN_TSR_TME0 (1 << 26)__USQ_IBIT__ 0__PTRDIFF_MAX__ 0x7fffffffCAN_TSR_RQCP1 (1 << 8)INT64_MIN (-INT64_MAX - 1)RCC_CFGR_PPRE2_DIV16 0x7UINT_FAST32_MAXRCC_APB2ENR_SAI2EN (1 << 22)canportRCC_AHB2RSTR_GPIOFRST (1 << 5)BIT10 (1<<10)UINT_FAST64_MAX__STDC__ 1RCC_APB2SMENR_SDMMC1SMEN (1 << 10)RST_FLASH__ULLFRACT_IBIT__ 0__FLT32_MAX_EXP__ 128__SA_FBIT__ 15RCC_CCIPR_LPTIMxSEL_HSI16 2__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__UDA_FBIT__ 32CAN_BTR_SJW_2TQ (0x1 << 24)RCC_AHB1SMENR_DMA1SMEN (1 << 0)__UINT64_TYPE__ long long unsigned int__DBL_MAX_10_EXP__ 308RCC_APB1ENR2_LPUART1EN (1 << 0)INT_LEAST32_MIN__UINT_FAST64_MAX__ 0xffffffffffffffffULLUART4_BASE (PERIPH_BASE_APB1 + 0x4c00)USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6c00)RCC_PLLCFGR_PLLP (1 << 17)RCC_AHB1SMENR_CRCSMEN (1 << 12)__WCHAR_TYPE__ unsigned int__SA_IBIT__ 16__UDA_IBIT__ 32__ELF__ 1RCC_CIER_HSI48RDYIE (1 << 10)__SIZEOF_LONG__ 4DWT_BASE (PPBI_BASE + 0x1000)__ARM_ARCH 7RCC_CFGR_SWS_SHIFT 2BIT11 (1<<11)RST_CAN1_BoolRCC_AHB2RSTR MMIO32(RCC_BASE + RCC_AHB2RSTR_OFFSET)LIBOPENCM3_MEMORYMAP_H RCC_CR_MSIRANGE_16MHZ 8RCC_APB2RSTR_SDMMC1RST (1 << 10)BIT3 (1<<3)WCHAR_MAXRCC_PLLCFGR_PLLQ_MASK 0x3CAN_MCR_RESET (1 << 15)CAN_RDHxR(can_base,fifo) MMIO32((can_base) + (fifo) + 0xC)RCC_CFGR_SW_HSI16 0x1_STDBOOL_H SIG_ATOMIC_MIN__SHRT_WIDTH__ 16__STRICT_ANSI__ 1WINT_MINRCC_APB2ENR_TIM17EN (1 << 18)__INTPTR_TYPE__ intRST_FMC__DQ_FBIT__ 63__UACCUM_EPSILON__ 0x1P-16UKRCC_APB1SMENR1_LPTIM1SMEN (1 << 31)__INT_FAST16_WIDTH__ 32CAN_MSR_ERRI (1 << 2)RCC_CCIPR_LPTIMxSEL_APB 0__FLT_HAS_INFINITY__ 1RCC_APB1RSTR1_TIM4RST (1 << 2)uint16_tRCC_CICR_PLLRDYC (1 << 5)RCC_APB1ENR1_USART2EN (1 << 17)INT_FAST64_MAX __INT_FAST64_MAX__BIT12 (1<<12)__LLACCUM_IBIT__ 32RCC_APB1RSTR1_PWRRST (1 << 28)lengthRCC_AHB1ENR_TSCEN (1 << 16)__FP_FAST_FMAF32 1CAN_BTR_TS1_12TQ (0xB << 16)RCC_APB1SMENR1_LCDSMEN (1 << 9)RCC_CFGR_MCOPRE_DIV4 2CAN_RF1R_RFOM1 (1 << 5)RCC_CIFR_LSIRDYF (1 << 0)CAN_BTR_TS2_MASK (0x7 << 20)__SFRACT_MIN__ (-0.5HR-0.5HR)__INT_LEAST16_WIDTH__ 16__USFRACT_MIN__ 0.0UHRRCC_APB1SMENR1_USART2SMEN (1 << 17)__INT_LEAST32_TYPE__ long int__DBL_HAS_INFINITY__ 1GPIO_PORT_G_BASE (PERIPH_BASE_AHB2 + 0x1800)BIT13 (1<<13)RCC_CCIPR_USART1SEL_APB 0RCC_APB1RSTR1_I2C3RST (1 << 23)__SHRT_MAX__ 0x7fffRCC_CFGR_PPRE2_NODIV 0x0PTRDIFF_MAX __PTRDIFF_MAX__BIT4 (1<<4)POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)CAN_MCR_NART (1 << 4)__FLT_DIG__ 6__FLT32_HAS_INFINITY__ 1CAN_MSR(can_base) MMIO32((can_base) + 0x004)CAN_TIxR_EXID_SHIFT 3RCC_CSR_MSIRANGE_SHIFT 8__INT_FAST64_MAX__ 0x7fffffffffffffffLLRCC_CFGR_MCO_PLL 0x5CAN_TSR_TERR2 (1 << 19)CAN_MSR_TXM (1 << 8)__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)RCC_APB1RSTR1_CAN1RST (1 << 25)__GCC_ATOMIC_CHAR_LOCK_FREE 2CAN_MSR_WKUI (1 << 3)RCC_BDCR_LSERDY (1 << 1)GNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsRCC_BDCR MMIO32(RCC_BASE + 0x90)RCC_APB2SMENR_TIM8SMEN (1 << 13)__UINT64_MAX__ 0xffffffffffffffffULLRCC_CCIPR_UART5SEL_SHIFT 8__SIZEOF_INT__ 4__ARMEL__ 1__FLT32X_MAX_10_EXP__ 308CAN_IER_FMPIE1 (1 << 4)BIT14 (1<<14)RCC_AHB1ENR MMIO32(RCC_BASE + RCC_AHB1ENR_OFFSET)ITM_BASE (PPBI_BASE + 0x0000)__WCHAR_WIDTH__ 32CAN_IER_FOVIE0 (1 << 3)__SIG_ATOMIC_TYPE__ int__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1RCC_AHB2ENR_AESEN (1 << 16)RCC_APB1RSTR1_TIM6RST (1 << 4)CAN_RDTxR_TIME_MASK (0xFFFF << 16)RCC_CR_MSIRGSEL (1 << 3)RCC_CCIPR_I2CxSEL_APB 0__GCC_ATOMIC_LONG_LOCK_FREE 2__UINT16_C(c) c__PRAGMA_REDEFINE_EXTNAME 1__INT_LEAST64_TYPE__ long long intRCC_CCIPR_UARTxSEL_APB RCC_CCIPR_USARTxSEL_APBLPUART1_BASE (PERIPH_BASE_APB1 + 0x8000)RCC_PLLCFGR_PLLSRC_MASK 0x3maskUINTMAX_MAXRCC_AHB2SMENR_GPIODSMEN (1 << 3)__HAVE_SPECULATION_SAFE_VALUE 1CAN_BTR_TS1_9TQ (0x8 << 16)I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)CAN_TSR_ABRQ2 (1 << 23)UINTMAX_C(c) __UINTMAX_C(c)__QQ_FBIT__ 7__LDBL_DECIMAL_DIG__ 17BIT15 (1<<15)RCC_CFGR_PPRE1_DIV4 0x5__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xINT8_CRCC_CR_MSIRANGE_1MHZ 4RCC_AHB1SMENR_TSCSMEN (1 << 16)RCC_APB2RSTR_USART1RST (1 << 14)BIT5 (1<<5)USB_OTG_FS_BASE (0x50000000U + 0x00000)__BIGGEST_ALIGNMENT__ 8__ARM_ARCH__UINT8_TYPE__ unsigned charRCC_AHB2RSTR_GPIOARST (1 << 0)RCC_CFGR_STOPWUCK_HSI16 (1 << 15)__FLT32_MIN_10_EXP__ (-37)CAN_IER_FFIE1 (1 << 5)RCC_CSR_MSIRANGE_8MHZ 7RCC_APB1ENR1_UART4EN (1 << 19)__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLK__FLT32_NORM_MAX__ 3.4028234663852886e+38F32CAN_BTR_SJW_MASK (0x3 << 24)__INT_LEAST16_MAX__ 0x7fffRCC_CIER_PLLRDYIE (1 << 5)CAN_TDTxR_TGT (1 << 5)RCC_CICR_PLLSAI2RDYC (1 << 7)CAN_TSR_ALST0 (1 << 2)CAN_TDTxR_TIME_MASK (0xFFFF << 15)RCC_CR_PLLON (1 << 24)BIT16 (1<<16)CAN_BTR_TS2_5TQ (0x4 << 20)__UINT16_TYPE__ short unsigned intRCC_AHB2SMENR_GPIOFSMEN (1 << 5)CAN_ESR_EPVF (1 << 1)CAN_TSR_TXOK0 (1 << 1)RCC_APB2RSTR_SYSCFGRST (1 << 0)CAN_TSR_TERR1 (1 << 11)__ULLFRACT_FBIT__ 64RCC_CFGR_MCOPRE_DIV8 3RST_DMA1RST_DMA2MMIO8(addr) (*(volatile uint8_t *)(addr))__FLT32X_HAS_INFINITY__ 1FMC_BASE (0xa0000000U)CAN_BTR_TS2_8TQ (0x7 << 20)RCC_BDCR_LSEDRV_MASK 0x3LIBOPENCM3_CM3_MEMORYMAP_H __INT8_C(c) c__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)INFO_BASE (0x1fff0000U)__ARM_EABI__ 1RCC_PLLCFGR_PLLR_DIV4 1RCC_AHB2SMENR_GPIOASMEN (1 << 0)UINT64_C(c) __UINT64_C(c)RST_TIM15RST_TIM16__FLT32_EPSILON__ 1.1920928955078125e-7F32INT_LEAST8_MAX __INT_LEAST8_MAX__false 0__FLT_MAX_EXP__ 128RCC_AHB2ENR_GPIOBEN (1 << 1)__INT64_MAX__ 0x7fffffffffffffffLLBIT17 (1<<17)__ATOMIC_SEQ_CST 5RCC_APB1SMENR1_TIM7SMEN (1 << 5)DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7590)RCC_CR MMIO32(RCC_BASE + 0x00)CAN_TSR_LOW1 (1 << 30)__FLT32X_MAX_EXP__ 1024SDMMC1_BASE (PERIPH_BASE_APB2 + 0x2800)__FLT32_MANT_DIG__ 24RCC_ICSCR_MSICAL_MASK 0xffCAN_FiR1(can_base,bank) MMIO32((can_base) + 0x240 + ((bank) * 0x8) + 0x0)__UINT_FAST8_TYPE__ unsigned intRCC_BDCR_RTCSEL_SHIFT 8CAN_IER_SLKIE (1 << 17)__UTA_FBIT__ 64DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)__DBL_DIG__ 15INTPTR_MAX __INTPTR_MAX__RCC_AHB1SMENR_DMA2SMEN (1 << 1)__DECIMAL_DIG__ 17CAN_FIFO1 0x1C0INT_FAST16_MININT_FAST8_MAX __INT_FAST8_MAX__RCC_CFGR_HPRE_MASK 0xf__ARM_PCS_VFP 1DESIG_PACKAGE MMIO16((INFO_BASE + 0x7500))PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)__GCC_IEC_559_COMPLEX 0UINT64_CRCC_APB1ENR1_LPTIM1EN (1 << 31)RCC_PLLCFGR_PLLP_DIV17 RCC_PLLCFGR_PLLPBIT18 (1<<18)__ARM_FP16_FORMAT_IEEE__LFRACT_IBIT__ 0RCC_CCIPR_SAI1SEL_SHIFT 22__USER_LABEL_PREFIX__ RCC_PLLCFGR_PLLM_SHIFT 0x4RCC_APB1RSTR1_SPI3RST (1 << 15)RCC_CIFR_PLLRDYF (1 << 5)CAN_BTR_SJW_4TQ (0x3 << 24)INT64_MAX __INT64_MAX____QQ_IBIT__ 0CAN_MCR_RFLM (1 << 3)can_filter_initRCC_AHB3ENR_FMCEN (1 << 0)UINT_LEAST64_MAXRST_PWRSPI2_BASE (PERIPH_BASE_APB1 + 0x3800)__DBL_MIN__ ((double)2.2250738585072014e-308L)RCC_CFGR_STOPWUCK_MSI (0 << 15)__INT_FAST8_MAX__ 0x7fffffffRCC_APB2SMENR_SYSCFGSMEN (1 << 0)RCC_CR_PLLSAI2ON (1 << 28)__INT_FAST8_WIDTH__ 32RCC_CCIPR_I2CxSEL_HSI16 2RCC_AHB3SMENR_OFFSET 0x70CAN_IER_LECIE (1 << 11)__LDBL_MAX__ 1.7976931348623157e+308LINT_FAST32_MAXRCC_APB1SMENR1 MMIO32(RCC_BASE + RCC_APB1SMENR1_OFFSET)CAN_IER_FFIE0 (1 << 2)CAN_BTR_TS1_2TQ (0x1 << 16)__FLT32_MIN_EXP__ (-125)ST_VREFINT_CAL MMIO16((INFO_BASE + 0x75aa))CORESIGHT_LSR_SLK (1<<1)RCC_BDCR_BDRST (1 << 16)CAN_BTR_TS2_SHIFT 20__UINT32_C(c) c ## UL__LDBL_MIN_EXP__ (-1021)__DBL_MIN_10_EXP__ (-307)IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)BIT7 (1<<7)__UFRACT_MIN__ 0.0URRCC_PLLCFGR_PLLSRC_NONE 0CAN_ESR_LEC_SOFT_ERROR (0x7 << 4)__FLT_MIN_10_EXP__ (-37)RCC_CCIPR_USART2SEL_SHIFT 2RCC_APB1ENR1_TIM7EN (1 << 5)CAN_BTR_TS1_5TQ (0x4 << 16)RCC_APB1SMENR1_OFFSET 0x78INT_LEAST64_MAX __INT_LEAST64_MAX____UDQ_IBIT__ 0AES_BASE (0x50000000U + 0x60000)RCC_CCIPR_USART1SEL_HSI16 2__DBL_MANT_DIG__ 53__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)__PTRDIFF_WIDTH__ 32RCC_AHB1SMENR_OFFSET 0x68__ULLACCUM_MIN__ 0.0ULLKRCC_APB1RSTR1_OFFSET 0x38__SACCUM_IBIT__ 8RCC_APB1SMENR1_TIM2SMEN (1 << 0)INT_FAST64_MAXWWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)RCC_CICR_LSIRDYC (1 << 0)RCC_APB1SMENR1_TIM4SMEN (1 << 2)DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)__ULFRACT_IBIT__ 0RCC_APB2ENR_SAI1EN (1 << 21)__WINT_MAX__ 0xffffffffURCC_CCIPR_LPUART1SEL_MASK 0x3can_filter_id_mask_16bit_init__ARM_FP16_FORMAT_ALTERNATIVERCC_CCIPR_I2C2SEL_SHIFT 14UINTPTR_MAXINT_LEAST32_MIN (-INT_LEAST32_MAX - 1)__USACCUM_FBIT__ 8can_available_mailbox__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1__UINT32_TYPE__ long unsigned intCAN_BTR_TS1_14TQ (0xD << 16)__FLT_EPSILON__ 1.1920928955078125e-7F__USA_IBIT__ 16CAN_ESR_LEC_MASK (0x7 << 4)RCC_PLLCFGR_PLLR_MASK 0x3__UINT8_C(c) cenableRCC_CFGR_SWS_HSE 0x2CAN_RIxR_RTR (1 << 1)RCC_CFGR_MCOPRE_MASK 0x7CAN_BTR_SILM (1 << 31)RST_RNGUINT16_MAX __UINT16_MAX__RCC_APB2RSTR_TIM15RST (1 << 16)CAN_RDTxR_TIME_SHIFT 16__ULLFRACT_MIN__ 0.0ULLRRCC_CCIPR_ADCSEL_NONE 0CAN_FMR(can_base) MMIO32((can_base) + 0x200)unsigned char__ARM_FEATURE_QRDMXCAN_TI0R(can_base) CAN_TIxR(can_base, CAN_MBOX0)RCC_CCIPR_LPTIMxSEL_LSE 3BIT8 (1<<8)__SFRACT_IBIT__ 0CAN_TSR_TXOK2 (1 << 17)__ORDER_LITTLE_ENDIAN__ 1234RCC_CIFR_HSIRDYF (1 << 3)FMC3_BANK_BASE (0x80000000U)RCC_CCIPR_USARTxSEL_APB 0RCC_APB1ENR1_CAN1EN (1 << 25)RCC_PLLCFGR_PLLQ_DIV4 1can_resetRCC_APB2SMENR_OFFSET 0x80RCC_AHB1SMENR_SRAM1SMEN (1 << 9)RCC_CR_PLLSAI1RDY (1 << 27)__DBL_MAX_EXP__ 1024LIBOPENCM3_CAN_H __ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULK__LLFRACT_IBIT__ 0__UINT_LEAST16_MAX__ 0xffff__SIZE_WIDTH__ 32../can.c__ARM_FEATURE_FP16_FML__ULFRACT_FBIT__ 32RCC_APB1RSTR1_TIM3RST (1 << 1)BIT2 (1<<2)__SIZEOF_SIZE_T__ 4RCC_CCIPR_CLK48SEL_PLL 2CAN_TDT1R(can_base) CAN_TDTxR((can_base), CAN_MBOX1)RCC_AHB2ENR_ADCEN (1 << 13)CAN_TI1R(can_base) CAN_TIxR(can_base, CAN_MBOX1)INT_LEAST16_MAX __INT_LEAST16_MAX____UINT_LEAST64_MAX__ 0xffffffffffffffffULLRCC_APB1SMENR1_WWDGSMEN (1 << 11)RCC_CCIPR_USART1SEL_LSE 3RCC_CCIPR_LPUART1SEL_SYS 1NVIC_BASE (SCS_BASE + 0x0100)__SFRACT_FBIT__ 7DMA2_BASE (PERIPH_BASE_AHB1 + 0x0400)RCC_CSR_RMVF (1 << 23)__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32RCC_CSR_OBLRSTF (1 << 25)PTRDIFF_MIN (-PTRDIFF_MAX - 1)CAN_ESR_LEC_STUFF_ERROR (0x1 << 4)__DBL_DECIMAL_DIG__ 17__SIZEOF_LONG_LONG__ 8FIREWALL_BASE (PERIPH_BASE_APB2 + 0x1C00)SIZE_MAXRCC_CR_MSIRANGE_200KHZ 1WCHAR_MAX __WCHAR_MAX__RCC_AHB1RSTR_FLASHRST (1 << 8)__FLT32_DECIMAL_DIG__ 9GPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000)CAN_RF1R_FMP1_MASK (0x3 << 0)BIT9 (1<<9)RCC_AHB1RSTR_CRCRST (1 << 12)RCC_CR_MSIRANGE_SHIFT 4UINT8_CRCC_CR_HSIKERON (1 << 9)__WINT_TYPE__ unsigned intrdhxrUINT_LEAST32_MAX __UINT_LEAST32_MAX__RCC_CFGR_MCO_MSI 0x2SCB_BASE (SCS_BASE + 0x0D00)/build/libopencm3/lib/stm32/l4loopbackRCC_APB2ENR_SPI1EN (1 << 12)RCC_PLLCFGR_PLLSRC_HSI16 2RCC_AHB3SMENR_FMCSMEN (1 << 0)CAN_ESR_LEC_DOM_ERROR (0x5 << 4)__INT16_MAX__ 0x7fff__ULACCUM_EPSILON__ 0x1P-32ULK__FLT_MANT_DIG__ 24RCC_AHB2ENR_RNGEN (1 << 18)CAN_BTR_TS2_7TQ (0x6 << 20)__ULACCUM_FBIT__ 32TIM1_BASE (PERIPH_BASE_APB2 + 0x2C00)__FLT64_HAS_QUIET_NAN__ 1wait_ackRCC_BDCR_RTCSEL_NONE 0tdlxr__ARM_ARCH_PROFILE 77fifo__ULACCUM_IBIT__ 32RCC_CFGR_PPRE2_DIV4 0x5__ARM_FEATURE_COPROC 15BIT20 (1<<20)CAN_ESR_REC_MASK (0xF << 24)STM32L4 1__INT_LEAST8_MAX__ 0x7f__FLT_MIN_EXP__ (-125)RCC_ICSCR_HSITRIM_SHIFT 24__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__RCC_CFGR_PPRE2_SHIFT 11CAN_TDLxR(can_base,mbox) MMIO32((can_base) + (mbox) + 0x8)__UINT64_C(c) c ## ULL__FRACT_IBIT__ 0__FLT_RADIX__ 2__USA_FBIT__ 16__LDBL_IS_IEC_60559__ 2__FLT32X_DIG__ 15UINT_FAST8_MAX __UINT_FAST8_MAX____LDBL_EPSILON__ 2.2204460492503131e-16L__ARM_BF16_FORMAT_ALTERNATIVE__FLT_EVAL_METHOD_TS_18661_3__ 0__SQ_FBIT__ 31__UINTMAX_MAX__ 0xffffffffffffffffULLRCC_APB1ENR1_OPAMPEN (1 << 30)__ACCUM_EPSILON__ 0x1P-15KRCC_PLLSAI2_CFGR MMIO32(RCC_BASE + 0x14)RCC_CCIPR_USART1SEL_MASK 0x3__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LKRCC_CFGR_HPRE_DIV16 0xbCAN_RIxR_EXID_SHIFT 3CAN_TSR_ALST2 (1 << 18)RCC_CR_MSIRANGE_400KHZ 2RCC_PLLCFGR_PLLQEN (1 << 20)RCC_CCIPR_UART4SEL_SHIFT 6INT_FAST32_MIN__FRACT_EPSILON__ 0x1P-15R__FLT32X_MANT_DIG__ 53RCC_PLLCFGR_PLLQ_DIV6 2__GCC_ATOMIC_INT_LOCK_FREE 2RST_SDMMC1BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)RCC_PLLCFGR_PLLSRC_HSE 3CAN_BTR_TS1_10TQ (0x9 << 16)__INT_WIDTH__ 32I2C3_BASE (PERIPH_BASE_APB1 + 0x5c00)CAN_BTR_TS2_4TQ (0x3 << 20)RCC_CFGR_SW_SHIFT 0PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)CAN_RDTxR_FMI_MASK (0xFF << 8)rflmRCC_CFGR_MCO_HSI16 0x3RCC_AHB2ENR_GPIOAEN (1 << 0)CAN_IER_FOVIE1 (1 << 6)__FLT32_IS_IEC_60559__ 2__UDQ_FBIT__ 64__FLT64_DIG__ 15__ARM_NEONRCC_CFGR_MCO_SHIFT 24RCC_AHB2SMENR_AESSMEN (1 << 16)__ARM_ARCH_7EM__ 1__INT16_C(c) cINT_FAST8_MAXRCC_CFGR_PPRE1_NODIV 0x0RCC_APB1SMENR1_TIM3SMEN (1 << 1)BIT22 (1<<22)__FLT32X_DECIMAL_DIG__ 17CAN_BTR_BRP_MASK (0x3FFUL << 0)RCC_CSR_MSIRANGE_2MHZ 5__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2can_filter_id_list_32bit_init__INT16_TYPE__ short intRCC_APB2RSTR_DFSDMRST (1 << 24)RCC_CICR_CSSC (1 << 8)__bool_true_false_are_defined 1RCC_CCIPR_ADCSEL_PLLSAI1R 1__FRACT_MIN__ (-0.5R-0.5R)SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)CAN_MBOX1 0x190SWPMI1_BASE (PERIPH_BASE_APB1 + 0x8800)RCC_CCIPR_LPUART1SEL_SHIFT 10RCC_CCIPR_I2C1SEL_SHIFT 12CAN_TDH0R(can_base) CAN_TDHxR((can_base), CAN_MBOX0)RCC_BDCR_LSCOSEL (1 << 25)RCC_PLLCFGR_PLLR_DIV6 2CAN_MSR_RX (1 << 11)_GCC_STDINT_H CAN_BTR_TS1_4TQ (0x3 << 16)RST_SAI1RST_SAI2RCC_CFGR_SW_MSI 0x0RCC_CCIPR_USARTxSEL_HSI16 2RCC_CIER_MSIRDYIE (1 << 2)__UHQ_FBIT__ 16uint8_tRCC_CFGR MMIO32(RCC_BASE + 0x08)INTMAX_MIN (-INTMAX_MAX - 1)mailboxRCC_CFGR_MCO_HSI48 0x8RCC_CFGR_SWS_PLL 0x3RCC_CSR_MSIRANGE_1MHZ 4CAN_BTR_TS1_3TQ (0x2 << 16)RCC_CFGR_MCOPRE_DIV16 4RCC_BDCR_LSEDRV_LOW 0abomCAN_BTR_TS1_7TQ (0x6 << 16)BIT23 (1<<23)QUADSPI_BANK_BASE (0x90000000U)__FP_FAST_FMAF 1RCC_AHB1ENR_FLASHEN (1 << 8)__WCHAR_MIN__ 0UCAN_TSR_TXOK1 (1 << 9)RCC_APB2SMENR_TIM16SMEN (1 << 17)RCC_CIFR MMIO32(RCC_BASE + 0x1c)RCC_CSR_MSIRANGE_MASK 0xfRCC_APB2ENR_FWEN (1 << 7)CAN_BTR_TS1_13TQ (0xC << 16)RCC_APB2ENR_OFFSET 0x60RST_QSPIRCC_CFGR_HPRE_NODIV 0x0__LLFRACT_EPSILON__ 0x1P-63LLR__INT_FAST64_WIDTH__ 64__FRACT_FBIT__ 15CAN_RF0R(can_base) MMIO32((can_base) + 0x00C)RCC_CFGR_PPRE1_DIV8 0x6RCC_PLLCFGR_PLLSRC_MSI 1__INT32_MAX__ 0x7fffffffLCAN_RDTxR_DLC_MASK (0xF << 0)__CHAR_UNSIGNED__ 1RST_I2C2BIT24 (1<<24)CAN_BTR_TS1_16TQ (0xF << 16)__SCHAR_MAX__ 0x7fRCC_CCIPR_SAIxSEL_PLLSAI1P 0INT16_MAX __INT16_MAX__CAN_RF1R_FULL1 (1 << 3)TPIU_BASE (PPBI_BASE + 0x40000)__SACCUM_EPSILON__ 0x1P-7HKCAN_TSR_RQCP0 (1 << 0)RCC_CCIPR_ADCSEL_SHIFT 28DAC_BASE (PERIPH_BASE_APB1 + 0x7400)__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRCAN_BTR(can_base) MMIO32((can_base) + 0x01C)RCC_CR_MSIRANGE_48MHZ 11CAN_RDT0R(can_base) CAN_RDTxR((can_base), CAN_FIFO0)__HA_FBIT__ 7__UACCUM_MIN__ 0.0UKRCC_ICSCR_MSICAL_SHIFT 0INT_LEAST32_MAX __INT_LEAST32_MAX__CAN_RIxR_STID_MASK (0x7FF)RCC_APB1RSTR2 MMIO32(RCC_BASE + RCC_APB1RSTR2_OFFSET)__UFRACT_EPSILON__ 0x1P-16UR__FLT_HAS_QUIET_NAN__ 1CAN_MCR_TXFP (1 << 2)UINT_FAST64_MAX __UINT_FAST64_MAX__BIT25 (1<<25)__FLT32X_NORM_MAX__ 1.7976931348623157e+308F32xRCC_PLLCFGR_PLLP_DIV7 0SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__USART1_BASE (PERIPH_BASE_APB2 + 0x3800)__FLT64_HAS_INFINITY__ 1RCC_AHB2SMENR_SRAM2SMEN (1 << 9)UINTMAX_CRCC_CCIPR_CLK48SEL_MSI 3__SCHAR_WIDTH__ 8__INT32_C(c) c ## L__ORDER_PDP_ENDIAN__ 3412__ATOMIC_ACQUIRE 2RST_USART1RST_USART2__LONG_LONG_MAX__ 0x7fffffffffffffffLL__INT_FAST32_WIDTH__ 32__INT_FAST64_TYPE__ long long int__ACCUM_FBIT__ 15CAN_IER_TMEIE (1 << 0)CAN_TSR_ALST1 (1 << 10)__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_QBIT 1CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)TIM16_BASE (PERIPH_BASE_APB2 + 0x4400)UINT32_C(c) __UINT32_C(c)CAN_FMR_FINIT (1 << 0)RCC_CR_MSION (1 << 0)__SACCUM_MAX__ 0X7FFFP-7HKBIT26 (1<<26)RCC_APB1RSTR1_LCDRST (1 << 9)__LDBL_NORM_MAX__ 1.7976931348623157e+308LRCC_CR_HSIRDY (1 << 10)__ACCUM_IBIT__ 16UINT64_MAX __UINT64_MAX__timestamp__INTMAX_WIDTH__ 64EXTI_BASE (PERIPH_BASE_APB2 + 0x0400)RST_ADC__ARM_FEATURE_LDREX 7CAN_TIxR_IDE (1 << 2)__INT_LEAST64_WIDTH__ 64RCC_AHB2SMENR_GPIOCSMEN (1 << 2)RCC_CIFR_HSI48RDYF (1 << 10)RCC_ICSCR_HSICAL_SHIFT 16INT8_C(c) __INT8_C(c)RCC_CCIPR_USARTxSEL_LSE 3__ARM_32BIT_STATE 1__ATOMIC_RELAXED 0RCC_AHB2SMENR_GPIOESMEN (1 << 4)__LFRACT_MAX__ 0X7FFFFFFFP-31LR__LDBL_MIN__ 2.2250738585072014e-308LRCC_CCIPR_USART1SEL_SHIFT 0RCC_APB1RSTR2_LPTIM2RST (1 << 5)__THUMB_INTERWORK__ 1RCC_AHB2ENR_GPIOHEN (1 << 7)PPBI_BASE (0xE0000000U)CAN_TIxR_STID_SHIFT 21BIT27 (1<<27)__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)CAN_TDL0R(can_base) CAN_TDLxR((can_base), CAN_MBOX0)__FRACT_MAX__ 0X7FFFP-15RRCC_CFGR_HPRE_DIV64 0xc__USQ_FBIT__ 32__GCC_IEC_559 0__FLT_IS_IEC_60559__ 2__FLT32X_EPSILON__ 2.2204460492503131e-16F32xGPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800)RCC_CCIPR_SAI2SEL_SHIFT 24RST_AESCAN_RIxR(can_base,fifo) MMIO32((can_base) + (fifo) + 0x0)MMIO32(addr) (*(volatile uint32_t *)(addr))RCC_CCIPR_I2C3SEL_SHIFT 16RCC_APB1RSTR2_OFFSET 0x3cRCC_AHB1ENR_CRCEN (1 << 12)CAN_TIxR_EXID_MASK (0x1FFFFFF << 3)__SIZE_MAX__ 0xffffffffUCAN_MCR_DBF (1 << 16)can_transmit__ATOMIC_RELEASE 3BIT28 (1<<28)RCC_APB1RSTR1_I2C1RST (1 << 21)__INT_LEAST8_WIDTH__ 8__GNUC__ 12__ARM_FEATURE_COPROCUINTMAX_MAX __UINTMAX_MAX__RCC_ICSCR MMIO32(RCC_BASE + 0x04)__INT_FAST16_TYPE__ intTIM7_BASE (PERIPH_BASE_APB1 + 0x1400)CAN_MBOX2 0x1A0__INT_LEAST32_WIDTH__ 32RCC_AHB1RSTR_TSCRST (1 << 16)__UTQ_IBIT__ 0CAN_FM1R(can_base) MMIO32((can_base) + 0x204)__DBL_IS_IEC_60559__ 2RST_LPTIM1CAN_TDT2R(can_base) CAN_TDTxR((can_base), CAN_MBOX2)__UTA_IBIT__ 64__SIZEOF_WINT_T__ 4CAN_TDH2R(can_base) CAN_TDHxR((can_base), CAN_MBOX2)RCC_AHB1RSTR_DMA2RST (1 << 1)RCC_CFGR_MCOPRE_DIV1 0RCC_CCIPR_LPUART1SEL_HSI16 2__ARM_FEATURE_IDIV 1RCC_APB1RSTR1_USART2RST (1 << 17)CAN_RIxR_STID_SHIFT 21RCC_CCIPR MMIO32(RCC_BASE + 0x88)CAN_TSR(can_base) MMIO32((can_base) + 0x008)__ARM_FEATURE_SAT 1RCC_APB1ENR1_PWREN (1 << 28)__INT_MAX__ 0x7fffffffRCC_CR_MSIPLLEN (1 << 2)__FLT_MAX__ 3.4028234663852886e+38F__INT_LEAST8_TYPE__ signed char__GXX_ABI_VERSION 1017BIT29 (1<<29)INT32_C__LFRACT_FBIT__ 31__ARM_ARCH_ISA_THUMBCAN_MCR_ABOM (1 << 6)CAN_TSR_TME1 (1 << 27)__SIZEOF_WCHAR_T__ 4INTMAX_C__USACCUM_MAX__ 0XFFFFP-8UHK__WINT_MIN__ 0U__INT8_MAX__ 0x7fRCC_AHB2ENR_OFFSET 0x4cRCC_APB2ENR_TIM8EN (1 << 13)__INT_LEAST32_MAX__ 0x7fffffffLRCC_APB1SMENR1_OPAMPSMEN (1 << 30)RCC_CCIPR_USARTxSEL_MASK 0x3__USACCUM_EPSILON__ 0x1P-8UHKRCC_AHB2SMENR_GPIOBSMEN (1 << 1)awumCAN_TDTxR_DLC_SHIFT 0__USFRACT_EPSILON__ 0x1P-8UHRRCC_CFGR_MCOPRE_SHIFT 28__INTMAX_C(c) c ## LLCAN_TSR_ABRQ0 (1 << 7)SAI1_BASE (PERIPH_BASE_APB2 + 0x5400)__UINT_FAST16_MAX__ 0xffffffffU__ARM_ARCH_EXT_IDIV__ 1__UINT_FAST64_TYPE__ long long unsigned intCOMP_BASE (PERIPH_BASE_APB2 + 0x0200)CAN_RDTxR_DLC_SHIFT 0BIT0 (1<<0)RCC_CR_HSION (1 << 8)RCC_BDCR_RTCEN (1 << 15)RCC_CFGR_PPRE1_DIV2 0x4RST_TIM17STIR_BASE (SCS_BASE + 0x0F00)RTC_BASE (PERIPH_BASE_APB1 + 0x2800)RCC_CIER_PLLSAI1RDYIE (1 << 6)RCC_AHB2ENR_GPIOEEN (1 << 4)RCC_CSR_SFTRSTF (1 << 28)RCC_APB2RSTR_SAI1RST (1 << 21)LIBOPENCM3_MEMORYMAP_COMMON_H CAN_BTR_TS1_6TQ (0x5 << 16)__UINT_FAST8_MAX__ 0xffffffffUttcmRCC_CIFR_PLLSAI2RDYF (1 << 7)RCC_CIFR_HSERDYF (1 << 4)__SQ_IBIT__ 0LCD_BASE (PERIPH_BASE_APB1 + 0x2400)RCC_CCIPR_UARTxSEL_SYS RCC_CCIPR_USARTxSEL_SYSINT_FAST16_MIN (-INT_FAST16_MAX - 1)RST_TSC__ARM_FEATURE_SIMD32 1RCC_PLLCFGR_PLLSRC_SHIFT 0__UHQ_IBIT__ 0ST_TSENSE_CAL2_110C MMIO16((INFO_BASE + 0x75ca))RCC_APB2SMENR_TIM15SMEN (1 << 16)RCC_AHB3SMENR_QSPISMEN (1 << 8)fifoid_arrayCAN_MCR_TTCM (1 << 7)RCC_APB1ENR1_TIM6EN (1 << 4)__thumb2__ 1__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1RCC_AHB2ENR MMIO32(RCC_BASE + RCC_AHB2ENR_OFFSET)__LACCUM_FBIT__ 31__ULACCUM_MIN__ 0.0ULKRCC_CFGR_HPRE_SHIFT 4RCC_CR_MSIRANGE_4MHZ 6RCC_CFGR_SW_HSE 0x2RCC_AHB3RSTR_QSPIRST (1 << 8)RCC_CCIPR_CLK48SEL_MASK 0x3RCC_CCIPR_ADCSEL_PLLSAI2R 2RCC_PLLCFGR_PLLN_SHIFT 0x8CAN_BTR_TS1_15TQ (0xE << 16)__LONG_MAX__ 0x7fffffffL__LACCUM_IBIT__ 32VREFBUF_BASE (PERIPH_BASE_APB2 + 0x0030)__FLT64_NORM_MAX__ 1.7976931348623157e+308F64INTPTR_MAXRCC_CICR_HSIRDYC (1 << 3)RCC_PLLCFGR_PLLQ_DIV8 3CAN_RF1R_FOVR1 (1 << 4)INT_FAST16_MAX __INT_FAST16_MAX__RCC_ICSCR_HSICAL_MASK 0xffRCC_CICR_LSECSSC (1 << 9)RCC_PLLPEN (1 << 16)__FLT32X_IS_IEC_60559__ 2RCC_APB1RSTR1_LPTIM1RST (1 << 31)RCC_APB1SMENR1_TIM5SMEN (1 << 3)RCC_CFGR_MCO_HSE 0x4UINT_FAST32_MAX __UINT_FAST32_MAX__RCC_CIER_LSE_CSSIE (1 << 9)UINT32_CTIM2_BASE (PERIPH_BASE_APB1 + 0x0000)short unsigned intRCC_AHB2RSTR_AESRST (1 << 16)signed charRCC_CCIPR_LPTIMxSEL_MASK 0x3RCC_CFGR_PPRE2_MASK 0x7LIBOPENCM3_RCC_H RCC_PLLCFGR_PLLR_DIV8 3RCC_APB2SMENR_SAI2SMEN (1 << 22)BIT6 (1<<6)INTMAX_C(c) __INTMAX_C(c)WINT_MAX __WINT_MAX__CAN_IER(can_base) MMIO32((can_base) + 0x014)DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 0x14)__CHAR_BIT__ 8INTMAX_MINRCC_APB1RSTR1_UART4RST (1 << 19)RCC_CR_MSIRANGE_2MHZ 5CAN_MSR_SAMP (1 << 10)CAN_RF1R(can_base) MMIO32((can_base) + 0x010)RCC_CFGR_SWS_MSI 0x0RCC_CFGR_PPRE1_SHIFT 8RCC_AHB2RSTR_ADCRST (1 << 13)RCC_APB2RSTR_TIM16RST (1 << 17)__ARM_FEATURE_DOTPRODBEGIN_DECLS CAN_TDH1R(can_base) CAN_TDHxR((can_base), CAN_MBOX1)RCC_BDCR_LSESYSDIS (1 << 7)PERIPH_BASE_AHB2 (0x48000000U)CAN_RI0R(can_base) CAN_RIxR((can_base), CAN_FIFO0)__GXX_TYPEINFO_EQUALITY_INLINE 0__FLT64_MIN__ 2.2250738585072014e-308F64__INTPTR_MAX__ 0x7fffffff__ARM_FP16_ARGSRCC_APB2RSTR_TIM8RST (1 << 13)FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000)__GCC_ATOMIC_POINTER_LOCK_FREE 2RCC_CSR_FWRSTF (1 << 24)CAN_MSR_RXM (1 << 9)CAN_TDTxR(can_base,mbox) MMIO32((can_base) + (mbox) + 0x4)__DBL_MAX__ ((double)1.7976931348623157e+308L)RCC_CFGR_MCOPRE_DIV2 1__FLT32_MAX_10_EXP__ 38RST_GPIOARST_GPIOBRST_GPIOCRST_GPIODRST_GPIOERST_GPIOFRST_GPIOGRST_GPIOHITR_BASE (SCS_BASE + 0x0000)INT_LEAST8_MAX__WINT_WIDTH__ 32can_filter_id_mask_32bit_initPERIPH_BASE (0x40000000U)__LDBL_HAS_DENORM__ 1RST_TIM2tdhxrUINT_FAST8_MAXCAN_RDTxR_FMI_SHIFT 8__INT_FAST32_MAX__ 0x7fffffffRST_TIM8RCC_CIFR_CSSF (1 << 8)RCC_APB1ENR1_TIM3EN (1 << 1)__USES_INITFINI__ 1BIT30 (1<<30)__FLT64_MAX_EXP__ 1024RCC_APB1ENR1_LCDEN (1 << 9)RCC_CR_PLLSAI2RDY (1 << 29)RCC_CFGR_PPRE1_DIV16 0x7RCC_CICR_MSIRDYC (1 << 2)__REGISTER_PREFIX__ CAN_MBOX0 0x180nartRCC_BDCR_RTCSEL_LSE 1CAN_ESR_EWGF (1 << 0)__USFRACT_MAX__ 0XFFP-8UHRCAN_FiR2(can_base,bank) MMIO32((can_base) + 0x240 + ((bank) * 0x8) + 0x4)CAN_TIxR_TXRQ (1 << 0)CAN_FMR_CAN2SB_MASK (0x3F << CAN_FMR_CAN2SB_SHIFT)CRS_BASE (PERIPH_BASE_APB1 + 0x6000)RCC_CRRCR MMIO32(RCC_BASE + 0x98)WCHAR_MIN __WCHAR_MIN__CAN_BTR_TS1_MASK (0xF << 16)BIT1 (1<<1)CAN_RF0R_FMP0_MASK (0x3 << 0)RCC_AHB2SMENR_OTGFSSMEN (1 << 12)RCC_AHB2SMENR_RNGSMEN (1 << 18)id_list_mode__ARM_FEATURE_NUMERIC_MAXMINCAN_RDT1R(can_base) CAN_RDTxR((can_base), CAN_FIFO1)RCC_APB1ENR2_SWPMI1EN (1 << 2)RCC_APB1SMENR1_I2C2SMEN (1 << 22)RST_DFSDM__INT_FAST8_TYPE__ intUINT8_C(c) __UINT8_C(c)UINT32_MAXRCC_APB1SMENR1_SPI3SMEN (1 << 15)__ARM_FEATURE_BF16_SCALAR_ARITHMETIC__FLT_MIN__ 1.1754943508222875e-38FRCC_CSR MMIO32(RCC_BASE + 0x94)__STDC_HOSTED__ 1__UINTMAX_C(c) c ## ULLRCC_BDCR_RTCSEL_HSEDIV32 3RST_USBGPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400)can_fifo_release__UACCUM_MAX__ 0XFFFFFFFFP-16UKRCC_CSR_LPWRRSTF (1 << 31)FMC1_BANK_BASE (0x60000000U)RCC_CFGR_HPRE_DIV4 0x9INT_LEAST64_MAXlong intRCC_CFGR_MCO_SYSCLK 0x1CAN_TDHxR(can_base,mbox) MMIO32((can_base) + (mbox) + 0xC)__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)INT16_MAX__DBL_HAS_DENORM__ 1TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1__FLT64_MAX_10_EXP__ 308CAN_ESR_BOFF (1 << 2)__INTPTR_WIDTH__ 32CAN_TSR_ABRQ1 (1 << 15)__PTRDIFF_TYPE__ int__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2CAN_RDLxR(can_base,fifo) MMIO32((can_base) + (fifo) + 0x8)__GNUC_STDC_INLINE__ 1CAN_MSR_INAK (1 << 0)UINT64_MAX__ARM_FPCAN_TSR_LOW2 (1 << 31)RCC_APB2ENR_TIM1EN (1 << 11)RCC_AHB2SMENR_GPIOGSMEN (1 << 6)RCC_CICR_LSERDYC (1 << 1)RCC_CSR_BORRSTF (1 << 27)RCC_CIER_LSERDYIE (1 << 1)RCC_CCIPR_I2CxSEL_MASK 0x3RCC_APB2SMENR MMIO32(RCC_BASE + RCC_APB2SMENR_OFFSET)__UTQ_FBIT__ 128LIBOPENCM3_CM3_COMMON_H RCC_AHB2SMENR MMIO32(RCC_BASE + RCC_AHB2SMENR_OFFSET)RCC_APB1ENR1_I2C2EN (1 << 22)RCC_CCIPR_CLK48SEL_HSI48 0RCC_APB1SMENR1_I2C1SMEN (1 << 21)RCC_CIFR_PLLSAI1RDYF (1 << 6)__ARM_FEATURE_DSP 1CORESIGHT_LAR_KEY 0xC5ACCE55__ARM_FEATURE_CRYPTORCC_CFGR_HPRE_DIV256 0xeCAN_TIxR_RTR (1 << 1)FPB_BASE (PPBI_BASE + 0x2000)RCC_CCIPR_LPTIM2SEL_SHIFT 20CAN_ESR_LEC_FORM_ERROR (0x2 << 4)__FLT32_HAS_DENORM__ 1RCC_CFGR_MCO_MASK 0xfRCC_AHB2RSTR_GPIOHRST (1 << 7)INT32_MIN (-INT32_MAX - 1)__ARM_FEATURE_FP16_SCALAR_ARITHMETICRCC_BDCR_LSEDRV_SHIFT 3__SACCUM_FBIT__ 7__HQ_FBIT__ 15CAN_MSR_INAK_TIMEOUT 0x0000FFFFRCC_CFGR_HPRE_DIV512 0xfuint32_tRCC_APB1SMENR2_LPTIM2SMEN (1 << 5)__LLFRACT_FBIT__ 63__LDBL_DIG__ 15__CHAR32_TYPE__ long unsigned intRCC_APB1SMENR2 MMIO32(RCC_BASE + RCC_APB1SMENR2_OFFSET)SIG_ATOMIC_MIN __SIG_ATOMIC_MIN__RCC_CFGR_SW_PLL 0x3__GCC_ATOMIC_SHORT_LOCK_FREE 2RCC_AHB2ENR_GPIOGEN (1 << 6)CAN_TDL1R(can_base) CAN_TDLxR((can_base), CAN_MBOX1)RCC_AHB1ENR_DMA2EN (1 << 1)__ULFRACT_MAX__ 0XFFFFFFFFP-32ULRRCC_CRRCR_HSI48ON (1 << 0)CAN_TIxR(can_base,mbox) MMIO32((can_base) + (mbox) + 0x0)__SIZEOF_POINTER__ 4RCC_CCIPR_LPUART1SEL_APB 0__GCC_ASM_FLAG_OUTPUTS__ 1CAN_ESR_LEC_CRC_ERROR (0x6 << 4)RCC_APB1SMENR1_CAN1SMEN (1 << 25)RCC_CR_MSIRANGE_32MHZ 10RCC_CFGR_HPRE_DIV128 0xdUINT_LEAST64_MAX __UINT_LEAST64_MAX____UINTMAX_TYPE__ long long unsigned intCAN_RIxR_EXID_MASK (0x1FFFFFFF)RCC_APB2SMENR_TIM17SMEN (1 << 18)can_initCAN_TDTxR_DLC_MASK (0xF << 0)RCC_AHB2RSTR_RNGRST (1 << 18)INT_FAST16_MAXGPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0c00)USART3_BASE (PERIPH_BASE_APB1 + 0x4800)INTPTR_MINRCC_BDCR_LSECSSON (1 << 5)RCC_CR_MSIRANGE_MASK 0xfCAN_IER_EPVIE (1 << 9)RCC_AHB1RSTR MMIO32(RCC_BASE + RCC_AHB1RSTR_OFFSET)long unsigned int__GCC_DESTRUCTIVE_SIZE 64RCC_PLLCFGR_PLLREN (1<<24)RCC_BDCR_LSECSSD (1 << 6)__FINITE_MATH_ONLY__ 0RCC_CCIPR_CLK48SEL_SHIFT 26CAN1 BX_CAN1_BASERCC_CR_PLLRDY (1 << 25)__ULLACCUM_EPSILON__ 0x1P-32ULLK__GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"MMIO64(addr) (*(volatile uint64_t *)(addr))__STDC_VERSION__ 199901L__LFRACT_MIN__ (-0.5LR-0.5LR)PTRDIFF_MAXRCC_CFGR_MCO_NOCLK 0x0RST_OTGFS__LLFRACT_MIN__ (-0.5LLR-0.5LLR)RST_UART4RST_UART5RCC_CCIPR_ADCSEL_MASK 0x3INT64_C(c) __INT64_C(c)__GCC_ATOMIC_LLONG_LOCK_FREE 1RCC_APB2ENR_SDMMC1EN (1 << 10)mask1mask2__ULFRACT_EPSILON__ 0x1P-32ULRRST_TIM1rdlxrRST_TIM3RST_TIM4RST_TIM5RST_TIM6RST_TIM7__LONG_LONG_WIDTH__ 64INT_LEAST64_MINCAN_FFA1R(can_base) MMIO32((can_base) + 0x214)RCC_CFGR_PPRE2_DIV2 0x4RCC_CFGR_MCO_LSI 0x6__VERSION__ "12.2.1 20221205"CAN_FA1R(can_base) MMIO32((can_base) + 0x21C)__FLT64_EPSILON__ 2.2204460492503131e-16F64GPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400)CAN_RDH0R(can_base) CAN_RDHxR((can_base), CAN_FIFO0)__ULLACCUM_FBIT__ 32__LDBL_HAS_QUIET_NAN__ 1RCC_CR_CSSON (1 << 19)__WCHAR_MAX__ 0xffffffffUUART5_BASE (PERIPH_BASE_APB1 + 0x5000)CAN_ESR(can_base) MMIO32((can_base) + 0x018)RCC_BDCR_LSEON (1 << 0)__GCC_HAVE_DWARF2_CFI_ASM 1RCC_APB2ENR_DFSDMEN (1 << 24)__ULLACCUM_IBIT__ 32RCC_APB2SMENR_SAI1SMEN (1 << 21)__LDBL_MANT_DIG__ 53RCC_APB2ENR_USART1EN (1 << 14)CAN_BTR_TS2_2TQ (0x1 << 20)true 1RCC_AHB2RSTR_OFFSET 0x2c__DQ_IBIT__ 0CAN_IER_WKUIE (1 << 16)__FLT64_MAX__ 1.7976931348623157e+308F64RCC_APB2RSTR_SPI1RST (1 << 12)INT_LEAST8_MINRCC_CRRCR_HSI48RDY (1 << 1)CORESIGHT_LSR_SLI (1<<0)__UQQ_IBIT__ 0LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))CAN_TSR_RQCP2 (1 << 16)DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x75e0)__ARM_FEATURE_CDERCC_AHB2ENR_GPIODEN (1 << 3)RCC_CCIPR_USART1SEL_SYS 1__LLACCUM_EPSILON__ 0x1P-31LLKSYS_TICK_BASE (SCS_BASE + 0x0010)RST_USART3RCC_APB1ENR2_LPTIM2EN (1 << 5)__ARM_FEATURE_LDREX__UINT_LEAST32_MAX__ 0xffffffffUL__ACCUM_MIN__ (-0X1P15K-0X1P15K)__ORDER_BIG_ENDIAN__ 4321__ARM_FEATURE_CMSECAN_MSR_SLAK (1 << 1)RCC_AHB2ENR_GPIOFEN (1 << 5)PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)__UFRACT_MAX__ 0XFFFFP-16URRCC_AHB1RSTR_DMA1RST (1 << 0)I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)__FLT64_IS_IEC_60559__ 2__UINT_FAST32_TYPE__ unsigned intCAN_RF0R_FOVR0 (1 << 4)RCC_AHB3ENR_OFFSET 0x50__SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)CAN_TI2R(can_base) CAN_TIxR(can_base, CAN_MBOX2)RCC_APB1ENR1_SPI3EN (1 << 15)CAN_IER_EWGIE (1 << 8)INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__UINT_FAST16_TYPE__ unsigned intRCC_APB1RSTR2_SWPMI1RST (1 << 2)RCC_APB1ENR1_TIM5EN (1 << 3)CAN_ESR_LEC_REC_ERROR (0x4 << 4)INT32_C(c) __INT32_C(c)__FLT_DECIMAL_DIG__ 9BIT31 (1<<31)__INT32_TYPE__ long int__USACCUM_IBIT__ 8GPIO_PORT_H_BASE (PERIPH_BASE_AHB2 + 0x1c00)RCC_AHB3ENR MMIO32(RCC_BASE + RCC_AHB3ENR_OFFSET)RCC_CCIPR_I2CxSEL_SYS 1__ULFRACT_MIN__ 0.0ULRRCC_APB1RSTR1_DAC1RST (1 << 29)fifo_idCAN_TDT0R(can_base) CAN_TDTxR((can_base), CAN_MBOX0)__UINTPTR_TYPE__ unsigned intBIT21 (1<<21)RCC_AHB2RSTR_GPIOCRST (1 << 2)CAN_BTR_SJW_1TQ (0x0 << 24)UINT8_MAX __UINT8_MAX__RCC_APB1RSTR1 MMIO32(RCC_BASE + RCC_APB1RSTR1_OFFSET)__ARM_FEATURE_BF16_VECTOR_ARITHMETICRCC_BDCR_LSEBYP (1 << 2)UINT8_MAXRCC_AHB3ENR_QSPIEN (1 << 8)RCC_APB1SMENR1_SPI2SMEN (1 << 14)__ARM_SIZEOF_MINIMAL_ENUM 1RCC_APB2RSTR_OFFSET 0x40RCC_AHB1RSTR_OFFSET 0x28__INT64_C(c) c ## LLINT_LEAST16_MAXRCC_APB1ENR1 MMIO32(RCC_BASE + RCC_APB1ENR1_OFFSET)__DA_FBIT__ 31__FLT32_MIN__ 1.1754943508222875e-38F32SIZE_MAX __SIZE_MAX__INT8_MIN__GCC_ATOMIC_BOOL_LOCK_FREE 2INT_FAST64_MINRCC_CSR_MSIRANGE_4MHZ 6UINT_LEAST16_MAX __UINT_LEAST16_MAX__RCC_AHB2SMENR_ADCSMEN (1 << 13)__FLT_MAX_10_EXP__ 38CAN_ESR_TEC_MASK (0xF << 16)WINT_MIN __WINT_MIN__CAN_MSR_SLAKI (1 << 4)__DA_IBIT__ 32__TQ_FBIT__ 127__VFP_FP__ 1RCC_CCIPR_ADCSEL_SYS 3__ARM_ASM_SYNTAX_UNIFIED__ 1releaseRCC_PLLCFGR_PLLQ_SHIFT 21INT32_MAX__ARM_FP 4RCC_CSR_WWDGRSTF (1 << 30)RCC_PLLCFGR_PLLM_MASK 0x7RCC_APB1SMENR1_I2C3SMEN (1 << 23)RCC_APB1SMENR1_UART5SMEN (1 << 20)RCC_APB1ENR2_OFFSET 0x5cRCC_APB2SMENR_DFSDMSMEN (1 << 24)CAN_RDL0R(can_base) CAN_RDLxR((can_base), CAN_FIFO0)CAN_TSR_LOW0 (1 << 29)CAN_TIxR_STID_MASK (0x7FF << 21)CAN_FS1R(can_base) MMIO32((can_base) + 0x20C)__ARM_SIZEOF_WCHAR_T 4TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)__SIZEOF_DOUBLE__ 8__UINT_FAST32_MAX__ 0xffffffffU__LDBL_MAX_EXP__ 1024CAN_MCR_SLEEP (1 << 1)RCC_BDCR_RTCSEL_MASK 0x3RCC_PLLCFGR_PLLQ_DIV2 0RST_I2C1QUADSPI_BASE (0xa0001000U)rcc_periph_rstRCC_CR_HSERDY (1 << 17)__ARM_FEATURE_FP16_VECTOR_ARITHMETICRCC_APB1RSTR1_USART3RST (1 << 18)RCC_AHB2RSTR_GPIOERST (1 << 4)__INTMAX_MAX__ 0x7fffffffffffffffLLINT64_MAXdata8RCC_APB1ENR1_TIM2EN (1 << 0)dataRCC_CR_HSIASFS (1 << 11)__LONG_WIDTH__ 32RCC_CICR_HSERDYC (1 << 4)__OPTIMIZE__ 1USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x6800)__arm__ 1PTRDIFF_MINRCC_APB1RSTR1_UART5RST (1 << 20)ADC1_BASE (0x50000000U + 0x40000)RCC_CR_HSEBYP (1 << 18)UINT32_MAX __UINT32_MAX____OPTIMIZE_SIZE__ 1RCC_CFGR_PPRE1_MASK 0x7__ATOMIC_ACQ_REL 4RST_SPI1RST_SPI2RST_SPI3INT_FAST32_MIN (-INT_FAST32_MAX - 1)__INT8_TYPE__ signed char__LDBL_DENORM_MIN__ 4.9406564584124654e-324LRCC_CCIPR_USARTxSEL_SYS 1SYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000)RCC_CR_MSIRANGE_100KHZ 0RCC_APB1RSTR1_OPAMPRST (1 << 30)LIBOPENCM3_RCC_COMMON_ALL_H RCC_CIER_HSERDYIE (1 << 4)LPTIM2_BASE (PERIPH_BASE_APB1 + 0x9400)RCC_CFGR_MCO_LSE 0x7UINT_LEAST32_MAX__ACCUM_MAX__ 0X7FFFFFFFP-15KRCC_CIFR_LSECSSF (1 << 9)__FLT64_MIN_EXP__ (-1021)__INT_FAST32_TYPE__ intcan_receiveCAN_BTR_TS1_11TQ (0xA << 16)RCC_APB2ENR_TIM16EN (1 << 17)__FLT32_HAS_QUIET_NAN__ 1RCC_APB2RSTR_SAI2RST (1 << 22)__ARM_NEON__TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)USART2_BASE (PERIPH_BASE_APB1 + 0x4400)RCC_BDCR_LSCOEN (1 << 24)INT8_MAXRCC_CIER_LSIRDYIE (1 << 0)RCC_CSR_LSIRDY (1 << 1)CORESIGHT_LAR_OFFSET 0xfb0RCC_CICR_PLLSAI1RDYC (1 << 6)RCC_APB1ENR1_I2C1EN (1 << 21)RST_SWPMI1WCHAR_MIN__FLT32X_MIN_EXP__ (-1021)RNG_BASE (0x50000000U + 0x60800)__ARM_ARCH_PROFILERCC_CCIPR_SAIxSEL_MASK 0x3RCC_CCIPR_LPTIM1SEL_SHIFT 18RCC_CCIPR_LPUART1SEL_LSE 3RCC_AHB2RSTR_GPIOGRST (1 << 6)MMIO16(addr) (*(volatile uint16_t *)(addr))SCS_BASE (PPBI_BASE + 0xE000)INT16_MINRCC_CIER_HSIRDYIE (1 << 3)CAN_ESR_LEC_NO_ERROR (0x0 << 4)RCC_CCIPR_UARTxSEL_MASK RCC_CCIPR_USARTxSEL_MASKlong long unsigned intCAN_BTR_TS2_1TQ (0x0 << 20)UINTPTR_MAX __UINTPTR_MAX__INT8_MAX __INT8_MAX__RCC_PLLCFGR_PLLM(x) ((x)-1)CAN_BTR_LBKM (1 << 30)silentINT64_CRCC_APB1SMENR1_TIM6SMEN (1 << 4)RST_CRCcan_enable_irqRCC_CFGR_SW_MASK 0x3CAN_TDL2R(can_base) CAN_TDLxR((can_base), CAN_MBOX2)RCC_CR_MSIRANGE_800KHZ 3BIT19 (1<<19)UINT_FAST16_MAXRST_CRS__FLT64_DECIMAL_DIG__ 17__UINTPTR_MAX__ 0xffffffffU__ARM_FEATURE_COMPLEXRCC_AHB1ENR_DMA1EN (1 << 0)rcc_periph_reset_pulse__SFRACT_EPSILON__ 0x1P-7HR__ATOMIC_CONSUME 1data32__INT_LEAST16_TYPE__ short intRST_LCD__UINT_LEAST64_TYPE__ long long unsigned intEND_DECLS INT32_MAX __INT32_MAX__GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000)__USFRACT_FBIT__ 8RCC_CSR_IWDGRSTF (1 << 29)RST_ADC1RCC_CIFR_MSIRDYF (1 << 2)RCC_CR_MSIRDY (1 << 1)RCC_CCIPR_UARTxSEL_HSI16 RCC_CCIPR_USARTxSEL_HSI16__GCC_ATOMIC_WCHAR_T_LOCK_FREE 2RCC_CCIPR_SAIxSEL_PLLSAI2P 1RCC_APB2RSTR_TIM17RST (1 << 18)CAN_MCR_INRQ (1 << 0)RCC_APB1RSTR1_TIM5RST (1 << 3)__SIZEOF_PTRDIFF_T__ 4RCC_APB1ENR1_USART3EN (1 << 18)FMC_QUADSPI_BASE (0xA0000000U)RCC_APB1ENR1_UART5EN (1 << 20)RCC_AHB3SMENR MMIO32(RCC_BASE + RCC_AHB3SMENR_OFFSET)RCC_APB1ENR1_I2C3EN (1 << 23)DMA1_BASE (PERIPH_BASE_AHB1 + 0x0000)RCC_APB1RSTR1_SPI2RST (1 << 14)RCC_CFGR_HPRE_DIV8 0xa__FLT32X_HAS_QUIET_NAN__ 1__GNUC_EXECUTION_CHARSET_NAME "UTF-8"CAN_FMR_CAN2SB_SHIFT 8RCC_AHB3RSTR MMIO32(RCC_BASE + RCC_AHB3RSTR_OFFSET)CAN_IER_FMPIE0 (1 << 1)RCC_CCIPR_SAIxSEL_PLL 2RCC_CSR_RESET_FLAGS (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF | RCC_CSR_IWDGRSTF | RCC_CSR_SFTRSTF | RCC_CSR_BORRSTF | RCC_CSR_PINRSTF | RCC_CSR_OBLRSTF | RCC_CSR_FWRSTF)CAN_IER_BOFIE (1 << 10)__SIG_ATOMIC_WIDTH__ 32__DBL_MIN_EXP__ (-1021)can_disable_irqRCC_BASE (PERIPH_BASE_AHB1 + 0x1000)MPU_BASE (SCS_BASE + 0x0D90)TIM15_BASE (PERIPH_BASE_APB2 + 0x4000)RCC_APB2RSTR_TIM1RST (1 << 11)UINT16_MAXINT_LEAST16_MINRCC_AHB2RSTR_OTGFSRST (1 << 12)__LDBL_MAX_10_EXP__ 308SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)RCC_AHB3RSTR_FMCRST (1 << 0)RCC_ICSCR_MSITRIM_SHIFT 8RST_SYSCFGCAN_TSR_CODE_MASK (0x3 << 24)__INT64_TYPE__ long long intRCC_CFGR_SWS_HSI16 0x1INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)__ARM_FEATURE_CRC32__TA_FBIT__ 63CAN_RDH1R(can_base) CAN_RDHxR((can_base), CAN_FIFO1)bool _Bool__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64RCC_ICSCR_HSITRIM_MASK 0x1f__UINT_LEAST32_TYPE__ long unsigned intCAN_BTR_SJW_3TQ (0x2 << 24)SAI2_BASE (PERIPH_BASE_APB2 + 0x5800)RCC_APB1SMENR2_SWPMI1SMEN (1 << 2)INT32_MIN__HA_IBIT__ 8INT16_C(c) __INT16_C(c)__TA_IBIT__ 64INT8_MIN (-INT8_MAX - 1)__FLT32X_HAS_DENORM__ 1TSC_BASE (PERIPH_BASE_AHB1 + 0x4000)INT16_CRCC_CR_MSIRANGE_8MHZ 7RCC_APB2SMENR_USART1SMEN (1 << 14)RCC_PLLCFGR MMIO32(RCC_BASE + 0x0c)__HQ_IBIT__ 0scale_32bitlong long int__FLT_EVAL_METHOD__ 0RCC_CIFR_LSERDYF (1 << 1)RCC_CFGR_PPRE2_DIV8 0x6CAN_BTR_TS1_1TQ (0x0 << 16)RCC_CR_HSEON (1 << 16)__UHA_FBIT__ 8__ULLFRACT_EPSILON__ 0x1P-64ULLRRCC_CSR_PINRSTF (1 << 26)__ARM_FEATURE_CLZ 1INT_LEAST32_MAXCAN_RF0R_FULL0 (1 << 3)__FLT64_MIN_10_EXP__ (-307)RCC_APB2SMENR_TIM1SMEN (1 << 11)__ARM_FEATURE_FMA 1RCC_APB1RSTR1_TIM7RST (1 << 5)CAN_ESR_LEC_ACK_ERROR (0x3 << 4)__ARM_NEON_FP__FDPIC__CORESIGHT_LSR_OFFSET 0xfb4INT64_MIN__UINT16_MAX__ 0xffffRCC_AHB1ENR_OFFSET 0x48OPAMP_BASE (PERIPH_BASE_APB1 + 0x7800)RCC_AHB2ENR_GPIOCEN (1 << 2)RCC_APB1ENR1_SPI2EN (1 << 14)CAN_TDTxR_TIME_SHIFT 15__UFRACT_IBIT__ 0RCC_APB1SMENR2_LPUART1SMEN (1 << 0)BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)__DBL_HAS_QUIET_NAN__ 1__LDBL_MIN_10_EXP__ (-307)RCC_BDCR_LSEDRV_HIGH 3RST_LPTIM2RCC_CCIPR_SWPMI1SEL (1 << 30)SIG_ATOMIC_MAX__USFRACT_IBIT__ 0RCC_AHB2SMENR_OFFSET 0x6c__FLT32X_MIN_10_EXP__ (-307)WINT_MAXTIM17_BASE (PERIPH_BASE_APB2 + 0x4800)CAN_BTR_SJW_SHIFT 24__DEC_EVAL_METHOD__ 2CAN_BTR_TS1_8TQ (0x7 << 16)__LDBL_HAS_INFINITY__ 1DFSDM_BASE (PERIPH_BASE_APB2 + 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unsigned charINTMAX_MAXUINT16_CRCC_APB1SMENR1_DAC1SMEN (1 << 29)__CHAR16_TYPE__ short unsigned intINT_FAST8_MININT16_MIN (-INT16_MAX - 1)RCC_PLLCFGR_PLLR_DIV2 0CAN_RF0R_RFOM0 (1 << 5)__UFRACT_FBIT__ 16CAN_MCR_AWUM (1 << 5)unsigned intID_BASE (SCS_BASE + 0x0FD0)_REG_BIT(base,bit) (((base) << 5) + (bit))__ARM_FEATURE_MVEST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0x75a8))RCC_BDCR_RTCSEL_LSI 2RCC_APB1ENR1_OFFSET 0x58__UHA_IBIT__ 8__ARM_FEATURE_CDE_COPROC__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRshort int__UQQ_FBIT__ 8__GNUC_MINOR__ 2CAN_RDL1R(can_base) CAN_RDLxR((can_base), CAN_FIFO1)RCC_CIER MMIO32(RCC_BASE + 0x18)BBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)RCC_AHB1SMENR_FLASHSMEN (1 << 8)RST_I2C3INTMAX_MAX __INTMAX_MAX__RCC_AHB2RSTR_GPIODRST (1 << 3)__INTMAX_TYPE__ long long intRCC_APB1RSTR2_LPUART1RST (1 << 0)__UINT_LEAST16_TYPE__ short unsigned intRCC_CFGR_HPRE_DIV2 0x8__FLT32_MAX__ 3.4028234663852886e+38F32RCC_CCIPR_USART3SEL_SHIFT 4RCC_PLLSAI1_CFGR MMIO32(RCC_BASE + 0x10)RCC_CSR_LSION (1 << 0)RCC_APB1SMENR1_UART4SMEN (1 << 19)RCC_APB2ENR_SYSCFGEN (1 << 0)TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)RCC_BDCR_LSEDRV_MEDHIGH 2RST_LPUART1__FLT_DENORM_MIN__ 1.4012984643248171e-45FCAN_BTR_TS2_3TQ (0x2 << 20)INT_FAST32_MAX __INT_FAST32_MAX__RCC_CCIPR_SAIxSEL_EXT 3TIM8_BASE (PERIPH_BASE_APB2 + 0x3400)RCC_CCIPR_DFSDMSEL (1 << 31)INT_FAST64_MIN (-INT_FAST64_MAX - 1)__UINT_LEAST8_MAX__ 0xff__ARM_ARCH_ISA_THUMB 2__UINT32_MAX__ 0xffffffffULCAN_RIxR_IDE (1 << 2)can_filter_id_list_16bit_initRCC_PLLCFGR_PLLN_MASK 0x7f__GNUC_PATCHLEVEL__ 1GCC: (15:12.2.rel1-1) 12.2.1 20221205˙˙˙˙| $*B „…†‡Žv BA„…†‡Ž A„…LĹÄA„ŽK A„…KĹÄA„ŽK ĘB„…†‡Ž4®B(„…†‡‰ŠŽN BÎĘÉČÇĆĹÄBA A3aeabi)7E-M M "ń˙ ” `h "#%')=?+-/13579;A 4hśÍţ0aŹ @C ˝ ÇŢ*ç÷ 3 Qo~ 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C[€DŁ=E‚IÇJ„`KşNLütM `Np"OCPĚQŽ'RŽsSSzT©oUýpV·‰W’‡XéR[÷\¸g]'S^tu_i'`Ş+c¤dÚ!eťfö-g‚!h[li‚*jíxlVmýbn,EołuqŞOr~-u(xůzy“)zË,{žZ|Fn}(p€¦Qß‚´"»D(íP)ô*Ăi+Ą…3Š4 6V7Ľt8C[9ô:Ż~; y;d-<5 =đ >'„?q6@@uA,WB}CęWD_EŐF0:GŁHęrIĐ\J„kK‡rL÷mMIN&COŽmP Qh!RyRSÜ Ty‹URV>KW±‹X~YBZ[ËS\Mj`w{a)5bÉcw0d=heSfüŠgF{h\CiŃLjČDkFLl¶mLu6%vÔPwZsx[~y•,zű{ň.|Q7}Đ ~oj¸.€vŠŁt‚…Z„C…m†M-‡u ‹E]Ś=5…‘T"’Śn“Ś:•?–¨-—‹ťHcžŔźy/ CˇMŽ˘ŕzŁľI¦=§Ë‹¨p9©¶ŠŞŔ «1¬i‰çŠ®*ŻĆ°Ă&ł÷´n2·Ę0¸÷ą¬jşME»$hĽŕ†˝/MŔě‡Á%Â‘Ă–^Ä“jĹb}Ć#|Éý[Ę’ŚËbĚ“Íž?Îl=Ď?Đ¶?ŃăIŇ~,ÓzSÖ‚O× hŘŢcŮ±Ú§:ŰâFŢ˙qßE€ŕę$á¸Wâ5@ă‘…ćçç:|č<"ébZęŁë†?ě.îwďFXđň+ń3`ň”óźrô—l÷‡ řdůŽúĐA€|o[V‰Ě^Š‰hŤĚ/Ž0‹Ź ą7‘QO’b$›+śHžĘ<ź] {$ˇ2-˘`4ŁB¤Ţ#ĄŐ ©›zŞ”«L¬GMË®D!ŻPk°ž.± ˛Ż>łŰf·eM¸ď ą{|ş…»€&Ľ"˝PľŇUżă0Ŕ2ÁfFÇÎnČ·É™gĘ"(Ë"uĐ®^ŃÄ_Ňt%ÓjJÔ¸Őü{ÖÜj×3Ř€ŮQÚe`Ű÷ áßpâęžqëőCěž$í±\î´'ďTIđ(eńžňe8ófô6őS‡öt~÷ /řZů\|ú<<űŠoü„=ýăiţ‰pY„ß;…Ć‹]ŚMŤ 0ŽjoŹŚ9‘ů,’ý‹“1k”4‡•Ł_—ë&˘‡Ł¸k¤µĄó¦÷ŻŠi°ţd±LH˛pmł÷@´¦iµĄ]¶·»¸×ąBPş×tĂôJÄh7Ń [Ň=Ó`eÔ‘YŐ}aÖ2\×ń|Ř˘Ů±BÚg?ŰÉEÜ2ÝbŢĚ$ßI8ŕc^áŻ!âĚ[ăjäGĺ˙^î~ďç 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4.9406564584124654e-324F64RCC_OTGFSCORESIGHT_LSR_SLK (1<<1)__GCC_ATOMIC_WCHAR_T_LOCK_FREE 2LCD_BASE (PERIPH_BASE_APB1 + 0x2400)__CHAR_UNSIGNED__ 1CORESIGHT_LAR_KEY 0xC5ACCE55USART3_BASE (PERIPH_BASE_APB1 + 0x4800)RCC_AHB2RSTR_GPIOHRST (1 << 7)RCC_AHB2ENR_GPIOCEN (1 << 2)CRS_CR_ESYNCIE (1 << 3)RCC_QSPIRCC_USB__FLT64_HAS_INFINITY__ 1__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GCC_DESTRUCTIVE_SIZE 64__LACCUM_EPSILON__ 0x1P-31LKRCC_CIFR_LSECSSF (1 << 9)__PTRDIFF_MAX__ 0x7fffffffRCC_CR_PLLSAI1RDY (1 << 27)__INTMAX_C(c) c ## LLRCC_CR_MSIRANGE_800KHZ 3RCC_AHB3RSTR_FMCRST (1 << 0)__INTMAX_MAX__ 0x7fffffffffffffffLLCRS_CFGR_SYNCSRC_LSE (1 << CRS_CFGR_SYNCSRC_SHIFT)__TQ_IBIT__ 0rcc_periph_clken__FLT64_DECIMAL_DIG__ 17WINT_MIN __WINT_MIN__INT_FAST64_MAXOPAMP_BASE (PERIPH_BASE_APB1 + 0x7800)RCC_ICSCR_MSICAL_SHIFT 0__ATOMIC_CONSUME 1__ULACCUM_FBIT__ 32__WCHAR_MAX__ 0xffffffffURCC_APB1SMENR1_PWRSMEN (1 << 28)RCC_AHB1ENR_TSCEN (1 << 16)RCC_PLLCFGR_PLLR_DIV6 2RCC_AHB2ENR_GPIODEN (1 << 3)RCC_APB2ENR_SDMMC1EN (1 << 10)RCC_AHB1ENR_DMA1EN (1 << 0)RCC_CCIPR_USART1SEL_SYS 1RCC_AHB2SMENR_GPIOCSMEN (1 << 2)signed charINT64_MAX __INT64_MAX__INTMAX_MIN__SIZEOF_LONG_LONG__ 8RCC_PLLCFGR_PLLQ_DIV6 2__DBL_MAX_10_EXP__ 308__FRACT_MIN__ (-0.5R-0.5R)__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLK__USACCUM_MAX__ 0XFFFFP-8UHK__SFRACT_FBIT__ 7__INTMAX_WIDTH__ 64__ARM_FEATURE_BF16_SCALAR_ARITHMETIC__SQ_IBIT__ 0__ORDER_PDP_ENDIAN__ 3412__SIZE_TYPE__ unsigned intRCC_AHB1ENR_FLASHEN (1 << 8)RCC_AHB2SMENR_OTGFSSMEN (1 << 12)CRS_CFGR MMIO32(CRS_BASE + 0x04)__FLT_HAS_DENORM__ 1__INT8_TYPE__ signed char__FLT32_MIN__ 1.1754943508222875e-38F32RCC_APB2SMENR_SAI1SMEN (1 << 21)__USACCUM_MIN__ 0.0UHKGPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000)__FLT32_DECIMAL_DIG__ 9__DECIMAL_DIG__ 17__LDBL_MIN_EXP__ (-1021)UINTPTR_MAX __UINTPTR_MAX____LDBL_MANT_DIG__ 53SCC_SDMMC1INT64_MIN (-INT64_MAX - 1)CRS_CFGR_SYNCSRC_GPIO (0 << CRS_CFGR_SYNCSRC_SHIFT)CRS_CR_TRIM (0x3F << CRS_CR_TRIM_SHIFT)RCC_APB2SMENR_SDMMC1SMEN (1 << 10)__UINT8_C(c) c__CHAR32_TYPE__ long unsigned int__INT16_TYPE__ short intRCC_APB1RSTR1 MMIO32(RCC_BASE + RCC_APB1RSTR1_OFFSET)__FLT64_MAX__ 1.7976931348623157e+308F64RCC_CCIPR_ADCSEL_PLLSAI1R 1UINT_FAST32_MAXRCC_CFGR_MCO_HSE 0x4RCC_CIER_LSIRDYIE (1 << 0)RCC_APB1RSTR2_OFFSET 0x3cRCC_PLLCFGR_PLLSRC_NONE 0RCC_CCIPR_UARTxSEL_LSE RCC_CCIPR_USARTxSEL_LSEINT_FAST64_MAX __INT_FAST64_MAX__RCC_CR_MSION (1 << 0)__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1__STDC_HOSTED__ 1__ULLFRACT_FBIT__ 64__SIG_ATOMIC_TYPE__ intRCC_CICR_LSECSSC (1 << 9)RCC_PLLSAI1_CFGR MMIO32(RCC_BASE + 0x10)CRS_ISR_TRIMOVF (1 << 10)RCC_CIFR_CSSF (1 << 8)__INT_FAST64_TYPE__ long long int__ARM_FEATURE_COPROC 15GPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800)CRS_CFGR_RELOAD_VAL(x) ((x) << CRS_CFGR_RELOAD_SHIFT)ST_TSENSE_CAL2_110C MMIO16((INFO_BASE + 0x75ca))RCC_CFGR_MCO_PLL 0x5INT32_MIN (-INT32_MAX - 1)__FLT32_MAX_10_EXP__ 38RCC_CSR_MSIRANGE_MASK 0xfRCC_CFGR_HPRE_DIV8 0xaRCC_AHB2SMENR_GPIOHSMEN (1 << 7)RCC_CIFR_PLLSAI1RDYF (1 << 6)RCC_APB2SMENR_SYSCFGSMEN (1 << 0)RCC_BDCR_LSEDRV_MASK 0x3__USFRACT_MAX__ 0XFFP-8UHRLPTIM1_BASE (PERIPH_BASE_APB1 + 0x7c00)__FP_FAST_FMAF32 1RCC_APB1SMENR1_TIM5SMEN (1 << 3)__UINTPTR_MAX__ 0xffffffffU__FLT32_MIN_EXP__ (-125)RCC_CR_MSIRANGE_4MHZ 6RCC_APB1ENR2_SWPMI1EN (1 << 2)RCC_APB2SMENR_TIM15SMEN (1 << 16)UINT32_MAX __UINT32_MAX__RCC_CIER_MSIRDYIE (1 << 2)RCC_APB2RSTR_DFSDMRST (1 << 24)RCC_AHB1ENR MMIO32(RCC_BASE + RCC_AHB1ENR_OFFSET)__ULFRACT_FBIT__ 32RCC_APB2ENR_USART1EN (1 << 14)__FLT64_MIN_10_EXP__ (-307)RCC_APB1SMENR1_LPTIM1SMEN (1 << 31)__GNUC_EXECUTION_CHARSET_NAME "UTF-8"RCC_CIFR MMIO32(RCC_BASE + 0x1c)BIT10 (1<<10)__INT_FAST64_WIDTH__ 64__STDC_VERSION__ 199901LINT_LEAST64_MAX __INT_LEAST64_MAX__SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)RCC_CCIPR_SAI1SEL_SHIFT 22RCC_AHB2SMENR MMIO32(RCC_BASE + RCC_AHB2SMENR_OFFSET)RCC_CFGR_MCOPRE_DIV8 3__SFRACT_EPSILON__ 0x1P-7HR__INT32_C(c) c ## LUINT32_C(c) __UINT32_C(c)__ORDER_BIG_ENDIAN__ 4321SIZE_MAXSYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000)__UINTPTR_TYPE__ unsigned int__SQ_FBIT__ 31INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)RCC_CR_MSIRGSEL (1 << 3)SCC_SAI1SCC_SAI2__UHQ_FBIT__ 16RCC_APB1ENR2_LPTIM2EN (1 << 5)__FLT64_MIN_EXP__ (-1021)RCC_AHB1RSTR_CRCRST (1 << 12)__PTRDIFF_WIDTH__ 32RCC_DFSDMLIBOPENCM3_RCC_H __UINT_FAST8_MAX__ 0xffffffffURCC_CFGR_PPRE1_DIV2 0x4RCC_APB1ENR1_OPAMPEN (1 << 30)UINT16_C(c) __UINT16_C(c)__LACCUM_IBIT__ 32RCC_CSR_SFTRSTF (1 << 28)RCC_CCIPR_UARTxSEL_HSI16 RCC_CCIPR_USARTxSEL_HSI16__INT_FAST16_WIDTH__ 32INTMAX_CRCC_CFGR_STOPWUCK_MSI (0 << 15)RCC_CCIPR_I2C2SEL_SHIFT 14__VFP_FP__ 1RCC_ICSCR_MSITRIM_SHIFT 8__LLFRACT_MIN__ (-0.5LLR-0.5LLR)INT_FAST8_MAXCRS_ISR_FECAP (0xFFFF << CRS_ISR_FECAP_SHIFT)__UINT_FAST16_MAX__ 0xffffffffURCC_APB1SMENR1_TIM6SMEN (1 << 4)RCC_CFGR_PPRE2_DIV2 0x4__INTPTR_MAX__ 0x7fffffffINT64_C(c) __INT64_C(c)../common/crs_common_all.cSCC_SPI1SCC_SPI2__GCC_IEC_559_COMPLEX 0__UFRACT_MIN__ 0.0UR__THUMB_INTERWORK__ 1RCC_CFGR_SWS_PLL 0x3RCC_CFGR_MCO_SHIFT 24WCHAR_MAX __WCHAR_MAX__RCC_APB2SMENR_TIM8SMEN (1 << 13)__FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX__RCC_CSR_MSIRANGE_4MHZ 6INT8_C(c) __INT8_C(c)RCC_AHB2ENR_GPIOEEN (1 << 4)RCC_APB1RSTR1_I2C1RST (1 << 21)RCC_PWRRCC_APB1RSTR2_LPUART1RST (1 << 0)__ACCUM_FBIT__ 15PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)__UACCUM_IBIT__ 16long intUINT8_MAXIWDG_BASE (PERIPH_BASE_APB1 + 0x3000)SIZE_MAX __SIZE_MAX__RCC_CICR_PLLSAI2RDYC (1 << 7)__INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17RCC_CCIPR_CLK48SEL_SHIFT 26__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1RCC_SAI1RCC_SAI2__FLT32X_EPSILON__ 2.2204460492503131e-16F32xRCC_ICSCR_MSICAL_MASK 0xffRCC_CCIPR_SAIxSEL_PLLSAI1P 0NVIC_BASE (SCS_BASE + 0x0100)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32USART2_BASE (PERIPH_BASE_APB1 + 0x4400)__FLT64_MAX_10_EXP__ 308__UINTMAX_C(c) c ## ULLRCC_PLLCFGR_PLLN_MASK 0x7f__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed charRCC_AHB1RSTR MMIO32(RCC_BASE + RCC_AHB1RSTR_OFFSET)RCC_AHB1ENR_DMA2EN (1 << 1)__GCC_ATOMIC_BOOL_LOCK_FREE 2BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON____FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX____UINTMAX_TYPE__ long long unsigned int__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRRCC_APB1SMENR1_TIM4SMEN (1 << 2)RCC_CSR_MSIRANGE_8MHZ 7short unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)BIT7 (1<<7)BIT17 (1<<17)__FLT32X_MIN_10_EXP__ (-307)UINT8_MAX __UINT8_MAX__SCC_LPUART1SIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICRCC_SPI2LIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)CRS_CR_TRIM_SHIFT 8__DBL_IS_IEC_60559__ 2__UINT_FAST32_MAX__ 0xffffffffURCC_AHB3ENR_OFFSET 0x50__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4I2C3_BASE (PERIPH_BASE_APB1 + 0x5c00)RCC_APB2RSTR_TIM15RST (1 << 16)RCC_AHB2SMENR_ADCSMEN (1 << 13)CRS_ICR_ESYNCC (1 << 3)RCC_AHB1SMENR_DMA1SMEN (1 << 0)RCC_BDCR_RTCEN (1 << 15)__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32DMA1_BASE (PERIPH_BASE_AHB1 + 0x0000)PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)RCC_BDCR_RTCSEL_NONE 0RCC_CIER_PLLSAI1RDYIE (1 << 6)SCC_CAN1GNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsRCC_AHB2SMENR_AESSMEN (1 << 16)BIT27 (1<<27)SCC_PWRRCC_LPUART1RCC_CCIPR_LPUART1SEL_HSI16 2RCC_APB2ENR_SYSCFGEN (1 << 0)RCC_CCIPR_CLK48SEL_HSI48 0__UTA_FBIT__ 64INTMAX_C(c) __INTMAX_C(c)RCC_BDCR_LSESYSDIS (1 << 7)RCC_CIFR_MSIRDYF (1 << 2)__FLT_DECIMAL_DIG__ 9RCC_CRRCR_HSI48RDY (1 << 1)__thumb__ 1__INT_LEAST32_MAX__ 0x7fffffffL__VERSION__ "12.2.1 20221205"RCC_APB1ENR1_OFFSET 0x58CRS_CFGR_RELOAD_SHIFT 0INT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)__ARM_FEATURE_FMA 1__GNUC_STDC_INLINE__ 1__FRACT_FBIT__ 15__FLT_HAS_QUIET_NAN__ 1__GNUC_PATCHLEVEL__ 1__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2RCC_PLLCFGR_PLLP (1 << 17)PTRDIFF_MINRCC_TIM5__UINT_LEAST16_MAX__ 0xffffRCC_TIM6RCC_APB1SMENR1_OFFSET 0x78RCC_AHB2RSTR_GPIOARST (1 << 0)PPBI_BASE (0xE0000000U)__ARM_ARCH_PROFILE 77RCC_CIFR_PLLRDYF (1 << 5)INT32_MAXRCC_AHB3SMENR_OFFSET 0x70GPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000)RCC_APB1ENR1_TIM6EN (1 << 4)__FLT_DIG__ 6GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400)MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINRCC_PLLCFGR_PLLR_DIV2 0RCC_ICSCR_HSITRIM_MASK 0x1fSDMMC1_BASE (PERIPH_BASE_APB2 + 0x2800)__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)__FRACT_MAX__ 0X7FFFP-15RRCC_CCIPR_LPUART1SEL_LSE 3TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)INT_LEAST32_MAX __INT_LEAST32_MAX__RCC_CIER_LSERDYIE (1 << 1)SCC_DMA1RCC_SDMMC1__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5RCC_APB1SMENR1_USART2SMEN (1 << 17)RCC_PLLCFGR_PLLSRC_HSE 3RCC_CIER_PLLRDYIE (1 << 5)SCC_AESRCC_APB1RSTR1_DAC1RST (1 << 29)__DQ_IBIT__ 0RCC_APB1ENR1_SPI2EN (1 << 14)RCC_CFGR_SW_HSE 0x2RCC_AHB2SMENR_GPIODSMEN (1 << 3)RCC_CSR_LSION (1 << 0)RCC_CR_MSIRANGE_SHIFT 4__UINT16_MAX__ 0xffff__TQ_FBIT__ 127RCC_AHB2RSTR_ADCRST (1 << 13)RCC_RNG__USQ_FBIT__ 32INT_FAST16_MINRCC_AHB2SMENR_GPIOESMEN (1 << 4)RCC_CSR_IWDGRSTF (1 << 29)__thumb2__ 1__ULLACCUM_FBIT__ 32FMC_QUADSPI_BASE (0xA0000000U)RCC_AHB2SMENR_SRAM2SMEN (1 << 9)USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6c00)RCC_CICR_PLLSAI1RDYC (1 << 6)INT_FAST32_MIN (-INT_FAST32_MAX - 1)RCC_CFGR_MCO_MASK 0xf__STRICT_ANSI__ 1RCC_APB2RSTR_SYSCFGRST (1 << 0)FMC3_BANK_BASE (0x80000000U)UINT_LEAST8_MAXUINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)TIM8_BASE (PERIPH_BASE_APB2 + 0x3400)RCC_APB1RSTR1_CAN1RST (1 << 25)__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__RCC_AHB1RSTR_DMA2RST (1 << 1)RCC_BDCR_LSECSSON (1 << 5)RCC_APB2ENR_SAI2EN (1 << 22)__USA_IBIT__ 16__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1DBGMCU_BASE (PPBI_BASE + 0x00042000)PTRDIFF_MIN (-PTRDIFF_MAX - 1)UART5_BASE (PERIPH_BASE_APB1 + 0x5000)RCC_BDCR_LSEDRV_HIGH 3__UINT_FAST64_TYPE__ long long unsigned intPERIPH_BASE_AHB2 (0x48000000U)CRS_CR_SYNCOKIE (1 << 0)DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7590)__FLT_MIN__ 1.1754943508222875e-38FCRS_ICR_SYNCOKC (1 << 0)__HA_FBIT__ 7RCC_CFGR_MCO_HSI48 0x8__FDPIC__WINT_MAXRCC_GPIOARCC_GPIOBRCC_GPIOCRCC_GPIODRCC_GPIOERCC_GPIOFRCC_GPIOGRCC_GPIOHGPIO_PORT_G_BASE (PERIPH_BASE_AHB2 + 0x1800)RCC_CSR_PINRSTF (1 << 26)INT_FAST64_MIN__USFRACT_IBIT__ 0RCC_CCIPR_UARTxSEL_APB RCC_CCIPR_USARTxSEL_APBRCC_CIER_HSI48RDYIE (1 << 10)__LDBL_EPSILON__ 2.2204460492503131e-16LRCC_CCIPR_USART1SEL_APB 0CRS_CFGR_FELIM_SHIFT 16__USFRACT_MIN__ 0.0UHRTSC_BASE (PERIPH_BASE_AHB1 + 0x4000)RCC_BDCR_LSEDRV_SHIFT 3__ARM_NEONRCC_PLLCFGR_PLLQ_DIV2 0__UINT8_MAX__ 0xffRCC_CCIPR_LPTIM2SEL_SHIFT 20__LDBL_MAX_EXP__ 1024SCC_LPTIM1SCC_LPTIM2LIBOPENCM3_MEMORYMAP_H RCC_CFGR_HPRE_MASK 0xfRCC_CR_MSIRANGE_400KHZ 2SCC_RNG__DBL_HAS_DENORM__ 1DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)RCC_APB2RSTR_USART1RST (1 << 14)CRS_ISR_FEDIR (1 << 15)RCC_CIER_HSERDYIE (1 << 4)RCC_CR_MSIRDY (1 << 1)RCC_APB1RSTR1_OFFSET 0x38QUADSPI_BASE (0xa0001000U)__DA_FBIT__ 31RCC_ICSCR_MSITRIM_MASK 0xffRCC_CCIPR_UART5SEL_SHIFT 8__GXX_ABI_VERSION 1017GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0c00)__INT_LEAST16_MAX__ 0x7fffRCC_CCIPR_ADCSEL_MASK 0x3__FLT_DENORM_MIN__ 1.4012984643248171e-45FRCC_PLLCFGR_PLLREN (1<<24)RCC_CIFR_HSIRDYF (1 << 3)RCC_CR_MSIRANGE_16MHZ 8INT_LEAST8_MAX __INT_LEAST8_MAX__RCC_CR_MSIRANGE_1MHZ 4RCC_APB1RSTR1_SPI2RST (1 << 14)CRS_ISR_SYNCERR (1 << 8)__UINT32_C(c) c ## ULRCC_AHB1SMENR_SRAM1SMEN (1 << 9)RCC_CFGR_MCOPRE_DIV4 2__UACCUM_MIN__ 0.0UK__FLT_EPSILON__ 1.1920928955078125e-7FRCC_PLLCFGR_PLLSRC_SHIFT 0TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)RCC_APB2RSTR_SAI1RST (1 << 21)RCC_AHB1SMENR_FLASHSMEN (1 << 8)__PTRDIFF_TYPE__ int__ARM_ARCH_ISA_THUMBRCC_CR_PLLSAI1ON (1 << 26)RCC_CCIPR_LPUART1SEL_SHIFT 10__ARM_FEATURE_MATMUL_INT8RCC_CFGR_PPRE2_NODIV 0x0RCC_CICR_MSIRDYC (1 << 2)LIBOPENCM3_CM3_MEMORYMAP_H __GCC_ATOMIC_SHORT_LOCK_FREE 2RCC_CCIPR_UARTxSEL_MASK RCC_CCIPR_USARTxSEL_MASKRCC_AHB2SMENR_GPIOGSMEN (1 << 6)RCC_CCIPR_LPUART1SEL_SYS 1RCC_APB2ENR_TIM1EN (1 << 11)__USACCUM_FBIT__ 8RCC_CCIPR_I2CxSEL_MASK 0x3__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1RCC_APB1ENR1_USART2EN (1 << 17)SCC_DAC1__LACCUM_FBIT__ 31SCS_BASE (PPBI_BASE + 0xE000)RCC_CFGR_STOPWUCK_HSI16 (1 << 15)RCC_CICR_LSERDYC (1 << 1)SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)__FLT32_HAS_QUIET_NAN__ 1I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)RCC_APB2SMENR_SPI1SMEN (1 << 12)RCC_CSR_OBLRSTF (1 << 25)RCC_BDCR_LSECSSD (1 << 6)__LDBL_HAS_INFINITY__ 1RCC_CCIPR_LPUART1SEL_APB 0RCC_AHB2RSTR_GPIOERST (1 << 4)__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))__FLT32X_MAX_10_EXP__ 308DWT_BASE (PPBI_BASE + 0x1000)RCC_CCIPR_CLK48SEL_PLLSAI1Q 1RCC_CIER_HSIRDYIE (1 << 3)bool _BoolRCC_CRCRCC_APB2ENR_TIM15EN (1 << 16)UINTMAX_MAX __UINTMAX_MAX__RCC_CSR_LPWRRSTF (1 << 31)__SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffRCC_CR_PLLSAI2ON (1 << 28)BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)SCC_TIM1RCC_CRSSCC_TIM3__FP_FAST_FMAF 1SCC_TIM5SCC_TIM6SCC_TIM7SCC_TIM8__FLT32X_IS_IEC_60559__ 2RCC_APB1RSTR1_USART3RST (1 << 18)PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)RCC_CIER MMIO32(RCC_BASE + 0x18)RCC_APB2RSTR_OFFSET 0x40LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))UINT32_MAXRCC_OPAMP__INT_LEAST16_WIDTH__ 16__DEC_EVAL_METHOD__ 2__ARM_FEATURE_FP16_FMLCRS_CFGR_SYNCDIV_DIV2 (1 << CRS_CFGR_SYNCDIV_SHIFT)RCC_CR_MSIRANGE_2MHZ 5RCC_AHB3ENR_FMCEN (1 << 0)RCC_CCIPR_I2CxSEL_APB 0__USFRACT_EPSILON__ 0x1P-8UHRRCC_PLLCFGR_PLLSRC_MSI 1RCC_APB2ENR_TIM8EN (1 << 13)RCC_DAC1__OPTIMIZE_SIZE__ 1__USFRACT_FBIT__ 8__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLKRCC_APB1ENR1_LCDEN (1 << 9)RCC_APB1RSTR1_UART5RST (1 << 20)__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX__RCC_CSR_WWDGRSTF (1 << 30)__UINT32_MAX__ 0xffffffffULCRS_CFGR_RELOAD (0xFFFF << CRS_CFGR_RELOAD_SHIFT)RCC_CCIPR_ADCSEL_SYS 3RCC_CFGR_MCO_MSI 0x2__INT_LEAST8_MAX__ 0x7fRCC_AHB3SMENR_QSPISMEN (1 << 8)__GCC_ATOMIC_POINTER_LOCK_FREE 2__ARM_FEATURE_QBIT 1__ARM_FEATURE_CLZ 1__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXRCC_AHB3ENR MMIO32(RCC_BASE + RCC_AHB3ENR_OFFSET)RCC_CICR MMIO32(RCC_BASE + 0x20)RCC_CAN1RCC_ICSCR_HSICAL_MASK 0xffRCC_CFGR_SWS_MASK 0x3__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024CRS_CFGR_SYNCSRC_SHIFT 28RCC_TIM1RCC_TIM2RCC_TIM3RCC_TIM4__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)RCC_TIM7RCC_TIM8__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1__ACCUM_MAX__ 0X7FFFFFFFP-15KRCC_APB1RSTR2_SWPMI1RST (1 << 2)__INT8_MAX__ 0x7fBIT14 (1<<14)RCC_CCIPR_USART2SEL_SHIFT 2RCC_APB1RSTR1_TIM6RST (1 << 4)__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16RCC_CIER_PLLSAI2RDYIE (1 << 7)__SHRT_WIDTH__ 16BIT20 (1<<20)__ARM_FEATURE_MVERCC_CFGR_MCO_NOCLK 0x0__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intRCC_CFGR_HPRE_DIV64 0xcRCC_APB1RSTR1_TIM4RST (1 << 2)SWPMI1_BASE (PERIPH_BASE_APB1 + 0x8800)UINT_LEAST16_MAX __UINT_LEAST16_MAX__INT_FAST32_MIN__FLT_EVAL_METHOD_TS_18661_3__ 0RCC_AHB3RSTR MMIO32(RCC_BASE + RCC_AHB3RSTR_OFFSET)SCC_ADC1__SCHAR_WIDTH__ 8BIT18 (1<<18)UINT_FAST16_MAX__UINT_FAST8_TYPE__ unsigned intRCC_CIFR_LSERDYF (1 << 1)__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RBIT24 (1<<24)CRS_CFGR_SYNCSRC (3 << CRS_CFGR_SYNCSRC_SHIFT)RCC_CCIPR_I2CxSEL_SYS 1__INT32_MAX__ 0x7fffffffLRCC_APB1ENR1_UART4EN (1 << 19)RCC_PLLCFGR_PLLR_DIV8 3RCC_CFGR_HPRE_DIV16 0xbRCC_CFGR_HPRE_DIV256 0xeUINTMAX_MAXRCC_APB1SMENR1_UART4SMEN (1 << 19)BIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLLRCC_CFGR_SW_MASK 0x3__ARM_FEATURE_BF16_VECTOR_ARITHMETICRCC_CCIPR_USART3SEL_SHIFT 4INFO_BASE (0x1fff0000U)__FLT32_MANT_DIG__ 24INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32RCC_AHB2ENR_GPIOHEN (1 << 7)__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN__SCC_GPIOBINT8_MAX __INT8_MAX__RCC_CSR_LSIRDY (1 << 1)BIT28 (1<<28)RCC_BDCR_LSEDRV_MEDHIGH 2RCC_PLLPEN (1 << 16)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2SCC_GPIOFRCC_APB1SMENR1_LCDSMEN (1 << 9)SCC_GPIOG__DBL_MAX_EXP__ 1024SCC_WWDG__ATOMIC_RELEASE 3SCC_TIM2UINT_FAST8_MAX__FLT_MANT_DIG__ 24RCC_BDCR_BDRST (1 << 16)RCC_APB1ENR1_UART5EN (1 << 20)__UDQ_IBIT__ 0RCC_APB2SMENR_TIM1SMEN (1 << 11)TIM1_BASE (PERIPH_BASE_APB2 + 0x2C00)RCC_AHB1SMENR MMIO32(RCC_BASE + RCC_AHB1SMENR_OFFSET)RCC_CR_HSERDY (1 << 17)SCC_FLASH__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UK__FLT64_NORM_MAX__ 1.7976931348623157e+308F64RCC_CSR_BORRSTF (1 << 27)RCC_APB1RSTR1_OPAMPRST (1 << 30)UINTPTR_MAXcrs_autotrim_usb_enable__LDBL_DENORM_MIN__ 4.9406564584124654e-324LRCC_ADC1__INT64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_SAT 1__ULLFRACT_IBIT__ 0CRS CRS_BASERCC_CR_HSIASFS (1 << 11)SCC_SPI3MMIO16(addr) (*(volatile uint16_t *)(addr))RCC_LPTIM1RCC_LPTIM2AES_BASE (0x50000000U + 0x60000)RCC_CFGR_PPRE2_DIV8 0x6DAC_BASE (PERIPH_BASE_APB1 + 0x7400)__GNUC__ 12BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)WCHAR_MAXRCC_APB1ENR1_USART3EN (1 << 18)RCC_CCIPR_LPTIMxSEL_HSI16 2__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16RCC_CICR_LSIRDYC (1 << 0)__UFRACT_EPSILON__ 0x1P-16UR__USES_INITFINI__ 1RCC_APB2SMENR_DFSDMSMEN (1 << 24)__UQQ_IBIT__ 0RCC_CFGR_SWS_SHIFT 2CORESIGHT_LSR_OFFSET 0xfb4RCC_APB1ENR1_TIM3EN (1 << 1)__GCC_ATOMIC_LONG_LOCK_FREE 2__ULACCUM_MIN__ 0.0ULK__LDBL_MAX__ 1.7976931348623157e+308L__ARM_ARCH 7UART4_BASE (PERIPH_BASE_APB1 + 0x4c00)__FLT_RADIX__ 2BIT3 (1<<3)long long intTPIU_BASE (PPBI_BASE + 0x40000)RCC_CIER_LSE_CSSIE (1 << 9)__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAXRCC_AHB2ENR_ADCEN (1 << 13)SCC_GPIOA__LDBL_HAS_QUIET_NAN__ 1SCC_GPIOCSCC_GPIODSCC_GPIOE__LONG_LONG_WIDTH__ 64BIT6 (1<<6)SCC_GPIOHRCC_UART4RCC_UART5RCC_APB1SMENR1_I2C1SMEN (1 << 21)RCC_CCIPR_LPUART1SEL_MASK 0x3__UINT_FAST64_MAX__ 0xffffffffffffffffULLRCC_APB1RSTR1_I2C3RST (1 << 23)__ARM_FP__HA_IBIT__ 8__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1RCC_CFGR_MCOPRE_MASK 0x7BIT9 (1<<9)RCC_CFGR_HPRE_DIV512 0xf__FLT32X_MIN__ 2.2250738585072014e-308F32xINTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024RCC_FWUINT16_MAXRCC_AHB2RSTR_OTGFSRST (1 << 12)RCC_APB1ENR2_LPUART1EN (1 << 0)__FLT64_MIN__ 2.2250738585072014e-308F64RCC_APB1SMENR1_TIM2SMEN (1 << 0)RCC_AHB3ENR_QSPIEN (1 << 8)CRS_CFGR_FELIM (0xFF << CRS_CFGR_FELIM_SHIFT)RCC_APB1SMENR2 MMIO32(RCC_BASE + RCC_APB1SMENR2_OFFSET)RCC_CCIPR_USART1SEL_HSI16 2__ARM_ARCH_PROFILE__INT64_TYPE__ long long int__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4RCC_CCIPR_USARTxSEL_APB 0RCC_CR_HSION (1 << 8)RCC_CCIPR_LPTIMxSEL_MASK 0x3RCC_CR_HSIRDY (1 << 10)__WCHAR_MIN__ 0UCRS_BASE (PERIPH_BASE_APB1 + 0x6000)RCC_AES__UFRACT_MAX__ 0XFFFFP-16URRCC_AHB1RSTR_OFFSET 0x28RCC_CR_HSEON (1 << 16)INT64_MAXFPB_BASE (PPBI_BASE + 0x2000)RCC_APB2RSTR_SAI2RST (1 << 22)RCC_CFGR_PPRE2_SHIFT 11RCC_CIFR_PLLSAI2RDYF (1 << 7)RCC_CICR_HSI48RDYC (1 << 10)INT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0RCC_BDCR_RTCSEL_LSI 2RCC_CCIPR_USARTxSEL_LSE 3SCC_DFSDMSTIR_BASE (SCS_BASE + 0x0F00)SCC_ADC__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__COMP_BASE (PERIPH_BASE_APB2 + 0x0200)RCC_TIM15RCC_TIM16RCC_TIM17SYS_TICK_BASE (SCS_BASE + 0x0010)CRS_ISR_ESYNCF (1 << 3)RCC_BDCR_LSEDRV_MEDLOW 1RCC_PLLCFGR_PLLSRC_HSI16 2CRS_ICR_ERRC (1 << 2)RCC_CFGR_SWS_MSI 0x0__UFRACT_FBIT__ 16FMC_BASE (0xa0000000U)__UDQ_FBIT__ 64INT16_MIN (-INT16_MAX - 1)RCC_CCIPR_SAIxSEL_MASK 0x3__LDBL_MAX_10_EXP__ 308RCC_APB2SMENR_USART1SMEN (1 << 14)RCC_AHB2ENR_GPIOBEN (1 << 1)__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)__INT_FAST32_TYPE__ intRCC_CICR_HSERDYC (1 << 4)unsigned intRCC_CR_MSIRANGE_MASK 0xfCRS_CR MMIO32(CRS_BASE + 0x00)RCC_AHB2RSTR_GPIOCRST (1 << 2)__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1RCC_CSR_FWRSTF (1 << 24)__USACCUM_IBIT__ 8ITM_BASE (PPBI_BASE + 0x0000)ST_VREFINT_CAL MMIO16((INFO_BASE + 0x75aa))__FLT64_HAS_DENORM__ 1__ULLACCUM_IBIT__ 32__UACCUM_EPSILON__ 0x1P-16UKRCC_APB1SMENR2_OFFSET 0x7c__UTA_IBIT__ 64SCB_BASE (SCS_BASE + 0x0D00)__FLT_EVAL_METHOD__ 0RCC_AHB3SMENR MMIO32(RCC_BASE + RCC_AHB3SMENR_OFFSET)__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32DFSDM_BASE (PERIPH_BASE_APB2 + 0x6000)RCC_CR_PLLON (1 << 24)RCC_BASE (PERIPH_BASE_AHB1 + 0x1000)__ARM_FEATURE_LDREXRCC_SYSCFG__UQQ_FBIT__ 8RCC_CFGR_HPRE_SHIFT 4__WINT_TYPE__ unsigned int__ARM_FP16_ARGS__GCC_IEC_559 0RCC_CSR MMIO32(RCC_BASE + 0x94)INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX____LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4__STDC__ 1RCC_AHB2SMENR_RNGSMEN (1 << 18)SCC_OPAMPRCC_AHB3RSTR_OFFSET 0x30__ARM_FEATURE_IDIV 1SCC_OTGFS__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__CORESIGHT_LAR_OFFSET 0xfb0__UINT8_TYPE__ unsigned charRCC_APB2ENR_SAI1EN (1 << 21)__UINT_LEAST8_TYPE__ unsigned charCRS_CFGR_SYNCDIV_NODIV (0 << CRS_CFGR_SYNCDIV_SHIFT)RCC_AHB1SMENR_TSCSMEN (1 << 16)RCC_CICR_HSIRDYC (1 << 3)UINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"INT8_MINRCC_APB2ENR_DFSDMEN (1 << 24)RCC_PLLCFGR_PLLM_SHIFT 0x4RCC_APB1SMENR1_CAN1SMEN (1 << 25)CRS_CR_SWSYNC (1 << 7)PERIPH_BASE (0x40000000U)true 1CRS_ISR_FECAP_SHIFT 16__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)RCC_CCIPR_CLK48SEL_PLL 2RCC_AHB1ENR_OFFSET 0x48RCC_CCIPR_LPTIMxSEL_LSI 1__FLT32X_MIN_EXP__ (-1021)RCC_BDCR_LSEON (1 << 0)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)RCC_CFGR_SW_PLL 0x3__GCC_ATOMIC_CHAR_LOCK_FREE 2RCC_AHB2ENR_OFFSET 0x4c__LFRACT_EPSILON__ 0x1P-31LRFMC1_BANK_BASE (0x60000000U)STM32L4 1RCC_PLLCFGR_PLLQ_MASK 0x3RCC_APB1SMENR1_TIM7SMEN (1 << 5)RCC_APB1SMENR1_OPAMPSMEN (1 << 30)__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX____FLT32X_NORM_MAX__ 1.7976931348623157e+308F32x__arm__ 1RCC_CR MMIO32(RCC_BASE + 0x00)RCC_CCIPR_LPTIMxSEL_APB 0__FLT32_MIN_10_EXP__ (-37)RCC_APB1RSTR2_LPTIM2RST (1 << 5)RCC_APB1ENR1_PWREN (1 << 28)MMIO64(addr) (*(volatile uint64_t *)(addr))__ARM_FP16_FORMAT_ALTERNATIVERCC_APB1SMENR1_TIM3SMEN (1 << 1)RCC_APB1RSTR1_LCDRST (1 << 9)__LDBL_NORM_MAX__ 1.7976931348623157e+308LRCC_PLLCFGR_PLLR_DIV4 1INTPTR_MINRCC_CR_MSIRANGE_48MHZ 11DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)INT16_MAX __INT16_MAX____BIGGEST_ALIGNMENT__ 8RCC_SPI1RCC_APB1ENR1_LPTIM1EN (1 << 31)RCC_CCIPR_LPTIMxSEL_LSE 3CRS_CR_CEN (1 << 5)RCC_SPI3__TA_IBIT__ 64RCC_APB1SMENR1_I2C3SMEN (1 << 23)CRS_CFGR_SYNCDIV_SHIFT 24RCC_AHB2SMENR_GPIOASMEN (1 << 0)RCC_APB1ENR1_TIM5EN (1 << 3)__ARM_FEATURE_QRDMXRCC_CFGR_HPRE_NODIV 0x0RCC_CCIPR_LPTIM1SEL_SHIFT 18RCC_APB1ENR1_I2C3EN (1 << 23)__ARM_ARCH_ISA_THUMB 2RCC_APB1SMENR2_LPTIM2SMEN (1 << 5)__LONG_LONG_MAX__ 0x7fffffffffffffffLLRCC_APB1RSTR1_PWRRST (1 << 28)RCC_APB1ENR2_OFFSET 0x5c__WINT_WIDTH__ 32SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__RCC_BDCR_RTCSEL_MASK 0x3__USQ_IBIT__ 0RCC_CRRCR_HSI48ON (1 << 0)BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1RCC_AHB2ENR_GPIOFEN (1 << 5)_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN____SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__DBL_MIN_EXP__ (-1021)RCC_APB1ENR1_TIM7EN (1 << 5)__LDBL_HAS_DENORM__ 1RCC_CFGR_PPRE1_DIV8 0x6RCC_AHB2RSTR_RNGRST (1 << 18)RCC_PLLCFGR_PLLM_MASK 0x7INT8_MIN (-INT8_MAX - 1)RCC_APB1ENR1_TIM2EN (1 << 0)RCC_AHB2ENR MMIO32(RCC_BASE + RCC_AHB2ENR_OFFSET)__FLT32_DIG__ 6CRS_CFGR_SYNCDIV_DIV32 (5 << CRS_CFGR_SYNCDIV_SHIFT)INT_LEAST16_MAXRCC_APB2RSTR_SDMMC1RST (1 << 10)RCC_AHB2RSTR_AESRST (1 << 16)BIT15 (1<<15)RCC_AHB2RSTR_OFFSET 0x2cFIREWALL_BASE (PERIPH_BASE_APB2 + 0x1C00)RCC_PLLCFGR_PLLQ_DIV4 1CRS_ISR_SYNCOOKF (1 << 0)RCC_AHB2RSTR_GPIOBRST (1 << 1)VREFBUF_BASE (PERIPH_BASE_APB2 + 0x0030)BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)CRS_CFGR_SYNCSRC_USB_SOF (2 << CRS_CFGR_SYNCSRC_SHIFT)RCC_APB1ENR1_CAN1EN (1 << 25)RCC_APB2ENR_FWEN (1 << 7)__ACCUM_MIN__ (-0X1P15K-0X1P15K)RCC_LCD__ARM_FEATURE_CRYPTO__INT_LEAST32_TYPE__ long intRCC_CFGR_HPRE_DIV4 0x9BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__FRACT_IBIT__ 0RCC_CCIPR_USART1SEL_SHIFT 0RCC_CCIPR_USART1SEL_LSE 3UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234ADC1_BASE (0x50000000U + 0x40000)__FLT_NORM_MAX__ 3.4028234663852886e+38FRCC_CFGR_MCOPRE_DIV1 0RCC_APB1SMENR2_LPUART1SMEN (1 << 0)long long unsigned intSCC_DMA2__FLT_MIN_10_EXP__ (-37)BIT31 (1<<31)__ULACCUM_IBIT__ 32RCC_CFGR_SWS_HSE 0x2__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__ULLACCUM_EPSILON__ 0x1P-32ULLK__APCS_32__ 1__DQ_FBIT__ 63INT_LEAST64_MAX__SACCUM_IBIT__ 8_REG_BIT(base,bit) (((base) << 5) + (bit))__UHQ_IBIT__ 0TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)LIBOPENCM3_MEMORYMAP_COMMON_H RCC_AHB2ENR_AESEN (1 << 16)BIT29 (1<<29)RCC_APB1RSTR1_I2C2RST (1 << 22)__INT_FAST16_TYPE__ intRCC_APB1ENR1_DAC1EN (1 << 29)__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)__ULFRACT_MAX__ 0XFFFFFFFFP-32ULRRCC_CCIPR_I2C1SEL_SHIFT 12__UINT_LEAST16_TYPE__ short unsigned intRCC_APB1RSTR1_UART4RST (1 << 19)RCC_CCIPR_I2C3SEL_SHIFT 16__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned intRCC_CCIPR_USARTxSEL_SYS 1RCC_APB2SMENR_TIM17SMEN (1 << 18)__FLT32X_DIG__ 15RCC_CIFR_LSIRDYF (1 << 0)RCC_APB2SMENR_SAI2SMEN (1 << 22)__UTQ_FBIT__ 128RCC_APB2ENR_TIM17EN (1 << 18)__LLACCUM_EPSILON__ 0x1P-31LLK__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffffRCC_AHB1RSTR_FLASHRST (1 << 8)DMA2_BASE (PERIPH_BASE_AHB1 + 0x0400)PTRDIFF_MAX __PTRDIFF_MAX____SIZEOF_SHORT__ 2RCC_CFGR_SWS_HSI16 0x1RCC_CFGR_PPRE2_DIV16 0x7RCC_CR_PLLRDY (1 << 25)SCC_LCDSCC_UART4SCC_UART5RCC_CCIPR_SAIxSEL_PLL 2RCC_PLLCFGR_PLLM(x) ((x)-1)__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKUINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRRCC_BDCR_RTCSEL_LSE 1RCC_APB1SMENR1_SPI2SMEN (1 << 14)RCC_DMA1RCC_DMA2__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intRCC_AHB2ENR_RNGEN (1 << 18)RCC_AHB2ENR_GPIOGEN (1 << 6)CRS_ISR MMIO32(CRS_BASE + 0x08)RCC_APB1RSTR1_TIM3RST (1 << 1)RCC_APB1ENR1_TIM4EN (1 << 2)RCC_APB1SMENR1_USART3SMEN (1 << 18)WCHAR_MINRCC_CRRCR MMIO32(RCC_BASE + 0x98)RCC_CR_MSIRANGE_8MHZ 7BEGIN_DECLS RCC_CFGR_PPRE1_DIV16 0x7RCC_CFGR_PPRE2_DIV4 0x5RCC_CSR_MSIRANGE_1MHZ 4RCC_AHB2RSTR_GPIOFRST (1 << 5)CRS_CFGR_SYNCDIV_DIV128 (7 << CRS_CFGR_SYNCDIV_SHIFT)RCC_APB2RSTR_SPI1RST (1 << 12)RCC_CIFR_HSERDYF (1 << 4)CRS_ISR_SYNCMISS (1 << 9)RCC_APB1ENR2 MMIO32(RCC_BASE + RCC_APB1ENR2_OFFSET)RCC_AHB1ENR_CRCEN (1 << 12)RCC_CCIPR_USARTxSEL_HSI16 2__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__FLT32X_MAX__ 1.7976931348623157e+308F32xGPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400)__ARM_EABI__ 1RCC_PLLCFGR_PLLQEN (1 << 20)INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1__ARM_FEATURE_DSP 1RCC_CR_MSIPLLEN (1 << 2)RCC_APB1SMENR1_DAC1SMEN (1 << 29)TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)__QQ_IBIT__ 0RCC_AHB2ENR_OTGFSEN (1 << 12)RCC_AHB2SMENR_OFFSET 0x6cRCC_CCIPR_DFSDMSEL (1 << 31)SCC_TIM15SCC_TIM16SCC_TIM17__LLACCUM_FBIT__ 31RCC_APB2ENR MMIO32(RCC_BASE + RCC_APB2ENR_OFFSET)LIBOPENCM3_RCC_COMMON_ALL_H DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 0x14)__GNUC_MINOR__ 2RCC_ICSCR_HSICAL_SHIFT 16__UINT_LEAST32_TYPE__ long unsigned intRCC_AHB1RSTR_TSCRST (1 << 16)__ARM_FEATURE_NUMERIC_MAXMINTIM4_BASE (PERIPH_BASE_APB1 + 0x0800)__INTMAX_TYPE__ long long int__GCC_ATOMIC_INT_LOCK_FREE 2RCC_APB2RSTR_TIM17RST (1 << 18)RCC_APB1RSTR1_TIM5RST (1 << 3)TIM16_BASE (PERIPH_BASE_APB2 + 0x4400)INT_LEAST8_MININTMAX_MAXRCC_APB1SMENR1_SPI3SMEN (1 << 15)ID_BASE (SCS_BASE + 0x0FD0)DESIG_PACKAGE MMIO16((INFO_BASE + 0x7500))__ARM_ARCH_7EM__ 1__ARM_FEATURE_FP16_SCALAR_ARITHMETIC__LFRACT_MIN__ (-0.5LR-0.5LR)__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1RCC_AHB3RSTR_QSPIRST (1 << 8)TIM17_BASE (PERIPH_BASE_APB2 + 0x4800)__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CSCC_USART1SCC_USART2SCC_USART3RCC_CCIPR_SAIxSEL_PLLSAI2P 1INT64_MINRCC_APB1RSTR1_LPTIM1RST (1 << 31)__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_CRCC_FMCRCC_CFGR_SW_MSI 0x0UINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRRCC_APB2ENR_OFFSET 0x60RCC_PLLCFGR_PLLQ_DIV8 3/build/libopencm3/lib/stm32/l4__SIZEOF_SIZE_T__ 4RCC_APB1ENR1 MMIO32(RCC_BASE + RCC_APB1ENR1_OFFSET)__UINT64_TYPE__ long long unsigned int__INT64_C(c) c ## LLRCC_CR_MSIRANGE_100KHZ 0__LDBL_MIN_10_EXP__ (-307)USART1_BASE (PERIPH_BASE_APB2 + 0x3800)USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x6800)CRS_ICR_SYNCWARNC (1 << 1)RCC_APB2ENR_TIM16EN (1 << 17)RCC_APB1SMENR1_UART5SMEN (1 << 20)__LDBL_MIN__ 2.2250738585072014e-308LRCC_CCIPR_UART4SEL_SHIFT 6__ARM_FEATURE_CDE__ACCUM_IBIT__ 16RCC_CR_MSIRANGE_32MHZ 10CRS_CR_AUTOTRIMEN (1 << 6)RCC_AHB2ENR_GPIOAEN (1 << 0)RCC_TSCEXTI_BASE (PERIPH_BASE_APB2 + 0x0400)RCC_AHB1RSTR_DMA1RST (1 << 0)RCC_APB2RSTR MMIO32(RCC_BASE + RCC_APB2RSTR_OFFSET)FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000)short intRNG_BASE (0x50000000U + 0x60800)CRS_CFGR_SYNCDIV_DIV8 (3 << CRS_CFGR_SYNCDIV_SHIFT)RCC_CSR_RESET_FLAGS (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF | RCC_CSR_IWDGRSTF | RCC_CSR_SFTRSTF | RCC_CSR_BORRSTF | RCC_CSR_PINRSTF | RCC_CSR_OBLRSTF | RCC_CSR_FWRSTF)__FLT32_IS_IEC_60559__ 2RCC_CSR_MSIRANGE_SHIFT 8__UINT16_C(c) c__UDA_IBIT__ 32SCC_SWPMI1RCC_PLLCFGR_PLLQ_SHIFT 21UINT_LEAST32_MAXRCC_PLLSAI2_CFGR MMIO32(RCC_BASE + 0x14)__UINT32_TYPE__ long unsigned intBIT2 (1<<2)INT64_C__ATOMIC_RELAXED 0__ARM_FEATURE_COPROCRCC_BDCR_LSEDRV_LOW 0RCC_CCIPR_CLK48SEL_MASK 0x3__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53RCC_CCIPR_UARTxSEL_SYS RCC_CCIPR_USARTxSEL_SYSCORESIGHT_LSR_SLI (1<<0)BIT5 (1<<5)BIT1 (1<<1)INT8_CGPIO_PORT_H_BASE (PERIPH_BASE_AHB2 + 0x1c00)INT_LEAST32_MAX__ARM_ARCH_EXT_IDIV__ 1SCC_I2C1SCC_I2C2SCC_I2C3__DBL_DECIMAL_DIG__ 17RCC_CSR_MSIRANGE_2MHZ 5BIT8 (1<<8)SCC_FMCCRS_CR_SYNCWARNIE (1 << 1)INT16_C(c) __INT16_C(c)INT32_C(c) __INT32_C(c)RCC_APB1SMENR1_I2C2SMEN (1 << 22)__INT16_MAX__ 0x7fffrcc_periph_clock_enableRCC_BDCR_LSEBYP (1 << 2)TIM15_BASE (PERIPH_BASE_APB2 + 0x4000)RCC_AHB2SMENR_GPIOFSMEN (1 << 5)RCC_CIFR_HSI48RDYF (1 << 10)__INT_WIDTH__ 32__ARM_FEATURE_SIMD32 1RCC_CFGR_MCOPRE_SHIFT 28DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x75e0)RCC_APB1SMENR1_WWDGSMEN (1 << 11)RCC_CR_HSEBYP (1 << 18)SCC_SYSCFG__QQ_FBIT__ 7RCC_CR_PLLSAI2RDY (1 << 29)RTC_BASE (PERIPH_BASE_APB1 + 0x2800)__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64RCC_AHB2RSTR_GPIOGRST (1 << 6)INT16_CRCC_CFGR_PPRE1_SHIFT 8RCC_PLLCFGR_PLLR_MASK 0x3SCC_TSCRCC_APB1RSTR1_TIM7RST (1 << 5)RCC_CICR_CSSC (1 << 8)__ULLFRACT_EPSILON__ 0x1P-64ULLRfalse 0__UINT_LEAST32_MAX__ 0xffffffffUL__SIZEOF_WINT_T__ 4RCC_APB1ENR1_I2C2EN (1 << 22)__ARM_FEATURE_UNALIGNED 1__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17RCC_CFGR_PPRE1_MASK 0x7__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1RCC_USART1__FLT32X_HAS_DENORM__ 1CRS_CFGR_SYNCDIV_DIV16 (4 << CRS_CFGR_SYNCDIV_SHIFT)__ULLACCUM_MIN__ 0.0ULLK__INT_FAST32_WIDTH__ 32RCC_CR_MSIRANGE_200KHZ 1RCC_APB1RSTR1_SPI3RST (1 << 15)RCC_I2C1RCC_I2C2RCC_I2C3CRS_CR_ERRIE (1 << 2)RCC_CCIPR_SWPMI1SEL (1 << 30)__ARM_ASM_SYNTAX_UNIFIED__ 1RCC_BDCR MMIO32(RCC_BASE + 0x90)SCC_TIM4SCC_CRCINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODRCC_APB1ENR1_SPI3EN (1 << 15)RCC_APB2SMENR_TIM16SMEN (1 << 17)RCC_APB1ENR1_I2C1EN (1 << 21)RCC_CFGR_MCOPRE_DIV2 1__ARM_PCS_VFP 1RCC_PLLCFGR_PLLR_SHIFT 25RCC_AHB2RSTR_GPIODRST (1 << 3)__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H RCC_CFGR_SW_HSI16 0x1LPUART1_BASE (PERIPH_BASE_APB1 + 0x8000)RCC_CCIPR_SAI2SEL_SHIFT 24INT_LEAST64_MIN__GCC_CONSTRUCTIVE_SIZE 64RCC_ADC__LLFRACT_IBIT__ 0RCC_APB1SMENR2_SWPMI1SMEN (1 << 2)uint32_tRCC_AHB1SMENR_DMA2SMEN (1 << 1)BIT12 (1<<12)RCC_CFGR_HPRE_DIV128 0xdMPU_BASE (SCS_BASE + 0x0D90)__SACCUM_EPSILON__ 0x1P-7HKRCC_CFGR_PPRE1_DIV4 0x5__GCC_ASM_FLAG_OUTPUTS__ 1RCC_BDCR_LSCOSEL (1 << 25)ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0x75a8))__ARM_FP 4LPTIM2_BASE (PERIPH_BASE_APB1 + 0x9400)RCC_CCIPR_ADCSEL_SHIFT 28__UINT_FAST16_TYPE__ unsigned int__UHA_IBIT__ 8RCC_CCIPR_CLK48SEL_MSI 3__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULK__LDBL_DIG__ 15POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXRCC_AHB1SMENR_OFFSET 0x68BIT16 (1<<16)__WINT_MIN__ 0UINT_LEAST16_MINCRS_CFGR_SYNCDIV (7 << CRS_CFGR_SYNCDIV_SHIFT)__FLT64_DIG__ 15RCC_BDCR_RTCSEL_SHIFT 8__WINT_MAX__ 0xffffffffUBIT22 (1<<22)__INT_LEAST8_WIDTH__ 8RCC_APB1RSTR2 MMIO32(RCC_BASE + RCC_APB1RSTR2_OFFSET)WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)RCC_AHB2SMENR_GPIOBSMEN (1 << 1)__INT_LEAST16_TYPE__ short intRCC_AHB3SMENR_FMCSMEN (1 << 0)RCC_PLLCFGR MMIO32(RCC_BASE + 0x0c)__DBL_MAX__ ((double)1.7976931348623157e+308L)RCC_ICSCR_HSITRIM_SHIFT 24INT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1UINTMAX_CRCC_CFGR_SW_SHIFT 0CRS_ICR MMIO32(CRS_BASE + 0x0c)INT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1RCC_FLASH__HQ_FBIT__ 15__bool_true_false_are_defined 1RCC_BDCR_LSERDY (1 << 1)BIT26 (1<<26)CRS_CFGR_SYNCDIV_DIV4 (2 << CRS_CFGR_SYNCDIV_SHIFT)RCC_BDCR_LSCOEN (1 << 24)__SIZE_MAX__ 0xffffffffUSPI2_BASE (PERIPH_BASE_APB1 + 0x3800)RCC_CFGR_PPRE2_MASK 0x7__ARM_ARCHRCC_CCIPR_SAIxSEL_EXT 3__LONG_MAX__ 0x7fffffffLRCC_APB2RSTR_TIM1RST (1 << 11)RCC_APB1RSTR1_USART2RST (1 << 17)RCC_CCIPR_USART1SEL_MASK 0x3SAI2_BASE (PERIPH_BASE_APB2 + 0x5800)RCC_AHB2RSTR MMIO32(RCC_BASE + RCC_AHB2RSTR_OFFSET)RCC_CFGR_PPRE1_NODIV 0x0__ARM_FEATURE_LDREX 7CRS_ISR_SYNCWARNF (1 << 1)PTRDIFF_MAXRCC_CCIPR MMIO32(RCC_BASE + 0x88)RCC_PLLCFGR_PLLP_DIV7 0RCC_PLLCFGR_PLLN_SHIFT 0x8__LLFRACT_EPSILON__ 0x1P-63LLRRCC_CR_HSIKERON (1 << 9)__SFRACT_MAX__ 0X7FP-7HR__FLT32X_MANT_DIG__ 53RCC_CCIPR_USARTxSEL_MASK 0x3RCC_APB1RSTR1_TIM2RST (1 << 0)__WCHAR_WIDTH__ 32RCC_BDCR_RTCSEL_HSEDIV32 3RCC_CFGR_MCO_LSI 0x6SCC_SRAM1SCC_SRAM2__INT16_C(c) cCRS_ISR_ERRF (1 << 2)SAI1_BASE (PERIPH_BASE_APB2 + 0x5400)INT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32RCC_USART2RCC_USART3RCC_CCIPR_ADCSEL_NONE 0SCC_QSPICRS_CFGR_SYNCPOL (1 << 31)__ATOMIC_ACQ_REL 4RCC_CR_MSIRANGE_24MHZ 9__HQ_IBIT__ 0__DBL_MIN_10_EXP__ (-307)RCC_CFGR_MCO_HSI16 0x3RCC_CCIPR_I2CxSEL_HSI16 2RCC_CFGR_MCO_LSE 0x7RCC_CR_CSSON (1 << 19)RCC_APB2ENR_SPI1EN (1 << 12)RCC_PLLCFGR_PLLSRC_MASK 0x3__FLT32_NORM_MAX__ 3.4028234663852886e+38F32RCC_APB1SMENR1 MMIO32(RCC_BASE + RCC_APB1SMENR1_OFFSET)RCC_APB2SMENR_OFFSET 0x80RCC_CFGR_MCO_SYSCLK 0x1UINT64_C(c) __UINT64_C(c)RCC_APB2RSTR_TIM8RST (1 << 13)RCC_APB2RSTR_TIM16RST (1 << 17)__UINTMAX_MAX__ 0xffffffffffffffffULLRCC_CCIPR_ADCSEL_PLLSAI2R 2__DBL_MANT_DIG__ 53RCC_CFGR_HPRE_DIV2 0x8__ULFRACT_IBIT__ 0CRS_CFGR_SYNCDIV_DIV64 (6 << CRS_CFGR_SYNCDIV_SHIFT)INT_FAST16_MAXITR_BASE (SCS_BASE + 0x0000)RCC_CSR_RMVF (1 << 23)QUADSPI_BANK_BASE (0x90000000U)__INT_MAX__ 0x7fffffff__INT_LEAST64_TYPE__ long long intRCC_AHB1SMENR_CRCSMEN (1 << 12)CRS_CFGR_FELIM_VAL(x) ((x) << CRS_CFGR_FELIM_SHIFT)RCC_CFGR MMIO32(RCC_BASE + 0x08)__ARM_FEATURE_CDE_COPROCRCC_PLLCFGR_PLLP_DIV17 RCC_PLLCFGR_PLLPUINT32_CRCC_CFGR_MCOPRE_DIV16 4GCC: (15:12.2.rel1-1) 12.2.1 20221205˙˙˙˙| 4AŽA3aeabi)7E-M M "ń˙ 0 *, "$&(.?pˇÓ8lĄ -0 Ó4 ëcrs_common_all.c$t$dwm4.0.c5e6bdb01417bb5a599260a3f8c9cb62wm4.common.h.21.c9066c2f6b12c71b40226ea6107829a4wm4.stdint.h.29.6d480f4ba0f60596e88234283d42444fwm4.stdbool.h.29.4a1c88fe569adb8d03217dd16982ca34wm4.common.h.67.5c568a1f62c8e726909b04e29f9e1fc0wm4.memorymap.h.21.8c90486dae5eea2d8efddd23fe5d09d9wm4.memorymap.h.26.bb1efb6ce36cc052fd0489ef5a3533f5wm4.crs_common_all.h.27.8f6af0e2be8d39f7130bfba366c1042bwm4.rcc.h.40.e8c13f444ba606cb63a83dcc96231a47crs_autotrim_usb_enablercc_periph_clock_enable . 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1)INT32_C(c) __INT32_C(c)__GNUC_STDC_INLINE__ 1DAC_DHR12R2_DACC2DHR_SHIFT 0__INT64_C(c) c ## LL__FRACT_FBIT__ 15__LLACCUM_EPSILON__ 0x1P-31LLK__GNUC_PATCHLEVEL__ 1__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2PTRDIFF_MIN__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)UINTPTR_MAX __UINTPTR_MAX____ARM_ARCH_PROFILE 77GPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000)__FLT64_MAX_10_EXP__ 308GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400)MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINLIBOPENCM3_DAC_COMMON_V1_H SDMMC1_BASE (PERIPH_BASE_APB2 + 0x2800)__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38DAC1 DAC_BASETIM6_BASE (PERIPH_BASE_APB1 + 0x1000)__FRACT_MAX__ 0X7FFFP-15RTIM3_BASE (PERIPH_BASE_APB1 + 0x0400)INT_LEAST32_MAX __INT_LEAST32_MAX__DAC_CR_TSEL1_T6 (0x0 << DAC_CR_TSEL1_SHIFT)__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5__UINT16_MAX__ 0xffff__TQ_FBIT__ 127uint16_t__thumb2__ 1__ULLACCUM_FBIT__ 32FMC_QUADSPI_BASE (0xA0000000U)INT_FAST32_MIN (-INT_FAST32_MAX - 1)__STRICT_ANSI__ 1FMC3_BANK_BASE (0x80000000U)UINT_LEAST8_MAXUINT8_C(c) __UINT8_C(c)dac_align__SIZEOF_LONG_DOUBLE__ 8CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)TIM8_BASE (PERIPH_BASE_APB2 + 0x3400)__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX____USA_IBIT__ 16__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1DBGMCU_BASE (PPBI_BASE + 0x00042000)PTRDIFF_MIN (-PTRDIFF_MAX - 1)USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6c00)__UINT_FAST64_TYPE__ long long unsigned intPERIPH_BASE_AHB2 (0x48000000U)DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7590)__FLT_MIN__ 1.1754943508222875e-38F__HA_FBIT__ 7__FDPIC__DAC_SR_DMAUDR2 (1 << 29)__UFRACT_MIN__ 0.0UR__FLT32_IS_IEC_60559__ 2GPIO_PORT_G_BASE (PERIPH_BASE_AHB2 + 0x1800)INT_FAST64_MINDAC_DHR12LD(dac) MMIO32((dac) + 0x24)__USFRACT_IBIT__ 0__LDBL_EPSILON__ 2.2204460492503131e-16L__USFRACT_MIN__ 0.0UHRTSC_BASE (PERIPH_BASE_AHB1 + 0x4000)__ARM_NEON__UINT8_MAX__ 0xff__LDBL_MAX_EXP__ 1024LIBOPENCM3_MEMORYMAP_H DAC_CR_TSEL1_T8 (0x1 << DAC_CR_TSEL1_SHIFT)__DBL_HAS_DENORM__ 1sourcemampQUADSPI_BASE (0xa0001000U)__DA_FBIT__ 31__GXX_ABI_VERSION 1017GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0c00)__INT_LEAST16_MAX__ 0x7fffDAC_CR_TSEL2_SHIFT 19__FLT_DENORM_MIN__ 1.4012984643248171e-45FDAC_DHR12R2(dac) MMIO32((dac) + 0x14)__ULLACCUM_EPSILON__ 0x1P-32ULLKINT_LEAST8_MAX __INT_LEAST8_MAX____UINT32_C(c) c ## ULDAC_CR_TSEL2_T4 (0x5 << DAC_CR_TSEL2_SHIFT)DAC_CR_TSEL2_SW (0x7 << DAC_CR_TSEL2_SHIFT)__UACCUM_MIN__ 0.0UKDAC_DOR2_DACC2DOR_SHIFT 0__FLT_EPSILON__ 1.1920928955078125e-7FTIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)DAC_CR_DMAEN1 (1 << 12)__ARM_ARCH_ISA_THUMBDAC_CR_TSEL1_T5 (0x3 << DAC_CR_TSEL1_SHIFT)__ARM_FEATURE_MATMUL_INT8LIBOPENCM3_CM3_MEMORYMAP_H __GCC_ATOMIC_SHORT_LOCK_FREE 2__USACCUM_FBIT__ 8__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1DAC_DHR12L1_DACC1DHR_MASK 0xFFF__LACCUM_FBIT__ 31SCS_BASE (PPBI_BASE + 0xE000)SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)__FLT32_HAS_QUIET_NAN__ 1I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)DAC_SWTRIGR(dac) MMIO32((dac) + 0x04)__LDBL_HAS_INFINITY__ 1__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))DAC_CR_BOFF1 (1 << 1)__FLT32X_MAX_10_EXP__ 308__ARM_ARCH_EXT_IDIV__ 1bool _BoolUINTMAX_MAX __UINTMAX_MAX____SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffDAC_DHR12L2_DACC2DHR_SHIFT 4BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)INT16_MAX __INT16_MAX____FP_FAST_FMAF 1__FLT32X_IS_IEC_60559__ 2PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)DAC_DHR8RD_DACC1DHR_SHIFT 0LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))FIREWALL_BASE (PERIPH_BASE_APB2 + 0x1C00)__INT_LEAST16_WIDTH__ 16DAC_CR_TSEL1_SHIFT 3SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)__ARM_FEATURE_FP16_FMLDAC_DHR12L2_DACC2DHR_MASK 0xFFFINT16_MIN (-INT16_MAX - 1)__USFRACT_EPSILON__ 0x1P-8UHR__WINT_MAX__ 0xffffffffU__USFRACT_FBIT__ 8CORESIGHT_LSR_SLI (1<<0)DAC_DHR12R2_DACC2DHR_MASK 0xFFF__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX____UINT32_MAX__ 0xffffffffULDAC_DHR12LD_DACC1DHR_MSK 0xFFF__INT_LEAST8_MAX__ 0x7f__GCC_ATOMIC_POINTER_LOCK_FREE 2__ARM_FEATURE_QBIT 1__ARM_FEATURE_CLZ 1__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXDAC_DHR12L1_DACC1DHR_SHIFT 4DAC_DHR8R1_DACC1DHR_MASK 0xFF__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024__UINT_LEAST32_MAX__ 0xffffffffUL__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1__ACCUM_MAX__ 0X7FFFFFFFP-15K__INT8_MAX__ 0x7fBIT14 (1<<14)__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16__SHRT_WIDTH__ 16BIT20 (1<<20)__ARM_FEATURE_MVE__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intSWPMI1_BASE (PERIPH_BASE_APB1 + 0x8800)UINT_LEAST16_MAX __UINT_LEAST16_MAX__INT_FAST32_MIN__FLT_EVAL_METHOD_TS_18661_3__ 0__SCHAR_WIDTH__ 8BIT18 (1<<18)COMP_BASE (PERIPH_BASE_APB2 + 0x0200)SIZE_MAX__UINT_FAST8_TYPE__ unsigned intDAC_SWTRIGR_SWTRIG1 (1 << 0)__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RBIT24 (1<<24)__INT32_MAX__ 0x7fffffffLUINTMAX_MAXBIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_BF16_VECTOR_ARITHMETICINFO_BASE (0x1fff0000U)PPBI_BASE (0xE0000000U)__FLT32_MANT_DIG__ 24INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN__INT8_MAX __INT8_MAX__BIT28 (1<<28)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2DAC_CR(dac) MMIO32((dac) + 0x00)__DBL_MAX_EXP__ 1024__ATOMIC_RELEASE 3UINT_FAST8_MAX__FLT_MANT_DIG__ 24__UDQ_IBIT__ 0TIM1_BASE (PERIPH_BASE_APB2 + 0x2C00)__OPTIMIZE_SIZE__ 1__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UK__FLT64_NORM_MAX__ 1.7976931348623157e+308F64UINTPTR_MAX__LDBL_DENORM_MIN__ 4.9406564584124654e-324L__INT64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_SAT 1__ULLFRACT_IBIT__ 0MMIO16(addr) (*(volatile uint16_t *)(addr))AES_BASE (0x50000000U + 0x60000)dac_wave__GNUC__ 12BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)__FLT32_DIG__ 6WCHAR_MAX__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0UUART5_BASE (PERIPH_BASE_APB1 + 0x5000)__UQQ_IBIT__ 0CORESIGHT_LSR_OFFSET 0xfb4__GCC_ATOMIC_LONG_LOCK_FREE 2__ULACCUM_MIN__ 0.0ULK__LDBL_MAX__ 1.7976931348623157e+308L__ARM_ARCH 7UART4_BASE (PERIPH_BASE_APB1 + 0x4c00)__FLT_RADIX__ 2BIT3 (1<<3)long long intCORESIGHT_LAR_KEY 0xC5ACCE55__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAXchannel__LDBL_HAS_QUIET_NAN__ 1__LONG_LONG_WIDTH__ 64BIT6 (1<<6)DAC_DOR2(dac) MMIO32((dac) + 0x30)__UINT_FAST64_MAX__ 0xffffffffffffffffULLDAC_DHR8R2_DACC2DHR_MASK 0xFF__ARM_FP__HA_IBIT__ 8LIBOPENCM3_DAC_COMMON_ALL_H __INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1BIT9 (1<<9)__FLT32X_MIN__ 2.2250738585072014e-308F32xDAC_CR_TSEL2_T15 (0x3 << DAC_CR_TSEL2_SHIFT)INTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024UINT16_MAX__FLT64_MIN__ 2.2250738585072014e-308F64__INTMAX_C(c) c ## LLDAC_CR_TSEL1_T2 (0x4 << DAC_CR_TSEL1_SHIFT)__ARM_ARCH_PROFILE__INT64_TYPE__ long long int__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4DAC_DHR8RD_DACC2DHR_MSK 0xFFdac_disableDAC_DHR12RD(dac) MMIO32((dac) + 0x20)DAC_DHR12R1_DACC1DHR_MASK 0xFFFCRS_BASE (PERIPH_BASE_APB1 + 0x6000)__UFRACT_MAX__ 0XFFFFP-16URalignINT64_MAXFPB_BASE (PPBI_BASE + 0x2000)DAC_SWTRIGR_SWTRIG2 (1 << 1)INT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0STIR_BASE (SCS_BASE + 0x0F00)__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)ID_BASE (SCS_BASE + 0x0FD0)SYS_TICK_BASE (SCS_BASE + 0x0010)__UFRACT_FBIT__ 16FMC_BASE (0xa0000000U)__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)__LDBL_MAX_10_EXP__ 308DAC_CR_TEN1 (1 << 2)DAC_CR_TSEL1_SW (0x7 << DAC_CR_TSEL1_SHIFT)__INT_FAST32_TYPE__ intunsigned int__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1__USACCUM_IBIT__ 8__ARM_ARCH_7EM__ 1ST_VREFINT_CAL MMIO16((INFO_BASE + 0x75aa))DAC_DOR1(dac) MMIO32((dac) + 0x2C)__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UKDAC_CHANNEL_BOTH (DAC_CHANNEL1 | DAC_CHANNEL2)__UTA_IBIT__ 64__FLT_EVAL_METHOD__ 0__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32DFSDM_BASE (PERIPH_BASE_APB2 + 0x6000)RCC_BASE (PERIPH_BASE_AHB1 + 0x1000)__ARM_FEATURE_LDREXDAC_CR_WAVE2_SHIFT 22__UQQ_FBIT__ 8DAC_DHR8R1_DACC1DHR_SHIFT 0INT16_C__ARM_FP16_ARGS__GCC_IEC_559 0dac_load_data_buffer_dualINT_LEAST16_MAX __INT_LEAST16_MAX____LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4__STDC__ 1__ARM_FEATURE_IDIV 1__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN____UINT8_TYPE__ unsigned charDAC_CR_TSEL1_T7 (0x2 << DAC_CR_TSEL1_SHIFT)__ARM_FEATURE_COPROC 15UINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"DAC_CR_MAMPx_MASK 0xfINT8_MINPERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)DAC_DHR12RD_DACC2DHR_MASK 0xFFF__LDBL_MIN_10_EXP__ (-307)INT_LEAST16_MIN (-INT_LEAST16_MAX - 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1)__UINT8_C(c) c__INT16_TYPE__ short intINFO_BASE (0x1fff0000U)true 1__FLT64_MAX__ 1.7976931348623157e+308F64peripheral_sizeUINT_FAST32_MAXDMA1_CMAR(channel) DMA_CMAR(DMA1, channel)INT_FAST64_MAX __INT_FAST64_MAX____GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1__UINT_LEAST16_MAX__ 0xffff__STDC_HOSTED__ 1__ULLFRACT_FBIT__ 64__SIG_ATOMIC_TYPE__ intDMA2_CNDTR5 DMA2_CNDTR(DMA_CHANNEL5)__INT_FAST64_TYPE__ long long int__WINT_TYPE__ unsigned intGPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800)DMA1_CNDTR2 DMA1_CNDTR(DMA_CHANNEL2)ST_TSENSE_CAL2_110C MMIO16((INFO_BASE + 0x75ca))INT32_MIN (-INT32_MAX - 1)__FLT32_MAX_10_EXP__ 38dma_set_read_from_memoryDMA2_CNDTR2 DMA2_CNDTR(DMA_CHANNEL2)dma_enable_mem2mem_mode__USFRACT_MAX__ 0XFFP-8UHRLPTIM1_BASE (PERIPH_BASE_APB1 + 0x7c00)__FP_FAST_FMAF32 1__UINTPTR_MAX__ 0xffffffffU__FLT32_MIN_EXP__ (-125)DMA1_CPAR7 DMA1_CPAR(DMA_CHANNEL7)DMA1_CNDTR6 DMA1_CNDTR(DMA_CHANNEL6)dma_set_memory_sizeUINT32_MAX __UINT32_MAX____ULFRACT_FBIT__ 32__FLT64_MIN_10_EXP__ (-307)DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF(DMA_CHANNEL7)__GNUC_EXECUTION_CHARSET_NAME "UTF-8"DMA2_CMAR5 DMA2_CMAR(DMA_CHANNEL5)BIT10 (1<<10)__INT_FAST64_WIDTH__ 64__STDC_VERSION__ 199901LINT_LEAST64_MAX __INT_LEAST64_MAX__TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)__SFRACT_EPSILON__ 0x1P-7HRUINT_LEAST16_MAX __UINT_LEAST16_MAX__UINT32_C(c) __UINT32_C(c)__ORDER_BIG_ENDIAN__ 4321SIZE_MAXSYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000)__SQ_FBIT__ 31DMA_CCR_PL_HIGH (0x2 << 12)DWT_BASE (PPBI_BASE + 0x1000)INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)DMA1_CCR(channel) DMA_CCR(DMA1, channel)prioDMA_CHANNEL2 2__UHQ_FBIT__ 16__FLT64_MIN_EXP__ (-1021)ITM_BASE (PPBI_BASE + 0x0000)__PTRDIFF_WIDTH__ 32DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF(DMA_CHANNEL2)DMA_ISR_TEIF3 DMA_ISR_TEIF(DMA_CHANNEL3)__UINT_FAST8_MAX__ 0xffffffffUUINT16_C(c) __UINT16_C(c)DMA_CCR_PINC (1 << 6)__LACCUM_IBIT__ 32DMA_CHANNEL7 7__INT_FAST16_WIDTH__ 32INTMAX_C__VERSION__ "12.2.1 20221205"__VFP_FP__ 1__LLFRACT_MIN__ (-0.5LLR-0.5LLR)INT_FAST8_MAX__UINT_FAST16_MAX__ 0xffffffffU__INTPTR_MAX__ 0x7fffffffINT64_C(c) __INT64_C(c)DMA1_CSELR DMA_CSELR(DMA1)__GCC_IEC_559_COMPLEX 0__UFRACT_MIN__ 0.0URWCHAR_MAX __WCHAR_MAX____FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX____UINT_LEAST8_TYPE__ unsigned char__ACCUM_FBIT__ 15PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)__UACCUM_IBIT__ 16long intUINT8_MAXIWDG_BASE (PERIPH_BASE_APB1 + 0x3000)SIZE_MAX __SIZE_MAX____INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1DMA_ISR_TEIF4 DMA_ISR_TEIF(DMA_CHANNEL4)__FLT32X_EPSILON__ 2.2204460492503131e-16F32xNVIC_BASE (SCS_BASE + 0x0100)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32USART2_BASE (PERIPH_BASE_APB1 + 0x4400)__UINTMAX_C(c) c ## ULL__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed charDMA_CCR_PSIZE_16BIT (0x1 << 8)__GCC_ATOMIC_BOOL_LOCK_FREE 2BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON____FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX____TA_FBIT__ 63__THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRDMA2_CCR5 DMA2_CCR(DMA_CHANNEL5)short unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)BIT7 (1<<7)BIT17 (1<<17)__FLT32X_MIN_10_EXP__ (-307)UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)__DBL_IS_IEC_60559__ 2__UINT_FAST32_MAX__ 0xffffffffU__DEC_EVAL_METHOD__ 2__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4I2C3_BASE (PERIPH_BASE_APB1 + 0x5c00)DMA_ISR_HTIF1 DMA_ISR_HTIF(DMA_CHANNEL1)INTMAX_MAX __INTMAX_MAX____INT_LEAST32_WIDTH__ 32__FLT32X_MIN_EXP__ (-1021)DMA1_BASE (PERIPH_BASE_AHB1 + 0x0000)DMA_IFCR_CIF7 DMA_IFCR_CIF(DMA_CHANNEL7)GNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsBIT27 (1<<27)DMA_IFCR_CTEIF(channel) (DMA_IFCR_CTEIF_BIT << (DMA_FLAG_OFFSET(channel)))TIM1_BASE (PERIPH_BASE_APB2 + 0x2C00)__UTA_FBIT__ 64INTMAX_C(c) __INTMAX_C(c)__FLT_DECIMAL_DIG__ 9__thumb__ 1__INT_LEAST32_MAX__ 0x7fffffffLLIBOPENCM3_MEMORYMAP_COMMON_H signed charuint8_tINT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)DMA_CCR_PL_MASK (0x3 << 12)INT32_C(c) __INT32_C(c)__GNUC_STDC_INLINE__ 1DMA1_IFCR DMA_IFCR(DMA1)DMA1_CPAR6 DMA1_CPAR(DMA_CHANNEL6)__FRACT_FBIT__ 15__LLACCUM_EPSILON__ 0x1P-31LLKDMA_IFCR_CTCIF(channel) (DMA_IFCR_CTCIF_BIT << (DMA_FLAG_OFFSET(channel)))__GNUC_PATCHLEVEL__ 1__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2PTRDIFF_MINdma_disable_peripheral_increment_mode__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)UINTPTR_MAX __UINTPTR_MAX__DMA_ISR_HTIF2 DMA_ISR_HTIF(DMA_CHANNEL2)DMA_CCR_MSIZE_MASK (0x3 << 10)GPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000)__FLT64_MAX_10_EXP__ 308GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400)MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINSDMMC1_BASE (PERIPH_BASE_APB2 + 0x2800)__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)__FRACT_MAX__ 0X7FFFP-15RDMA2_IFCR DMA_IFCR(DMA2)TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)INT_LEAST32_MAX __INT_LEAST32_MAX__DMA2_CMAR3 DMA2_CMAR(DMA_CHANNEL3)__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5DMA_IFCR_CGIF4 DMA_IFCR_CGIF(DMA_CHANNEL4)DMA_HTIF (1 << 2)__UINT16_MAX__ 0xffff__TQ_FBIT__ 127DMA_ISR_TEIF5 DMA_ISR_TEIF(DMA_CHANNEL5)DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF(DMA_CHANNEL6)__USQ_FBIT__ 32INT_FAST16_MINDMA2_CPAR2 DMA2_CPAR(DMA_CHANNEL2)__SIZEOF_SHORT__ 2__ULLACCUM_FBIT__ 32FMC_QUADSPI_BASE (0xA0000000U)DMA2_CPAR(channel) DMA_CPAR(DMA2, channel)_BoolDMA1_CCR3 DMA1_CCR(DMA_CHANNEL3)__FLT_DENORM_MIN__ 1.4012984643248171e-45FINT_FAST32_MIN (-INT_FAST32_MAX - 1)__STRICT_ANSI__ 1FMC3_BANK_BASE (0x80000000U)UINT_LEAST8_MAXUINT8_C(c) __UINT8_C(c)DMA_CCR_MSIZE_SHIFT 10__SIZEOF_LONG_DOUBLE__ 8CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)TIM8_BASE (PERIPH_BASE_APB2 + 0x3400)__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX____USA_IBIT__ 16dma_enable_memory_increment_mode__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1DBGMCU_BASE (PPBI_BASE + 0x00042000)PTRDIFF_MIN (-PTRDIFF_MAX - 1)UART5_BASE (PERIPH_BASE_APB1 + 0x5000)__UINT_FAST64_TYPE__ long long unsigned intPERIPH_BASE_AHB2 (0x48000000U)DMA_CCR_PL_SHIFT 12DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7590)__FLT_MIN__ 1.1754943508222875e-38F__HA_FBIT__ 7__FDPIC____UINT32_C(c) c ## UL__FLT32_IS_IEC_60559__ 2GPIO_PORT_G_BASE (PERIPH_BASE_AHB2 + 0x1800)__HAVE_SPECULATION_SAFE_VALUE 1INT_FAST64_MIN__USFRACT_IBIT__ 0__INT32_C(c) c ## L__LDBL_EPSILON__ 2.2204460492503131e-16L__USFRACT_MIN__ 0.0UHRTSC_BASE (PERIPH_BASE_AHB1 + 0x4000)__ARM_NEON__UINT8_MAX__ 0xffDMA_IFCR_CIF5 DMA_IFCR_CIF(DMA_CHANNEL5)__LDBL_MAX_EXP__ 1024LIBOPENCM3_MEMORYMAP_H DMA2_CSELR DMA_CSELR(DMA2)__DBL_HAS_DENORM__ 1DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)QUADSPI_BASE (0xa0001000U)__DA_FBIT__ 31flagsDMA2_CCR3 DMA2_CCR(DMA_CHANNEL3)__GXX_ABI_VERSION 1017GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0c00)__INT_LEAST16_MAX__ 0x7fffID_BASE (SCS_BASE + 0x0FD0)DMA_IFCR_CGIF2 DMA_IFCR_CGIF(DMA_CHANNEL2)__ULLACCUM_EPSILON__ 0x1P-32ULLKDMA_ISR_TCIF(channel) (DMA_ISR_TCIF_BIT << (DMA_FLAG_OFFSET(channel)))INT_LEAST8_MAX __INT_LEAST8_MAX__DMA_CSELR(dma_base) MMIO32((dma_base) + 0xA8)TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)__UACCUM_MIN__ 0.0UKdma_get_interrupt_flag__FLT_EPSILON__ 1.1920928955078125e-7FDMA_ISR_HTIF4 DMA_ISR_HTIF(DMA_CHANNEL4)DMA_IFCR_CIF6 DMA_IFCR_CIF(DMA_CHANNEL6)__SIZEOF_DOUBLE__ 8DMA2_CPAR4 DMA2_CPAR(DMA_CHANNEL4)__ARM_ARCH_ISA_THUMBDMA1_CMAR1 DMA1_CMAR(DMA_CHANNEL1)DMA_IFCR_CIF(channel) (DMA_IFCR_CIF_BIT << (DMA_FLAG_OFFSET(channel)))__ARM_FEATURE_MATMUL_INT8__UINT8_TYPE__ unsigned charDMA_CMAR(dma_base,channel) MMIO32((dma_base) + 0x14 + (0x14 * ((channel) - 1)))LIBOPENCM3_CM3_MEMORYMAP_H __GCC_ATOMIC_SHORT_LOCK_FREE 2dma_disable_transfer_error_interrupt__USACCUM_FBIT__ 8__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1__LACCUM_FBIT__ 31SCS_BASE (PPBI_BASE + 0xE000)DMA_IFCR_CTEIF_BIT DMA_TEIFSPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)__FLT32_HAS_QUIET_NAN__ 1I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)__LDBL_HAS_INFINITY__ 1dma_enable_transfer_error_interruptUINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))__FLT32X_MAX_10_EXP__ 308DMA_ISR_TCIF7 DMA_ISR_TCIF(DMA_CHANNEL7)__ARM_ARCH_EXT_IDIV__ 1bool _BoolDMA_ISR_TEIF(channel) (DMA_ISR_TEIF_BIT << (DMA_FLAG_OFFSET(channel)))UINTMAX_MAX __UINTMAX_MAX____SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffBBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)INT16_MAX __INT16_MAX__DMA_ISR_HTIF3 DMA_ISR_HTIF(DMA_CHANNEL3)__FP_FAST_FMAF 1__FLT32X_IS_IEC_60559__ 2PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)DMA_ISR_TEIF1 DMA_ISR_TEIF(DMA_CHANNEL1)LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))FIREWALL_BASE (PERIPH_BASE_APB2 + 0x1C00)__INT_LEAST16_WIDTH__ 16SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)__ARM_FEATURE_FP16_FMLDMA1_CNDTR4 DMA1_CNDTR(DMA_CHANNEL4)dma_clear_interrupt_flagsDMA1_CCR6 DMA1_CCR(DMA_CHANNEL6)INT16_MIN (-INT16_MAX - 1)__USFRACT_EPSILON__ 0x1P-8UHRDMA_IFCR_CHTIF(channel) (DMA_IFCR_CHTIF_BIT << (DMA_FLAG_OFFSET(channel)))__WINT_MAX__ 0xffffffffU__USFRACT_FBIT__ 8CORESIGHT_LSR_SLI (1<<0)DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF(DMA_CHANNEL3)dma_disable_half_transfer_interrupt__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX____UINT32_MAX__ 0xffffffffUL__INT_LEAST8_MAX__ 0x7f__GCC_ATOMIC_POINTER_LOCK_FREE 2__ARM_FEATURE_QBIT 1__ARM_FEATURE_CLZ 1__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXDMA_CCR_EN (1 << 0)DMA2_CMAR4 DMA2_CMAR(DMA_CHANNEL4)__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024__UINT_LEAST32_MAX__ 0xffffffffUL__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)DMA2_CNDTR(channel) DMA_CNDTR(DMA2, channel)__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1DMA1_CNDTR7 DMA1_CNDTR(DMA_CHANNEL7)DMA_CCR_PL_MEDIUM (0x1 << 12)DMA2_CNDTR3 DMA2_CNDTR(DMA_CHANNEL3)__ACCUM_MAX__ 0X7FFFFFFFP-15K__INT8_MAX__ 0x7fBIT14 (1<<14)__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16__SHRT_WIDTH__ 16BIT20 (1<<20)__ARM_FEATURE_MVE__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intDMA_ISR_MASK(channel) (DMA_FLAGS << DMA_FLAG_OFFSET(channel))SWPMI1_BASE (PERIPH_BASE_APB1 + 0x8800)SAI1_BASE (PERIPH_BASE_APB2 + 0x5400)INT_FAST32_MIN__FLT_EVAL_METHOD_TS_18661_3__ 0address__SCHAR_WIDTH__ 8BIT18 (1<<18)COMP_BASE (PERIPH_BASE_APB2 + 0x0200)channel__UINT_FAST8_TYPE__ unsigned int__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RBIT24 (1<<24)__INT32_MAX__ 0x7fffffffLUINTMAX_MAXBIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_BF16_VECTOR_ARITHMETICdma_set_priorityPPBI_BASE (0xE0000000U)__FLT32_MANT_DIG__ 24INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN__DMA2_CNDTR4 DMA2_CNDTR(DMA_CHANNEL4)INT8_MAX __INT8_MAX__DMA2_CPAR3 DMA2_CPAR(DMA_CHANNEL3)BIT28 (1<<28)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2DMA_CCR(dma_base,channel) MMIO32((dma_base) + 0x08 + (0x14 * ((channel) - 1)))__DBL_MAX_EXP__ 1024__ATOMIC_RELEASE 3UINT_FAST8_MAX__FLT_MANT_DIG__ 24dma_set_number_of_data__UDQ_IBIT__ 0__INT_LEAST32_TYPE__ long int__OPTIMIZE_SIZE__ 1__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UK__FLT64_NORM_MAX__ 1.7976931348623157e+308F64UINTPTR_MAXDMA_TCIF (1 << 1)DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF(DMA_CHANNEL1)__LDBL_DENORM_MIN__ 4.9406564584124654e-324L__INT64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_SAT 1interrupts__ULLFRACT_IBIT__ 0DMA_ISR_TEIF_BIT DMA_TEIFDMA_FLAG_OFFSET(channel) (4*((channel) - 1))dma_enable_peripheral_increment_modeMMIO16(addr) (*(volatile uint16_t *)(addr))AES_BASE (0x50000000U + 0x60000)DAC_BASE (PERIPH_BASE_APB1 + 0x7400)__GNUC__ 12BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)WCHAR_MAXDMA_IFCR_CIF1 DMA_IFCR_CIF(DMA_CHANNEL1)DMA_IFCR_CIF_BIT 0xFDMA_ISR_TCIF6 DMA_ISR_TCIF(DMA_CHANNEL6)__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0U__UQQ_IBIT__ 0CORESIGHT_LSR_OFFSET 0xfb4__GCC_ATOMIC_LONG_LOCK_FREE 2__ULACCUM_MIN__ 0.0ULK__LDBL_MAX__ 1.7976931348623157e+308L__ARM_ARCH 7__FLT_RADIX__ 2BIT3 (1<<3)long long intCORESIGHT_LAR_KEY 0xC5ACCE55__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAX__LDBL_HAS_QUIET_NAN__ 1__LONG_LONG_WIDTH__ 64BIT6 (1<<6)DMA1_CCR2 DMA1_CCR(DMA_CHANNEL2)DMA_IFCR_CGIF1 DMA_IFCR_CGIF(DMA_CHANNEL1)DMA_ISR_TCIF2 DMA_ISR_TCIF(DMA_CHANNEL2)__UINT_FAST64_MAX__ 0xffffffffffffffffULL__ARM_FP__HA_IBIT__ 8__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1BIT9 (1<<9)__FLT32X_MIN__ 2.2250738585072014e-308F32xdma_set_peripheral_size__FLT64_MAX_EXP__ 1024UINT16_MAXDMA_CHANNEL4 4__FLT64_MIN__ 2.2250738585072014e-308F64__INTMAX_C(c) c ## LLdma_disable_transfer_complete_interruptDMA1_CPAR1 DMA1_CPAR(DMA_CHANNEL1)__ARM_ARCH_PROFILE__INT64_TYPE__ long long int__LFRACT_FBIT__ 31__CHAR_BIT__ 8interrupt__SIZEOF_WCHAR_T__ 4DMA1_CMAR2 DMA1_CMAR(DMA_CHANNEL2)DMA_CCR_MEM2MEM (1 << 14)CRS_BASE (PERIPH_BASE_APB1 + 0x6000)__UFRACT_MAX__ 0XFFFFP-16URINT64_MAXFPB_BASE (PPBI_BASE + 0x2000)DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF(DMA_CHANNEL2)INT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0dma_enable_transfer_complete_interrupt__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)SYS_TICK_BASE (SCS_BASE + 0x0010)DMA_IFCR_CGIF_BIT DMA_GIF__UFRACT_FBIT__ 16FMC_BASE (0xa0000000U)__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF(DMA_CHANNEL4)__LDBL_MAX_10_EXP__ 308DMA_FLAGS (DMA_TEIF | DMA_TCIF | DMA_HTIF | DMA_GIF)DMA_ISR(dma_base) MMIO32((dma_base) + 0x00)DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF(DMA_CHANNEL1)DMA_CCR_PL_LOW (0x0 << 12)__INT_FAST32_TYPE__ intunsigned intDMA_IFCR_CTCIF7 DMA_IFCR_CTCIF(DMA_CHANNEL7)__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1DMA_IFCR_CIF3 DMA_IFCR_CIF(DMA_CHANNEL3)DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF(DMA_CHANNEL3)__USACCUM_IBIT__ 8__ARM_ARCH_7EM__ 1ST_VREFINT_CAL MMIO16((INFO_BASE + 0x75aa))__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UK__UTA_IBIT__ 64__FLT_EVAL_METHOD__ 0DMA_CCR_MINC (1 << 7)__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32DMA_IFCR(dma_base) MMIO32((dma_base) + 0x04)DFSDM_BASE (PERIPH_BASE_APB2 + 0x6000)RCC_BASE (PERIPH_BASE_AHB1 + 0x1000)__ARM_FEATURE_LDREX../common/dma_common_l1f013.c__UQQ_FBIT__ 8INT16_Cflag__ARM_FP16_ARGS__GCC_IEC_559 0INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX__DMA_GIF (1 << 0)__LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4__STDC__ 1__ARM_FEATURE_IDIV 1__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__dma_disable_channel__ARM_FEATURE_COPROC 15UINT64_MAX __UINT64_MAX__USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6c00)INT8_MINDMA_CCR_CIRC (1 << 5)DMA_IFCR_CGIF3 DMA_IFCR_CGIF(DMA_CHANNEL3)PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)LIBOPENCM3_DMA_H __USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)__LDBL_MIN_10_EXP__ (-307)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1DMA_CSELR_CxS_SHIFT(channel) (4 * ((channel) - 1))__GCC_ATOMIC_CHAR_LOCK_FREE 2__LFRACT_EPSILON__ 0x1P-31LRFMC1_BANK_BASE (0x60000000U)STM32L4 1DMA1_CNDTR(channel) DMA_CNDTR(DMA1, channel)DMA_ISR_TCIF5 DMA_ISR_TCIF(DMA_CHANNEL5)__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX____FLT32X_NORM_MAX__ 1.7976931348623157e+308F32x__arm__ 1DMA_ISR_GIF(channel) (DMA_ISR_GIF_BIT << (DMA_FLAG_OFFSET(channel)))DMA_CHANNEL3 3DMA_IFCR_CGIF7 DMA_IFCR_CGIF(DMA_CHANNEL7)__FLT32_MIN_10_EXP__ (-37)MMIO64(addr) (*(volatile uint64_t *)(addr))DMA_TEIF (1 << 3)__ARM_FP16_FORMAT_ALTERNATIVE__LDBL_NORM_MAX__ 1.7976931348623157e+308LINTPTR_MINDESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)__ARM_ARCH_PROFILE 77__SACCUM_IBIT__ 8__ARM_FEATURE_QRDMX__ARM_ARCH_ISA_THUMB 2DMA_ISR_TEIF2 DMA_ISR_TEIF(DMA_CHANNEL2)__LONG_LONG_MAX__ 0x7fffffffffffffffLL__WINT_WIDTH__ 32SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__STIR_BASE (SCS_BASE + 0x0F00)UINT_LEAST16_MAX__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN____SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)DMA_ISR_TCIF1 DMA_ISR_TCIF(DMA_CHANNEL1)__DBL_MIN_EXP__ (-1021)__LDBL_HAS_DENORM__ 1INT8_MIN (-INT8_MAX - 1)__FLT32_DIG__ 6INT_LEAST16_MAXBIT15 (1<<15)DMA_ISR_GIF_BIT DMA_GIFVREFBUF_BASE (PERIPH_BASE_APB2 + 0x0030)BIT21 (1<<21)PERIPH_BASE (0x40000000U)__SACCUM_FBIT__ 7__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1INT32_MAX__ACCUM_MIN__ (-0X1P15K-0X1P15K)__ARM_FEATURE_CRYPTOUART4_BASE (PERIPH_BASE_APB1 + 0x4c00)DMA2 DMA2_BASEBIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__FRACT_IBIT__ 0UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234ADC1_BASE (0x50000000U + 0x40000)__FLT_NORM_MAX__ 3.4028234663852886e+38FDMA_IFCR_CGIF5 DMA_IFCR_CGIF(DMA_CHANNEL5)long long unsigned int__FLT_MIN_10_EXP__ (-37)GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000)__ULACCUM_IBIT__ 32__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__PTRDIFF_TYPE__ int__APCS_32__ 1__DQ_FBIT__ 63INT_LEAST64_MAXuint16_tDMA_CCR_PSIZE_32BIT (0x2 << 8)__UHQ_IBIT__ 0dma_disable_memory_increment_modeINT_LEAST8_MINBIT29 (1<<29)__INT_FAST16_TYPE__ intINT64_C__ULFRACT_MAX__ 0XFFFFFFFFP-32ULR__UINT_LEAST16_TYPE__ short unsigned intDMA_CNDTR(dma_base,channel) MMIO32((dma_base) + 0x0C + (0x14 * ((channel) - 1)))__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned int__FLT32X_DIG__ 15DMA2_CCR2 DMA2_CCR(DMA_CHANNEL2)__UTQ_FBIT__ 128__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffffDMA_CHANNEL5 5DMA2_BASE (PERIPH_BASE_AHB1 + 0x0400)PTRDIFF_MAX __PTRDIFF_MAX__DMA1_CMAR3 DMA1_CMAR(DMA_CHANNEL3)DMA1_CNDTR3 DMA1_CNDTR(DMA_CHANNEL3)UINT_FAST16_MAX__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKDMA_ISR_TCIF3 DMA_ISR_TCIF(DMA_CHANNEL3)UINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRDMA_IFCR_CTCIF6 DMA_IFCR_CTCIF(DMA_CHANNEL6)__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intWCHAR_MINdma_enable_circular_modeDMA1_CPAR2 DMA1_CPAR(DMA_CHANNEL2)BEGIN_DECLS DMA_ISR_TCIF4 DMA_ISR_TCIF(DMA_CHANNEL4)DMA1_CNDTR1 DMA1_CNDTR(DMA_CHANNEL1)__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__FLT32X_MAX__ 1.7976931348623157e+308F32xGPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400)DMA_ISR_HTIF_BIT DMA_HTIF__ARM_EABI__ 1DMA_ISR_HTIF7 DMA_ISR_HTIF(DMA_CHANNEL7)INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1DMA_CCR_DIR (1 << 4)__ARM_FEATURE_DSP 1DMA1 DMA1_BASEDMA_ISR_GIF4 DMA_ISR_GIF(DMA_CHANNEL4)TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)__QQ_IBIT__ 0DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF(DMA_CHANNEL2)__LLACCUM_FBIT__ 31LIBOPENCM3_DMA_COMMON_F13_H __UINTMAX_TYPE__ long long unsigned intDESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 0x14)__USQ_IBIT__ 0__UINT_LEAST32_TYPE__ long unsigned intnumber__ARM_FEATURE_NUMERIC_MAXMIN__INTMAX_TYPE__ long long int__GCC_ATOMIC_INT_LOCK_FREE 2DMA1_CCR5 DMA1_CCR(DMA_CHANNEL5)TIM16_BASE (PERIPH_BASE_APB2 + 0x4400)DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF(DMA_CHANNEL5)INTMAX_MAXDESIG_PACKAGE MMIO16((INFO_BASE + 0x7500))__ARM_FEATURE_FP16_SCALAR_ARITHMETIC__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1TIM17_BASE (PERIPH_BASE_APB2 + 0x4800)__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CDMA2_CPAR5 DMA2_CPAR(DMA_CHANNEL5)INT64_MINdma_set_memory_address__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intDMA_ISR_GIF6 DMA_ISR_GIF(DMA_CHANNEL6)UINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRDMA1_CMAR5 DMA1_CMAR(DMA_CHANNEL5)/build/libopencm3/lib/stm32/l4__SIZEOF_SIZE_T__ 4__UINT64_TYPE__ long long unsigned int__INT64_C(c) c ## LLDMA2_CNDTR1 DMA2_CNDTR(DMA_CHANNEL1)DMA_IFCR_CTCIF_BIT DMA_TCIFUSART1_BASE (PERIPH_BASE_APB2 + 0x3800)USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x6800)dma_enable_channelTPIU_BASE (PPBI_BASE + 0x40000)DMA_CHANNEL1 1__LDBL_MIN__ 2.2250738585072014e-308LDMA_ISR_GIF3 DMA_ISR_GIF(DMA_CHANNEL3)__ARM_FEATURE_CDE__ACCUM_IBIT__ 16DMA2_ISR DMA_ISR(DMA2)dma_channel_reset__GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"CORESIGHT_LAR_OFFSET 0xfb0EXTI_BASE (PERIPH_BASE_APB2 + 0x0400)DMA_IFCR_CHTIF_BIT DMA_HTIFDMA1_CPAR4 DMA1_CPAR(DMA_CHANNEL4)FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000)short intRNG_BASE (0x50000000U + 0x60800)DMA2_CCR1 DMA2_CCR(DMA_CHANNEL1)__UINT16_C(c) cBIT31 (1<<31)__UDA_IBIT__ 32DMA1_ISR DMA_ISR(DMA1)DMA_CCR_MSIZE_32BIT (0x2 << 10)UINT_LEAST32_MAXDMA2_CMAR(channel) DMA_CMAR(DMA2, channel)BIT2 (1<<2)__ATOMIC_RELAXED 0__ARM_FEATURE_COPROCDMA_IFCR_CHTIF5 DMA_IFCR_CHTIF(DMA_CHANNEL5)__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53DMA_IFCR_CIF2 DMA_IFCR_CIF(DMA_CHANNEL2)BIT5 (1<<5)BIT1 (1<<1)DMA1_CPAR(channel) DMA_CPAR(DMA1, channel)INT8_CGPIO_PORT_H_BASE (PERIPH_BASE_AHB2 + 0x1c00)INT_LEAST32_MAXDMA2_CMAR1 DMA2_CMAR(DMA_CHANNEL1)__USES_INITFINI__ 1DMA_CCR_TCIE (1 << 1)__DBL_DECIMAL_DIG__ 17DMA_IFCR_CGIF6 DMA_IFCR_CGIF(DMA_CHANNEL6)DMA_ISR_GIF1 DMA_ISR_GIF(DMA_CHANNEL1)BIT8 (1<<8)DMA_CCR_MSIZE_8BIT (0x0 << 10)INT16_C(c) __INT16_C(c)DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF(DMA_CHANNEL7)UINT32_MAX__INT16_MAX__ 0x7fff__INT_WIDTH__ 32__ARM_FEATURE_SIMD32 1DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x75e0)DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF(DMA_CHANNEL1)__QQ_FBIT__ 7DMA_ISR_GIF2 DMA_ISR_GIF(DMA_CHANNEL2)RTC_BASE (PERIPH_BASE_APB1 + 0x2800)__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64LPTIM2_BASE (PERIPH_BASE_APB1 + 0x9400)__ULLACCUM_IBIT__ 32DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF(DMA_CHANNEL3)__ULLFRACT_EPSILON__ 0x1P-64ULLRfalse 0__SIZEOF_WINT_T__ 4DMA_CPAR(dma_base,channel) MMIO32((dma_base) + 0x10 + (0x14 * ((channel) - 1)))__ARM_FEATURE_UNALIGNED 1__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17DMA1_CMAR4 DMA1_CMAR(DMA_CHANNEL4)DMA1_CMAR7 DMA1_CMAR(DMA_CHANNEL7)__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1__FLT32X_HAS_DENORM__ 1__ULLACCUM_MIN__ 0.0ULLK__INT_FAST32_WIDTH__ 32DMA1_CPAR3 DMA1_CPAR(DMA_CHANNEL3)__TA_IBIT__ 64DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF(DMA_CHANNEL5)DMA_CCR_PSIZE_SHIFT 8__ARM_ASM_SYNTAX_UNIFIED__ 1__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPROD__thumb2__ 1__ARM_PCS_VFP 1__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H LPUART1_BASE (PERIPH_BASE_APB1 + 0x8000)INT_LEAST64_MIN__GCC_CONSTRUCTIVE_SIZE 64__LLFRACT_IBIT__ 0mem_sizeuint32_tBIT12 (1<<12)DMA_ISR_TEIF6 DMA_ISR_TEIF(DMA_CHANNEL6)DMA2_CCR4 DMA2_CCR(DMA_CHANNEL4)MPU_BASE (SCS_BASE + 0x0D90)__SACCUM_EPSILON__ 0x1P-7HK__GCC_ASM_FLAG_OUTPUTS__ 1ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0x75a8))__ARM_FP 4dma_enable_half_transfer_interrupt__UINT_FAST16_TYPE__ unsigned int__UHA_IBIT__ 8__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULKdma_get_number_of_data__LDBL_DIG__ 15POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXBIT16 (1<<16)DMA_CHANNEL6 6__WINT_MIN__ 0UINT_LEAST16_MIN__FLT64_DIG__ 15TIM15_BASE (PERIPH_BASE_APB2 + 0x4000)BIT22 (1<<22)__INT_LEAST8_WIDTH__ 8DMA_ISR_HTIF(channel) (DMA_ISR_HTIF_BIT << (DMA_FLAG_OFFSET(channel)))WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)__INT_LEAST16_TYPE__ short int__DBL_MAX__ ((double)1.7976931348623157e+308L)INT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1UINTMAX_CINT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1DMA_ISR_GIF7 DMA_ISR_GIF(DMA_CHANNEL7)__HQ_FBIT__ 15__bool_true_false_are_defined 1DMA_ISR_TEIF7 DMA_ISR_TEIF(DMA_CHANNEL7)BIT26 (1<<26)__SIZE_MAX__ 0xffffffffUSPI2_BASE (PERIPH_BASE_APB1 + 0x3800)DMA_IFCR_CGIF(channel) (DMA_IFCR_CGIF_BIT << (DMA_FLAG_OFFSET(channel)))__ARM_ARCH__LONG_MAX__ 0x7fffffffLDMA_CCR_TEIE (1 << 3)DMA_CCR_MSIZE_16BIT (0x1 << 10)SAI2_BASE (PERIPH_BASE_APB2 + 0x5800)DMA_CCR_PSIZE_MASK (0x3 << 8)__ARM_FEATURE_LDREX 7PTRDIFF_MAXDMA_CSELR_CxS_MASK (0x0f)DMA2_CCR(channel) DMA_CCR(DMA2, channel)__LLFRACT_EPSILON__ 0x1P-63LLR__SFRACT_MAX__ 0X7FP-7HR__FLT32X_MANT_DIG__ 53__WCHAR_WIDTH__ 32WINT_MAX__INT16_C(c) cINT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32DMA1_CCR4 DMA1_CCR(DMA_CHANNEL4)__ATOMIC_ACQ_REL 4DMA1_CCR7 DMA1_CCR(DMA_CHANNEL7)__HQ_IBIT__ 0__DBL_MIN_10_EXP__ (-307)DMA1_CCR1 DMA1_CCR(DMA_CHANNEL1)DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF(DMA_CHANNEL4)DMA_IFCR_CIF4 DMA_IFCR_CIF(DMA_CHANNEL4)__FLT32_NORM_MAX__ 3.4028234663852886e+38F32BIT11 (1<<11)UINT64_C(c) __UINT64_C(c)__UINTMAX_MAX__ 0xffffffffffffffffULLDMA1_CNDTR5 DMA1_CNDTR(DMA_CHANNEL5)__DBL_MANT_DIG__ 53DMA_CCR_PL_VERY_HIGH (0x3 << 12)__ULFRACT_IBIT__ 0INT_FAST16_MAXITR_BASE (SCS_BASE + 0x0000)QUADSPI_BANK_BASE (0x90000000U)__INT_MAX__ 0x7fffffff__INT_LEAST64_TYPE__ long long intDMA1_CMAR6 DMA1_CMAR(DMA_CHANNEL6)__ARM_FEATURE_CDE_COPROCDMA_IFCR_CHTIF6 DMA_IFCR_CHTIF(DMA_CHANNEL6)UINT32_CGCC: (15:12.2.rel1-1) 12.2.1 20221205˙˙˙˙| A3aeabi)7E-M M "ń˙ !!""##$$%%&&')*,.0DF2468:<>@BH?pˇÓ8l¨ GJ â ô %=Nbz›˝â!>W{ Ăç 6!I"]#x$Ź%¦&dma_common_l1f013.c$twm4.0.c5e6bdb01417bb5a599260a3f8c9cb62wm4.common.h.21.c9066c2f6b12c71b40226ea6107829a4wm4.stdint.h.29.6d480f4ba0f60596e88234283d42444fwm4.stdbool.h.29.4a1c88fe569adb8d03217dd16982ca34wm4.common.h.67.5c568a1f62c8e726909b04e29f9e1fc0wm4.memorymap.h.21.8c90486dae5eea2d8efddd23fe5d09d9wm4.memorymap.h.26.bb1efb6ce36cc052fd0489ef5a3533f5wm4.dma_common_l1f013.h.40.d146a609b72d90beef1aca4a3724028bwm4.dma_common_csel.h.33.10bcdc1d66140fa425c6f7a4cd4745fedma_channel_resetdma_clear_interrupt_flagsdma_get_interrupt_flagdma_enable_mem2mem_modedma_set_prioritydma_set_memory_sizedma_set_peripheral_sizedma_enable_memory_increment_modedma_disable_memory_increment_modedma_enable_peripheral_increment_modedma_disable_peripheral_increment_modedma_enable_circular_modedma_set_read_from_peripheraldma_set_read_from_memorydma_enable_transfer_error_interruptdma_disable_transfer_error_interruptdma_enable_half_transfer_interruptdma_disable_half_transfer_interruptdma_enable_transfer_complete_interruptdma_disable_transfer_complete_interruptdma_enable_channeldma_disable_channeldma_set_peripheral_addressdma_set_memory_addressdma_get_number_of_datadma_set_number_of_data: @@@="?&>-@4@;@B@G@T@Y@f@k@x@@Ť@’@7˛;¶;»@Ć;Ę;Ď@Ţ@ę5;; @;;"@(3B;F;K@V;Z;_@n@t1Ž;’;—@˘;¦;«@ş@Ŕ/Ú;Ţ;ă@î;ň;ř@ţ-;;!@,;0;6@<+V;Z;_@j;n;t@z)”;;ť@¨;¬;˛@¸'Ň;Ö;Ű@ć;ę;đ@ö%;;@$;(;.@4#N;R;W@b;f;l@r!Ś;;•@ ;¤;Ş@°Ę;Î;Ó@Ţ;â;č@î;;@; ;&@+D;H;M@W;[;a@f;;@’;–;ś@ˇş;ľ;Ă@Í;Ń;×@Üő;ů;ţ@;;@0;4;9@C;G;M@Rk;o;t@~;‚;‡@•@šł;·;Ľ@Ć;Ę;Ď@Ý@â ű;˙;@;;@%@*C;G;L@V;Z;`@k „;;Ť@—;›; @Ş;®;ł@Ľ;Ŕ;Č@Í@Ňî@ř;ü;@;;@;!;'@.F@P;T;7'7@5^5u3Ś3Ł1ş1Ń/ç/ţ--++A+X)n)…'›'˛%Č%ß#ő#!"!9Of|“©ŔÖí0G]tŠˇ·Î ä ű( ? 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64__ARM_FEATURE_BF16_SCALAR_ARITHMETIC__SQ_IBIT__ 0__ORDER_PDP_ENDIAN__ 3412__SIZE_TYPE__ unsigned intGPIO10 (1 << 10)__FLT_HAS_DENORM__ 1__INT8_TYPE__ signed char__ARM_ARCH_PROFILE 77__USACCUM_MIN__ 0.0UHKGPIOB_ASCR GPIO_ASCR(GPIOB)__FLT32_DECIMAL_DIG__ 9__DECIMAL_DIG__ 17__LDBL_MIN_EXP__ (-1021)GPIOI_PUPDR GPIO_PUPDR(GPIOI)__LDBL_MANT_DIG__ 53INT64_MIN (-INT64_MAX - 1)GPIOJ GPIO_PORT_J_BASESYSCFG_EXTICR_GPIOE 4__UINT8_C(c) c__INT16_TYPE__ short inttrue 1__FLT64_MAX__ 1.7976931348623157e+308F64GPIOE_ASCR GPIO_ASCR(GPIOE)UINT_FAST32_MAXGPIOF_ODR GPIO_ODR(GPIOF)GPIO_BSRR(port) MMIO32((port) + 0x18)GPIO5 (1 << 5)GPIOI_AFRH GPIO_AFRH(GPIOI)INT_FAST64_MAX __INT_FAST64_MAX____GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1SYSCFG_CFGR2_PVDL (1 << 2)GPIOC_PUPDR GPIO_PUPDR(GPIOC)__UINT_LEAST16_MAX__ 0xffff__STDC_HOSTED__ 1__ULLFRACT_FBIT__ 64__SIG_ATOMIC_TYPE__ intGPIOC_AFRL GPIO_AFRL(GPIOC)__INT_FAST64_TYPE__ long long int__WINT_TYPE__ unsigned intGPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800)ST_TSENSE_CAL2_110C MMIO16((INFO_BASE + 0x75ca))exti_select_sourceINT32_MIN (-INT32_MAX - 1)__FLT32_MAX_10_EXP__ 38GPIO0 (1 << 0)GPIOG_BSRR GPIO_BSRR(GPIOG)__USFRACT_MAX__ 0XFFP-8UHRLPTIM1_BASE (PERIPH_BASE_APB1 + 0x7c00)__FP_FAST_FMAF32 1GPIOH GPIO_PORT_H_BASE__UINTPTR_MAX__ 0xffffffffUGPIO_AF8 0x8__FLT32_MIN_EXP__ (-125)UINT32_MAX __UINT32_MAX__GPIO_MODE_AF 0x2EXTI32 (1 << 0)__ULFRACT_FBIT__ 32__FLT64_MIN_10_EXP__ (-307)__GNUC_EXECUTION_CHARSET_NAME "UTF-8"BIT10 (1<<10)__INT_FAST64_WIDTH__ 64__STDC_VERSION__ 199901LINT_LEAST64_MAX __INT_LEAST64_MAX__GPIOE_LCKR GPIO_LCKR(GPIOE)EXTI_EMR MMIO32(EXTI_BASE + 0x04)__SFRACT_EPSILON__ 0x1P-7HRexti_trigger_typeGPIOK_MODER GPIO_MODER(GPIOK)UINT_LEAST16_MAX __UINT_LEAST16_MAX__UINT32_C(c) __UINT32_C(c)__ORDER_BIG_ENDIAN__ 4321I2C3_BASE (PERIPH_BASE_APB1 + 0x5c00)SYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000)__SQ_FBIT__ 31GPIOI_IDR GPIO_IDR(GPIOI)DWT_BASE (PPBI_BASE + 0x1000)INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)__TQ_IBIT__ 0__UHQ_FBIT__ 16__FLT64_MIN_EXP__ (-1021)GPIOK_OTYPER GPIO_OTYPER(GPIOK)__PTRDIFF_WIDTH__ 32__UINT_FAST8_MAX__ 0xffffffffUUINT16_C(c) __UINT16_C(c)__LACCUM_IBIT__ 32extiGPIO_AF10 0xa__INT_FAST16_WIDTH__ 32LIBOPENCM3_EXTI_COMMON_ALL_H INTMAX_C__VFP_FP__ 1__LLFRACT_MIN__ (-0.5LLR-0.5LLR)INT_FAST8_MAX__UINT_FAST16_MAX__ 0xffffffffU__INTPTR_MAX__ 0x7fffffffINT64_C(c) __INT64_C(c)__GCC_IEC_559_COMPLEX 0__UFRACT_MIN__ 0.0URWCHAR_MAX __WCHAR_MAX____FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX__GPIOI_OTYPER GPIO_OTYPER(GPIOI)__UINT_LEAST8_TYPE__ unsigned char__ACCUM_FBIT__ 15PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)LIBOPENCM3_GPIO_COMMON_ALL_H __UACCUM_IBIT__ 16long intUINT8_MAXIWDG_BASE (PERIPH_BASE_APB1 + 0x3000)SIZE_MAX __SIZE_MAX__SYSCFG_SKR MMIO32(SYSCFG_BASE + 0x24)GPIOH_AFRH GPIO_AFRH(GPIOH)__INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1GPIO9 (1 << 9)__FLT32X_EPSILON__ 2.2204460492503131e-16F32xEXTI0 (1 << 0)GPIOH_OSPEEDR GPIO_OSPEEDR(GPIOH)NVIC_BASE (SCS_BASE + 0x0100)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32USART2_BASE (PERIPH_BASE_APB1 + 0x4400)__UINTMAX_C(c) c ## ULL__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed charGPIOJ_AFRL GPIO_AFRL(GPIOJ)GPIOJ_OTYPER GPIO_OTYPER(GPIOJ)__GCC_ATOMIC_BOOL_LOCK_FREE 2BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON__GPIO_AF1 0x1__FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX____THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLR__FLT64_DECIMAL_DIG__ 17shiftshort unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)BIT7 (1<<7)BIT17 (1<<17)__FLT32X_MIN_10_EXP__ (-307)UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)__DBL_IS_IEC_60559__ 2__UINT_FAST32_MAX__ 0xffffffffU__DEC_EVAL_METHOD__ 2__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4SYSCFG_EXTICR_GPIOB 1__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32DMA1_BASE (PERIPH_BASE_AHB1 + 0x0000)GPIO_AF9 0x9GPIOB_PUPDR GPIO_PUPDR(GPIOB)GNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsBIT27 (1<<27)TIM1_BASE (PERIPH_BASE_APB2 + 0x2C00)GPIOH_ODR GPIO_ODR(GPIOH)__UTA_FBIT__ 64INTMAX_C(c) __INTMAX_C(c)__FLT_DECIMAL_DIG__ 9__thumb__ 1__INT_LEAST32_MAX__ 0x7fffffffL__VERSION__ "12.2.1 20221205"uint8_tINT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)SYSCFG_SCSR_SRAM2ER (1 << 0)INT32_C(c) __INT32_C(c)__GNUC_STDC_INLINE__ 1GPIOE_BRR GPIO_BRR(GPIOE)GPIO_PUPD_PULLUP 0x1__INT64_C(c) c ## LL__FRACT_FBIT__ 15__LLACCUM_EPSILON__ 0x1P-31LLK__GNUC_PATCHLEVEL__ 1__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2PTRDIFF_MINSYSCFG_EXTICR(i) MMIO32(SYSCFG_BASE + 0x08 + (i)*4)__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)exti_get_flag_statusUINTPTR_MAX __UINTPTR_MAX__SYSCFG_CFGR1_I2C_PB6_FMP (1 << 16)INT32_MAXGPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000)__FLT64_MAX_10_EXP__ 308GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400)MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINEXTI_TRIGGER_RISINGSDMMC1_BASE (PERIPH_BASE_APB2 + 0x2800)__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)__FRACT_MAX__ 0X7FFFP-15RTIM3_BASE (PERIPH_BASE_APB1 + 0x0400)INT_LEAST32_MAX __INT_LEAST32_MAX__SYSCFG_CFGR2_ECCL (1 << 3)__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5GPIO2 (1 << 2)GPIO_ASCR(port) MMIO32((port) + 0x2c)GPIO_AF7 0x7GPIO11 (1 << 11)EXTI24 (1 << 24)__UINT16_MAX__ 0xffff__TQ_FBIT__ 127SYSCFG_EXTICR_GPIOA 0GPIOJ_PUPDR GPIO_PUPDR(GPIOJ)EXTI11 (1 << 11)__USQ_FBIT__ 32INT_FAST16_MIN__thumb2__ 1__ULLACCUM_FBIT__ 32FMC_QUADSPI_BASE (0xA0000000U)EXTI25 (1 << 25)__FLT_DENORM_MIN__ 1.4012984643248171e-45FINT_FAST32_MIN (-INT_FAST32_MAX - 1)__STRICT_ANSI__ 1FMC3_BANK_BASE (0x80000000U)UINT_LEAST8_MAXGPIOG_AFRH GPIO_AFRH(GPIOG)UINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)TIM8_BASE (PERIPH_BASE_APB2 + 0x3400)GPIO_OTYPER(port) MMIO32((port) + 0x04)__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__GPIOD_PUPDR GPIO_PUPDR(GPIOD)__USA_IBIT__ 16__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1EXTI6 (1 << 6)PTRDIFF_MIN (-PTRDIFF_MAX - 1)USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6c00)SYSCFG_MEMRMP_MEM_MODE_SYSTEM 1__UINT_FAST64_TYPE__ long long unsigned intDESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 0x14)GPIOG_AFRL GPIO_AFRL(GPIOG)exti_disable_request__FLT_MIN__ 1.1754943508222875e-38FGPIOG_ODR GPIO_ODR(GPIOG)__HA_FBIT__ 7GPIOD_ASCR GPIO_ASCR(GPIOD)__FDPIC____FLT32_IS_IEC_60559__ 2GPIOI_OSPEEDR GPIO_OSPEEDR(GPIOI)GPIO_PORT_G_BASE (PERIPH_BASE_AHB2 + 0x1800)__HAVE_SPECULATION_SAFE_VALUE 1INT_FAST64_MIN__USFRACT_IBIT__ 0__INT32_C(c) c ## L__LDBL_EPSILON__ 2.2204460492503131e-16LGPIOB_MODER GPIO_MODER(GPIOB)__USFRACT_MIN__ 0.0UHRTSC_BASE (PERIPH_BASE_AHB1 + 0x4000)__ARM_NEON__UINT8_MAX__ 0xff__LDBL_MAX_EXP__ 1024LIBOPENCM3_MEMORYMAP_H GPIOK_BSRR GPIO_BSRR(GPIOK)__DBL_HAS_DENORM__ 1DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)GPIO8 (1 << 8)GPIO_OSPEED_LOW 0x0GPIOB_AFRL GPIO_AFRL(GPIOB)QUADSPI_BASE (0xa0001000U)__DA_FBIT__ 31__GXX_ABI_VERSION 1017GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0c00)__INT_LEAST16_MAX__ 0x7fffGPIOI GPIO_PORT_I_BASEID_BASE (SCS_BASE + 0x0FD0)__LDBL_MAX__ 1.7976931348623157e+308LGPIOJ_IDR GPIO_IDR(GPIOJ)GPIOC_ODR GPIO_ODR(GPIOC)GPIOA_LCKR GPIO_LCKR(GPIOA)exti_enable_requestINT_LEAST8_MAX __INT_LEAST8_MAX__GPIOK_ODR GPIO_ODR(GPIOK)__UINT32_C(c) c ## ULEXTI19 (1 << 19)__UACCUM_MIN__ 0.0UKSYSCFG_EXTICR2 SYSCFG_EXTICR(1)__FLT_EPSILON__ 1.1920928955078125e-7FGPIO_MODE_MASK(n) (0x3 << (2 * (n)))GPIO_AF0 0x0SYSCFG_CFGR1_I2C1_FMP (1 << 20)TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)__PTRDIFF_TYPE__ int__ARM_ARCH_ISA_THUMBGPIOH_ASCR GPIO_ASCR(GPIOH)__ARM_FEATURE_MATMUL_INT8__UINT8_TYPE__ unsigned charLIBOPENCM3_CM3_MEMORYMAP_H __GCC_ATOMIC_SHORT_LOCK_FREE 2SYSCFG_CFGR2 MMIO32(SYSCFG_BASE + 0x1C)__USACCUM_FBIT__ 8__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1__LACCUM_FBIT__ 31SCS_BASE (PPBI_BASE + 0xE000)GPIOC_BSRR GPIO_BSRR(GPIOC)GPIOF_PUPDR GPIO_PUPDR(GPIOF)SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)__FLT32_HAS_QUIET_NAN__ 1I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)GPIOB_ODR GPIO_ODR(GPIOB)__LDBL_HAS_INFINITY__ 1GPIOD_MODER GPIO_MODER(GPIOD)__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))__FLT32X_MAX_10_EXP__ 308GPIO_PUPD_PULLDOWN 0x2__ARM_ARCH_EXT_IDIV__ 1GPIOG_OSPEEDR GPIO_OSPEEDR(GPIOG)GPIOK_AFRL GPIO_AFRL(GPIOK)GPIO_PUPD_NONE 0x0bool _BoolUINTMAX_MAX __UINTMAX_MAX__EXTI37 (1 << 5)__SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffGPIOA_IDR GPIO_IDR(GPIOA)BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)GPIO3 (1 << 3)INT16_MAX __INT16_MAX____FP_FAST_FMAF 1__FLT32X_IS_IEC_60559__ 2GPIO_OSPEED_2MHZ 0x0PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)GPIOF_BSRR GPIO_BSRR(GPIOF)exti_set_triggerLIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))FIREWALL_BASE (PERIPH_BASE_APB2 + 0x1C00)GPIOK_OSPEEDR GPIO_OSPEEDR(GPIOK)__INT_LEAST16_WIDTH__ 16SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)__ARM_FEATURE_FP16_FMLINT16_MIN (-INT16_MAX - 1)__USFRACT_EPSILON__ 0x1P-8UHR__WINT_MAX__ 0xffffffffU__USFRACT_FBIT__ 8CORESIGHT_LSR_SLI (1<<0)GPIOK_IDR GPIO_IDR(GPIOK)GPIOE GPIO_PORT_E_BASE__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX____UINT32_MAX__ 0xffffffffULGPIOK_AFRH GPIO_AFRH(GPIOK)SYSCFG_CFGR1_FPU_IE_DENORMAL (1 << 30)__INT_LEAST8_MAX__ 0x7f__GCC_ATOMIC_POINTER_LOCK_FREE 2__ARM_FEATURE_QBIT 1__ARM_FEATURE_CLZ 1GPIO4 (1 << 4)__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXGPIO_ODR(port) MMIO32((port) + 0x14)GPIO_OSPEED_HIGH 0x2SYSCFG_CFGR1_FPU_IE_OVERFLOW (1 << 29)GPIOK GPIO_PORT_K_BASE__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024SYSCFG_SCSR_SRAM2BSY (1 << 1)GPIO_MODER(port) MMIO32((port) + 0x00)__UINT_LEAST32_MAX__ 0xffffffffULSYSCFG_EXTICR_FIELDSIZE 4__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1SYSCFG_SWPR MMIO32(SYSCFG_BASE + 0x20)GPIOJ_OSPEEDR GPIO_OSPEEDR(GPIOJ)__ACCUM_MAX__ 0X7FFFFFFFP-15K__INT8_MAX__ 0x7fBIT14 (1<<14)GPIO_OSPEED_MASK(n) (0x3 << (2 * (n)))__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16SYSCFG_MEMRMP_MEM_MODE_FMC 2__SHRT_WIDTH__ 16BIT20 (1<<20)__ARM_FEATURE_MVEextis__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intSYSCFG_CFGR1_FPU_IE_INVALID (1 << 26)GPIOF_AFRL GPIO_AFRL(GPIOF)SWPMI1_BASE (PERIPH_BASE_APB1 + 0x8800)SAI1_BASE (PERIPH_BASE_APB2 + 0x5400)INT_FAST32_MINGPIO_AFRH(port) MMIO32((port) + 0x24)__FLT_EVAL_METHOD_TS_18661_3__ 0__SCHAR_WIDTH__ 8BIT18 (1<<18)COMP_BASE (PERIPH_BASE_APB2 + 0x0200)SYSCFG_CFGR1_FPU_IE_DIVZERO (1 << 27)SIZE_MAX__UINT_FAST8_TYPE__ unsigned intEXTI10 (1 << 10)__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RBIT24 (1<<24)GPIO_AF11 0xb__INT32_MAX__ 0x7fffffffL__GXX_TYPEINFO_EQUALITY_INLINE 0lineUINTMAX_MAXGPIO13 (1 << 13)BIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLLGPIOI_ODR GPIO_ODR(GPIOI)__ARM_FEATURE_BF16_VECTOR_ARITHMETICINFO_BASE (0x1fff0000U)PPBI_BASE (0xE0000000U)SYSCFG_CFGR1_I2C_PB7_FMP (1 << 17)__FLT32_MANT_DIG__ 24GPIOG_ASCR GPIO_ASCR(GPIOG)INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN__GPIOH_LCKR GPIO_LCKR(GPIOH)INT8_MAX __INT8_MAX__BIT28 (1<<28)trigEXTI_RTSR MMIO32(EXTI_BASE + 0x08)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2GPIOF_BRR GPIO_BRR(GPIOF)__DBL_MAX_EXP__ 1024__ATOMIC_RELEASE 3../common/exti_common_all.cUINT_FAST8_MAX__FLT_MANT_DIG__ 24__UDQ_IBIT__ 0__INT_LEAST32_TYPE__ long int__OPTIMIZE_SIZE__ 1__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UK__FLT64_NORM_MAX__ 1.7976931348623157e+308F64GPIOE_IDR GPIO_IDR(GPIOE)GPIOE_PUPDR GPIO_PUPDR(GPIOE)UINTPTR_MAX__LDBL_DENORM_MIN__ 4.9406564584124654e-324L__INT64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_SAT 1GPIO_OTYPE_PP 0x0__ULLFRACT_IBIT__ 0SYSCFG_CFGR1_FPU_IE_INEXACT (1 << 31)MMIO16(addr) (*(volatile uint16_t *)(addr))AES_BASE (0x50000000U + 0x60000)SYSCFG_MEMRMP MMIO32(SYSCFG_BASE + 0x00)DAC_BASE (PERIPH_BASE_APB1 + 0x7400)__GNUC__ 12BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)GPIOF_AFRH GPIO_AFRH(GPIOF)WCHAR_MAX__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0UUART5_BASE (PERIPH_BASE_APB1 + 0x5000)__UQQ_IBIT__ 0CORESIGHT_LSR_OFFSET 0xfb4GPIO_AF15 0xf__GCC_ATOMIC_LONG_LOCK_FREE 2__ULACCUM_MIN__ 0.0ULK__INT_MAX__ 0x7fffffff__ARM_ARCH 7__FLT_RADIX__ 2BIT3 (1<<3)long long intCORESIGHT_LAR_KEY 0xC5ACCE55__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAX__LDBL_HAS_QUIET_NAN__ 1EXTI36 (1 << 4)__LONG_LONG_WIDTH__ 64BIT6 (1<<6)GPIO_AF14 0xe__UINT_FAST64_MAX__ 0xffffffffffffffffULL__ARM_FPGPIOA_AFRL GPIO_AFRL(GPIOA)__HA_IBIT__ 8__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1EXTI20 (1 << 20)BIT9 (1<<9)__FLT32X_MIN__ 2.2250738585072014e-308F32xINTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024UINT16_MAXPERIPH_BASE_AHB2 (0x48000000U)__FLT64_MIN__ 2.2250738585072014e-308F64__INTMAX_C(c) c ## LLLIBOPENCM3_GPIO_COMMON_F24_H __ARM_ARCH_PROFILE__INT64_TYPE__ long long intGPIO_OSPEED_50MHZ 0x2__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4maskGPIOC GPIO_PORT_C_BASECRS_BASE (PERIPH_BASE_APB1 + 0x6000)GPIO_MODE_INPUT 0x0__UFRACT_MAX__ 0XFFFFP-16URINT64_MAXFPB_BASE (PPBI_BASE + 0x2000)GPIOC_LCKR GPIO_LCKR(GPIOC)INT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0GPIOG GPIO_PORT_G_BASESTIR_BASE (SCS_BASE + 0x0F00)GPIOE_MODER GPIO_MODER(GPIOE)__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)SYS_TICK_BASE (SCS_BASE + 0x0010)__UFRACT_FBIT__ 16FMC_BASE (0xa0000000U)__UDQ_FBIT__ 64exti_reset_requestGPIO6 (1 << 6)LIBOPENCM3_EXTI_H GPIOD_ODR GPIO_ODR(GPIOD)EXTI7 (1 << 7)__INT_FAST32_TYPE__ intGPIOB_BSRR GPIO_BSRR(GPIOB)unsigned intEXTI31 (1 << 31)__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1EXTI4 (1 << 4)GPIOA_BRR GPIO_BRR(GPIOA)__USACCUM_IBIT__ 8ITM_BASE (PPBI_BASE + 0x0000)GPIO_MODE(n,mode) ((mode) << (2 * (n)))SYSCFG_SKR_KEY2 0x53GPIO_OSPEED_25MHZ 0x1__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UKSYSCFG_EXTICR_GPIOD 3__UTA_IBIT__ 64EXTI27 (1 << 27)__FLT_EVAL_METHOD__ 0GPIO12 (1 << 12)__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32DFSDM_BASE (PERIPH_BASE_APB2 + 0x6000)RCC_BASE (PERIPH_BASE_AHB1 + 0x1000)__ARM_FEATURE_LDREX__UQQ_FBIT__ 8EXTI12 (1 << 12)INT16_CGPIOE_BSRR GPIO_BSRR(GPIOE)__ARM_FP16_ARGS__GCC_IEC_559 0INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX__GPIOH_IDR GPIO_IDR(GPIOH)__LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4bits__STDC__ 1EXTI26 (1 << 26)SYSCFG_SKR_KEY1 0xCA__ARM_FEATURE_IDIV 1__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__DBGMCU_BASE (PPBI_BASE + 0x00042000)EXTI30 (1 << 30)EXTI13 (1 << 13)__ARM_FEATURE_COPROC 15UINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"INT8_MINGPIOD GPIO_PORT_D_BASEGPIO14 (1 << 14)PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)__LDBL_MIN_10_EXP__ (-307)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1EXTI14 (1 << 14)__GCC_ATOMIC_CHAR_LOCK_FREE 2__LFRACT_EPSILON__ 0x1P-31LRFMC1_BANK_BASE (0x60000000U)STM32L4 1__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX____FLT32X_NORM_MAX__ 1.7976931348623157e+308F32xGPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC)__arm__ 1__FLT32_MIN_10_EXP__ (-37)MMIO64(addr) (*(volatile uint64_t *)(addr))SYSCFG_CFGR1_I2C_PB9_FMP (1 << 19)GPIOG_IDR GPIO_IDR(GPIOG)__ARM_FP16_FORMAT_ALTERNATIVE__LDBL_NORM_MAX__ 1.7976931348623157e+308LINTPTR_MINDESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)GPIOH_MODER GPIO_MODER(GPIOH)__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)GPIOA_OTYPER GPIO_OTYPER(GPIOA)__TA_IBIT__ 64GPIOG_MODER GPIO_MODER(GPIOG)__FLT32_MIN__ 1.1754943508222875e-38F32SYSCFG_CFGR2_CCL (1 << 0)EXTICR_SELECTION_REG(x) SYSCFG_EXTICR(x)GPIOE_AFRL GPIO_AFRL(GPIOE)EXTI18 (1 << 18)__ARM_FEATURE_QRDMXGPIO_OTYPE_OD 0x1__ARM_ARCH_ISA_THUMB 2__LONG_LONG_MAX__ 0x7fffffffffffffffLL__WINT_WIDTH__ 32GPIOC_MODER GPIO_MODER(GPIOC)SIG_ATOMIC_MAX __SIG_ATOMIC_MAX____USQ_IBIT__ 0BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1SYSCFG_EXTICR_GPIOC 2_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN__GPIOD_BSRR GPIO_BSRR(GPIOD)__SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)EXTI35 (1 << 3)__DBL_MIN_EXP__ (-1021)GPIOA GPIO_PORT_A_BASE__LDBL_HAS_DENORM__ 1EXTICR_SELECTION_FIELDSIZE SYSCFG_EXTICR_FIELDSIZEINT8_MIN (-INT8_MAX - 1)GPIOE_OSPEEDR GPIO_OSPEEDR(GPIOE)GPIO1 (1 << 1)EXTI_IMR MMIO32(EXTI_BASE + 0x00)SYSCFG_EXTICR_GPIOH 7__FLT32_DIG__ 6INT_LEAST16_MAXGPIOG_LCKR GPIO_LCKR(GPIOG)BIT15 (1<<15)GPIOB_AFRH GPIO_AFRH(GPIOB)VREFBUF_BASE (PERIPH_BASE_APB2 + 0x0030)GPIO_LCKK (1 << 16)BIT21 (1<<21)PERIPH_BASE (0x40000000U)__SACCUM_FBIT__ 7__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)GPIOI_LCKR GPIO_LCKR(GPIOI)__ACCUM_MIN__ (-0X1P15K-0X1P15K)GPIO_AF5 0x5__ARM_FEATURE_CRYPTOUART4_BASE (PERIPH_BASE_APB1 + 0x4c00)SYSCFG_EXTICR1 SYSCFG_EXTICR(0)GPIOJ_ODR GPIO_ODR(GPIOJ)BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__FRACT_IBIT__ 0GPIO_OSPEED_VERYHIGH 0x3UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2GPIO_PUPDR(port) MMIO32((port) + 0x0c)BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234__FLT_NORM_MAX__ 3.4028234663852886e+38Flong long unsigned int__FLT_MIN_10_EXP__ (-37)GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000)GPIOG_BRR GPIO_BRR(GPIOG)__ULACCUM_IBIT__ 32__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__ULLACCUM_EPSILON__ 0x1P-32ULLK__APCS_32__ 1__DQ_FBIT__ 63GPIOE_AFRH GPIO_AFRH(GPIOE)GPIO_PUPD(n,pupd) ((pupd) << (2 * (n)))INT_LEAST64_MAX__SACCUM_IBIT__ 8__UHQ_IBIT__ 0TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)LIBOPENCM3_MEMORYMAP_COMMON_H EXTI_FTSR MMIO32(EXTI_BASE + 0x0c)BIT29 (1<<29)LIBOPENCM3_GPIO_COMMON_F234_H __INT_FAST16_TYPE__ intGPIOF_IDR GPIO_IDR(GPIOF)INT64_C__ULFRACT_MAX__ 0XFFFFFFFFP-32ULRSYSCFG_SWPR2 MMIO32(SYSCFG_BASE + 0x29)__UINT_LEAST16_TYPE__ short unsigned int__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned int__FLT32X_DIG__ 15EXTI3 (1 << 3)GPIOI_BSRR GPIO_BSRR(GPIOI)__UTQ_FBIT__ 128DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7590)__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffffSYSCFG_SWPR2_PxWP(x) (1 << (x - 32))DMA2_BASE (PERIPH_BASE_AHB1 + 0x0400)PTRDIFF_MAX __PTRDIFF_MAX____SIZEOF_SHORT__ 2EXTI1 (1 << 1)EXTI16 (1 << 16)UINT_FAST16_MAX__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKGPIOC_BRR GPIO_BRR(GPIOC)GPIO_LCKR(port) MMIO32((port) + 0x1c)UINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRGPIO_AF4 0x4__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intGPIOF_MODER GPIO_MODER(GPIOF)GPIOH_PUPDR GPIO_PUPDR(GPIOH)GPIOK_LCKR GPIO_LCKR(GPIOK)GPIOF_ASCR GPIO_ASCR(GPIOF)WCHAR_MINGPIOB_IDR GPIO_IDR(GPIOB)BEGIN_DECLS GPIOJ_AFRH GPIO_AFRH(GPIOJ)SYSCFG_MEMRMP_MEM_MODE_MASK 7SYSCFG_CFGR1_I2C2_FMP (1 << 21)GPIOC_AFRH GPIO_AFRH(GPIOC)__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__FLT32X_MAX__ 1.7976931348623157e+308F32xGPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400)GPIOB_LCKR GPIO_LCKR(GPIOB)GPIOA_ASCR GPIO_ASCR(GPIOA)ST_VREFINT_CAL MMIO16((INFO_BASE + 0x75aa))GPIOA_MODER GPIO_MODER(GPIOA)INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1SYSCFG_MEMRMP_MEM_MODE_SRAM 3__ARM_FEATURE_DSP 1GPIOE_OTYPER GPIO_OTYPER(GPIOE)TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)__QQ_IBIT__ 0__LLACCUM_FBIT__ 31__UINTMAX_TYPE__ long long unsigned intLIBOPENCM3_SYSCFG_H __GNUC_MINOR__ 2GPIO7 (1 << 7)__UINT_LEAST32_TYPE__ long unsigned intGPIO_AFR(n,af) ((af) << ((n) * 4))__ARM_FEATURE_NUMERIC_MAXMIN__INTMAX_TYPE__ long long int__GCC_ATOMIC_INT_LOCK_FREE 2GPIOA_BSRR GPIO_BSRR(GPIOA)TIM16_BASE (PERIPH_BASE_APB2 + 0x4400)GPIOG_PUPDR GPIO_PUPDR(GPIOG)INT_LEAST8_MININTMAX_MAXGPIOB GPIO_PORT_B_BASEDESIG_PACKAGE MMIO16((INFO_BASE + 0x7500))__ARM_ARCH_7EM__ 1__ARM_FEATURE_FP16_SCALAR_ARITHMETIC__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1TIM17_BASE (PERIPH_BASE_APB2 + 0x4800)__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CINT64_MIN__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intGPIOE_ODR GPIO_ODR(GPIOE)UINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULREXTI34 (1 << 2)/build/libopencm3/lib/stm32/l4__SIZEOF_SIZE_T__ 4__UINT64_TYPE__ long long unsigned intgpioportUSART1_BASE (PERIPH_BASE_APB2 + 0x3800)USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x6800)GPIOD_IDR GPIO_IDR(GPIOD)GPIOB_BRR GPIO_BRR(GPIOB)TPIU_BASE (PPBI_BASE + 0x40000)__LDBL_MIN__ 2.2250738585072014e-308LGPIOD_OTYPER GPIO_OTYPER(GPIOD)SYSCFG_CFGR1_FPU_IE_UNDERFLOW (1 << 28)__ARM_FEATURE_CDE__ACCUM_IBIT__ 16EXTI_TRIGGER_FALLINGGPIOJ_MODER GPIO_MODER(GPIOJ)CORESIGHT_LAR_OFFSET 0xfb0EXTI_BASE (PERIPH_BASE_APB2 + 0x0400)LIBOPENCM3_GPIO_H GPIO_AF12 0xcFLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000)short intRNG_BASE (0x50000000U + 0x60800)__UINT16_C(c) cBIT31 (1<<31)__UDA_IBIT__ 32UINT_LEAST32_MAXGPIOI_MODER GPIO_MODER(GPIOI)GPIOD_LCKR GPIO_LCKR(GPIOD)BIT2 (1<<2)EXTI9 (1 << 9)__ATOMIC_RELAXED 0__ARM_FEATURE_COPROCGPIOA_ODR GPIO_ODR(GPIOA)__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53GPIO_BRR(port) MMIO32((port) + 0x28)BIT5 (1<<5)EXTI28 (1 << 28)BIT1 (1<<1)INT8_CGPIO_PORT_H_BASE (PERIPH_BASE_AHB2 + 0x1c00)INT_LEAST32_MAX__USES_INITFINI__ 1__DBL_DECIMAL_DIG__ 17BIT8 (1<<8)__ULACCUM_FBIT__ 32INT16_C(c) __INT16_C(c)UINT32_MAXGPIO_OSPEED_MED 0x1GPIO_MODE_OUTPUT 0x1__INT16_MAX__ 0x7fffGPIOC_ASCR GPIO_ASCR(GPIOC)__INT_WIDTH__ 32__ARM_FEATURE_SIMD32 1DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x75e0)GPIOD_AFRL GPIO_AFRL(GPIOD)__QQ_FBIT__ 7GPIOC_OTYPER GPIO_OTYPER(GPIOC)RTC_BASE (PERIPH_BASE_APB1 + 0x2800)GPIO_AF3 0x3__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64GPIO_IDR(port) MMIO32((port) + 0x10)SYSCFG_CFGR1_BOOSTEN (1 << 8)GPIO_AFRL(port) MMIO32((port) + 0x20)LPTIM2_BASE (PERIPH_BASE_APB1 + 0x9400)__ULLACCUM_IBIT__ 32GPIO_OSPEEDR(port) MMIO32((port) + 0x08)__ULLFRACT_EPSILON__ 0x1P-64ULLRfalse 0GPIOI_AFRL GPIO_AFRL(GPIOI)__SIZEOF_WINT_T__ 4__ARM_FEATURE_UNALIGNED 1EXTI_TRIGGER_BOTH__LDBL_DECIMAL_DIG__ 17__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1SYSCFG_CFGR1_FWDIS (1 << 0)__FLT32X_HAS_DENORM__ 1__ULLACCUM_MIN__ 0.0ULLK__INT_FAST32_WIDTH__ 32EXTI21 (1 << 21)GPIOF_LCKR GPIO_LCKR(GPIOF)GPIO_MODE_ANALOG 0x3__ARM_ASM_SYNTAX_UNIFIED__ 1GPIOJ_LCKR GPIO_LCKR(GPIOJ)__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODGPIOA_AFRH GPIO_AFRH(GPIOA)GPIOH_BSRR GPIO_BSRR(GPIOH)SYSCFG_SCSR MMIO32(SYSCFG_BASE + 0x18)__ARM_PCS_VFP 1__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H GPIOG_OTYPER GPIO_OTYPER(GPIOG)LPUART1_BASE (PERIPH_BASE_APB1 + 0x8000)INT_LEAST64_MIN__GCC_CONSTRUCTIVE_SIZE 64__LLFRACT_IBIT__ 0uint32_tEXTI23 (1 << 23)BIT12 (1<<12)GPIOB_OTYPER GPIO_OTYPER(GPIOB)MPU_BASE (SCS_BASE + 0x0D90)__SACCUM_EPSILON__ 0x1P-7HK__GCC_ASM_FLAG_OUTPUTS__ 1ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0x75a8))__ARM_FP 4__UINT_FAST16_TYPE__ unsigned intGPIOA_OSPEEDR GPIO_OSPEEDR(GPIOA)__UHA_IBIT__ 8__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULK__LDBL_DIG__ 15POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXEXTI_SWIER MMIO32(EXTI_BASE + 0x10)BIT16 (1<<16)__WINT_MIN__ 0UINT_LEAST16_MINSYSCFG_EXTICR4 SYSCFG_EXTICR(3)__FLT64_DIG__ 15TIM15_BASE (PERIPH_BASE_APB2 + 0x4000)BIT22 (1<<22)__INT_LEAST8_WIDTH__ 8WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)__INT_LEAST16_TYPE__ short intSYSCFG_CFGR1 MMIO32(SYSCFG_BASE + 0x04)__DBL_MAX__ ((double)1.7976931348623157e+308L)INT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1UINTMAX_C__LDBL_MAX_10_EXP__ 308GPIOH_BRR GPIO_BRR(GPIOH)SYSCFG_MEMRMP_MEM_MODE_FLASH 0GPIOD_BRR GPIO_BRR(GPIOD)INT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1GPIO15 (1 << 15)EXTI22 (1 << 22)GPIOH_OTYPER GPIO_OTYPER(GPIOH)__HQ_FBIT__ 15__bool_true_false_are_defined 1BIT26 (1<<26)__SIZE_MAX__ 0xffffffffUSPI2_BASE (PERIPH_BASE_APB1 + 0x3800)EXTI15 (1 << 15)EXTI5 (1 << 5)EXTI2 (1 << 2)EXTI33 (1 << 1)__ARM_ARCH__LONG_MAX__ 0x7fffffffLEXTI29 (1 << 29)SYSCFG_CFGR2_SPF (1 << 8)GPIO_OSPEED_100MHZ 0x3SAI2_BASE (PERIPH_BASE_APB2 + 0x5800)__ARM_FEATURE_LDREX 7PTRDIFF_MAXSYSCFG_CFGR2_SPL (1 << 1)__LLFRACT_EPSILON__ 0x1P-63LLR__SFRACT_MAX__ 0X7FP-7HR__FLT32X_MANT_DIG__ 53__WCHAR_WIDTH__ 32WINT_MAX__INT16_C(c) cGPIOD_AFRH GPIO_AFRH(GPIOD)INT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32EXTI17 (1 << 17)GPIOD_OSPEEDR GPIO_OSPEEDR(GPIOD)SYSCFG_CFGR1_I2C3_FMP (1 << 22)GPIO_AFR_MASK(n) (0xf << ((n) * 4))__ATOMIC_ACQ_REL 4EXTI8 (1 << 8)__HQ_IBIT__ 0__DBL_MIN_10_EXP__ (-307)EXTI_PR MMIO32(EXTI_BASE + 0x14)GPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB)GPIOC_IDR GPIO_IDR(GPIOC)__FLT32_NORM_MAX__ 3.4028234663852886e+38F32GPIOH_AFRL GPIO_AFRL(GPIOH)UINT64_C(c) __UINT64_C(c)SYSCFG_CFGR1_I2C_PB8_FMP (1 << 18)__UINTMAX_MAX__ 0xffffffffffffffffULL__DBL_MANT_DIG__ 53GPIO_AF13 0xd__ULFRACT_IBIT__ 0GPIO_ALL 0xffffINT_FAST16_MAXITR_BASE (SCS_BASE + 0x0000)GPIOF GPIO_PORT_F_BASEQUADSPI_BANK_BASE (0x90000000U)__ARM_EABI__ 1__INT_LEAST64_TYPE__ long long intGPIOA_PUPDR GPIO_PUPDR(GPIOA)SYSCFG_MEMRMP_MEM_MODE_QSPI 6__ARM_FEATURE_CDE_COPROCUINT32_CGCC: (15:12.2.rel1-1) 12.2.1 20221205˙˙˙˙| H $°B$„ …†‡‰Š‹ŽA3aeabi)7E-M M "ń˙D”!?A#%')+-/13579;=C@q˘Ô9m§ ŕ UŹ ľBE ďH )<Q°exti_common_all.c$t$dwm4.0.c5e6bdb01417bb5a599260a3f8c9cb62wm4.common.h.21.c9066c2f6b12c71b40226ea6107829a4wm4.stdint.h.29.6d480f4ba0f60596e88234283d42444fwm4.stdbool.h.29.4a1c88fe569adb8d03217dd16982ca34wm4.common.h.67.5c568a1f62c8e726909b04e29f9e1fc0wm4.memorymap.h.21.8c90486dae5eea2d8efddd23fe5d09d9wm4.memorymap.h.26.bb1efb6ce36cc052fd0489ef5a3533f5wm4.exti_common_all.h.29.0c2e2fc3a4fa73c9d031cf0c9c76f7e0wm4.exti_common_v1.h.32.43696415ba411f20ec0e3d65f2d54271wm4.gpio_common_all.h.37.fedbbcb9179f773c905aa3c3e4b7dbddwm4.gpio_common_f234.h.48.1db4d0a0536896711e20c0a147f92021wm4.gpio_common_f24.h.48.d7799bf98ecad7663b4b299525c33e1bwm4.gpio.h.45.1a567f279811a2250901d3d88a79c054wm4.syscfg.h.34.32ec8076f0540826ee285f1c476624cfexti_set_triggerexti_enable_requestexti_disable_requestexti_reset_requestexti_get_flag_statusexti_select_source "&-4;BGT[`mt‚‡™źĄ¬±ŔĘÎÓŕęîóř(,<@GRakouz‰—ś«ąľÍŰâíú&>Xk’ (08 #)/5; !'"-#7@H$N%Ya&j'y‚‹“(™)ź*Ą+˛,şŔ#)/5;AGMSY_ekqw}‰Ź•›ˇ§łążĹËŃ×Ýăéďőű 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unsigned intWINT_MAX __WINT_MAX____USA_IBIT__ 16__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1PTRDIFF_MIN (-PTRDIFF_MAX - 1)USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6c00)__UINT_FAST64_TYPE__ long long unsigned intDESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 0x14)DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7590)__FLT_MIN__ 1.1754943508222875e-38F__HA_FBIT__ 7__FDPIC____FLT32_IS_IEC_60559__ 2GPIO_PORT_G_BASE (PERIPH_BASE_AHB2 + 0x1800)__HAVE_SPECULATION_SAFE_VALUE 1INT_FAST64_MIN__USFRACT_IBIT__ 0__INT32_C(c) c ## L__LDBL_EPSILON__ 2.2204460492503131e-16L__USFRACT_MIN__ 0.0UHRTSC_BASE (PERIPH_BASE_AHB1 + 0x4000)__ARM_NEON__UINT8_MAX__ 0xff__LDBL_MAX_EXP__ 1024FLASH_OPTR_nRST_SHDW (1 << 14)LIBOPENCM3_MEMORYMAP_H __DBL_HAS_DENORM__ 1DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)FLASH_CR_MER2 (1 << 15)FLASH_PCROP1SR_PCROP1_STRT_SHIFT 0FLASH_ECCR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x18)QUADSPI_BASE (0xa0001000U)__DA_FBIT__ 31FLASH_PCROP2ER_PCROP2_END_SHIFT 0__GXX_ABI_VERSION 1017GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 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4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__DBL_MIN_EXP__ (-1021)flash_program_option_bytesFLASH_PCROP1ER_PCROP1_END_SHIFT 0INT8_MIN (-INT8_MAX - 1)FLASH_KEYR_KEY2 ((uint32_t)0xcdef89ab)__FLT32_DIG__ 6INT_LEAST16_MAXBIT15 (1<<15)VREFBUF_BASE (PERIPH_BASE_APB2 + 0x0030)BIT21 (1<<21)PERIPH_BASE (0x40000000U)__SACCUM_FBIT__ 7__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1INT32_MAX__ACCUM_MIN__ (-0X1P15K-0X1P15K)__ARM_FEATURE_CRYPTOUART4_BASE (PERIPH_BASE_APB1 + 0x4c00)BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__FRACT_IBIT__ 0UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2FLASH_ACR_LATENCY_SHIFT 0FLASH_OPTR_IWDG_STOP (1 << 17)BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234__FLT_NORM_MAX__ 3.4028234663852886e+38Flong long unsigned int__FLT_MIN_10_EXP__ (-37)GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000)__ULACCUM_IBIT__ 32__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__PTRDIFF_TYPE__ intFLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14)__APCS_32__ 1__DQ_FBIT__ 63INT_LEAST64_MAX__SACCUM_IBIT__ 8__UHQ_IBIT__ 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1__FLT32X_EPSILON__ 2.2204460492503131e-16F32xNVIC_BASE (SCS_BASE + 0x0100)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32USART2_BASE (PERIPH_BASE_APB1 + 0x4400)__UINTMAX_C(c) c ## ULL__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed char__GCC_ATOMIC_BOOL_LOCK_FREE 2BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON____FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX____THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRshort unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)BIT7 (1<<7)BIT17 (1<<17)__FLT32X_MIN_10_EXP__ (-307)UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)__DBL_IS_IEC_60559__ 2__UINT_FAST32_MAX__ 0xffffffffU__DEC_EVAL_METHOD__ 2__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32__FLT32X_MIN_EXP__ (-1021)DMA1_BASE (PERIPH_BASE_AHB1 + 0x0000)FLASH_PCROP2SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x44)GNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsBIT27 (1<<27)TIM1_BASE (PERIPH_BASE_APB2 + 0x2C00)FLASH_WRP2BR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x50)__UTA_FBIT__ 64INTMAX_C(c) __INTMAX_C(c)FLASH_OPTR_nRST_STOP (1 << 12)__FLT_DECIMAL_DIG__ 9__thumb__ 1__INT_LEAST32_MAX__ 0x7fffffffLLIBOPENCM3_MEMORYMAP_COMMON_H signed charFLASH_WRP2BR_WRP2B_STRT_SHIFT 0INT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)INT32_C(c) __INT32_C(c)__GNUC_STDC_INLINE__ 1FLASH_CR_EOPIE (1 << 24)__FRACT_FBIT__ 15__LLACCUM_EPSILON__ 0x1P-31LLK__GNUC_PATCHLEVEL__ 1__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2PTRDIFF_MIN__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)UINTPTR_MAX __UINTPTR_MAX____ARM_ARCH_PROFILE 77FLASH_SR_PROGERR (1 << 3)FLASH_SR_PGSERR (1 << 7)GPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000)__FLT64_MAX_10_EXP__ 308GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400)MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINFLASH_OPTR_RDP_LEVEL_1 0xBBSDMMC1_BASE (PERIPH_BASE_APB2 + 0x2800)__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)__FRACT_MAX__ 0X7FFFP-15RTIM3_BASE (PERIPH_BASE_APB1 + 0x0400)INT_LEAST32_MAX __INT_LEAST32_MAX____INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5LIBOPENCM3_FLASH_H FLASH_SR_RDERR (1 << 14)FLASH_OPTR_BOR_LEVEL_0 0FLASH_OPTR_BOR_LEVEL_1 1__UINT16_MAX__ 0xffffFLASH_PCROP2ER MMIO32(FLASH_MEM_INTERFACE_BASE + 0x48)FLASH_CR_MER1 (1 << 2)__TQ_FBIT__ 127FLASH_KEYR_KEY1 ((uint32_t)0x45670123)FLASH_ACR_DCEN (1 << 10)__USQ_FBIT__ 32../common/flash_common_all.cINT_FAST16_MINFLASH_SR_OPTVERR (1 << 15)__thumb2__ 1__ULLACCUM_FBIT__ 32FMC_QUADSPI_BASE (0xA0000000U)INT_FAST32_MIN (-INT_FAST32_MAX - 1)__STRICT_ANSI__ 1FMC3_BANK_BASE (0x80000000U)UINT_LEAST8_MAXFLASH_OPTR_BOR_LEVEL_2 2UINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)TIM8_BASE (PERIPH_BASE_APB2 + 0x3400)__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX____USA_IBIT__ 16__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1PTRDIFF_MIN (-PTRDIFF_MAX - 1)USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6c00)__UINT_FAST64_TYPE__ long long unsigned intDESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 0x14)DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7590)__FLT_MIN__ 1.1754943508222875e-38F__HA_FBIT__ 7__FDPIC__WINT_MAX__UFRACT_MIN__ 0.0UR__FLT32_IS_IEC_60559__ 2__UTA_IBIT__ 64GPIO_PORT_G_BASE (PERIPH_BASE_AHB2 + 0x1800)INT_FAST64_MIN__USFRACT_IBIT__ 0__INT32_C(c) c ## L__LDBL_EPSILON__ 2.2204460492503131e-16L__USFRACT_MIN__ 0.0UHRTSC_BASE (PERIPH_BASE_AHB1 + 0x4000)__ARM_NEON__UINT8_MAX__ 0xff__LDBL_MAX_EXP__ 1024FLASH_OPTR_nRST_SHDW (1 << 14)LIBOPENCM3_MEMORYMAP_H __DBL_HAS_DENORM__ 1DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)FLASH_CR_MER2 (1 << 15)FLASH_PCROP1SR_PCROP1_STRT_SHIFT 0FLASH_ECCR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x18)QUADSPI_BASE (0xa0001000U)__DA_FBIT__ 31FLASH_PCROP2ER_PCROP2_END_SHIFT 0__GXX_ABI_VERSION 1017GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0c00)__INT_LEAST16_MAX__ 0x7fff__FLT_DENORM_MIN__ 1.4012984643248171e-45F__ULLACCUM_EPSILON__ 0x1P-32ULLKINT_LEAST8_MAX __INT_LEAST8_MAX____UINT32_C(c) c ## UL__UACCUM_MIN__ 0.0UK__FLT_EPSILON__ 1.1920928955078125e-7FTIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)FLASH_OPTR_SRAM2_RST (1 << 25)__ARM_ARCH_ISA_THUMBFLASH_OPTKEYR_KEY1 ((uint32_t)0x08192a3b)__ARM_FEATURE_MATMUL_INT8__UINT8_TYPE__ unsigned charLIBOPENCM3_CM3_MEMORYMAP_H __GCC_ATOMIC_SHORT_LOCK_FREE 2__USACCUM_FBIT__ 8__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1__LACCUM_FBIT__ 31SCS_BASE (PPBI_BASE + 0xE000)FLASH_OPTR_nRST_STDBY (1 << 13)SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)__FLT32_HAS_QUIET_NAN__ 1I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)__LDBL_HAS_INFINITY__ 1__TA_FBIT__ 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0xffffffffUL__INT_LEAST8_MAX__ 0x7fFLASH_SR_EOP (1 << 0)__GCC_ATOMIC_POINTER_LOCK_FREE 2__ARM_FEATURE_QBIT 1__ARM_FEATURE_CLZ 1__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEX__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024__UINT_LEAST32_MAX__ 0xffffffffULflash_prefetch_disable__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)FLASH_ACR_PRFTEN (1 << 8)__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1__ACCUM_MAX__ 0X7FFFFFFFP-15KFLASH_OPTR_BFB2 (1 << 20)__INT8_MAX__ 0x7fFLASH_PCROP1SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x24)BIT14 (1<<14)FLASH_CR_BKER (1 << 11)__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16__SHRT_WIDTH__ 16BIT20 (1<<20)__ARM_FEATURE_MVE__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intSWPMI1_BASE (PERIPH_BASE_APB1 + 0x8800)SAI1_BASE (PERIPH_BASE_APB2 + 0x5400)FLASH_ACR_LATENCY_MASK 0x07INT_FAST32_MIN__FLT_EVAL_METHOD_TS_18661_3__ 0__SCHAR_WIDTH__ 8BIT18 (1<<18)COMP_BASE (PERIPH_BASE_APB2 + 0x0200)SIZE_MAX__UINT_FAST8_TYPE__ unsigned int__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RBIT24 (1<<24)__INT32_MAX__ 0x7fffffffLUINTMAX_MAXBIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_BF16_VECTOR_ARITHMETICFLASH_ECCR_BK_ECC (1 << 19)INFO_BASE (0x1fff0000U)PPBI_BASE (0xE0000000U)__FLT32_MANT_DIG__ 24INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN__INT8_MAX __INT8_MAX__FLASH_ACR_ICEN (1 << 9)BIT28 (1<<28)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2__DBL_MAX_EXP__ 1024__ATOMIC_RELEASE 3UINT_FAST8_MAX__FLT_MANT_DIG__ 24__UDQ_IBIT__ 0__INT_LEAST32_TYPE__ long intFLASH_SR_FASTERR (1 << 9)__OPTIMIZE_SIZE__ 1__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UK__FLT64_NORM_MAX__ 1.7976931348623157e+308F64UINTPTR_MAXFLASH_CR_OBL_LAUNCH (1 << 27)__LDBL_DENORM_MIN__ 4.9406564584124654e-324L__INT64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_SAT 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0FLASH_OPTR_WWDG_SW (1 << 19)MMIO16(addr) (*(volatile uint16_t *)(addr))AES_BASE (0x50000000U + 0x60000)DAC_BASE (PERIPH_BASE_APB1 + 0x7400)__GNUC__ 12BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)WCHAR_MAXFLASH_PDKEYR_PDKEY2 ((uint32_t)0xfafbfcfd)__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0UUART5_BASE (PERIPH_BASE_APB1 + 0x5000)__UQQ_IBIT__ 0CORESIGHT_LSR_OFFSET 0xfb4__GCC_ATOMIC_LONG_LOCK_FREE 2__ULACCUM_MIN__ 0.0ULKFLASH_CR_RDERRIE (1 << 26)__LDBL_MAX__ 1.7976931348623157e+308L__ARM_ARCH 7FLASH_WRP2AR_WRP2A_STRT_MASK 0xffFLASH_ACR_SLEEP_PD (1 << 14)__FLT_RADIX__ 2BIT3 (1<<3)long long intCORESIGHT_LAR_KEY 0xC5ACCE55__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAXFLASH_ACR_RUN_PD (1 << 13)__LDBL_HAS_QUIET_NAN__ 1FLASH_PCROP2SR_PCROP2_STRT_SHIFT 0__LONG_LONG_WIDTH__ 64BIT6 (1<<6)__UINT_FAST64_MAX__ 0xffffffffffffffffULL__ARM_FP__HA_IBIT__ 8__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1BIT9 (1<<9)__FLT32X_MIN__ 2.2250738585072014e-308F32xINTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024FLASH_OPTR_RDP_SHIFT 0UINT16_MAXPERIPH_BASE_AHB2 (0x48000000U)__FLT64_MIN__ 2.2250738585072014e-308F64__INTMAX_C(c) c ## LL__ARM_ARCH_PROFILE__INT64_TYPE__ long long int__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4FLASH_SR_PGAERR (1 << 5)CRS_BASE (PERIPH_BASE_APB1 + 0x6000)__UFRACT_MAX__ 0XFFFFP-16URINT64_MAXFPB_BASE (PPBI_BASE + 0x2000)INT_FAST64_MIN (-INT_FAST64_MAX - 1)STIR_BASE (SCS_BASE + 0x0F00)FLASH_ECCR_ECCD (1 << 31)__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)ID_BASE (SCS_BASE + 0x0FD0)SYS_TICK_BASE (SCS_BASE + 0x0010)FLASH_CR_START (1 << 16)FLASH_WRP2AR_WRP2A_STRT_SHIFT 0__UFRACT_FBIT__ 16FMC_BASE (0xa0000000U)__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)FLASH_WRP1AR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x2C)__LDBL_MAX_10_EXP__ 308__INT_FAST32_TYPE__ intunsigned int__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1__USACCUM_IBIT__ 8FLASH_CR_PNB_SHIFT 3ITM_BASE (PPBI_BASE + 0x0000)FLASH_WRP1AR_WRP1A_END_MASK 0xffST_VREFINT_CAL MMIO16((INFO_BASE + 0x75aa))__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UKFLASH_CR_OPTLOCK (1 << 30)FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08)FLASH_ACR_DCRST (1 << 12)__FLT_EVAL_METHOD__ 0FLASH_OPTR_RDP_LEVEL_0 0xAA__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32DFSDM_BASE (PERIPH_BASE_APB2 + 0x6000)RCC_BASE (PERIPH_BASE_AHB1 + 0x1000)__ARM_FEATURE_LDREX__UQQ_FBIT__ 8INT16_C__ARM_FP16_ARGS__GCC_IEC_559 0INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX____LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4__STDC__ 1__ARM_FEATURE_IDIV 1FLASH_PCROP2SR_PCROP2_STRT_MASK 0xffff__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__DBGMCU_BASE (PPBI_BASE + 0x00042000)__ARM_FEATURE_COPROC 15UINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"INT8_MINFLASH_OPTR_nBOOT1 (1 << 23)PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)FLASH_WRP2BR_WRP2B_END_SHIFT 16__LDBL_MIN_10_EXP__ (-307)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1__GCC_ATOMIC_CHAR_LOCK_FREE 2__LFRACT_EPSILON__ 0x1P-31LRFMC1_BANK_BASE (0x60000000U)STM32L4 1__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX____FLT32X_NORM_MAX__ 1.7976931348623157e+308F32x__arm__ 1__FLT32_MIN_10_EXP__ (-37)MMIO64(addr) (*(volatile uint64_t *)(addr))FLASH_WRP2AR_WRP2A_END_SHIFT 16__ARM_FP16_FORMAT_ALTERNATIVEFLASH_SR_OPERR (1 << 1)__LDBL_NORM_MAX__ 1.7976931348623157e+308LINTPTR_MINDESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)__TA_IBIT__ 64FLASH_WRP1AR_WRP1A_STRT_MASK 0xff__ARM_FEATURE_QRDMX__ARM_ARCH_ISA_THUMB 2__LONG_LONG_MAX__ 0x7fffffffffffffffLL__WINT_WIDTH__ 32SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__FLASH_OPTR_BOR_LEVEL_3 3FLASH_ECCR_SYSF_ECC (1 << 20)BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1FLASH_WRP1AR_WRP1A_END_SHIFT 16_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN____SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__DBL_MIN_EXP__ (-1021)__LDBL_HAS_DENORM__ 1FLASH_PCROP1ER_PCROP1_END_SHIFT 0INT8_MIN (-INT8_MAX - 1)FLASH_KEYR_KEY2 ((uint32_t)0xcdef89ab)__FLT32_DIG__ 6INT_LEAST16_MAXBIT15 (1<<15)VREFBUF_BASE (PERIPH_BASE_APB2 + 0x0030)BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1INT32_MAX__ACCUM_MIN__ (-0X1P15K-0X1P15K)__ARM_FEATURE_CRYPTOUART4_BASE (PERIPH_BASE_APB1 + 0x4c00)BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__FRACT_IBIT__ 0UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2FLASH_ACR_LATENCY_SHIFT 0FLASH_OPTR_IWDG_STOP (1 << 17)BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234__FLT_NORM_MAX__ 3.4028234663852886e+38Flong long unsigned int__FLT_MIN_10_EXP__ (-37)GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000)__ULACCUM_IBIT__ 32__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__PTRDIFF_TYPE__ intFLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14)__APCS_32__ 1__DQ_FBIT__ 63INT_LEAST64_MAX__SACCUM_IBIT__ 8__UHQ_IBIT__ 0TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)INT_LEAST8_MINBIT29 (1<<29)__INT_FAST16_TYPE__ intINT64_C__ULFRACT_MAX__ 0XFFFFFFFFP-32ULR__UINT_LEAST16_TYPE__ short unsigned int__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned int__FLT32X_DIG__ 15__UTQ_FBIT__ 128FLASH_WRP2AR_WRP2A_END_MASK 0xffFLASH_SR_WRPERR (1 << 4)__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffffDMA2_BASE (PERIPH_BASE_AHB1 + 0x0400)PTRDIFF_MAX __PTRDIFF_MAX____SIZEOF_SHORT__ 2FLASH_ACR_LATENCY_0WS 0x00UINT_FAST16_MAX__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKUINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULR__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intFLASH_ECCR_ECCIE (1 << 24)FLASH_OPTR_IWDG_STDBY (1 << 18)FLASH_WRP2AR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x4C)WCHAR_MINBEGIN_DECLS FLASH_SR_MISERR (1 << 8)FLASH_SR_BSY (1 << 16)FLASH_OPTR_RDP_MASK 0xff__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__FLT32X_MAX__ 1.7976931348623157e+308F32xGPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400)__ARM_EABI__ 1INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1__ARM_FEATURE_DSP 1TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)__QQ_IBIT__ 0__LLACCUM_FBIT__ 31__UINTMAX_TYPE__ long long unsigned int__USQ_IBIT__ 0__UINT_LEAST32_TYPE__ long unsigned int__ARM_FEATURE_NUMERIC_MAXMIN__INTMAX_TYPE__ long long int__GCC_ATOMIC_INT_LOCK_FREE 2TIM16_BASE (PERIPH_BASE_APB2 + 0x4400)FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C)INTMAX_MAXFLASH_CR_PG (1 << 0)DESIG_PACKAGE MMIO16((INFO_BASE + 0x7500))__ARM_ARCH_7EM__ 1__ARM_FEATURE_FP16_SCALAR_ARITHMETIC__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1FLASH_ECCR_ECCC (1 << 30)TIM17_BASE (PERIPH_BASE_APB2 + 0x4800)__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CFLASH_ECCR_ADDR_ECC_MASK 0x7ffffINT64_MIN__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intUINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRFLASH_PCROP1ER_PCROP_RDP (1 << 31)/build/libopencm3/lib/stm32/l4__SIZEOF_SIZE_T__ 4__UINT64_TYPE__ long long unsigned int__INT64_C(c) c ## LLUSART1_BASE (PERIPH_BASE_APB2 + 0x3800)USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x6800)FLASH_WRP1BR_WRP1B_END_MASK 0xffTPIU_BASE (PPBI_BASE + 0x40000)__LONG_MAX__ 0x7fffffffL__ARM_FEATURE_CDE__ACCUM_IBIT__ 16CORESIGHT_LAR_OFFSET 0xfb0EXTI_BASE (PERIPH_BASE_APB2 + 0x0400)FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000)short intRNG_BASE (0x50000000U + 0x60800)__UINT16_C(c) cBIT31 (1<<31)__UDA_IBIT__ 32UINT_LEAST32_MAXBIT2 (1<<2)__ATOMIC_RELAXED 0__ARM_FEATURE_COPROC__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53BIT5 (1<<5)BIT1 (1<<1)INT8_CGPIO_PORT_H_BASE (PERIPH_BASE_AHB2 + 0x1c00)INT_LEAST32_MAX__USES_INITFINI__ 1__DBL_DECIMAL_DIG__ 17BIT8 (1<<8)INT16_C(c) __INT16_C(c)UINT32_MAX__INT16_MAX__ 0x7fffFLASH_OPTR_BOR_LEVEL_4 4__INT_WIDTH__ 32__ARM_FEATURE_SIMD32 1FLASH_OPTKEYR_KEY2 ((uint32_t)0x4c5d6e7f)DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x75e0)__QQ_FBIT__ 7RTC_BASE (PERIPH_BASE_APB1 + 0x2800)__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64LPTIM2_BASE (PERIPH_BASE_APB1 + 0x9400)__ULLACCUM_IBIT__ 32__ULLFRACT_EPSILON__ 0x1P-64ULLRfalse 0__SIZEOF_WINT_T__ 4FLASH_WRP1AR_WRP1A_STRT_SHIFT 0__ARM_FEATURE_UNALIGNED 1__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1__FLT32X_HAS_DENORM__ 1__ULLACCUM_MIN__ 0.0ULLK__INT_FAST32_WIDTH__ 32FLASH_PCROP2ER_PCROP2_END_MASK 0xffffFLASH_PDKEYR_PDKEY1 ((uint32_t)0x04152637)__ARM_ASM_SYNTAX_UNIFIED__ 1__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODFLASH_OPTR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20)__ARM_PCS_VFP 1FLASH_CR_OPTSTRT (1 << 17)__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H LPUART1_BASE (PERIPH_BASE_APB1 + 0x8000)INT_LEAST64_MIN__GCC_CONSTRUCTIVE_SIZE 64__LLFRACT_IBIT__ 0uint32_tBIT12 (1<<12)MPU_BASE (SCS_BASE + 0x0D90)__SACCUM_EPSILON__ 0x1P-7HK__GCC_ASM_FLAG_OUTPUTS__ 1ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0x75a8))__ARM_FP 4flash_unlock__UINT_FAST16_TYPE__ unsigned int__UHA_IBIT__ 8__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULK__LDBL_DIG__ 15POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXBIT16 (1<<16)__WINT_MIN__ 0UINT_LEAST16_MINFLASH_OPTR_IDWG_SW (1 << 16)__FLT64_DIG__ 15TIM15_BASE (PERIPH_BASE_APB2 + 0x4000)BIT22 (1<<22)__INT_LEAST8_WIDTH__ 8WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)__INT_LEAST16_TYPE__ short int__DBL_MAX__ ((double)1.7976931348623157e+308L)INT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1UINTMAX_CINT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1__HQ_FBIT__ 15__bool_true_false_are_defined 1FLASH_WRP1BR_WRP1B_STRT_SHIFT 0BIT26 (1<<26)__SIZE_MAX__ 0xffffffffUSPI2_BASE (PERIPH_BASE_APB1 + 0x3800)__ARM_ARCH__SFRACT_IBIT__ 0SAI2_BASE (PERIPH_BASE_APB2 + 0x5800)FLASH_ACR_LATENCY_3WS 0x03__ARM_FEATURE_LDREX 7FLASH_PCROP1SR_PCROP1_STRT_MASK 0xffffPTRDIFF_MAX__LLFRACT_EPSILON__ 0x1P-63LLR__SFRACT_MAX__ 0X7FP-7HR__FLT32X_MANT_DIG__ 53__WCHAR_WIDTH__ 32FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00)__INT16_C(c) cINT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32__ATOMIC_ACQ_REL 4__HQ_IBIT__ 0__DBL_MIN_10_EXP__ (-307)FLASH_WRP2BR_WRP2B_END_MASK 0xff__FLT32_NORM_MAX__ 3.4028234663852886e+38F32UINT64_C(c) __UINT64_C(c)FLASH_WRP2BR_WRP2B_STRT_MASK 0xff__UINTMAX_MAX__ 0xffffffffffffffffULLFLASH_ECCR_ADDR_ECC_SHIFT 0__DBL_MANT_DIG__ 53FLASH_CR_PNB_MASK 0xff__ULFRACT_IBIT__ 0INT_FAST16_MAXITR_BASE (SCS_BASE + 0x0000)QUADSPI_BANK_BASE (0x90000000U)__INT_MAX__ 0x7fffffff__INT_LEAST64_TYPE__ long long intFLASH_ACR_LATENCY_2WS 0x02__ARM_FEATURE_CDE_COPROCUINT32_CGCC: (15:12.2.rel1-1) 12.2.1 20221205˙˙˙˙| A3aeabi)7E-M M "ń˙ +-!#%')/?pˇÓ8l« .1 Ű čóflash_common_f.c$t$dwm4.0.c5e6bdb01417bb5a599260a3f8c9cb62wm4.common.h.21.c9066c2f6b12c71b40226ea6107829a4wm4.stdint.h.29.6d480f4ba0f60596e88234283d42444fwm4.stdbool.h.29.4a1c88fe569adb8d03217dd16982ca34wm4.common.h.67.5c568a1f62c8e726909b04e29f9e1fc0wm4.memorymap.h.21.8c90486dae5eea2d8efddd23fe5d09d9wm4.memorymap.h.26.bb1efb6ce36cc052fd0489ef5a3533f5wm4.flash_common_idcache.h.29.c4c8bedb8492fa8fe35d5d69bd7daa91wm4.flash.h.50.fcd70b2de44a0c7ed837612101985a6dflash_unlockflash_lockflash_clear_eop_flag "&-4;BIPUcjx}‚Ť’ť˘ '-7@HNYqw#)/5;AGMSY_ekqw}‰Ź•›ˇ§łążĹËŃ×Ýăéďőű %+17=CIOU[agmsy…‹‘—ťŁ©Żµ»ÁÇÍÓŮßĺëń÷ý !'-39?EKQW]ciou{‡Ť“™źĄ«±·˝ĂÉĎŐŰáçíóů˙#)/5;AGMSY_ekqw}‰Ź•›ˇ§łążĹËŃ×Ýăéďőű %+17=CIOU[agmsy…‹‘—ťŁ©Żµ»ÁÇÍÓŮßĺëń÷ý !'-39?EKQW]ciou{‡Ť“™źĄ«±·˝ĂÉĎŐŰáçíóů˙#)/5;AGMSY_ekqw}‰Ź•›ˇ§łążĹËŃ×Ýăéďőű %+17=CIOU[agmsy…‹‘—ťŁ©Żµ»ÁÇÍÓŮßĺëń÷ý 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15PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)__UACCUM_IBIT__ 16long intUINT8_MAXIWDG_BASE (PERIPH_BASE_APB1 + 0x3000)SIZE_MAX __SIZE_MAX__GPIOH_AFRH GPIO_AFRH(GPIOH)__INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1GPIO9 (1 << 9)__FLT32X_EPSILON__ 2.2204460492503131e-16F32xGPIOH_OSPEEDR GPIO_OSPEEDR(GPIOH)NVIC_BASE (SCS_BASE + 0x0100)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32USART2_BASE (PERIPH_BASE_APB1 + 0x4400)__UINTMAX_C(c) c ## ULL__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed charGPIOJ_AFRL GPIO_AFRL(GPIOJ)GPIOJ_OTYPER GPIO_OTYPER(GPIOJ)__GCC_ATOMIC_BOOL_LOCK_FREE 2BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON__GPIO_AF1 0x1__FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX____THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRshort unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)BIT7 (1<<7)BIT17 (1<<17)__FLT32X_MIN_10_EXP__ (-307)UINT8_MAX __UINT8_MAX__gpio_getSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)__DBL_IS_IEC_60559__ 2__UINT_FAST32_MAX__ 0xffffffffU__DEC_EVAL_METHOD__ 2__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32__FLT32X_MIN_EXP__ (-1021)DMA1_BASE (PERIPH_BASE_AHB1 + 0x0000)GPIO_AF9 0x9GPIOB_PUPDR GPIO_PUPDR(GPIOB)GNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsBIT27 (1<<27)TIM1_BASE (PERIPH_BASE_APB2 + 0x2C00)GPIOH_ODR GPIO_ODR(GPIOH)__UTA_FBIT__ 64INTMAX_C(c) __INTMAX_C(c)__FLT_DECIMAL_DIG__ 9__thumb__ 1__INT_LEAST32_MAX__ 0x7fffffffLLIBOPENCM3_MEMORYMAP_COMMON_H __VERSION__ "12.2.1 20221205"INT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)INT32_C(c) __INT32_C(c)__GNUC_STDC_INLINE__ 1GPIOE_BRR GPIO_BRR(GPIOE)GPIO_PUPD_PULLUP 0x1LIBOPENCM3_GPIO_COMMON_ALL_H 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(0xA0000000U)GPIOA_MODER GPIO_MODER(GPIOA)INT_FAST32_MIN (-INT_FAST32_MAX - 1)__STRICT_ANSI__ 1FMC3_BANK_BASE (0x80000000U)UINT_LEAST8_MAXGPIOG_AFRH GPIO_AFRH(GPIOG)UINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)TIM8_BASE (PERIPH_BASE_APB2 + 0x3400)GPIO_OTYPER(port) MMIO32((port) + 0x04)__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__GPIOD_PUPDR GPIO_PUPDR(GPIOD)__USA_IBIT__ 16__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1PTRDIFF_MIN (-PTRDIFF_MAX - 1)USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6c00)__UINT_FAST64_TYPE__ long long unsigned intDESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 0x14)GPIOG_AFRL GPIO_AFRL(GPIOG)DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7590)__FLT_MIN__ 1.1754943508222875e-38FGPIOG_ODR GPIO_ODR(GPIOG)__HA_FBIT__ 7GPIOD_ASCR GPIO_ASCR(GPIOD)__FDPIC____UFRACT_MIN__ 0.0UR__FLT32_IS_IEC_60559__ 2GPIOI_OSPEEDR GPIO_OSPEEDR(GPIOI)GPIO_PORT_G_BASE (PERIPH_BASE_AHB2 + 0x1800)INT_FAST64_MIN__USFRACT_IBIT__ 0__INT32_C(c) c ## L__LDBL_EPSILON__ 2.2204460492503131e-16LGPIOB_MODER GPIO_MODER(GPIOB)__USFRACT_MIN__ 0.0UHRTSC_BASE (PERIPH_BASE_AHB1 + 0x4000)__ARM_NEON__UINT8_MAX__ 0xff__LDBL_MAX_EXP__ 1024LIBOPENCM3_MEMORYMAP_H GPIOK_BSRR GPIO_BSRR(GPIOK)__DBL_HAS_DENORM__ 1DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)GPIO8 (1 << 8)GPIO_OSPEED_LOW 0x0GPIOB_AFRL GPIO_AFRL(GPIOB)QUADSPI_BASE (0xa0001000U)__DA_FBIT__ 31__GXX_ABI_VERSION 1017GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0c00)__INT_LEAST16_MAX__ 0x7fffGPIOI GPIO_PORT_I_BASE__FLT_DENORM_MIN__ 1.4012984643248171e-45F__ULLACCUM_EPSILON__ 0x1P-32ULLKGPIOC_ODR GPIO_ODR(GPIOC)GPIOA_LCKR GPIO_LCKR(GPIOA)INT_LEAST8_MAX __INT_LEAST8_MAX__GPIOK_ODR GPIO_ODR(GPIOK)__UINT32_C(c) c ## ULGPIOD_LCKR GPIO_LCKR(GPIOD)__UACCUM_MIN__ 0.0UK__FLT_EPSILON__ 1.1920928955078125e-7FGPIO_MODE_MASK(n) (0x3 << (2 * (n)))GPIO_AF0 0x0TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)__ARM_ARCH_ISA_THUMBGPIOH_ASCR GPIO_ASCR(GPIOH)__ARM_FEATURE_MATMUL_INT8__UINT8_TYPE__ unsigned charLIBOPENCM3_CM3_MEMORYMAP_H __GCC_ATOMIC_SHORT_LOCK_FREE 2__USACCUM_FBIT__ 8__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1__LACCUM_FBIT__ 31SCS_BASE (PPBI_BASE + 0xE000)GPIOC_BSRR GPIO_BSRR(GPIOC)GPIOF_PUPDR GPIO_PUPDR(GPIOF)SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)__FLT32_HAS_QUIET_NAN__ 1I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)GPIOB_ODR GPIO_ODR(GPIOB)__LDBL_HAS_INFINITY__ 1GPIOD_MODER GPIO_MODER(GPIOD)__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))__FLT32X_MAX_10_EXP__ 308GPIOJ_IDR GPIO_IDR(GPIOJ)__ARM_ARCH_EXT_IDIV__ 1GPIOG_OSPEEDR GPIO_OSPEEDR(GPIOG)GPIOK_AFRL GPIO_AFRL(GPIOK)GPIO_PUPD_NONE 0x0bool _BoolUINTMAX_MAX __UINTMAX_MAX____SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffGPIOA_IDR GPIO_IDR(GPIOA)BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)GPIO3 (1 << 3)INT16_MAX __INT16_MAX____FP_FAST_FMAF 1__FLT32X_IS_IEC_60559__ 2GPIO_OSPEED_2MHZ 0x0PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)GPIOF_BSRR GPIO_BSRR(GPIOF)LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))FIREWALL_BASE (PERIPH_BASE_APB2 + 0x1C00)GPIOK_OSPEEDR GPIO_OSPEEDR(GPIOK)__INT_LEAST16_WIDTH__ 16SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)__ARM_FEATURE_FP16_FMLINT16_MIN (-INT16_MAX - 1)__USFRACT_EPSILON__ 0x1P-8UHR__WINT_MAX__ 0xffffffffU__OPTIMIZE_SIZE__ 1__USFRACT_FBIT__ 8CORESIGHT_LSR_SLI (1<<0)GPIOE GPIO_PORT_E_BASE__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX____UINT32_MAX__ 0xffffffffULGPIOK_AFRH GPIO_AFRH(GPIOK)__INT_LEAST8_MAX__ 0x7f__GCC_ATOMIC_POINTER_LOCK_FREE 2__ARM_FEATURE_QBIT 1__ARM_FEATURE_CLZ 1GPIO4 (1 << 4)__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXGPIO_ODR(port) MMIO32((port) + 0x14)GPIO_OSPEED_HIGH 0x2GPIOK GPIO_PORT_K_BASE__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024GPIO_MODER(port) MMIO32((port) + 0x00)__UINT_LEAST32_MAX__ 0xffffffffUL__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1GPIOJ_OSPEEDR GPIO_OSPEEDR(GPIOJ)__ACCUM_MAX__ 0X7FFFFFFFP-15K__INT8_MAX__ 0x7fportGPIO_OSPEED_MASK(n) (0x3 << (2 * (n)))__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16__SHRT_WIDTH__ 16BIT20 (1<<20)__ARM_FEATURE_MVE__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intGPIOF_AFRL GPIO_AFRL(GPIOF)SWPMI1_BASE (PERIPH_BASE_APB1 + 0x8800)SAI1_BASE (PERIPH_BASE_APB2 + 0x5400)INT_FAST32_MINGPIO_AFRH(port) MMIO32((port) + 0x24)__FLT_EVAL_METHOD_TS_18661_3__ 0__SCHAR_WIDTH__ 8BIT18 (1<<18)COMP_BASE (PERIPH_BASE_APB2 + 0x0200)SIZE_MAX__UINT_FAST8_TYPE__ unsigned int__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RBIT24 (1<<24)../common/gpio_common_all.c__INT32_MAX__ 0x7fffffffLUINTMAX_MAXBIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLLGPIOI_ODR GPIO_ODR(GPIOI)__ARM_FEATURE_BF16_VECTOR_ARITHMETICINFO_BASE (0x1fff0000U)PPBI_BASE (0xE0000000U)__FLT32_MANT_DIG__ 24GPIOG_ASCR GPIO_ASCR(GPIOG)INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN__GPIOH_LCKR GPIO_LCKR(GPIOH)INT8_MAX __INT8_MAX__BIT28 (1<<28)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2GPIOF_BRR GPIO_BRR(GPIOF)__DBL_MAX_EXP__ 1024__ATOMIC_RELEASE 3UINT_FAST8_MAX__FLT_MANT_DIG__ 24__UDQ_IBIT__ 0__INT_LEAST32_TYPE__ long intgpioport__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UK__FLT64_NORM_MAX__ 1.7976931348623157e+308F64GPIOE_IDR GPIO_IDR(GPIOE)GPIOE_PUPDR GPIO_PUPDR(GPIOE)UINTPTR_MAX__LDBL_DENORM_MIN__ 4.9406564584124654e-324L__INT64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_SAT 1GPIO_OTYPE_PP 0x0__ULLFRACT_IBIT__ 0MMIO16(addr) (*(volatile uint16_t *)(addr))AES_BASE (0x50000000U + 0x60000)DAC_BASE (PERIPH_BASE_APB1 + 0x7400)__GNUC__ 12BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)GPIOF_AFRH GPIO_AFRH(GPIOF)WCHAR_MAX__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0UUART5_BASE (PERIPH_BASE_APB1 + 0x5000)__UQQ_IBIT__ 0CORESIGHT_LSR_OFFSET 0xfb4GPIO_AF15 0xf__GCC_ATOMIC_LONG_LOCK_FREE 2__ULACCUM_MIN__ 0.0ULK__LDBL_MAX__ 1.7976931348623157e+308L__ARM_ARCH 7GPIOI_PUPDR GPIO_PUPDR(GPIOI)__FLT_RADIX__ 2BIT3 (1<<3)long long intCORESIGHT_LAR_KEY 0xC5ACCE55__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAX__LDBL_HAS_QUIET_NAN__ 1__LONG_LONG_WIDTH__ 64BIT6 (1<<6)GPIO_AF14 0xe__UINT_FAST64_MAX__ 0xffffffffffffffffULLGPIO2 (1 << 2)GPIOA_AFRL GPIO_AFRL(GPIOA)__HA_IBIT__ 8__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1BIT9 (1<<9)__FLT32X_MIN__ 2.2250738585072014e-308F32xINTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024UINT16_MAXPERIPH_BASE_AHB2 (0x48000000U)__FLT64_MIN__ 2.2250738585072014e-308F64__INTMAX_C(c) c ## LLLIBOPENCM3_GPIO_COMMON_F24_H __ARM_ARCH_PROFILE__INT64_TYPE__ long long intGPIO_OSPEED_50MHZ 0x2__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4GPIOC GPIO_PORT_C_BASECRS_BASE (PERIPH_BASE_APB1 + 0x6000)GPIO_MODE_INPUT 0x0__UFRACT_MAX__ 0XFFFFP-16URINT64_MAXFPB_BASE (PPBI_BASE + 0x2000)GPIOC_LCKR GPIO_LCKR(GPIOC)INT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0GPIOG GPIO_PORT_G_BASESTIR_BASE (SCS_BASE + 0x0F00)__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__ID_BASE (SCS_BASE + 0x0FD0)SYS_TICK_BASE (SCS_BASE + 0x0010)__UFRACT_FBIT__ 16FMC_BASE (0xa0000000U)__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)GPIO6 (1 << 6)__LDBL_MAX_10_EXP__ 308GPIOD_ODR GPIO_ODR(GPIOD)__INT_FAST32_TYPE__ intGPIOB_BSRR GPIO_BSRR(GPIOB)unsigned intGPIOE_MODER GPIO_MODER(GPIOE)__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1GPIOA_BRR GPIO_BRR(GPIOA)__USACCUM_IBIT__ 8ITM_BASE (PPBI_BASE + 0x0000)GPIO_MODE(n,mode) ((mode) << (2 * (n)))ST_VREFINT_CAL MMIO16((INFO_BASE + 0x75aa))__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UK__UTA_IBIT__ 64__FLT_EVAL_METHOD__ 0GPIO12 (1 << 12)__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32DFSDM_BASE (PERIPH_BASE_APB2 + 0x6000)RCC_BASE (PERIPH_BASE_AHB1 + 0x1000)__ARM_FEATURE_LDREX__UQQ_FBIT__ 8INT16_CGPIOE_BSRR GPIO_BSRR(GPIOE)__ARM_FP16_ARGS__GCC_IEC_559 0INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX__GPIOH_IDR GPIO_IDR(GPIOH)__LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4GPIO13 (1 << 13)__STDC__ 1GPIOK_IDR GPIO_IDR(GPIOK)__ARM_FEATURE_IDIV 1__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__DBGMCU_BASE (PPBI_BASE + 0x00042000)gpio_set__ARM_FEATURE_COPROC 15UINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"INT8_MINGPIOD GPIO_PORT_D_BASEGPIO14 (1 << 14)PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)__LDBL_MIN_10_EXP__ (-307)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1__GCC_ATOMIC_CHAR_LOCK_FREE 2__LFRACT_EPSILON__ 0x1P-31LRFMC1_BANK_BASE (0x60000000U)STM32L4 1__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX____FLT32X_NORM_MAX__ 1.7976931348623157e+308F32xGPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC)__arm__ 1__FLT32_MIN_10_EXP__ (-37)MMIO64(addr) (*(volatile uint64_t *)(addr))gpio_port_writeGPIOG_IDR GPIO_IDR(GPIOG)__ARM_FP16_FORMAT_ALTERNATIVE__LDBL_NORM_MAX__ 1.7976931348623157e+308LINTPTR_MINDESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)GPIOH_MODER GPIO_MODER(GPIOH)__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)GPIOA_OTYPER GPIO_OTYPER(GPIOA)__TA_IBIT__ 64GPIOG_MODER GPIO_MODER(GPIOG)GPIOE_AFRL GPIO_AFRL(GPIOE)__ARM_FEATURE_QRDMXGPIO_OTYPE_OD 0x1__ARM_ARCH_ISA_THUMB 2__LONG_LONG_MAX__ 0x7fffffffffffffffLLBIT14 (1<<14)__WINT_WIDTH__ 32GPIOC_MODER GPIO_MODER(GPIOC)SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN__GPIOD_BSRR GPIO_BSRR(GPIOD)__SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__DBL_MIN_EXP__ (-1021)GPIOA GPIO_PORT_A_BASE__LDBL_HAS_DENORM__ 1INT8_MIN (-INT8_MAX - 1)GPIOE_OSPEEDR GPIO_OSPEEDR(GPIOE)GPIO1 (1 << 1)__FLT32_DIG__ 6INT_LEAST16_MAXGPIOG_LCKR GPIO_LCKR(GPIOG)BIT15 (1<<15)GPIO_AF11 0xbGPIOB_AFRH GPIO_AFRH(GPIOB)VREFBUF_BASE (PERIPH_BASE_APB2 + 0x0030)GPIO_LCKK (1 << 16)BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1INT32_MAXGPIOI_LCKR GPIO_LCKR(GPIOI)__ACCUM_MIN__ (-0X1P15K-0X1P15K)GPIO_AF5 0x5__ARM_FEATURE_CRYPTOUART4_BASE (PERIPH_BASE_APB1 + 0x4c00)GPIOJ_ODR GPIO_ODR(GPIOJ)BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__FRACT_IBIT__ 0GPIO_OSPEED_VERYHIGH 0x3UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2GPIO_PUPDR(port) MMIO32((port) + 0x0c)BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234__FLT_NORM_MAX__ 3.4028234663852886e+38Flong long unsigned int__FLT_MIN_10_EXP__ (-37)GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000)GPIOG_BRR GPIO_BRR(GPIOG)__ULACCUM_IBIT__ 32__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__PTRDIFF_TYPE__ int__APCS_32__ 1__DQ_FBIT__ 63GPIOE_AFRH GPIO_AFRH(GPIOE)GPIO_PUPD(n,pupd) ((pupd) << (2 * (n)))INT_LEAST64_MAX__SACCUM_IBIT__ 8reg32__UHQ_IBIT__ 0TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)INT_LEAST8_MINBIT29 (1<<29)LIBOPENCM3_GPIO_COMMON_F234_H __INT_FAST16_TYPE__ intGPIOF_IDR GPIO_IDR(GPIOF)INT64_C__ULFRACT_MAX__ 0XFFFFFFFFP-32ULR__UINT_LEAST16_TYPE__ short unsigned int__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned int__FLT32X_DIG__ 15GPIOI_BSRR GPIO_BSRR(GPIOI)__UTQ_FBIT__ 128__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffffGPIOK_MODER GPIO_MODER(GPIOK)DMA2_BASE (PERIPH_BASE_AHB1 + 0x0400)PTRDIFF_MAX __PTRDIFF_MAX____SIZEOF_SHORT__ 2GPIO_PUPD_PULLDOWN 0x2UINT_FAST16_MAX__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKGPIOC_BRR GPIO_BRR(GPIOC)GPIO_LCKR(port) MMIO32((port) + 0x1c)UINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRGPIO_AF4 0x4__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intGPIOF_MODER GPIO_MODER(GPIOF)gpio_port_readGPIOH_PUPDR GPIO_PUPDR(GPIOH)GPIOK_LCKR GPIO_LCKR(GPIOK)GPIOF_ASCR GPIO_ASCR(GPIOF)WCHAR_MINGPIOB_IDR GPIO_IDR(GPIOB)BEGIN_DECLS GPIOJ_AFRH GPIO_AFRH(GPIOJ)GPIOC_AFRH GPIO_AFRH(GPIOC)__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__FLT32X_MAX__ 1.7976931348623157e+308F32xGPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400)GPIOB_LCKR GPIO_LCKR(GPIOB)GPIOA_ASCR GPIO_ASCR(GPIOA)__ARM_EABI__ 1INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1__ARM_FEATURE_DSP 1__ARM_FPGPIOE_OTYPER GPIO_OTYPER(GPIOE)TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)__QQ_IBIT__ 0__LLACCUM_FBIT__ 31__UINTMAX_TYPE__ long long unsigned int__USQ_IBIT__ 0GPIO7 (1 << 7)__UINT_LEAST32_TYPE__ long unsigned intGPIO_AFR(n,af) ((af) << ((n) * 4))__ARM_FEATURE_NUMERIC_MAXMIN__INTMAX_TYPE__ long long int__GCC_ATOMIC_INT_LOCK_FREE 2GPIOA_BSRR GPIO_BSRR(GPIOA)TIM16_BASE (PERIPH_BASE_APB2 + 0x4400)GPIOG_PUPDR GPIO_PUPDR(GPIOG)INTMAX_MAXGPIOB GPIO_PORT_B_BASEDESIG_PACKAGE MMIO16((INFO_BASE + 0x7500))__ARM_ARCH_7EM__ 1__ARM_FEATURE_FP16_SCALAR_ARITHMETIC__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1TIM17_BASE (PERIPH_BASE_APB2 + 0x4800)__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CINT64_MIN__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intGPIOE_ODR GPIO_ODR(GPIOE)UINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULR/build/libopencm3/lib/stm32/l4__SIZEOF_SIZE_T__ 4__UINT64_TYPE__ long long unsigned int__INT64_C(c) c ## LLGPIO0 (1 << 0)gpio_toggleUSART1_BASE (PERIPH_BASE_APB2 + 0x3800)USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x6800)GPIOD_IDR GPIO_IDR(GPIOD)GPIOB_BRR GPIO_BRR(GPIOB)TPIU_BASE (PPBI_BASE + 0x40000)__LDBL_MIN__ 2.2250738585072014e-308LGPIOD_OTYPER GPIO_OTYPER(GPIOD)__ARM_FEATURE_CDE__ACCUM_IBIT__ 16GPIOJ_MODER GPIO_MODER(GPIOJ)CORESIGHT_LAR_OFFSET 0xfb0EXTI_BASE (PERIPH_BASE_APB2 + 0x0400)LIBOPENCM3_GPIO_H GPIO_AF12 0xcFLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000)short intRNG_BASE (0x50000000U + 0x60800)__UINT16_C(c) cBIT31 (1<<31)__UDA_IBIT__ 32UINT_LEAST32_MAXGPIOI_MODER GPIO_MODER(GPIOI)BIT2 (1<<2)__ATOMIC_RELAXED 0__ARM_FEATURE_COPROCGPIOA_ODR GPIO_ODR(GPIOA)__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53GPIO_BRR(port) MMIO32((port) + 0x28)BIT5 (1<<5)BIT1 (1<<1)INT8_CGPIO_PORT_H_BASE (PERIPH_BASE_AHB2 + 0x1c00)INT_LEAST32_MAX__USES_INITFINI__ 1__DBL_DECIMAL_DIG__ 17BIT8 (1<<8)INT16_C(c) __INT16_C(c)UINT32_MAXGPIO_OSPEED_MED 0x1GPIO_MODE_OUTPUT 0x1__INT16_MAX__ 0x7fffGPIOC_ASCR GPIO_ASCR(GPIOC)__INT_WIDTH__ 32__ARM_FEATURE_SIMD32 1DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x75e0)GPIOD_AFRL GPIO_AFRL(GPIOD)__QQ_FBIT__ 7GPIOC_OTYPER GPIO_OTYPER(GPIOC)RTC_BASE (PERIPH_BASE_APB1 + 0x2800)GPIO_AF3 0x3__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64GPIO_IDR(port) MMIO32((port) + 0x10)GPIO_AFRL(port) MMIO32((port) + 0x20)LPTIM2_BASE (PERIPH_BASE_APB1 + 0x9400)__ULLACCUM_IBIT__ 32GPIO_OSPEEDR(port) MMIO32((port) + 0x08)__ULLFRACT_EPSILON__ 0x1P-64ULLRfalse 0GPIOI_AFRL GPIO_AFRL(GPIOI)__SIZEOF_WINT_T__ 4__ARM_FEATURE_UNALIGNED 1__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1__FLT32X_HAS_DENORM__ 1__ULLACCUM_MIN__ 0.0ULLK__INT_FAST32_WIDTH__ 32GPIOF_LCKR GPIO_LCKR(GPIOF)GPIO_MODE_ANALOG 0x3__ARM_ASM_SYNTAX_UNIFIED__ 1GPIOJ_LCKR GPIO_LCKR(GPIOJ)__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODGPIOA_AFRH GPIO_AFRH(GPIOA)GPIOH_BSRR GPIO_BSRR(GPIOH)__ARM_PCS_VFP 1__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H GPIOG_OTYPER GPIO_OTYPER(GPIOG)LPUART1_BASE (PERIPH_BASE_APB1 + 0x8000)INT_LEAST64_MIN__GCC_CONSTRUCTIVE_SIZE 64__LLFRACT_IBIT__ 0uint32_tBIT12 (1<<12)GPIOB_OTYPER GPIO_OTYPER(GPIOB)MPU_BASE (SCS_BASE + 0x0D90)__SACCUM_EPSILON__ 0x1P-7HK__GCC_ASM_FLAG_OUTPUTS__ 1ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0x75a8))__ARM_FP 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0X7FP-7HR__FLT32X_MANT_DIG__ 53__WCHAR_WIDTH__ 32WINT_MAX__INT16_C(c) cGPIOD_AFRH GPIO_AFRH(GPIOD)INT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32GPIOD_OSPEEDR GPIO_OSPEEDR(GPIOD)GPIO_AFR_MASK(n) (0xf << ((n) * 4))__ATOMIC_ACQ_REL 4__HQ_IBIT__ 0__DBL_MIN_10_EXP__ (-307)dataGPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB)GPIOC_IDR GPIO_IDR(GPIOC)__FLT32_NORM_MAX__ 3.4028234663852886e+38F32GPIOH_AFRL GPIO_AFRL(GPIOH)UINT64_C(c) __UINT64_C(c)__UINTMAX_MAX__ 0xffffffffffffffffULL__DBL_MANT_DIG__ 53GPIO_AF13 0xd__ULFRACT_IBIT__ 0GPIO_ALL 0xffffINT_FAST16_MAXITR_BASE (SCS_BASE + 0x0000)GPIOF GPIO_PORT_F_BASEQUADSPI_BANK_BASE (0x90000000U)__INT_MAX__ 0x7fffffff__INT_LEAST64_TYPE__ long long intGPIOA_PUPDR GPIO_PUPDR(GPIOA)__ARM_FEATURE_CDE_COPROCUINT32_CGCC: (15:12.2.rel1-1) 12.2.1 20221205˙˙˙˙| A3aeabi)7E-M M "ń˙ 79!#%')+-/135;=nźŃ6j¤ ß := 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'*.2 = -// ,/x .!!.…! 0y '# " &.1</. 6!˛$!"&+.1</. . +J1</. 6!! GPIOJ_BSRR GPIO_BSRR(GPIOJ)SCB_BASE (SCS_BASE + 0x0D00)__UHA_FBIT__ 8USB_OTG_FS_BASE (0x50000000U + 0x00000)GPIO_AF6 0x6__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64GPIOK_PUPDR GPIO_PUPDR(GPIOK)CORESIGHT_LSR_SLK (1<<1)__GCC_ATOMIC_WCHAR_T_LOCK_FREE 2LCD_BASE (PERIPH_BASE_APB1 + 0x2400)__CHAR_UNSIGNED__ 1USART3_BASE (PERIPH_BASE_APB1 + 0x4800)GPIO_AF2 0x2__FLT64_HAS_INFINITY__ 1__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GNUC_MINOR__ 2__GCC_DESTRUCTIVE_SIZE 64__LACCUM_EPSILON__ 0x1P-31LK__PTRDIFF_MAX__ 0x7fffffff__ARM_FEATURE_FMA 1GPIO_PUPD_MASK(n) (0x3 << (2 * (n)))__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)__INTMAX_MAX__ 0x7fffffffffffffffLLADC1_BASE (0x50000000U + 0x40000)__FLT64_DECIMAL_DIG__ 17WINT_MIN __WINT_MIN__INT_FAST64_MAXOPAMP_BASE (PERIPH_BASE_APB1 + 0x7800)__ATOMIC_CONSUME 1__ULACCUM_FBIT__ 32__WCHAR_MAX__ 0xffffffffUGPIOF_OTYPER GPIO_OTYPER(GPIOF)GPIO_OSPEED(n,speed) ((speed) << (2 * (n)))GPIOB_ASCR GPIO_ASCR(GPIOB)INT64_MAX __INT64_MAX__INTMAX_MIN__SIZEOF_LONG_LONG__ 8__DBL_MAX_10_EXP__ 308__FRACT_MIN__ (-0.5R-0.5R)__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLKGPIO_OSPEED_25MHZ 0x1__USACCUM_MAX__ 0XFFFFP-8UHK__SFRACT_FBIT__ 7__INTMAX_WIDTH__ 64__ARM_FEATURE_BF16_SCALAR_ARITHMETIC__SQ_IBIT__ 0__ORDER_PDP_ENDIAN__ 3412__SIZE_TYPE__ unsigned intGPIO10 (1 << 10)gpios__FLT_HAS_DENORM__ 1__INT8_TYPE__ signed char__FLT32_MIN__ 1.1754943508222875e-38F32__USACCUM_MIN__ 0.0UHK__FLT32_DECIMAL_DIG__ 9__DECIMAL_DIG__ 17__LDBL_MIN_EXP__ (-1021)INT_FAST16_MIN__LDBL_MANT_DIG__ 53INT64_MIN (-INT64_MAX - 1)GPIOJ GPIO_PORT_J_BASE__UINT8_C(c) c__INT16_TYPE__ short inttrue 1__FLT64_MAX__ 1.7976931348623157e+308F64GPIOE_ASCR GPIO_ASCR(GPIOE)UINT_FAST32_MAXGPIOF_ODR GPIO_ODR(GPIOF)GPIO_BSRR(port) MMIO32((port) + 0x18)GPIO5 (1 << 5)GPIOI_AFRH GPIO_AFRH(GPIOI)INT_FAST64_MAX __INT_FAST64_MAX____GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1GPIOC_PUPDR GPIO_PUPDR(GPIOC)__UINT_LEAST16_MAX__ 0xffff__STDC_HOSTED__ 1__ULLFRACT_FBIT__ 64__SIG_ATOMIC_TYPE__ intGPIOC_AFRL GPIO_AFRL(GPIOC)__INT_FAST64_TYPE__ long long int__WINT_TYPE__ unsigned intGPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800)ST_TSENSE_CAL2_110C MMIO16((INFO_BASE + 0x75ca))INT32_MIN (-INT32_MAX - 1)__FLT32_MAX_10_EXP__ 38GPIO0 (1 << 0)GPIOG_BSRR GPIO_BSRR(GPIOG)__USFRACT_MAX__ 0XFFP-8UHRLPTIM1_BASE (PERIPH_BASE_APB1 + 0x7c00)__FP_FAST_FMAF32 1GPIOH GPIO_PORT_H_BASE__UINTPTR_MAX__ 0xffffffffUGPIO_AF8 0x8__FLT32_MIN_EXP__ (-125)UINT32_MAX __UINT32_MAX__GPIO_MODE_AF 0x2__ULFRACT_FBIT__ 32INT8_MIN (-INT8_MAX - 1)__FLT64_MIN_10_EXP__ (-307)__GNUC_EXECUTION_CHARSET_NAME "UTF-8"BIT10 (1<<10)__INT_FAST64_WIDTH__ 64__STDC_VERSION__ 199901LINT_LEAST64_MAX __INT_LEAST64_MAX__GPIOE_LCKR GPIO_LCKR(GPIOE)__SFRACT_EPSILON__ 0x1P-7HRGPIOK_MODER GPIO_MODER(GPIOK)UINT_LEAST16_MAX __UINT_LEAST16_MAX__UINT32_C(c) __UINT32_C(c)__ORDER_BIG_ENDIAN__ 4321I2C3_BASE (PERIPH_BASE_APB1 + 0x5c00)SYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000)__SQ_FBIT__ 31GPIOI_IDR GPIO_IDR(GPIOI)__UTA_FBIT__ 64__TQ_IBIT__ 0__UHQ_FBIT__ 16__FLT64_MIN_EXP__ (-1021)GPIOK_OTYPER GPIO_OTYPER(GPIOK)__PTRDIFF_WIDTH__ 32__UINT_FAST8_MAX__ 0xffffffffUUINT16_C(c) __UINT16_C(c)__LACCUM_IBIT__ 32GPIO_AF10 0xa__INT_FAST16_WIDTH__ 32INTMAX_C__VERSION__ "12.2.1 20221205"__VFP_FP__ 1__LLFRACT_MIN__ (-0.5LLR-0.5LLR)INT_FAST8_MAX__UINT_FAST16_MAX__ 0xffffffffU__INTPTR_MAX__ 0x7fffffffINT64_C(c) __INT64_C(c)__GCC_IEC_559_COMPLEX 0PERIPH_BASE (0x40000000U)WCHAR_MAX __WCHAR_MAX____FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX__GPIOI_OTYPER GPIO_OTYPER(GPIOI)__UINT_LEAST8_TYPE__ unsigned char__ACCUM_FBIT__ 15PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)__UACCUM_IBIT__ 16long intUINT8_MAXIWDG_BASE (PERIPH_BASE_APB1 + 0x3000)SIZE_MAX __SIZE_MAX__GPIOH_AFRH GPIO_AFRH(GPIOH)__INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1GPIO9 (1 << 9)__FLT32X_EPSILON__ 2.2204460492503131e-16F32xGPIOH_OSPEEDR GPIO_OSPEEDR(GPIOH)NVIC_BASE (SCS_BASE + 0x0100)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32USART2_BASE (PERIPH_BASE_APB1 + 0x4400)__UINTMAX_C(c) c ## ULL__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed charGPIOJ_AFRL GPIO_AFRL(GPIOJ)GPIOJ_OTYPER GPIO_OTYPER(GPIOJ)__GCC_ATOMIC_BOOL_LOCK_FREE 2BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON__GPIO_AF1 0x1__FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX____THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRshort unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)BIT7 (1<<7)BIT17 (1<<17)__FLT32X_MIN_10_EXP__ (-307)UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)__DBL_IS_IEC_60559__ 2__UINT_FAST32_MAX__ 0xffffffffU__DEC_EVAL_METHOD__ 2__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32__FLT32X_MIN_EXP__ (-1021)DMA1_BASE (PERIPH_BASE_AHB1 + 0x0000)GPIO_AF9 0x9GPIOB_PUPDR GPIO_PUPDR(GPIOB)GNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsBIT27 (1<<27)TIM1_BASE (PERIPH_BASE_APB2 + 0x2C00)GPIOH_ODR GPIO_ODR(GPIOH)__FLT_MIN_10_EXP__ (-37)INTMAX_C(c) __INTMAX_C(c)__FLT_DECIMAL_DIG__ 9__thumb__ 1__INT_LEAST32_MAX__ 0x7fffffffLLIBOPENCM3_MEMORYMAP_COMMON_H signed charuint8_tINT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)INT32_C(c) __INT32_C(c)__GNUC_STDC_INLINE__ 1GPIOE_BRR GPIO_BRR(GPIOE)GPIO_PUPD_PULLUP 0x1LIBOPENCM3_GPIO_COMMON_ALL_H __FRACT_FBIT__ 15__LLACCUM_EPSILON__ 0x1P-31LLK__GNUC_PATCHLEVEL__ 1__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2PTRDIFF_MIN__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)UINTPTR_MAX __UINTPTR_MAX____ARM_ARCH_PROFILE 77GPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000)__FLT64_MAX_10_EXP__ 308GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400)MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINGPIOF_OSPEEDR GPIO_OSPEEDR(GPIOF)pull_up_downSDMMC1_BASE (PERIPH_BASE_APB2 + 0x2800)__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)__FRACT_MAX__ 0X7FFFP-15RTIM3_BASE (PERIPH_BASE_APB1 + 0x0400)INT_LEAST32_MAX __INT_LEAST32_MAX____INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5GPIO2 (1 << 2)GPIO_ASCR(port) MMIO32((port) + 0x2c)GPIO_AF7 0x7GPIO11 (1 << 11)__UINT16_MAX__ 0xffff__TQ_FBIT__ 127GPIOJ_PUPDR GPIO_PUPDR(GPIOJ)__USQ_FBIT__ 32__USES_INITFINI__ 1__thumb2__ 1__ULLACCUM_FBIT__ 32FMC_QUADSPI_BASE (0xA0000000U)__FLT_DENORM_MIN__ 1.4012984643248171e-45F__STRICT_ANSI__ 1FMC3_BANK_BASE (0x80000000U)UINT_LEAST8_MAXGPIOG_AFRH GPIO_AFRH(GPIOG)UINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)TIM8_BASE (PERIPH_BASE_APB2 + 0x3400)GPIO_OTYPER(port) MMIO32((port) + 0x04)__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__GPIOD_PUPDR GPIO_PUPDR(GPIOD)__USA_IBIT__ 16__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1PTRDIFF_MIN (-PTRDIFF_MAX - 1)USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6c00)__UINT_FAST64_TYPE__ long long unsigned intDESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 0x14)moderGPIOG_AFRL GPIO_AFRL(GPIOG)DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7590)__FLT_MIN__ 1.1754943508222875e-38FGPIOG_ODR GPIO_ODR(GPIOG)__HA_FBIT__ 7GPIOD_ASCR GPIO_ASCR(GPIOD)__FDPIC____UFRACT_MIN__ 0.0UR__FLT32_IS_IEC_60559__ 2GPIOI_OSPEEDR GPIO_OSPEEDR(GPIOI)GPIO_PORT_G_BASE (PERIPH_BASE_AHB2 + 0x1800)INT_FAST64_MIN__USFRACT_IBIT__ 0__INT32_C(c) c ## L__LDBL_EPSILON__ 2.2204460492503131e-16LGPIOB_MODER GPIO_MODER(GPIOB)__USFRACT_MIN__ 0.0UHRTSC_BASE (PERIPH_BASE_AHB1 + 0x4000)__ARM_NEON__UINT8_MAX__ 0xff__LDBL_MAX_EXP__ 1024LIBOPENCM3_MEMORYMAP_H GPIOK_BSRR GPIO_BSRR(GPIOK)alt_func_numDESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)GPIO8 (1 << 8)GPIO_OSPEED_LOW 0x0GPIOB_AFRL GPIO_AFRL(GPIOB)QUADSPI_BASE (0xa0001000U)__DA_FBIT__ 31__GXX_ABI_VERSION 1017GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0c00)__INT_LEAST16_MAX__ 0x7fffGPIOI GPIO_PORT_I_BASEID_BASE (SCS_BASE + 0x0FD0)__ULLACCUM_EPSILON__ 0x1P-32ULLKGPIOC_ODR GPIO_ODR(GPIOC)GPIOA_LCKR GPIO_LCKR(GPIOA)INT_LEAST8_MAX __INT_LEAST8_MAX__GPIOK_ODR GPIO_ODR(GPIOK)__UINT32_C(c) c ## ULGPIOD_LCKR GPIO_LCKR(GPIOD)__UACCUM_MIN__ 0.0UK__FLT_EPSILON__ 1.1920928955078125e-7FGPIO_MODE_MASK(n) (0x3 << (2 * (n)))GPIO_AF0 0x0TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)__ARM_ARCH_ISA_THUMBGPIOH_ASCR GPIO_ASCR(GPIOH)__ARM_FEATURE_MATMUL_INT8__UINT8_TYPE__ unsigned charLIBOPENCM3_CM3_MEMORYMAP_H __GCC_ATOMIC_SHORT_LOCK_FREE 2__USACCUM_FBIT__ 8__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1__LACCUM_FBIT__ 31SCS_BASE (PPBI_BASE + 0xE000)GPIOC_BSRR GPIO_BSRR(GPIOC)GPIOF_PUPDR GPIO_PUPDR(GPIOF)SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)__FLT32_HAS_QUIET_NAN__ 1I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)GPIOB_ODR GPIO_ODR(GPIOB)__LDBL_HAS_INFINITY__ 1GPIOD_MODER GPIO_MODER(GPIOD)__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))__FLT32X_MAX_10_EXP__ 308GPIOJ_IDR GPIO_IDR(GPIOJ)otypeDWT_BASE (PPBI_BASE + 0x1000)GPIOG_OSPEEDR GPIO_OSPEEDR(GPIOG)GPIOK_AFRL GPIO_AFRL(GPIOK)GPIO_PUPD_NONE 0x0bool _BoolUINTMAX_MAX __UINTMAX_MAX____SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffGPIOA_IDR GPIO_IDR(GPIOA)BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)GPIO3 (1 << 3)INT16_MAX __INT16_MAX____FP_FAST_FMAF 1__FLT32X_IS_IEC_60559__ 2GPIO_OSPEED_2MHZ 0x0PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)GPIOF_BSRR GPIO_BSRR(GPIOF)LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))FIREWALL_BASE (PERIPH_BASE_APB2 + 0x1C00)GPIOK_OSPEEDR GPIO_OSPEEDR(GPIOK)__INT_LEAST16_WIDTH__ 16SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)__ARM_FEATURE_FP16_FMLINT16_MIN (-INT16_MAX - 1)__USFRACT_EPSILON__ 0x1P-8UHR__WINT_MAX__ 0xffffffffU__USFRACT_FBIT__ 8ospeedrCORESIGHT_LSR_SLI (1<<0)GPIOE GPIO_PORT_E_BASE__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX____UINT32_MAX__ 0xffffffffULGPIOK_AFRH GPIO_AFRH(GPIOK)../common/gpio_common_f0234.c__INT_LEAST8_MAX__ 0x7f__GCC_ATOMIC_POINTER_LOCK_FREE 2__ARM_FEATURE_QBIT 1__ARM_FEATURE_CLZ 1GPIO4 (1 << 4)__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXGPIO_ODR(port) MMIO32((port) + 0x14)GPIO_OSPEED_HIGH 0x2GPIOK GPIO_PORT_K_BASE__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024GPIO_MODER(port) MMIO32((port) + 0x00)__UINT_LEAST32_MAX__ 0xffffffffUL__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1GPIOJ_OSPEEDR GPIO_OSPEEDR(GPIOJ)__ACCUM_MAX__ 0X7FFFFFFFP-15K__INT8_MAX__ 0x7fBIT14 (1<<14)GPIO_OSPEED_MASK(n) (0x3 << (2 * (n)))__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16__SHRT_WIDTH__ 16BIT20 (1<<20)__ARM_FEATURE_MVE__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intGPIOF_AFRL GPIO_AFRL(GPIOF)SWPMI1_BASE (PERIPH_BASE_APB1 + 0x8800)SAI1_BASE (PERIPH_BASE_APB2 + 0x5400)INT_FAST32_MINGPIO_AFRH(port) MMIO32((port) + 0x24)__FLT_EVAL_METHOD_TS_18661_3__ 0__SCHAR_WIDTH__ 8BIT18 (1<<18)COMP_BASE (PERIPH_BASE_APB2 + 0x0200)SIZE_MAX__UINT_FAST8_TYPE__ unsigned int__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RBIT24 (1<<24)GPIO_AF11 0xb__INT32_MAX__ 0x7fffffffLUINTMAX_MAX__DBL_HAS_DENORM__ 1BIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLLGPIOI_ODR GPIO_ODR(GPIOI)__ARM_FEATURE_BF16_VECTOR_ARITHMETICINFO_BASE (0x1fff0000U)PPBI_BASE (0xE0000000U)__FLT32_MANT_DIG__ 24GPIOG_ASCR GPIO_ASCR(GPIOG)INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN__GPIOH_LCKR GPIO_LCKR(GPIOH)INT8_MAX __INT8_MAX__BIT28 (1<<28)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2GPIOF_BRR GPIO_BRR(GPIOF)__DBL_MAX_EXP__ 1024__ATOMIC_RELEASE 3UINT_FAST8_MAX__FLT_MANT_DIG__ 24__UDQ_IBIT__ 0__INT_LEAST32_TYPE__ long int__OPTIMIZE_SIZE__ 1__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UK__FLT64_NORM_MAX__ 1.7976931348623157e+308F64GPIOE_IDR GPIO_IDR(GPIOE)GPIOE_PUPDR GPIO_PUPDR(GPIOE)UINTPTR_MAX__LDBL_DENORM_MIN__ 4.9406564584124654e-324L__INT64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_SAT 1GPIO_OTYPE_PP 0x0__ULLFRACT_IBIT__ 0MMIO16(addr) (*(volatile uint16_t *)(addr))AES_BASE (0x50000000U + 0x60000)DAC_BASE (PERIPH_BASE_APB1 + 0x7400)__GNUC__ 12BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)GPIOF_AFRH GPIO_AFRH(GPIOF)WCHAR_MAX__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0UUART5_BASE (PERIPH_BASE_APB1 + 0x5000)__UQQ_IBIT__ 0CORESIGHT_LSR_OFFSET 0xfb4GPIO_AF15 0xf__GCC_ATOMIC_LONG_LOCK_FREE 2__ULACCUM_MIN__ 0.0ULK__LDBL_MAX__ 1.7976931348623157e+308L__ARM_ARCH 7GPIOI_PUPDR GPIO_PUPDR(GPIOI)__FLT_RADIX__ 2BIT3 (1<<3)long long intCORESIGHT_LAR_KEY 0xC5ACCE55__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAX__LDBL_HAS_QUIET_NAN__ 1__LONG_LONG_WIDTH__ 64BIT6 (1<<6)GPIO_AF14 0xe__UINT_FAST64_MAX__ 0xffffffffffffffffULL__ARM_FPGPIOA_AFRL GPIO_AFRL(GPIOA)__HA_IBIT__ 8__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1BIT9 (1<<9)__FLT32X_MIN__ 2.2250738585072014e-308F32xINTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024UINT16_MAXPERIPH_BASE_AHB2 (0x48000000U)__FLT64_MIN__ 2.2250738585072014e-308F64__INTMAX_C(c) c ## LLLIBOPENCM3_GPIO_COMMON_F24_H __ARM_ARCH_PROFILE__INT64_TYPE__ long long intGPIO_OSPEED_50MHZ 0x2__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4GPIOC GPIO_PORT_C_BASECRS_BASE (PERIPH_BASE_APB1 + 0x6000)GPIO_MODE_INPUT 0x0__UFRACT_MAX__ 0XFFFFP-16URINT64_MAXFPB_BASE (PPBI_BASE + 0x2000)GPIOC_LCKR GPIO_LCKR(GPIOC)INT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0GPIOG GPIO_PORT_G_BASESTIR_BASE (SCS_BASE + 0x0F00)__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)SYS_TICK_BASE (SCS_BASE + 0x0010)__UFRACT_FBIT__ 16FMC_BASE (0xa0000000U)__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)GPIO6 (1 << 6)__LDBL_MAX_10_EXP__ 308GPIOD_ODR GPIO_ODR(GPIOD)gpio_set_output_options__INT_FAST32_TYPE__ intGPIOB_BSRR GPIO_BSRR(GPIOB)unsigned intGPIOE_MODER GPIO_MODER(GPIOE)__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1GPIOA_BRR GPIO_BRR(GPIOA)__USACCUM_IBIT__ 8ITM_BASE (PPBI_BASE + 0x0000)GPIO_MODE(n,mode) ((mode) << (2 * (n)))ST_VREFINT_CAL MMIO16((INFO_BASE + 0x75aa))__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UK__UTA_IBIT__ 64__FLT_EVAL_METHOD__ 0GPIO12 (1 << 12)__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32DFSDM_BASE (PERIPH_BASE_APB2 + 0x6000)RCC_BASE (PERIPH_BASE_AHB1 + 0x1000)__ARM_FEATURE_LDREX__UQQ_FBIT__ 8INT16_CGPIOE_BSRR GPIO_BSRR(GPIOE)__ARM_FP16_ARGS__GCC_IEC_559 0__FLT32X_DIG__ 15INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX__GPIOH_IDR GPIO_IDR(GPIOH)__LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4GPIO13 (1 << 13)__STDC__ 1GPIOK_IDR GPIO_IDR(GPIOK)__ARM_FEATURE_IDIV 1__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__DBGMCU_BASE (PPBI_BASE + 0x00042000)__ARM_FEATURE_COPROC 15gpio_set_afUINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"INT8_MINGPIOD GPIO_PORT_D_BASEGPIO14 (1 << 14)PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)INT8_C__LDBL_MIN_10_EXP__ (-307)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1__GCC_ATOMIC_CHAR_LOCK_FREE 2__LFRACT_EPSILON__ 0x1P-31LRFMC1_BANK_BASE (0x60000000U)STM32L4 1__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX____FLT32X_NORM_MAX__ 1.7976931348623157e+308F32xGPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC)__arm__ 1__FLT32_MIN_10_EXP__ (-37)afrhMMIO64(addr) (*(volatile uint64_t *)(addr))GPIOG_IDR GPIO_IDR(GPIOG)__ARM_FP16_FORMAT_ALTERNATIVEafrl__LDBL_NORM_MAX__ 1.7976931348623157e+308LINTPTR_MINDESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)GPIOH_MODER GPIO_MODER(GPIOH)__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)GPIOA_OTYPER GPIO_OTYPER(GPIOA)__TA_IBIT__ 64GPIOG_MODER GPIO_MODER(GPIOG)GPIOE_AFRL GPIO_AFRL(GPIOE)__ARM_FEATURE_QRDMXGPIO_OTYPE_OD 0x1__ARM_ARCH_ISA_THUMB 2__LONG_LONG_MAX__ 0x7fffffffffffffffLL__WINT_WIDTH__ 32GPIOC_MODER GPIO_MODER(GPIOC)SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN__GPIOD_BSRR GPIO_BSRR(GPIOD)__SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__DBL_MIN_EXP__ (-1021)GPIOA GPIO_PORT_A_BASE__LDBL_HAS_DENORM__ 1INT_FAST32_MIN (-INT_FAST32_MAX - 1)GPIOE_OSPEEDR GPIO_OSPEEDR(GPIOE)GPIO1 (1 << 1)__FLT32_DIG__ 6INT_LEAST16_MAXGPIOG_LCKR GPIO_LCKR(GPIOG)BIT15 (1<<15)GPIOB_AFRH GPIO_AFRH(GPIOB)VREFBUF_BASE (PERIPH_BASE_APB2 + 0x0030)GPIO_LCKK (1 << 16)BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1INT32_MAXGPIOI_LCKR GPIO_LCKR(GPIOI)__ACCUM_MIN__ (-0X1P15K-0X1P15K)GPIO_AF5 0x5__ARM_FEATURE_CRYPTOUART4_BASE (PERIPH_BASE_APB1 + 0x4c00)GPIOJ_ODR GPIO_ODR(GPIOJ)BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__FRACT_IBIT__ 0GPIO_OSPEED_VERYHIGH 0x3UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2GPIO_PUPDR(port) MMIO32((port) + 0x0c)BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234__FLT_NORM_MAX__ 3.4028234663852886e+38Flong long unsigned intGPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000)GPIOG_BRR GPIO_BRR(GPIOG)__ULACCUM_IBIT__ 32__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__PTRDIFF_TYPE__ int__APCS_32__ 1__DQ_FBIT__ 63GPIOE_AFRH GPIO_AFRH(GPIOE)GPIO_PUPD(n,pupd) ((pupd) << (2 * (n)))INT_LEAST64_MAX__SACCUM_IBIT__ 8__UHQ_IBIT__ 0TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)INT_LEAST8_MINBIT29 (1<<29)LIBOPENCM3_GPIO_COMMON_F234_H __INT_FAST16_TYPE__ intGPIOF_IDR GPIO_IDR(GPIOF)INT64_C__ULFRACT_MAX__ 0XFFFFFFFFP-32ULR__UINT_LEAST16_TYPE__ short unsigned int__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned intgpio_mode_setupGPIOI_BSRR GPIO_BSRR(GPIOI)__UTQ_FBIT__ 128__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffffDMA2_BASE (PERIPH_BASE_AHB1 + 0x0400)PTRDIFF_MAX __PTRDIFF_MAX____SIZEOF_SHORT__ 2GPIO_PUPD_PULLDOWN 0x2UINT_FAST16_MAX__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKGPIOC_BRR GPIO_BRR(GPIOC)GPIO_LCKR(port) MMIO32((port) + 0x1c)UINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRGPIO_AF4 0x4__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intGPIOF_MODER GPIO_MODER(GPIOF)GPIOH_PUPDR GPIO_PUPDR(GPIOH)GPIOK_LCKR GPIO_LCKR(GPIOK)GPIOF_ASCR GPIO_ASCR(GPIOF)WCHAR_MINGPIOB_IDR GPIO_IDR(GPIOB)BEGIN_DECLS GPIOJ_AFRH GPIO_AFRH(GPIOJ)GPIOC_AFRH GPIO_AFRH(GPIOC)__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__FLT32X_MAX__ 1.7976931348623157e+308F32xGPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400)GPIOB_LCKR GPIO_LCKR(GPIOB)GPIOA_ASCR GPIO_ASCR(GPIOA)__ARM_EABI__ 1GPIOA_MODER GPIO_MODER(GPIOA)INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1__ARM_FEATURE_DSP 1GPIOE_OTYPER GPIO_OTYPER(GPIOE)TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)__QQ_IBIT__ 0__LLACCUM_FBIT__ 31__UINTMAX_TYPE__ long long unsigned int__USQ_IBIT__ 0GPIO7 (1 << 7)__UINT_LEAST32_TYPE__ long unsigned intGPIO_AFR(n,af) ((af) << ((n) * 4))__ARM_FEATURE_NUMERIC_MAXMIN__INTMAX_TYPE__ long long int__GCC_ATOMIC_INT_LOCK_FREE 2GPIOA_BSRR GPIO_BSRR(GPIOA)TIM16_BASE (PERIPH_BASE_APB2 + 0x4400)GPIOG_PUPDR GPIO_PUPDR(GPIOG)INTMAX_MAXGPIOB GPIO_PORT_B_BASEDESIG_PACKAGE MMIO16((INFO_BASE + 0x7500))__ARM_ARCH_7EM__ 1__ARM_FEATURE_FP16_SCALAR_ARITHMETIC__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1TIM17_BASE (PERIPH_BASE_APB2 + 0x4800)__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CINT64_MIN__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intGPIOE_ODR GPIO_ODR(GPIOE)UINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULR/build/libopencm3/lib/stm32/l4__SIZEOF_SIZE_T__ 4__UINT64_TYPE__ long long unsigned intuint16_t__INT64_C(c) c ## LLgpioportUSART1_BASE (PERIPH_BASE_APB2 + 0x3800)USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x6800)GPIOD_IDR GPIO_IDR(GPIOD)GPIOB_BRR GPIO_BRR(GPIOB)TPIU_BASE (PPBI_BASE + 0x40000)__LDBL_MIN__ 2.2250738585072014e-308LGPIOD_OTYPER GPIO_OTYPER(GPIOD)__ARM_FEATURE_CDE__ACCUM_IBIT__ 16GPIOJ_MODER GPIO_MODER(GPIOJ)CORESIGHT_LAR_OFFSET 0xfb0EXTI_BASE (PERIPH_BASE_APB2 + 0x0400)LIBOPENCM3_GPIO_H GPIO_AF12 0xcINT_LEAST32_MIN (-INT_LEAST32_MAX - 1)FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000)short intRNG_BASE (0x50000000U + 0x60800)__UINT16_C(c) cBIT31 (1<<31)__UDA_IBIT__ 32modeUINT_LEAST32_MAXGPIOI_MODER GPIO_MODER(GPIOI)BIT2 (1<<2)__ATOMIC_RELAXED 0__ARM_FEATURE_COPROCGPIOA_ODR GPIO_ODR(GPIOA)__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53GPIO_BRR(port) MMIO32((port) + 0x28)BIT5 (1<<5)BIT1 (1<<1)BIT26 (1<<26)GPIO_PORT_H_BASE (PERIPH_BASE_AHB2 + 0x1c00)INT_LEAST32_MAX__ARM_ARCH_EXT_IDIV__ 1__DBL_DECIMAL_DIG__ 17BIT8 (1<<8)INT16_C(c) __INT16_C(c)UINT32_MAXGPIO_OSPEED_MED 0x1GPIO_MODE_OUTPUT 0x1__INT16_MAX__ 0x7fffGPIOC_ASCR GPIO_ASCR(GPIOC)__INT_WIDTH__ 32__ARM_FEATURE_SIMD32 1DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x75e0)GPIOD_AFRL GPIO_AFRL(GPIOD)__QQ_FBIT__ 7GPIOC_OTYPER GPIO_OTYPER(GPIOC)RTC_BASE (PERIPH_BASE_APB1 + 0x2800)GPIO_AF3 0x3__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64GPIO_IDR(port) MMIO32((port) + 0x10)GPIO_AFRL(port) MMIO32((port) + 0x20)LPTIM2_BASE (PERIPH_BASE_APB1 + 0x9400)__ULLACCUM_IBIT__ 32GPIO_OSPEEDR(port) MMIO32((port) + 0x08)__ULLFRACT_EPSILON__ 0x1P-64ULLRfalse 0GPIOI_AFRL GPIO_AFRL(GPIOI)__SIZEOF_WINT_T__ 4__ARM_FEATURE_UNALIGNED 1__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1__FLT32X_HAS_DENORM__ 1__ULLACCUM_MIN__ 0.0ULLK__INT_FAST32_WIDTH__ 32GPIOF_LCKR GPIO_LCKR(GPIOF)GPIO_MODE_ANALOG 0x3__ARM_ASM_SYNTAX_UNIFIED__ 1GPIOJ_LCKR GPIO_LCKR(GPIOJ)__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODGPIOA_AFRH GPIO_AFRH(GPIOA)GPIOH_BSRR GPIO_BSRR(GPIOH)__ARM_PCS_VFP 1__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H GPIOG_OTYPER GPIO_OTYPER(GPIOG)LPUART1_BASE (PERIPH_BASE_APB1 + 0x8000)INT_LEAST64_MIN__GCC_CONSTRUCTIVE_SIZE 64__LLFRACT_IBIT__ 0uint32_tBIT12 (1<<12)GPIOB_OTYPER GPIO_OTYPER(GPIOB)MPU_BASE (SCS_BASE + 0x0D90)__SACCUM_EPSILON__ 0x1P-7HK__GCC_ASM_FLAG_OUTPUTS__ 1ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0x75a8))__ARM_FP 4__UINT_FAST16_TYPE__ unsigned intGPIOA_OSPEEDR GPIO_OSPEEDR(GPIOA)__UHA_IBIT__ 8__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULK__LDBL_DIG__ 15POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXBIT16 (1<<16)__WINT_MIN__ 0UINT_LEAST16_MIN__FLT64_DIG__ 15TIM15_BASE (PERIPH_BASE_APB2 + 0x4000)BIT22 (1<<22)__INT_LEAST8_WIDTH__ 8WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)__INT_LEAST16_TYPE__ short int__DBL_MAX__ ((double)1.7976931348623157e+308L)INT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1UINTMAX_CGPIOH_BRR GPIO_BRR(GPIOH)GPIOD_BRR GPIO_BRR(GPIOD)INT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1GPIO15 (1 << 15)GPIOH_OTYPER GPIO_OTYPER(GPIOH)__HQ_FBIT__ 15__bool_true_false_are_defined 1pupd__SIZE_MAX__ 0xffffffffUSPI2_BASE (PERIPH_BASE_APB1 + 0x3800)__ARM_ARCH__LONG_MAX__ 0x7fffffffLGPIO_OSPEED_100MHZ 0x3SAI2_BASE (PERIPH_BASE_APB2 + 0x5800)__ARM_FEATURE_LDREX 7PTRDIFF_MAX__LLFRACT_EPSILON__ 0x1P-63LLR__SFRACT_MAX__ 0X7FP-7HR__FLT32X_MANT_DIG__ 53__WCHAR_WIDTH__ 32WINT_MAXspeed__INT16_C(c) cGPIOD_AFRH GPIO_AFRH(GPIOD)INT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32GPIOD_OSPEEDR GPIO_OSPEEDR(GPIOD)GPIO_AFR_MASK(n) (0xf << ((n) * 4))__ATOMIC_ACQ_REL 4__HQ_IBIT__ 0__DBL_MIN_10_EXP__ (-307)GPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB)GPIOC_IDR GPIO_IDR(GPIOC)__FLT32_NORM_MAX__ 3.4028234663852886e+38F32GPIOH_AFRL GPIO_AFRL(GPIOH)UINT64_C(c) __UINT64_C(c)__UINTMAX_MAX__ 0xffffffffffffffffULL__DBL_MANT_DIG__ 53GPIO_AF13 0xd__ULFRACT_IBIT__ 0GPIO_ALL 0xffffINT_FAST16_MAXITR_BASE (SCS_BASE + 0x0000)GPIOF GPIO_PORT_F_BASEQUADSPI_BANK_BASE (0x90000000U)__INT_MAX__ 0x7fffffff__INT_LEAST64_TYPE__ long long intGPIOA_PUPDR GPIO_PUPDR(GPIOA)__ARM_FEATURE_CDE_COPROCUINT32_CGCC: (15:12.2.rel1-1) 12.2.1 20221205˙˙˙˙| @B„…†‡Ž6F„…†‡ŽXA„…†‡ŽA3aeabi)7E-M M "ń˙ 35!#%')+-/17?pˇÓ8l¦ á 69 J@Z6rXgpio_common_f0234.c$twm4.0.c5e6bdb01417bb5a599260a3f8c9cb62wm4.common.h.21.c9066c2f6b12c71b40226ea6107829a4wm4.stdint.h.29.6d480f4ba0f60596e88234283d42444fwm4.stdbool.h.29.4a1c88fe569adb8d03217dd16982ca34wm4.common.h.67.5c568a1f62c8e726909b04e29f9e1fc0wm4.memorymap.h.21.8c90486dae5eea2d8efddd23fe5d09d9wm4.memorymap.h.26.bb1efb6ce36cc052fd0489ef5a3533f5wm4.gpio_common_all.h.37.fedbbcb9179f773c905aa3c3e4b7dbddwm4.gpio_common_f234.h.48.1db4d0a0536896711e20c0a147f92021wm4.gpio_common_f24.h.48.d7799bf98ecad7663b4b299525c33e1bwm4.gpio.h.45.1a567f279811a2250901d3d88a79c054gpio_mode_setupgpio_set_output_optionsgpio_set_af "&-4;BGTYfkxŤ’— ¦łŔÔ Ř Ýç ë đú ţ %0 4 9FZ ^ cm q w~‰–Ł°Ä Č Í× Ű ŕę î ? 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"† K;- "Ś =‘ =– 7.."ś !ˇ =¦ =« !° !µ !ş !ż !Ë /Ö =ŕ =ę =ô =ţ =Ž >."K/000"/"</ ö} †..U ///!20 # MT4‚~. ô ./<n<Č"<" ! /===p. ! /==/+1LIBOPENCM3_CM3_MEMORYMAP_H __LACCUM_EPSILON__ 0x1P-31LK__thumb__ 1I2C_OAR1_OA1MODE_10BIT 1__UACCUM_FBIT__ 16__APCS_32__ 1I2C_CR2_NACK (1 << 15)__LFRACT_EPSILON__ 0x1P-31LR__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__RCC_APB1RSTR1_TIM2RST (1 << 0)__FLT_NORM_MAX__ 3.4028234663852886e+38FI2C_ICR_ADDRCF (1 << 3)RCC_APB1ENR2 MMIO32(RCC_BASE + RCC_APB1ENR2_OFFSET)__USACCUM_MIN__ 0.0UHK__ARM_FEATURE_MATMUL_INT8RCC_APB1SMENR2_OFFSET 0x7c__FLT32_DIG__ 6I2C_CR2_RD_WRN (1 << 10)__FLT32X_MAX__ 1.7976931348623157e+308F32x__UACCUM_IBIT__ 16RCC_APB2ENR_TIM15EN (1 << 16)INTPTR_MIN (-INTPTR_MAX - 1)RCC_CFGR_SWS_MASK 0x3RCC_APB2SMENR_SPI1SMEN (1 << 12)RCC_CCIPR_UARTxSEL_LSE RCC_CCIPR_USARTxSEL_LSE__INT_FAST16_MAX__ 0x7fffffffI2C_CR2_PECBYTE (1 << 26)RCC_AHB2ENR_OTGFSEN (1 << 12)TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)__FLT64_MANT_DIG__ 53UINT_LEAST8_MAX __UINT_LEAST8_MAX__UINT_FAST16_MAX __UINT_FAST16_MAX__RCC_AHB2RSTR_OFFSET 0x2cINT_LEAST16_MIN (-INT_LEAST16_MAX - 1)RCC_CICR MMIO32(RCC_BASE + 0x20)RCC_CCIPR_UARTxSEL_HSI16 RCC_CCIPR_USARTxSEL_HSI16RST_DAC1RCC_APB1SMENR1_PWRSMEN (1 << 28)RCC_AHB1SMENR MMIO32(RCC_BASE + RCC_AHB1SMENR_OFFSET)__USQ_IBIT__ 0__PTRDIFF_MAX__ 0x7fffffffRCC_APB2SMENR_OFFSET 0x80INT64_MIN (-INT64_MAX - 1)RCC_CFGR_PPRE2_DIV16 0x7UINT_FAST32_MAXRCC_APB2ENR_SAI2EN (1 << 22)CORESIGHT_LSR_SLI (1<<0)BIT10 (1<<10)UINT_FAST64_MAXI2C_TXDR(i2c_base) MMIO32((i2c_base) + 0x28)__STDC__ 1RCC_APB2SMENR_SDMMC1SMEN (1 << 10)I2C_OAR2_OA2MSK_OA2_7_OA2_6 (0x5 << 8)I2C_CR2_AUTOEND (1 << 25)I2C_CR1_SMBDEN (1 << 21)__ULLFRACT_IBIT__ 0__FLT32_MAX_EXP__ 128__SA_FBIT__ 15RCC_CCIPR_LPTIMxSEL_HSI16 2__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__UDA_FBIT__ 32RCC_AHB1SMENR_DMA1SMEN (1 << 0)LIBOPENCM3_I2C_H __DBL_MAX_10_EXP__ 308RCC_APB1ENR2_LPUART1EN (1 << 0)INT_LEAST32_MINi2c_set_prescaler__UINT_FAST64_MAX__ 0xffffffffffffffffULLUART4_BASE (PERIPH_BASE_APB1 + 0x4c00)__ARM_FEATURE_IDIV 1RCC_PLLCFGR_PLLP (1 << 17)RCC_AHB1SMENR_CRCSMEN (1 << 12)__WCHAR_TYPE__ unsigned intI2C_OAR2(i2c_base) MMIO32((i2c_base) + 0x0c)__UDA_IBIT__ 32i2c_speed_unknownI2C_OAR2_OA2MSK_OA2_7_OA2_5 (0x4 << 8)__ELF__ 1RCC_CIER_HSI48RDYIE (1 << 10)__SIZEOF_LONG__ 4DWT_BASE (PPBI_BASE + 0x1000)__ARM_ARCH 7I2C1_TIMINGR I2C_TIMINGR(I2C1)RCC_CFGR_SWS_SHIFT 2BIT11 (1<<11)RST_CAN1_BoolRCC_AHB2RSTR MMIO32(RCC_BASE + RCC_AHB2RSTR_OFFSET)LIBOPENCM3_MEMORYMAP_H RCC_APB2RSTR_SDMMC1RST (1 << 10)BIT3 (1<<3)RCC_PLLCFGR_PLLQ_MASK 0x3__UINT_LEAST64_TYPE__ long long unsigned intRCC_CFGR_SW_HSI16 0x1_STDBOOL_H I2C_OAR2_OA2MSK_OA2_7_OA2_4 (0x3 << 8)SIG_ATOMIC_MIN__SHRT_WIDTH__ 16__STRICT_ANSI__ 1I2C_CR1_DNF_SHIFT 8WINT_MINRCC_APB2ENR_TIM17EN (1 << 18)__INTPTR_TYPE__ intRST_FMC__DQ_FBIT__ 63__UACCUM_EPSILON__ 0x1P-16UKRCC_CCIPR MMIO32(RCC_BASE + 0x88)__INT_FAST16_WIDTH__ 32I2C_CR1(i2c_base) MMIO32((i2c_base) + 0x00)RCC_CCIPR_LPTIMxSEL_APB 0__FLT_HAS_INFINITY__ 1RCC_APB1RSTR1_TIM4RST (1 << 2)uint16_tRCC_CICR_PLLRDYC (1 << 5)RCC_APB1ENR1_USART2EN (1 << 17)INT_FAST64_MAX __INT_FAST64_MAX__BIT12 (1<<12)I2C_OAR2_OA2MSK_OA2_7_OA2_3 (0x2 << 8)__LLACCUM_IBIT__ 32RCC_APB1RSTR1_PWRRST (1 << 28)RCC_APB1SMENR1_LPTIM1SMEN (1 << 31)RCC_AHB1ENR_TSCEN (1 << 16)dnf_setting__FP_FAST_FMAF32 1_T_PTRDIFF_ I2C_CR2_SADD_10BIT_SHIFT 0i2c_set_data_setup_timeI2C_CR2_START (1 << 13)RCC_CFGR_MCO_LSI 0x6RCC_APB1SMENR1_LCDSMEN (1 << 9)RCC_CFGR_MCOPRE_DIV4 2RCC_CIFR_LSIRDYF (1 << 0)I2C_OAR2_OA2MSK_OA2_7_OA2_2 (0x1 << 8)__SFRACT_MIN__ (-0.5HR-0.5HR)__INT_LEAST16_WIDTH__ 16__USFRACT_MIN__ 0.0UHRRCC_APB1ENR2_SWPMI1EN (1 << 2)__INT_LEAST32_TYPE__ long int__DBL_HAS_INFINITY__ 1GPIO_PORT_G_BASE (PERIPH_BASE_AHB2 + 0x1800)BIT13 (1<<13)RCC_CCIPR_USART1SEL_APB 0RCC_APB1RSTR1_I2C3RST (1 << 23)__SHRT_MAX__ 0x7fffRCC_CFGR_PPRE2_NODIV 0x0i2c_disable_stretchingPTRDIFF_MAX __PTRDIFF_MAX__BIT4 (1<<4)__INT_LEAST16_MAX__ 0x7fffRCC_CSR_RMVF (1 << 23)__FLT32_HAS_INFINITY__ 1I2C2_PECR I2C_PECR(I2C2)RCC_CCIPR_SAIxSEL_MASK 0x3RCC_CSR_MSIRANGE_SHIFT 8RCC_BDCR_LSECSSON (1 << 5)RCC_CFGR_MCO_PLL 0x5__INT_FAST64_MAX__ 0x7fffffffffffffffLL__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GCC_ATOMIC_CHAR_LOCK_FREE 2__UINT_FAST16_TYPE__ unsigned intRCC_APB1SMENR2 MMIO32(RCC_BASE + RCC_APB1SMENR2_OFFSET)RCC_CCIPR_USARTxSEL_HSI16 2GNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsRCC_BDCR MMIO32(RCC_BASE + 0x90)RCC_APB2SMENR_TIM8SMEN (1 << 13)__UINT64_MAX__ 0xffffffffffffffffULLRCC_CCIPR_UART5SEL_SHIFT 8__SIZEOF_INT__ 4__ARMEL__ 1__FLT32X_MAX_10_EXP__ 308BIT14 (1<<14)ITM_BASE (PPBI_BASE + 0x0000)__WCHAR_WIDTH__ 32data__SIG_ATOMIC_TYPE__ int__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1RCC_APB1RSTR1_TIM6RST (1 << 4)I2C1_CR1 I2C_CR1(I2C1)RCC_CCIPR_I2CxSEL_APB 0__UINT16_C(c) cRCC_CR_PLLON (1 << 24)__PRAGMA_REDEFINE_EXTNAME 1__INT_LEAST64_TYPE__ long long intRCC_CCIPR_UARTxSEL_APB RCC_CCIPR_USARTxSEL_APBLPUART1_BASE (PERIPH_BASE_APB1 + 0x8000)RCC_PLLCFGR_PLLSRC_MASK 0x3UINTMAX_MAXRCC_AHB2SMENR_GPIODSMEN (1 << 3)___int_wchar_t_h __HAVE_SPECULATION_SAFE_VALUE 1I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)UINTMAX_C(c) __UINTMAX_C(c)__QQ_FBIT__ 7BIT15 (1<<15)RCC_CFGR_PPRE1_DIV4 0x5__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xINT8_CRCC_CR_MSIRANGE_1MHZ 4i2c_received_dataRCC_APB2RSTR_USART1RST (1 << 14)BIT22 (1<<22)BIT5 (1<<5)USB_OTG_FS_BASE (0x50000000U + 0x00000)I2C_ISR_PECERR (1 << 11)__ARM_ARCH__UINT8_TYPE__ unsigned charINT_FAST64_MIN (-INT_FAST64_MAX - 1)RCC_AHB2RSTR_GPIOARST (1 << 0)RCC_CFGR_STOPWUCK_HSI16 (1 << 15)__FLT32_MIN_10_EXP__ (-37)RCC_CSR_MSIRANGE_8MHZ 7RCC_APB1ENR1_UART4EN (1 << 19)I2C_CR1_NACKIE (1 << 4)__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLK__FLT32_NORM_MAX__ 3.4028234663852886e+38F32I2C_TIEMOUTR_TEXTEN (1 << 31)RCC_CIER_PLLRDYIE (1 << 5)RCC_CICR_PLLSAI2RDYC (1 << 7)__TA_IBIT__ 64interruptI2C_CR2_STOP (1 << 14)BIT16 (1<<16)__SACCUM_IBIT__ 8RCC_BDCR_BDRST (1 << 16)RCC_APB2RSTR_SYSCFGRST (1 << 0)I2C_ISR_DIR_READ (0x1 << 16)RCC_CFGR_MCOPRE_DIV8 3RST_DMA1RST_DMA2MMIO8(addr) (*(volatile uint8_t *)(addr))i2c_enable_analog_filter__FLT32X_HAS_INFINITY__ 1FMC_BASE (0xa0000000U)RCC_APB1SMENR1_USART3SMEN (1 << 18)I2C_CR2_NBYTES_SHIFT 16__INT8_C(c) cINFO_BASE (0x1fff0000U)__ARM_EABI__ 1RCC_PLLCFGR_PLLR_DIV4 1RCC_AHB2SMENR_GPIOASMEN (1 << 0)__CHAR_BIT__ 8UINT64_C(c) __UINT64_C(c)RST_TIM15RST_TIM16__FLT32_EPSILON__ 1.1920928955078125e-7F32INT_LEAST8_MAX __INT_LEAST8_MAX__false 0__FLT_MAX_EXP__ 128RCC_AHB2ENR_GPIOBEN (1 << 1)__INT64_MAX__ 0x7fffffffffffffffLLRCC_BDCR_LSEBYP (1 << 2)BIT17 (1<<17)__ATOMIC_SEQ_CST 5_GCC_SIZE_T DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7590)RCC_APB2RSTR_TIM15RST (1 << 16)RCC_CR MMIO32(RCC_BASE + 0x00)__USA_FBIT__ 16__FLT32X_MAX_EXP__ 1024SDMMC1_BASE (PERIPH_BASE_APB2 + 0x2800)__FLT32_MANT_DIG__ 24RCC_ICSCR_MSICAL_MASK 0xff__UINT_FAST8_TYPE__ unsigned intRCC_BDCR_RTCSEL_SHIFT 8__UTA_FBIT__ 64DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)I2C2_OAR2 I2C_OAR2(I2C2)__DBL_DIG__ 15INTPTR_MAX __INTPTR_MAX__RCC_AHB1SMENR_DMA2SMEN (1 << 1)__DECIMAL_DIG__ 17INT_FAST16_MININT_FAST8_MAX __INT_FAST8_MAX___STDDEF_H __ARM_PCS_VFP 1DESIG_PACKAGE MMIO16((INFO_BASE + 0x7500))i2c_enable_autoendPERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)__GCC_IEC_559_COMPLEX 0UINT64_CI2C_OAR2_OA2MSK_NO_MASK (0x0 << 8)__INT_FAST64_WIDTH__ 64__UINT64_TYPE__ long long unsigned intRCC_APB1ENR1_LPTIM1EN (1 << 31)RCC_PLLCFGR_PLLP_DIV17 RCC_PLLCFGR_PLLPBIT18 (1<<18)__LFRACT_IBIT__ 0I2C_ICR(i2c_base) MMIO32((i2c_base) + 0x1C)__USER_LABEL_PREFIX__ RCC_PLLCFGR_PLLM_SHIFT 0x4I2C2_CR1 I2C_CR1(I2C2)_SIZE_T_DECLARED RCC_APB1RSTR1_SPI3RST (1 << 15)I2C_CR2_HEAD10R (1 << 12)INT64_MAX __INT64_MAX____QQ_IBIT__ 0RCC_AHB3ENR_FMCEN (1 << 0)TIM17_BASE (PERIPH_BASE_APB2 + 0x4800)UINT_LEAST64_MAX__DBL_EPSILON__ ((double)2.2204460492503131e-16L)RST_PWRSPI2_BASE (PERIPH_BASE_APB1 + 0x3800)__DBL_MIN__ ((double)2.2250738585072014e-308L)RCC_CFGR_STOPWUCK_MSI (0 << 15)__INT_FAST8_MAX__ 0x7fffffffi2c_speed_sm_100kRCC_APB2SMENR_SYSCFGSMEN (1 << 0)RCC_APB1SMENR1_TIM3SMEN (1 << 1)RCC_CR_PLLSAI2ON (1 << 28)__INT_FAST8_WIDTH__ 32RCC_CCIPR_I2CxSEL_HSI16 2RCC_AHB3SMENR_OFFSET 0x70__LDBL_MAX__ 1.7976931348623157e+308LINT_FAST32_MAXRCC_AHB3RSTR_OFFSET 0x30RCC_AHB2RSTR_ADCRST (1 << 13)__FLT32_MIN_EXP__ (-125)ST_VREFINT_CAL MMIO16((INFO_BASE + 0x75aa))CORESIGHT_LSR_SLK (1<<1)RCC_BDCR_LSEDRV_MASK 0x3__UINT32_C(c) c ## UL__LDBL_MIN_EXP__ (-1021)I2C2_OAR1 I2C_OAR1(I2C2)IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)BIT7 (1<<7)GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000)_GCC_PTRDIFF_T RCC_PLLCFGR_PLLSRC_NONE 0_T_SIZE_ __FLT_MIN_10_EXP__ (-37)RCC_CCIPR_USART2SEL_SHIFT 2RCC_APB1ENR1_TIM7EN (1 << 5)RCC_CCIPR_USARTxSEL_MASK 0x3RCC_APB1SMENR1_OFFSET 0x78INT_LEAST64_MAX __INT_LEAST64_MAX____UDQ_IBIT__ 0AES_BASE (0x50000000U + 0x60000)RCC_CCIPR_USART1SEL_HSI16 2RCC_AHB3RSTR_QSPIRST (1 << 8)__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)__PTRDIFF_WIDTH__ 32RCC_AHB1SMENR_OFFSET 0x68waitprescalerI2C1_ISR I2C_ISR(I2C1)__ULLACCUM_MIN__ 0.0ULLK__INT_WCHAR_T_H RCC_APB1SMENR1_TIM2SMEN (1 << 0)I2C_ISR_TXIS (1 << 1)INT_FAST64_MAXWWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)RCC_CICR_LSIRDYC (1 << 0)RCC_APB1SMENR1_TIM4SMEN (1 << 2)DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)RCC_AHB2RSTR_GPIOCRST (1 << 2)RCC_APB2ENR_SAI1EN (1 << 21)__size_t __WINT_MAX__ 0xffffffffURCC_CCIPR_LPUART1SEL_MASK 0x3__ARM_FP16_FORMAT_ALTERNATIVERCC_CCIPR_I2C2SEL_SHIFT 14i2c_enable_interruptINT32_C(c) __INT32_C(c)__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1__UINT32_TYPE__ long unsigned int__FLT_EPSILON__ 1.1920928955078125e-7F__USA_IBIT__ 16RCC_PLLCFGR_PLLR_MASK 0x3__UINT8_C(c) cLIBOPENCM3_RCC_COMMON_ALL_H RCC_CFGR_SWS_HSE 0x2__ARM_FEATURE_NUMERIC_MAXMINRCC_CFGR_MCOPRE_MASK 0x7RCC_AHB3SMENR MMIO32(RCC_BASE + RCC_AHB3SMENR_OFFSET)RST_RNGI2C_OAR1_OA1 (1 << 10)UINT16_MAX __UINT16_MAX__RCC_CCIPR_CLK48SEL_SHIFT 26__ULLFRACT_MIN__ 0.0ULLRRCC_CCIPR_ADCSEL_NONE 0unsigned char__ARM_FEATURE_QRDMXRCC_CCIPR_LPTIMxSEL_LSE 3BIT8 (1<<8)__SFRACT_IBIT__ 0I2C_OAR2_OA2MSK_OA2_7 (0x6 << 8)__ORDER_LITTLE_ENDIAN__ 1234_PTRDIFF_T_DECLARED RCC_CIFR_HSIRDYF (1 << 3)FMC3_BANK_BASE (0x80000000U)I2C_TIEMOUTR_TIMOUTEN (1 << 15)RCC_CCIPR_USARTxSEL_APB 0RCC_APB1ENR1_CAN1EN (1 << 25)RCC_PLLCFGR_PLLQ_DIV4 1__FLT_DIG__ 6RCC_AHB1SMENR_SRAM1SMEN (1 << 9)I2C_TIEMOUTR_TIDLE_SCL_LOW (0x0 << 12)n_bytesI2C_OAR1_OA1EN_ENABLE (0x1 << 15)__DBL_MAX_EXP__ 1024__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULK__LLFRACT_IBIT__ 0__UINT_LEAST16_MAX__ 0xffff__SIZE_WIDTH__ 32__ARM_FEATURE_FP16_FML__ULFRACT_FBIT__ 32RCC_APB1RSTR1_TIM3RST (1 << 1)BIT2 (1<<2)__SIZEOF_SIZE_T__ 4I2C3_CR1 I2C_CR1(I2C3)RCC_CCIPR_CLK48SEL_PLL 2i2c_set_scl_high_period_PTRDIFF_T RCC_AHB2ENR_ADCEN (1 << 13)INT_LEAST16_MAX __INT_LEAST16_MAX____UINT_LEAST64_MAX__ 0xffffffffffffffffULLI2C_ISR_NACKF (1 << 4)RCC_APB1SMENR1_WWDGSMEN (1 << 11)RCC_CCIPR_USART1SEL_LSE 3RCC_CCIPR_LPUART1SEL_SYS 1NVIC_BASE (SCS_BASE + 0x0100)__SFRACT_FBIT__ 7DMA2_BASE (PERIPH_BASE_AHB1 + 0x0400)__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32i2c_set_write_transfer_dirRCC_CSR_OBLRSTF (1 << 25)PTRDIFF_MIN (-PTRDIFF_MAX - 1)I2C1_OAR1 I2C_OAR1(I2C1)__DBL_DECIMAL_DIG__ 17__SIZEOF_LONG_LONG__ 8FIREWALL_BASE (PERIPH_BASE_APB2 + 0x1C00)SIZE_MAXRCC_CR_MSIRANGE_200KHZ 1WCHAR_MAX __WCHAR_MAX__RCC_AHB1RSTR_FLASHRST (1 << 8)__FLT32_DECIMAL_DIG__ 9QUADSPI_BANK_BASE (0x90000000U)GPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000)rcc_periph_rstBIT9 (1<<9)RCC_AHB1RSTR_CRCRST (1 << 12)RCC_CR_MSIRANGE_SHIFT 4I2C_TIMINGR_SCLDEL_MASK (0xF << I2C_TIMINGR_SCLDEL_SHIFT)_WCHAR_T_DEFINED_ RCC_CR_HSIKERON (1 << 9)UINTMAX_C__WINT_TYPE__ unsigned intUINT_LEAST32_MAX __UINT_LEAST32_MAX__RCC_CFGR_MCO_MSI 0x2SCB_BASE (SCS_BASE + 0x0D00)RCC_APB1ENR1_I2C3EN (1 << 23)I2C3_CCR I2C_CCR(I2C3)RCC_APB2ENR_SPI1EN (1 << 12)RCC_PLLCFGR_PLLSRC_HSI16 2I2C2_ISR I2C_ISR(I2C2)RCC_AHB3SMENR_FMCSMEN (1 << 0)I2C1_RXDR I2C_RXDR(I2C1)__INT16_MAX__ 0x7fff__ULACCUM_EPSILON__ 0x1P-32ULK__FLT_MANT_DIG__ 24RCC_AHB2ENR_RNGEN (1 << 18)__ULACCUM_FBIT__ 32TIM1_BASE (PERIPH_BASE_APB2 + 0x2C00)__FLT64_HAS_QUIET_NAN__ 1I2C_CR1_RXDMAEN (1 << 15)I2C_ICR_OVRCF (1 << 10)RCC_BDCR_RTCSEL_NONE 0__ARM_ARCH_PROFILE 77__ULACCUM_IBIT__ 32RCC_CFGR_PPRE2_DIV4 0x5__ARM_FEATURE_COPROC 15BIT20 (1<<20)I2C3_DR I2C_DR(I2C3)I2C_CR1_ADDRIE (1 << 3)STM32L4 1_WCHAR_T_H __INT_LEAST8_MAX__ 0x7f__UQQ_FBIT__ 8I2C3_CR2 I2C_CR2(I2C3)RCC_ICSCR_HSITRIM_SHIFT 24__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__RCC_CFGR_PPRE2_SHIFT 11__UINT64_C(c) c ## ULL__FRACT_IBIT__ 0__FLT_RADIX__ 2RCC_APB1SMENR1_SPI2SMEN (1 << 14)__LDBL_IS_IEC_60559__ 2__FLT32X_DIG__ 15UINT_FAST8_MAX __UINT_FAST8_MAX____LDBL_EPSILON__ 2.2204460492503131e-16Li2c_disable_interrupt__ARM_BF16_FORMAT_ALTERNATIVE__FLT_EVAL_METHOD_TS_18661_3__ 0__SQ_FBIT__ 31__UINTMAX_MAX__ 0xffffffffffffffffULLRCC_APB1ENR1_OPAMPEN (1 << 30)I2C3_TRISE I2C_TRISE(I2C3)RCC_PLLSAI2_CFGR MMIO32(RCC_BASE + 0x14)RCC_CCIPR_USART1SEL_MASK 0x3__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LKRCC_CFGR_HPRE_DIV16 0xbRCC_CR_MSIRANGE_400KHZ 2RCC_PLLCFGR_PLLQEN (1 << 20)RCC_CCIPR_UART4SEL_SHIFT 6INT_FAST32_MIN__FRACT_EPSILON__ 0x1P-15R__FLT32X_MANT_DIG__ 53RCC_PLLCFGR_PLLQ_DIV6 2__GCC_ATOMIC_INT_LOCK_FREE 2RST_SDMMC1BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)RCC_PLLCFGR_PLLSRC_HSE 3__LDBL_DECIMAL_DIG__ 17__INT_WIDTH__ 32I2C3_BASE (PERIPH_BASE_APB1 + 0x5c00)RCC_CFGR_SW_SHIFT 0PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)I2C_CR2_ADD10 (1 << 11)RCC_BDCR_LSERDY (1 << 1)RCC_CFGR_MCO_HSI16 0x3RCC_AHB2ENR_GPIOAEN (1 << 0)CORESIGHT_LAR_KEY 0xC5ACCE55__FLT32_IS_IEC_60559__ 2__UDQ_FBIT__ 64I2C_OAR2_OA2EN (1 << 15)__ARM_NEONRCC_CFGR_MCO_SHIFT 24RCC_AHB2SMENR_AESSMEN (1 << 16)__ARM_ARCH_7EM__ 1__INT16_C(c) cINT_FAST8_MAXRCC_CFGR_PPRE1_NODIV 0x0RCC_CIFR_PLLRDYF (1 << 5)RCC_APB1RSTR1_OFFSET 0x38__FLT32X_DECIMAL_DIG__ 17RCC_CSR_MSIRANGE_2MHZ 5__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2__INT16_TYPE__ short intRCC_APB2RSTR_DFSDMRST (1 << 24)RCC_CICR_CSSC (1 << 8)__bool_true_false_are_defined 1RCC_CCIPR_ADCSEL_PLLSAI1R 1__FRACT_MIN__ (-0.5R-0.5R)SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)___int_size_t_h SWPMI1_BASE (PERIPH_BASE_APB1 + 0x8800)RCC_CCIPR_LPUART1SEL_SHIFT 10RCC_CIER_PLLSAI2RDYIE (1 << 7)_SIZE_T_DEFINED_ RCC_BDCR_LSCOSEL (1 << 25)RCC_PLLCFGR_PLLR_DIV6 2size_t__GCC_ATOMIC_LONG_LOCK_FREE 2_GCC_STDINT_H RST_SAI1RST_SAI2RCC_CFGR_SW_MSI 0x0RCC_CIER_MSIRDYIE (1 << 2)__UHQ_FBIT__ 16uint8_tRCC_APB1SMENR1_USART2SMEN (1 << 17)RCC_CFGR MMIO32(RCC_BASE + 0x08)INTMAX_MIN (-INTMAX_MAX - 1)__BIGGEST_ALIGNMENT__ 8RCC_CFGR_MCO_HSI48 0x8__ACCUM_EPSILON__ 0x1P-15KRCC_CFGR_SWS_PLL 0x3I2C_OAR2_OA2MSK_NO_CMP (0x7 << 8)RCC_CSR_MSIRANGE_1MHZ 4NULLRCC_CFGR_MCOPRE_DIV16 4RCC_BDCR_LSEDRV_LOW 0TIM16_BASE (PERIPH_BASE_APB2 + 0x4400)BIT23 (1<<23)I2C_TIEMOUTR_TIDLE_SCL_SDA_HIGH (0x1 << 12)__FP_FAST_FMAF 1RCC_AHB1ENR_FLASHEN (1 << 8)__WCHAR_MIN__ 0URCC_APB2SMENR_TIM16SMEN (1 << 17)RCC_CIFR MMIO32(RCC_BASE + 0x1c)RCC_AHB1SMENR_TSCSMEN (1 << 16)_GCC_WCHAR_T RCC_APB2ENR_FWEN (1 << 7)i2c_set_read_transfer_diri2c_peripheral_enableRCC_APB2ENR_OFFSET 0x60RST_QSPIRCC_CFGR_HPRE_NODIV 0x0__LLFRACT_EPSILON__ 0x1P-63LLRI2C_CR1_DNF_MASK 0xF__FRACT_FBIT__ 15addrRCC_CFGR_PPRE1_DIV8 0x6RCC_PLLCFGR_PLLSRC_MSI 1__INT32_MAX__ 0x7fffffffL__CHAR_UNSIGNED__ 1RST_I2C2BIT24 (1<<24)_BSD_WCHAR_T___SCHAR_MAX__ 0x7f__GCC_HAVE_DWARF2_CFI_ASM 1INT16_MAX __INT16_MAX___SIZE_T_ TPIU_BASE (PPBI_BASE + 0x40000)__SACCUM_EPSILON__ 0x1P-7HKRCC_CCIPR_ADCSEL_SHIFT 28DAC_BASE (PERIPH_BASE_APB1 + 0x7400)__need_size_t__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRI2C3_OAR2 I2C_OAR2(I2C3)RCC_CR_MSIRANGE_48MHZ 11__need_ptrdiff_tRCC_CICR_HSI48RDYC (1 << 10)i2c_speed_fmp_1m__HA_FBIT__ 7I2C_ICR_ARLOCF (1 << 9)__UACCUM_MIN__ 0.0UKRCC_ICSCR_MSICAL_SHIFT 0INT_LEAST32_MAX __INT_LEAST32_MAX__RCC_APB1RSTR2 MMIO32(RCC_BASE + RCC_APB1RSTR2_OFFSET)LIBOPENCM3_I2C_COMMON_V2_H __UFRACT_EPSILON__ 0x1P-16UR__FLT_HAS_QUIET_NAN__ 1UINT_FAST64_MAX __UINT_FAST64_MAX__I2C_ISR_OVR (1 << 10)BIT25 (1<<25)I2C2_TIMINGR I2C_TIMINGR(I2C2)__FLT32X_NORM_MAX__ 1.7976931348623157e+308F32xRCC_PLLCFGR_PLLP_DIV7 0SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__USART1_BASE (PERIPH_BASE_APB2 + 0x3800)RCC_AHB2RSTR_GPIOBRST (1 << 1)i2c_transfer_completeRCC_AHB2SMENR_SRAM2SMEN (1 << 9)RCC_AHB2ENR_AESEN (1 << 16)RCC_CR_MSIRANGE_24MHZ 9__SCHAR_WIDTH__ 8I2C_CR1_TXIE (1 << 1)__ORDER_PDP_ENDIAN__ 3412__ATOMIC_ACQUIRE 2RST_USART1RST_USART2I2C_CR2_RELOAD (1 << 24)__INT_FAST32_WIDTH__ 32I2C_CR1_RXIE (1 << 2)__INT_FAST64_TYPE__ long long intI2C_TIMINGR_SDADEL_SHIFT 16__ACCUM_FBIT__ 15__INT_LEAST64_MAX__ 0x7fffffffffffffffLLRCC_AHB2RSTR_RNGRST (1 << 18)CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)I2C_CR2_SADD_7BIT_SHIFT 1UINT32_C(c) __UINT32_C(c)__ARM_FEATURE_UNALIGNED 1RCC_CR_MSION (1 << 0)__SACCUM_MAX__ 0X7FFFP-7HKBIT26 (1<<26)INTMAX_MAXRCC_AHB2RSTR_GPIOFRST (1 << 5)RCC_CR_HSIRDY (1 << 10)I2C_TIMINGR_PRESC_SHIFT 28__ACCUM_IBIT__ 16UINT64_MAX __UINT64_MAX__I2C3_OAR1 I2C_OAR1(I2C3)__INTMAX_WIDTH__ 64RST_ADC__ARM_FEATURE_LDREX 7DBGMCU_BASE (PPBI_BASE + 0x00042000)__INT_LEAST64_WIDTH__ 64RCC_CIFR_HSI48RDYF (1 << 10)RCC_ICSCR_HSICAL_SHIFT 16I2C_TIMINGR_PRESC_MASK (0xF << 28)INT8_C(c) __INT8_C(c)RCC_CCIPR_USARTxSEL_LSE 3I2C_CR1_PECEN (1 << 23)__ARM_32BIT_STATE 1__ATOMIC_RELAXED 0RCC_AHB2SMENR_GPIOESMEN (1 << 4)__LFRACT_MAX__ 0X7FFFFFFFP-31LR__LDBL_MIN__ 2.2250738585072014e-308LRCC_CCIPR_USART1SEL_SHIFT 0RCC_APB1RSTR2_LPTIM2RST (1 << 5)i2c_speed_fm_400ki2c_set_digital_filter__THUMB_INTERWORK__ 1RCC_AHB2ENR_GPIOHEN (1 << 7)PPBI_BASE (0xE0000000U)I2C_ISR_STOPF (1 << 5)BIT27 (1<<27)I2C_ISR_RXNE (1 << 2)__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)__FRACT_MAX__ 0X7FFFP-15RRCC_CFGR_HPRE_DIV64 0xcI2C_ICR_BERRCF (1 << 8)__USQ_FBIT__ 32__GCC_IEC_559 0__FLT_IS_IEC_60559__ 2__FLT32X_EPSILON__ 2.2204460492503131e-16F32xGPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800)RCC_CCIPR_SAI2SEL_SHIFT 24RST_AESI2C_ISR_TC (1 << 6)i2c_get_dataMMIO32(addr) (*(volatile uint32_t *)(addr))RCC_CCIPR_I2C3SEL_SHIFT 16RCC_APB1RSTR2_OFFSET 0x3cRCC_AHB1ENR_CRCEN (1 << 12)__wchar_t__ I2C_ICR_STOPCF (1 << 5)i2c_disable_txdma_WCHAR_T_DECLARED __ATOMIC_RELEASE 3BIT28 (1<<28)RCC_APB1RSTR1_I2C1RST (1 << 21)__INT_LEAST8_WIDTH__ 8I2C_CR1_WUPEN (1 << 18)__GNUC__ 12RCC_CCIPR_SAIxSEL_PLLSAI1P 0__ARM_FEATURE_COPROCUINTMAX_MAX __UINTMAX_MAX__RCC_ICSCR MMIO32(RCC_BASE + 0x04)__INT_FAST16_TYPE__ int__INT_LEAST32_WIDTH__ 32RCC_AHB1RSTR_TSCRST (1 << 16)__UTQ_IBIT__ 0__DBL_IS_IEC_60559__ 2RST_LPTIM1RST_LPTIM2__UTA_IBIT__ 64__SIZEOF_WINT_T__ 4RCC_AHB1RSTR_DMA2RST (1 << 1)RCC_CFGR_MCOPRE_DIV1 0RCC_CCIPR_CLK48SEL_MSI 3i2c_set_7bit_addressRCC_CCIPR_LPUART1SEL_HSI16 2RCC_APB1ENR1_DAC1EN (1 << 29)RCC_APB1RSTR1_USART2RST (1 << 17)I2C_CR2(i2c_base) MMIO32((i2c_base) + 0x04)RCC_CR_PLLSAI1RDY (1 << 27)RCC_APB1ENR1_PWREN (1 << 28)i2c_transfer7__INT_MAX__ 0x7fffffffRST_LCD__FLT_MAX__ 3.4028234663852886e+38F__INT_LEAST8_TYPE__ signed char__GXX_ABI_VERSION 1017BIT29 (1<<29)INT32_C_WCHAR_T __LFRACT_FBIT__ 31__ARM_ARCH_ISA_THUMB__FLT64_IS_IEC_60559__ 2__SIZEOF_WCHAR_T__ 4INTMAX_C__USACCUM_MAX__ 0XFFFFP-8UHKRCC_AHB2ENR_GPIOEEN (1 << 4)__WINT_MIN__ 0U__INT8_MAX__ 0x7fRCC_AHB2ENR_OFFSET 0x4cRCC_APB2ENR_TIM8EN (1 << 13)I2C_ISR_ALERT (1 << 13)__INT_LEAST32_MAX__ 0x7fffffffLclock_megahzI2C_CR1_NOSTRETCH (1 << 17)RCC_APB2ENR MMIO32(RCC_BASE + RCC_APB2ENR_OFFSET)__USACCUM_EPSILON__ 0x1P-8UHKRCC_AHB2SMENR_GPIOBSMEN (1 << 1)period__LLACCUM_EPSILON__ 0x1P-31LLK_SYS_SIZE_T_H RCC_CFGR_MCOPRE_SHIFT 28__INTMAX_C(c) c ## LL__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)SAI1_BASE (PERIPH_BASE_APB2 + 0x5400)__UINT_FAST16_MAX__ 0xffffffffU__ARM_ARCH_EXT_IDIV__ 1__UINT_FAST64_TYPE__ long long unsigned intCOMP_BASE (PERIPH_BASE_APB2 + 0x0200)__ULFRACT_IBIT__ 0BIT0 (1<<0)RCC_CR_HSION (1 << 8)RCC_BDCR_RTCEN (1 << 15)RCC_CFGR_PPRE1_DIV2 0x4RST_TIM17STIR_BASE (SCS_BASE + 0x0F00)RTC_BASE (PERIPH_BASE_APB1 + 0x2800)RCC_CIER_PLLSAI1RDYIE (1 << 6)I2C1_TIMEOUTR I2C_TIMEOUTR(I2C1)RCC_APB1RSTR1_CAN1RST (1 << 25)__SIZE_MAX__ 0xffffffffU__ARM_FEATURE_QBIT 1RCC_APB2RSTR_SAI1RST (1 << 21)LIBOPENCM3_MEMORYMAP_COMMON_H __UINT_FAST8_MAX__ 0xffffffffURCC_CIFR_PLLSAI2RDYF (1 << 7)RCC_CIFR_HSERDYF (1 << 4)__SQ_IBIT__ 0LCD_BASE (PERIPH_BASE_APB1 + 0x2400)RCC_CCIPR_UARTxSEL_SYS RCC_CCIPR_USARTxSEL_SYSINT_FAST16_MIN (-INT_FAST16_MAX - 1)RST_TSC__ARM_FEATURE_SIMD32 1__need_NULLoffsetof(TYPE,MEMBER) __builtin_offsetof (TYPE, MEMBER)RCC_PLLCFGR_PLLSRC_SHIFT 0I2C2_RXDR I2C_RXDR(I2C2)__UHQ_IBIT__ 0ST_TSENSE_CAL2_110C MMIO16((INFO_BASE + 0x75ca))RCC_APB2SMENR_TIM15SMEN (1 << 16)RCC_AHB3SMENR_QSPISMEN (1 << 8)i2c_set_own_7bit_slave_addressRCC_APB1ENR1_TIM6EN (1 << 4)__thumb2__ 1__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1RCC_AHB2ENR MMIO32(RCC_BASE + RCC_AHB2ENR_OFFSET)__LACCUM_FBIT__ 31__ULACCUM_MIN__ 0.0ULKRCC_CFGR_HPRE_SHIFT 4RCC_CR_MSIRANGE_4MHZ 6RCC_CFGR_SW_HSE 0x2RCC_PLLCFGR_PLLQ_DIV8 3RCC_CCIPR_CLK48SEL_MASK 0x3RCC_CCIPR_ADCSEL_PLLSAI2R 2RCC_PLLCFGR_PLLN_SHIFT 0x8__LONG_MAX__ 0x7fffffffL__INT32_C(c) c ## LVREFBUF_BASE (PERIPH_BASE_APB2 + 0x0030)__FLT64_NORM_MAX__ 1.7976931348623157e+308F64INTPTR_MAXRCC_CICR_HSIRDYC (1 << 3)INT_FAST16_MAX __INT_FAST16_MAX__RCC_APB1SMENR1_I2C3SMEN (1 << 23)RCC_ICSCR_HSICAL_MASK 0xffRCC_CICR_LSECSSC (1 << 9)I2C2 I2C2_BASERCC_PLLPEN (1 << 16)__FLT32X_IS_IEC_60559__ 2RCC_APB1RSTR1_LPTIM1RST (1 << 31)RCC_APB1SMENR1_TIM5SMEN (1 << 3)RCC_CFGR_MCO_HSE 0x4UINT_FAST32_MAX __UINT_FAST32_MAX__RCC_CIER_LSE_CSSIE (1 << 9)UINT32_CTIM2_BASE (PERIPH_BASE_APB1 + 0x0000)short unsigned intRCC_AHB2RSTR_AESRST (1 << 16)signed charRCC_CCIPR_LPTIMxSEL_MASK 0x3__size_t__ LIBOPENCM3_RCC_H RCC_PLLCFGR_PLLR_DIV8 3RCC_APB1ENR1_TIM2EN (1 << 0)i2c_peripheral_disableRCC_APB2SMENR_SAI2SMEN (1 << 22)BIT6 (1<<6)INTMAX_C(c) __INTMAX_C(c)WINT_MAX __WINT_MAX__i2c_clear_stop__ULLACCUM_EPSILON__ 0x1P-32ULLKDESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 0x14)I2C_TIMINGR_SCLDEL_SHIFT 20INTMAX_MINRCC_APB1RSTR1_UART4RST (1 << 19)RCC_CR_MSIRANGE_2MHZ 5RCC_CFGR_SWS_MSI 0x0RCC_CFGR_PPRE1_SHIFT 8RCC_APB2RSTR_TIM16RST (1 << 17)__ARM_FEATURE_DOTPRODUINT_LEAST16_MAXI2C_OAR1(i2c_base) MMIO32((i2c_base) + 0x08)BEGIN_DECLS _BSD_SIZE_T_ I2C_OAR1_OA1_10BIT 1RCC_BDCR_LSESYSDIS (1 << 7)RCC_CFGR_PPRE2_DIV8 0x6UINT16_C(c) __UINT16_C(c)i2c_disable_autoend__FLT64_MIN__ 2.2250738585072014e-308F64__INTPTR_MAX__ 0x7fffffff__ARM_FP16_ARGS__UINT16_TYPE__ short unsigned intRCC_APB2RSTR_TIM8RST (1 << 13)FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000)_BSD_SIZE_T_DEFINED_ __GCC_ATOMIC_POINTER_LOCK_FREE 2RCC_CSR_FWRSTF (1 << 24)__SIG_ATOMIC_MAX__ 0x7fffffff__DBL_MAX__ ((double)1.7976931348623157e+308L)RCC_CFGR_MCOPRE_DIV2 1I2C_CR1_ERRIE (1 << 7)__FLT32_MAX_10_EXP__ 38RST_GPIOARST_GPIOBRST_GPIOCRST_GPIODINT_LEAST32_MIN (-INT_LEAST32_MAX - 1)RST_GPIOFRST_GPIOGRST_GPIOHITR_BASE (SCS_BASE + 0x0000)INT_LEAST8_MAX__WINT_WIDTH__ 32RCC_APB1RSTR2_SWPMI1RST (1 << 2)PERIPH_BASE (0x40000000U)__LDBL_HAS_DENORM__ 1_ANSI_STDDEF_H UINT_FAST8_MAXRST_TIM5__ARM_FP16_FORMAT_IEEEi2c_enable_rxdmaRST_TIM8RCC_CIFR_CSSF (1 << 8)RCC_APB1ENR1_TIM3EN (1 << 1)__USES_INITFINI__ 1BIT30 (1<<30)I2C_ISR_ARLO (1 << 9)RCC_APB1ENR1_LCDEN (1 << 9)RCC_CR_PLLSAI2RDY (1 << 29)RCC_CFGR_PPRE1_DIV16 0x7RCC_CICR_MSIRDYC (1 << 2)__REGISTER_PREFIX__ RCC_CFGR_PPRE2_MASK 0x7RCC_BDCR_RTCSEL_LSE 1__USFRACT_MAX__ 0XFFP-8UHRPERIPH_BASE_AHB2 (0x48000000U)CRS_BASE (PERIPH_BASE_APB1 + 0x6000)RCC_CRRCR MMIO32(RCC_BASE + 0x98)WCHAR_MIN __WCHAR_MIN____FLT32_MAX__ 3.4028234663852886e+38F32BIT1 (1<<1)RCC_AHB2SMENR_OTGFSSMEN (1 << 12)RCC_AHB2SMENR_RNGSMEN (1 << 18)__DBL_MIN_10_EXP__ (-307)I2C1_CR2 I2C_CR2(I2C1)RCC_APB1SMENR1_I2C2SMEN (1 << 22)RST_DFSDM__INT_FAST8_TYPE__ intUINT8_C(c) __UINT8_C(c)UINT32_MAXRCC_APB1SMENR1_SPI3SMEN (1 << 15)__ARM_FEATURE_BF16_SCALAR_ARITHMETICI2C_ISR_BUSY (1 << 15)RCC_CR_MSIRANGE_16MHZ 8RCC_CSR MMIO32(RCC_BASE + 0x94)__STDC_HOSTED__ 1__UINTMAX_C(c) c ## ULLRCC_APB1ENR1_OFFSET 0x58RST_USBGPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400)__UACCUM_MAX__ 0XFFFFFFFFP-16UKRCC_CSR_LPWRRSTF (1 << 31)FMC1_BANK_BASE (0x60000000U)RCC_CFGR_HPRE_DIV4 0x9RCC_APB1SMENR1_TIM7SMEN (1 << 5)long intRCC_CFGR_MCO_SYSCLK 0x1i2c_set_bytes_to_transfer__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)RCC_CR_MSIPLLEN (1 << 2)INT16_MAX__DBL_HAS_DENORM__ 1TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1__FLT64_MAX_10_EXP__ 308_WCHAR_T_DEFINED __PTRDIFF_TYPE__ int__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2__USACCUM_FBIT__ 8__GNUC_STDC_INLINE__ 1RST_FLASHUINT64_MAX__WCHAR_T__ __ARM_FPRCC_APB2ENR_TIM1EN (1 << 11)RCC_AHB2SMENR_GPIOGSMEN (1 << 6)RCC_CICR_LSERDYC (1 << 1)RCC_CSR_BORRSTF (1 << 27)_PTRDIFF_T_ RCC_CIER_LSERDYIE (1 << 1)RCC_CCIPR_I2CxSEL_MASK 0x3RCC_APB2SMENR MMIO32(RCC_BASE + RCC_APB2SMENR_OFFSET)__UTQ_FBIT__ 128LIBOPENCM3_CM3_COMMON_H RCC_AHB2SMENR MMIO32(RCC_BASE + RCC_AHB2SMENR_OFFSET)__PTRDIFF_T RCC_APB1ENR1_I2C2EN (1 << 22)RCC_CCIPR_CLK48SEL_HSI48 0RCC_CCIPR_LPTIMxSEL_LSI 1RCC_CIFR_PLLSAI1RDYF (1 << 6)__ARM_FEATURE_DSP 1I2C_CR2_SADD_7BIT_MASK (0x7F << I2C_CR2_SADD_7BIT_SHIFT)__ARM_FEATURE_CRYPTORCC_CFGR_HPRE_DIV256 0xeI2C_CR1_PE (1 << 0)RCC_CCIPR_LPTIM2SEL_SHIFT 20__FLT32_HAS_DENORM__ 1RCC_CFGR_MCO_MASK 0xfI2C3_SR1 I2C_SR1(I2C3)RCC_AHB2RSTR_GPIOHRST (1 << 7)INT32_MIN (-INT32_MAX - 1)__ARM_FEATURE_FP16_SCALAR_ARITHMETICRCC_BDCR_LSEDRV_SHIFT 3__SACCUM_FBIT__ 7__HQ_FBIT__ 15UINT8_CRCC_CFGR_HPRE_DIV512 0xfuint32_tRCC_APB1SMENR2_LPTIM2SMEN (1 << 5)__SIZE_T RST_UART4__FLT_MIN_EXP__ (-125)__LLFRACT_FBIT__ 63__LDBL_DIG__ 15__CHAR32_TYPE__ long unsigned intRCC_APB1RSTR1_USART3RST (1 << 18)SIG_ATOMIC_MIN __SIG_ATOMIC_MIN__I2C_ISR_ADDR (1 << 3)RCC_CFGR_SW_PLL 0x3__GCC_ATOMIC_SHORT_LOCK_FREE 2RCC_AHB2ENR_GPIOGEN (1 << 6)RCC_AHB1ENR_DMA2EN (1 << 1)__ULFRACT_MAX__ 0XFFFFFFFFP-32ULRRCC_CRRCR_HSI48ON (1 << 0)__SIZEOF_POINTER__ 4RCC_CCIPR_LPUART1SEL_APB 0__GCC_ASM_FLAG_OUTPUTS__ 1RCC_APB1SMENR1_CAN1SMEN (1 << 25)RCC_CR_MSIRANGE_32MHZ 10RCC_CFGR_HPRE_DIV128 0xdUINT_LEAST64_MAX __UINT_LEAST64_MAX____UINTMAX_TYPE__ long long unsigned int_T_SIZE I2C_ISR_TXE (1 << 0)RCC_APB2SMENR_TIM17SMEN (1 << 18)__INTPTR_WIDTH__ 32INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)INT_FAST16_MAXGPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0c00)USART3_BASE (PERIPH_BASE_APB1 + 0x4800)INTPTR_MINRCC_CCIPR_SAI1SEL_SHIFT 22RCC_CR_MSIRANGE_MASK 0xfI2C_ISR_BERR (1 << 8)RCC_AHB1RSTR MMIO32(RCC_BASE + RCC_AHB1RSTR_OFFSET)__FLT64_HAS_INFINITY__ 1__GCC_DESTRUCTIVE_SIZE 64RCC_PLLCFGR_PLLREN (1<<24)RCC_BDCR_LSECSSD (1 << 6)__FINITE_MATH_ONLY__ 0__LONG_LONG_MAX__ 0x7fffffffffffffffLLI2C_CR2_SADD_10BIT_MASK 0x3FFRCC_CR_PLLRDY (1 << 25)__ATOMIC_ACQ_REL 4_T_WCHAR_ RCC_AHB1RSTR_DMA1RST (1 << 0)__GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"MMIO64(addr) (*(volatile uint64_t *)(addr))__STDC_VERSION__ 199901L__LFRACT_MIN__ (-0.5LR-0.5LR)PTRDIFF_MAXRCC_CFGR_MCO_NOCLK 0x0RST_OTGFSI2C1 I2C1_BASE__LLFRACT_MIN__ (-0.5LLR-0.5LLR)/build/libopencm3/lib/stm32/l4I2C2_CR2 I2C_CR2(I2C2)RST_UART5RCC_CCIPR_ADCSEL_MASK 0x3INT64_C(c) __INT64_C(c)__GCC_ATOMIC_LLONG_LOCK_FREE 1RCC_APB2ENR_SDMMC1EN (1 << 10)__ULFRACT_EPSILON__ 0x1P-32ULRRST_TIM1RST_TIM2RST_TIM3RST_TIM4i2c_enable_stretchingRST_TIM6RST_TIM7__LONG_LONG_WIDTH__ 64INT_LEAST64_MINRCC_AHB3ENR_OFFSET 0x50RCC_CFGR_PPRE2_DIV2 0x4__VERSION__ "12.2.1 20221205"__FLT64_EPSILON__ 2.2204460492503131e-16F64__DEFINED_wchar_t GPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400)I2C3_SR2 I2C_SR2(I2C3)__ULLACCUM_FBIT__ 32__LDBL_HAS_QUIET_NAN__ 1RCC_CR_CSSON (1 << 19)__WCHAR_MAX__ 0xffffffffUUART5_BASE (PERIPH_BASE_APB1 + 0x5000)_SIZE_T RCC_BDCR_LSEON (1 << 0)RCC_APB2ENR_DFSDMEN (1 << 24)__ULLACCUM_IBIT__ 32RCC_APB2SMENR_SAI1SMEN (1 << 21)I2C_OAR1_OA1MODE_7BIT 0__LDBL_MANT_DIG__ 53RCC_APB2ENR_USART1EN (1 << 14)__ULLFRACT_FBIT__ 64WCHAR_MAX__DQ_IBIT__ 0__FLT64_MAX__ 1.7976931348623157e+308F64_SIZE_T_DEFINED INT_LEAST8_MINRCC_CRRCR_HSI48RDY (1 << 1)i2c_set_10bit_address__UQQ_IBIT__ 0LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x75e0)__ARM_FEATURE_CDEINT_FAST8_MINRCC_AHB2ENR_GPIODEN (1 << 3)RCC_CCIPR_USART1SEL_SYS 1SYS_TICK_BASE (SCS_BASE + 0x0010)RST_USART3RCC_APB1ENR2_LPTIM2EN (1 << 5)__ARM_FEATURE_LDREX__UINT_LEAST32_MAX__ 0xffffffffULI2C_CR1_TXDMAEN (1 << 14)UINTPTR_MAXNULL ((void *)0)__USFRACT_EPSILON__ 0x1P-8UHR__ORDER_BIG_ENDIAN__ 4321__ARM_FEATURE_CMSERCC_AHB2ENR_GPIOFEN (1 << 5)PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)__UFRACT_MAX__ 0XFFFFP-16URI2C1_BASE (PERIPH_BASE_APB1 + 0x5400)__UINT_FAST32_TYPE__ unsigned intRCC_AHB1ENR_OFFSET 0x48__SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)RCC_APB1ENR1_SPI3EN (1 << 15)true 1RCC_APB1ENR1_TIM5EN (1 << 3)I2C_TIMINGR(i2c_base) MMIO32((i2c_base) + 0x10)__need_wchar_t__FLT_DECIMAL_DIG__ 9BIT31 (1<<31)__INT32_TYPE__ long int_T_PTRDIFF __USACCUM_IBIT__ 8GPIO_PORT_H_BASE (PERIPH_BASE_AHB2 + 0x1c00)RCC_AHB3ENR MMIO32(RCC_BASE + RCC_AHB3ENR_OFFSET)RCC_CCIPR_I2CxSEL_SYS 1__ULFRACT_MIN__ 0.0ULRRCC_APB1RSTR1_DAC1RST (1 << 29)RCC_AHB1ENR MMIO32(RCC_BASE + RCC_AHB1ENR_OFFSET)I2C_OAR1_OA1_7BIT 0__UINTPTR_TYPE__ unsigned intBIT21 (1<<21)I2C_ISR_TIMEOUT (1 << 12)UINT8_MAX __UINT8_MAX__RCC_APB1RSTR1 MMIO32(RCC_BASE + RCC_APB1RSTR1_OFFSET)__ARM_FEATURE_BF16_VECTOR_ARITHMETICslaveRCC_AHB2SMENR_GPIOFSMEN (1 << 5)UINT8_MAXRCC_AHB3ENR_QSPIEN (1 << 8)POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)__ARM_SIZEOF_MINIMAL_ENUM 1RCC_APB2RSTR_OFFSET 0x40RCC_AHB1RSTR_OFFSET 0x28__INT64_C(c) c ## LLI2C_CR1_STOPIE (1 << 5)RCC_APB1ENR1 MMIO32(RCC_BASE + RCC_APB1ENR1_OFFSET)__DA_FBIT__ 31__FLT32_MIN__ 1.1754943508222875e-38F32SIZE_MAX __SIZE_MAX__INT8_MIN__FLT64_DIG__ 15__GCC_ATOMIC_BOOL_LOCK_FREE 2INT_FAST64_MINRCC_CSR_MSIRANGE_4MHZ 6__INT_FAST32_MAX__ 0x7fffffffRCC_AHB2SMENR_ADCSMEN (1 << 13)__FLT_MAX_10_EXP__ 38I2C2_TIMEOUTR I2C_TIMEOUTR(I2C2)RCC_APB2RSTR_SPI1RST (1 << 12)WINT_MIN __WINT_MIN____DA_IBIT__ 32__GXX_TYPEINFO_EQUALITY_INLINE 0__TQ_FBIT__ 127__VFP_FP__ 1INT_LEAST16_MAXRCC_CCIPR_ADCSEL_SYS 3__ARM_ASM_SYNTAX_UNIFIED__ 1i2c_send_stopRCC_PLLCFGR_PLLQ_SHIFT 21INT32_MAX__ARM_FP 4RCC_CSR_WWDGRSTF (1 << 30)RCC_PLLCFGR_PLLM_MASK 0x7I2C1_TXDR I2C_TXDR(I2C1)__UFRACT_MIN__ 0.0URRCC_APB1SMENR1_UART5SMEN (1 << 20)i2c_send_dataRCC_APB1ENR2_OFFSET 0x5cI2C_ISR_TCR (1 << 7)RCC_APB2SMENR_DFSDMSMEN (1 << 24)RCC_BDCR_RTCSEL_HSEDIV32 3I2C_ICR_ALERTCF (1 << 13)__ARM_SIZEOF_WCHAR_T 4_WCHAR_T_ RCC_APB1RSTR1_TIM7RST (1 << 5)TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)__SIZEOF_DOUBLE__ 8__UINT_FAST32_MAX__ 0xffffffffU__LDBL_MAX_EXP__ 1024i2c_busyRCC_BDCR_RTCSEL_MASK 0x3RST_I2C1QUADSPI_BASE (0xa0001000U)_BSD_WCHAR_T_ RCC_CR_HSERDY (1 << 17)__ARM_FEATURE_FP16_VECTOR_ARITHMETICI2C_TIMINGR_SCLL_MASK (0xFF << I2C_TIMINGR_SCLL_SHIFT)I2C_ISR(i2c_base) MMIO32((i2c_base) + 0x18)speedh_timeRCC_AHB2RSTR_GPIOERST (1 << 4)I2C_OAR1_OA1EN_DISABLE (0x0 << 15)i2c_transmit_int_status__INTMAX_MAX__ 0x7fffffffffffffffLLINT64_MAXI2C_CR1_ALERTEN (1 << 22)UINT_LEAST16_MAX __UINT_LEAST16_MAX__RCC_CR_HSIASFS (1 << 11)__LONG_WIDTH__ 32RCC_CICR_HSERDYC (1 << 4)__OPTIMIZE__ 1USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x6800)__arm__ 1PTRDIFF_MINRCC_APB1RSTR1_UART5RST (1 << 20)ADC1_BASE (0x50000000U + 0x40000)RCC_CR_HSEBYP (1 << 18)UINT32_MAX __UINT32_MAX____OPTIMIZE_SIZE__ 1I2C_TIMEOUTR(i2c_base) MMIO32((i2c_base) + 0x14)RCC_CFGR_PPRE1_MASK 0x7RST_SPI3I2C_CR1_SBC (1 << 16)RST_SPI1RST_SPI2RCC_AHB2SMENR_GPIOCSMEN (1 << 2)_T_WCHAR INT_FAST32_MIN (-INT_FAST32_MAX - 1)_SIZET_ __INT8_TYPE__ signed char__LDBL_DENORM_MIN__ 4.9406564584124654e-324Li2c_resetSYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000)RCC_CR_MSIRANGE_100KHZ 0RCC_APB1RSTR1_OPAMPRST (1 << 30)RCC_CIER_HSERDYIE (1 << 4)_STDDEF_H_ LPTIM2_BASE (PERIPH_BASE_APB1 + 0x9400)RCC_CFGR_MCO_LSE 0x7UINT_LEAST32_MAX__ACCUM_MAX__ 0X7FFFFFFFP-15KRCC_CIFR_LSECSSF (1 << 9)__FLT64_MIN_EXP__ (-1021)__INT_FAST32_TYPE__ intRCC_APB1RSTR1_LCDRST (1 << 9)RCC_APB2ENR_TIM16EN (1 << 17)__FLT32_HAS_QUIET_NAN__ 1RCC_APB2RSTR_SAI2RST (1 << 22)__ARM_NEON__TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)USART2_BASE (PERIPH_BASE_APB1 + 0x4400)i2c_set_own_10bit_slave_addressRCC_BDCR_LSCOEN (1 << 24)i2c_set_7bit_addr_modeINT8_MAXi2c_nackRCC_CIER_LSIRDYIE (1 << 0)RCC_CSR_LSIRDY (1 << 1)CORESIGHT_LAR_OFFSET 0xfb0RCC_CICR_PLLSAI1RDYC (1 << 6)prescRCC_APB1ENR1_I2C1EN (1 << 21)RST_SWPMI1WCHAR_MIN__FLT32X_MIN_EXP__ (-1021)I2C_ICR_PECCF (1 << 11)__ARM_FEATURE_SAT 1_BSD_PTRDIFF_T_ __WCHAR_T i2c_disable_rxdmaRNG_BASE (0x50000000U + 0x60800)__ARM_ARCH_PROFILEI2C_ISR_DIR_WRITE (0x0 << 16)__LACCUM_IBIT__ 32RCC_CCIPR_LPTIM1SEL_SHIFT 18RCC_CCIPR_LPUART1SEL_LSE 3RCC_AHB2RSTR_GPIOGRST (1 << 6)MMIO16(addr) (*(volatile uint16_t *)(addr))SCS_BASE (PPBI_BASE + 0xE000)I2C_ICR_NACKCF (1 << 4)___int_ptrdiff_t_h INT16_MINI2C1_PECR I2C_PECR(I2C1)RCC_CIER_HSIRDYIE (1 << 3)RCC_CCIPR_UARTxSEL_MASK RCC_CCIPR_USARTxSEL_MASKlong long unsigned int__SIZEOF_SHORT__ 2i2c_set_data_hold_timeUINTPTR_MAX __UINTPTR_MAX__INT8_MAX __INT8_MAX__RCC_PLLCFGR_PLLM(x) ((x)-1)__UINT8_MAX__ 0xffINT64_Ci2c_enable_txdmaRCC_APB1SMENR1_TIM6SMEN (1 << 4)RST_CRC__FLT64_MAX_EXP__ 1024RCC_CFGR_SW_MASK 0x3RCC_CR_MSIRANGE_800KHZ 3BIT19 (1<<19)UINT_FAST16_MAXRST_CRS__FLT64_DECIMAL_DIG__ 17__UINTPTR_MAX__ 0xffffffffU__ARM_FEATURE_COMPLEXRCC_AHB1ENR_DMA1EN (1 << 0)rcc_periph_reset_pulse__SFRACT_EPSILON__ 0x1P-7HR__ATOMIC_CONSUME 1__FLT_MIN__ 1.1754943508222875e-38F__INT_LEAST16_TYPE__ short intRCC_PLLCFGR_PLLQ_DIV2 0END_DECLS INT32_MAX __INT32_MAX____USFRACT_FBIT__ 8RST_ADC1i2c_speedsRCC_CIFR_MSIRDYF (1 << 2)RCC_CR_MSIRDY (1 << 1)__GCC_ATOMIC_WCHAR_T_LOCK_FREE 2RCC_CCIPR_SAIxSEL_PLLSAI2P 1RCC_APB2RSTR_TIM17RST (1 << 18)RCC_APB1RSTR1_TIM5RST (1 << 3)__SIZEOF_PTRDIFF_T__ 4RCC_APB1ENR1_USART3EN (1 << 18)FMC_QUADSPI_BASE (0xA0000000U)RCC_APB1ENR1_UART5EN (1 << 20)RCC_CCIPR_USARTxSEL_SYS 1DMA1_BASE (PERIPH_BASE_AHB1 + 0x0000)RCC_APB1RSTR1_SPI2RST (1 << 14)RCC_CFGR_HPRE_DIV8 0xa__FLT32X_HAS_QUIET_NAN__ 1__GNUC_EXECUTION_CHARSET_NAME "UTF-8"I2C_TIMINGR_SDADEL_MASK (0xF << I2C_TIMINGR_SDADEL_SHIFT)RCC_AHB3RSTR MMIO32(RCC_BASE + RCC_AHB3RSTR_OFFSET)__ACCUM_MIN__ (-0X1P15K-0X1P15K)RCC_CCIPR_SAIxSEL_PLL 2RCC_CSR_RESET_FLAGS (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF | RCC_CSR_IWDGRSTF | RCC_CSR_SFTRSTF | RCC_CSR_BORRSTF | RCC_CSR_PINRSTF | RCC_CSR_OBLRSTF | RCC_CSR_FWRSTF)__SIG_ATOMIC_WIDTH__ 32__DBL_MIN_EXP__ (-1021)i2c_set_speedRCC_BASE (PERIPH_BASE_AHB1 + 0x1000)MPU_BASE (SCS_BASE + 0x0D90)TIM15_BASE (PERIPH_BASE_APB2 + 0x4000)i2c_set_scl_low_periodRCC_APB2RSTR_TIM1RST (1 << 11)UINT16_MAXINT_LEAST16_MINRCC_AHB2RSTR_OTGFSRST (1 << 12)__LDBL_MAX_10_EXP__ 308I2C_CR1_SMBHEN (1 << 20)SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)RCC_AHB3RSTR_FMCRST (1 << 0)RCC_ICSCR_MSITRIM_SHIFT 8RST_SYSCFGI2C_CR1_ANFOFF (1 << 12)RCC_CFGR_SWS_HSI16 0x1INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)__ARM_FEATURE_CRC32__TA_FBIT__ 63__LDBL_NORM_MAX__ 1.7976931348623157e+308LI2C_OAR1_OA1MODE (1 << 10)I2C1_ICR I2C_ICR(I2C1)bool _Bool__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64RCC_ICSCR_HSITRIM_MASK 0x1f__UINT_LEAST32_TYPE__ long unsigned intRCC_CCIPR_I2C1SEL_SHIFT 12SAI2_BASE (PERIPH_BASE_APB2 + 0x5800)RCC_APB1SMENR2_SWPMI1SMEN (1 << 2)INT32_MIN__HA_IBIT__ 8INT16_C(c) __INT16_C(c)RCC_CR_MSIRGSEL (1 << 3)INT8_MIN (-INT8_MAX - 1)__FLT32X_HAS_DENORM__ 1TSC_BASE (PERIPH_BASE_AHB1 + 0x4000)INT16_CRCC_CR_MSIRANGE_8MHZ 7I2C_RXDR(i2c_base) MMIO32((i2c_base) + 0x24)RCC_APB2SMENR_USART1SMEN (1 << 14)RCC_PLLCFGR MMIO32(RCC_BASE + 0x0c)__HQ_IBIT__ 0long long int__FLT_EVAL_METHOD__ 0__SA_IBIT__ 16RCC_CIFR_LSERDYF (1 << 1)RCC_CR_HSEON (1 << 16)__UHA_FBIT__ 8RCC_CSR_MSIRANGE_MASK 0xfi2c_send_startRCC_CSR_PINRSTF (1 << 26)__ARM_FEATURE_CLZ 1INT_LEAST32_MAX__FLT64_MIN_10_EXP__ (-307)RCC_APB2SMENR_TIM1SMEN (1 << 11)__ARM_FEATURE_FMA 1__DEFINED_size_t i2c_disable_analog_filter__ARM_NEON_FPI2C_PECR(i2c_base) MMIO32((i2c_base) + 0x20)__FDPIC__CORESIGHT_LSR_OFFSET 0xfb4INT64_MIN__UINT16_MAX__ 0xffffOPAMP_BASE (PERIPH_BASE_APB1 + 0x7800)RCC_AHB2ENR_GPIOCEN (1 << 2)RCC_APB1ENR1_SPI2EN (1 << 14)__UFRACT_IBIT__ 0RCC_APB1SMENR2_LPUART1SMEN (1 << 0)BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)I2C_TIMINGR_SCLH_MASK (0xFF << I2C_TIMINGR_SCLH_SHIFT)__DBL_HAS_QUIET_NAN__ 1__LDBL_MIN_10_EXP__ (-307)RCC_BDCR_LSEDRV_HIGH 3RCC_CSR_IWDGRSTF (1 << 29)RCC_CCIPR_SWPMI1SEL (1 << 30)SIG_ATOMIC_MAX__USFRACT_IBIT__ 0RCC_AHB2SMENR_OFFSET 0x6c__FLT32X_MIN_10_EXP__ (-307)WINT_MAXRCC_CFGR_HPRE_MASK 0xf__DEC_EVAL_METHOD__ 2INT_LEAST64_MAX__LDBL_HAS_INFINITY__ 1long unsigned intDFSDM_BASE (PERIPH_BASE_APB2 + 0x6000)i2c_set_10bit_addr_mode__SFRACT_MAX__ 0X7FP-7HRRCC_APB1RSTR1_I2C2RST (1 << 22)RCC_APB1ENR1_TIM4EN (1 << 2)RST_OPAMPRCC_APB1SMENR1_OPAMPSMEN (1 << 30)USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6c00)RCC_CR_PLLSAI1ON (1 << 26)s_timeRCC_AHB2SMENR_GPIOHSMEN (1 << 7)__SIZEOF_LONG_DOUBLE__ 8LPTIM1_BASE (PERIPH_BASE_APB1 + 0x7c00)__FLT64_HAS_DENORM__ 1RCC_CCIPR_CLK48SEL_PLLSAI1Q 1__FLT_HAS_DENORM__ 1__LLACCUM_FBIT__ 31I2C_CR2_NBYTES_MASK (0xFF << I2C_CR2_NBYTES_SHIFT)UINT_LEAST8_MAX__THUMBEL__ 1__DBL_MANT_DIG__ 53RCC_BDCR_LSEDRV_MEDLOW 1RCC_PLLCFGR_PLLR_SHIFT 25RCC_APB2RSTR MMIO32(RCC_BASE + RCC_APB2RSTR_OFFSET)__GCC_CONSTRUCTIVE_SIZE 64I2C1_OAR2 I2C_OAR2(I2C1)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__TQ_IBIT__ 0RCC_APB1SMENR1_I2C1SMEN (1 << 21)__FLT32X_MIN__ 2.2250738585072014e-308F32xRCC_ICSCR_MSITRIM_MASK 0xff__SIZEOF_FLOAT__ 4I2C_ICR_TIMOUTCF (1 << 12)FPB_BASE (PPBI_BASE + 0x2000)__SIZE_T__ I2C_TIMINGR_SCLH_SHIFT 8__SIZE_TYPE__ unsigned intRCC_CSR_SFTRSTF (1 << 28)__UINT_LEAST8_TYPE__ unsigned charUINT16_CI2C3 I2C3_BASERCC_APB1SMENR1_DAC1SMEN (1 << 29)i2c_is_start__CHAR16_TYPE__ short unsigned intEXTI_BASE (PERIPH_BASE_APB2 + 0x0400)INT16_MIN (-INT16_MAX - 1)RCC_PLLCFGR_PLLR_DIV2 0I2C_TIMINGR_SCLL_SHIFT 0__UFRACT_FBIT__ 16unsigned intI2C2_ICR I2C_ICR(I2C2)ID_BASE (SCS_BASE + 0x0FD0)_REG_BIT(base,bit) (((base) << 5) + (bit))I2C_CR1_TCIE (1 << 6)__ARM_FEATURE_MVEST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0x75a8))RCC_BDCR_RTCSEL_LSI 2__INT64_TYPE__ long long int__UHA_IBIT__ 8__ARM_FEATURE_CDE_COPROC__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRRCC_APB1SMENR1 MMIO32(RCC_BASE + RCC_APB1SMENR1_OFFSET)short int__GNUC_MINOR__ 2RCC_CIER MMIO32(RCC_BASE + 0x18)BBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)RCC_AHB1SMENR_FLASHSMEN (1 << 8)RST_I2C3INTMAX_MAX __INTMAX_MAX__RCC_AHB2RSTR_GPIODRST (1 << 3)__INTMAX_TYPE__ long long intRCC_APB1RSTR2_LPUART1RST (1 << 0)__UINT_LEAST16_TYPE__ short unsigned intRCC_CFGR_HPRE_DIV2 0x8__ULLFRACT_EPSILON__ 0x1P-64ULLRRCC_CCIPR_USART3SEL_SHIFT 4RCC_PLLSAI1_CFGR MMIO32(RCC_BASE + 0x10)RCC_CSR_LSION (1 << 0)RCC_APB1SMENR1_UART4SMEN (1 << 19)I2C_CR1_GCEN (1 << 19)../common/i2c_common_v2.cRCC_APB2ENR_SYSCFGEN (1 << 0)TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)RCC_BDCR_LSEDRV_MEDHIGH 2RST_LPUART1__FLT_DENORM_MIN__ 1.4012984643248171e-45FI2C2_TXDR I2C_TXDR(I2C2)RST_GPIOEINT_FAST32_MAX __INT_FAST32_MAX__RCC_CCIPR_SAIxSEL_EXT 3TIM8_BASE (PERIPH_BASE_APB2 + 0x3400)RCC_CCIPR_DFSDMSEL (1 << 31)__DEFINED_ptrdiff_t __UINT_LEAST8_MAX__ 0xff__ARM_ARCH_ISA_THUMB 2__UINT32_MAX__ 0xffffffffULRCC_PLLCFGR_PLLN_MASK 0x7f__GNUC_PATCHLEVEL__ 1GCC: (15:12.2.rel1-1) 12.2.1 20221205˙˙˙˙| 0 ’A„…†‡ŽNBŽb ÎĂBA3aeabi)7E-M M "ń˙ , !!""##$$%%&&''(())**++,,--..//001122334455667788::<>?ACE[]GIKMOQSUWY_>o Ň7kś Ô ^a 0# 9 P _ m |›»ÉÖ ď 2Jay !¦ "˝ #Ô $ě%& '2 (L)f*s +† ,š-Ł.¬/Ä0Ú1ě2 3 4( 5: 6K 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LPTIM_CFGR_TRIGSEL_SHIFT)WCHAR_MAX __WCHAR_MAX____FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX__LPTIM2_CMP LPTIM_CMP(LPTIM2_BASE)__UINT_LEAST8_TYPE__ unsigned char__ACCUM_FBIT__ 15PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)__UACCUM_IBIT__ 16long intUINT8_MAXIWDG_BASE (PERIPH_BASE_APB1 + 0x3000)SIZE_MAX __SIZE_MAX____INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1__FLT32X_EPSILON__ 2.2204460492503131e-16F32xNVIC_BASE (SCS_BASE + 0x0100)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32USART2_BASE (PERIPH_BASE_APB1 + 0x4400)__UINTMAX_C(c) c ## ULLlptimer_disable_preload__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed char__GCC_ATOMIC_BOOL_LOCK_FREE 2BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON____FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX____THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRshort unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)BIT7 (1<<7)BIT17 (1<<17)__FLT32X_MIN_10_EXP__ (-307)UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLPTIM2_ICR LPTIM_ICR(LPTIM2_BASE)LIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)__DBL_IS_IEC_60559__ 2__UINT_FAST32_MAX__ 0xffffffffU__DEC_EVAL_METHOD__ 2__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4LPTIM_CFGR_TRIGEN_SHIFT 17__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32__FLT32X_MIN_EXP__ (-1021)DMA1_BASE (PERIPH_BASE_AHB1 + 0x0000)LPTIM_CFGR_PRESC_8 (3 << LPTIM_CFGR_PRESC_SHIFT)GNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsBIT27 (1<<27)TIM1_BASE (PERIPH_BASE_APB2 + 0x2C00)LPTIM_CR_ENABLE (1 << 0)__UTA_FBIT__ 64INTMAX_C(c) __INTMAX_C(c)__FLT_DECIMAL_DIG__ 9__thumb__ 1LPTIM_CFGR_PRESC_32 (5 << LPTIM_CFGR_PRESC_SHIFT)__INT_LEAST32_MAX__ 0x7fffffffLLIBOPENCM3_MEMORYMAP_COMMON_H signed charINT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)INT32_C(c) __INT32_C(c)__GNUC_STDC_INLINE__ 1__FRACT_FBIT__ 15__LLACCUM_EPSILON__ 0x1P-31LLK__GNUC_PATCHLEVEL__ 1__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2PTRDIFF_MIN__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)UINTPTR_MAX __UINTPTR_MAX____ARM_ARCH_PROFILE 77LPTIM_CFGR_TRGFLT_2 (1 << LPTIM_CFGR_TRGFLT_SHIFT)__LACCUM_FBIT__ 31LPTIM_CFGR_TRIGEN (3 << LPTIM_CFGR_TRIGEN_SHIFT)LPTIM_CFGR_CKFLT_4 (2 << LPTIM_CFGR_CKFLT_SHIFT)GPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000)lptimer_set_counter__FLT64_MAX_10_EXP__ 308GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400)MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINSDMMC1_BASE (PERIPH_BASE_APB2 + 0x2800)__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)__FRACT_MAX__ 0X7FFFP-15RTIM3_BASE (PERIPH_BASE_APB1 + 0x0400)INT_LEAST32_MAX __INT_LEAST32_MAX____INT_FAST32_MAX__ 0x7ffffffftrigenLPTIM_CFGR_TRIGEN_MASK 0x07__UINT16_MAX__ 0xffff__TQ_FBIT__ 127LPTIM_CR(tim_base) MMIO32((tim_base) + 0x10)LPTIM_CFGR_ENC (1 << 24)__USQ_FBIT__ 32INT_FAST16_MIN__thumb2__ 1__ULLACCUM_FBIT__ 32FMC_QUADSPI_BASE (0xA0000000U)LPTIM_CFGR_PRESC (7 << LPTIM_CFGR_PRESC_SHIFT)LPTIM_CFGR_CKPOL_RISING (0 << LPTIM_CFGR_CKPOL_SHIFT)_BoolLPTIM1_CNT LPTIM_CNT(LPTIM1_BASE)__FLT_DENORM_MIN__ 1.4012984643248171e-45FINT_FAST32_MIN (-INT_FAST32_MAX - 1)__STRICT_ANSI__ 1FMC3_BANK_BASE (0x80000000U)UINT_LEAST8_MAXlptimer_set_internal_clock_sourceUINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)TIM8_BASE (PERIPH_BASE_APB2 + 0x3400)LPTIM_CFGR_TIMOUT (1 << 19)__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX____USA_IBIT__ 16__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1DBGMCU_BASE (PPBI_BASE + 0x00042000)PTRDIFF_MIN (-PTRDIFF_MAX - 1)USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6c00)LPTIM_CFGR_WAVPOL (1 << 21)__UINT_FAST64_TYPE__ long long unsigned intPERIPH_BASE_AHB2 (0x48000000U)DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7590)__FLT_MIN__ 1.1754943508222875e-38Flptimer_set_waveform_polarity_high__HA_FBIT__ 7__FDPIC____FLT32_IS_IEC_60559__ 2GPIO_PORT_G_BASE (PERIPH_BASE_AHB2 + 0x1800)__HAVE_SPECULATION_SAFE_VALUE 1INT_FAST64_MIN__USFRACT_IBIT__ 0__INT32_C(c) c ## LLPTIM_CFGR_TRIGSEL_EXT_TRIG7 (7 << LPTIM_CFGR_TRIGSEL_SHIFT)__USFRACT_MIN__ 0.0UHRTSC_BASE (PERIPH_BASE_AHB1 + 0x4000)__ARM_NEON__UINT8_MAX__ 0xff__LDBL_MAX_EXP__ 1024LIBOPENCM3_MEMORYMAP_H LPTIM_CFGR_CKPOL (3 << LPTIM_CFGR_CKPOL_SHIFT)__DBL_HAS_DENORM__ 1DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)LPTIM_ISR_CMPOK (1 << 3)QUADSPI_BASE (0xa0001000U)__DA_FBIT__ 31__GXX_ABI_VERSION 1017GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0c00)__INT_LEAST16_MAX__ 0x7ffflptimer_enable_irqID_BASE (SCS_BASE + 0x0FD0)__ULLACCUM_EPSILON__ 0x1P-32ULLKlptimer_disableINT_LEAST8_MAX __INT_LEAST8_MAX__LPTIM_CFGR_TRIGEN_RISING (1 << LPTIM_CFGR_TRIGEN_SHIFT)__UINT32_C(c) c ## UL__UACCUM_MIN__ 0.0UK__FLT_EPSILON__ 1.1920928955078125e-7FTIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)LPTIM_CFGR_CKPOL_SHIFT 1__ARM_ARCH_ISA_THUMBLPTIM_CFGR_TRIGSEL_EXT_TRIG4 (4 << LPTIM_CFGR_TRIGSEL_SHIFT)__ARM_FEATURE_MATMUL_INT8LIBOPENCM3_CM3_MEMORYMAP_H __GCC_ATOMIC_SHORT_LOCK_FREE 2LPTIM_CFGR_PRESC_128 (7 << LPTIM_CFGR_PRESC_SHIFT)__USACCUM_FBIT__ 8__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1lptimer_set_periodcompare_valueSCS_BASE (PPBI_BASE + 0xE000)SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)__FLT32_HAS_QUIET_NAN__ 1I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)__LDBL_HAS_INFINITY__ 1__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))__FLT32X_MAX_10_EXP__ 308__ARM_ARCH_EXT_IDIV__ 1bool _BoolLPTIM_ICR_ARROKCF (1 << 4)LPTIM_ISR_CMPM (1 << 0)UINTMAX_MAX __UINTMAX_MAX____SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffLPTIM_CFGR_TRIGEN_FALLING (2 << LPTIM_CFGR_TRIGEN_SHIFT)BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)INT16_MAX __INT16_MAX____FP_FAST_FMAF 1__FLT32X_IS_IEC_60559__ 2LPTIM_CFGR_PRELOAD (1 << 22)PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))FIREWALL_BASE (PERIPH_BASE_APB2 + 0x1C00)__INT_LEAST16_WIDTH__ 16LPTIM_ISR_ARRM (1 << 1)SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)LPTIM_IER_UPIE (1 << 5)__ARM_FEATURE_FP16_FMLLPTIM_IER_EXTTRIGIE (1 << 2)INT16_MIN (-INT16_MAX - 1)__USFRACT_EPSILON__ 0x1P-8UHR__WINT_MAX__ 0xffffffffU__USFRACT_FBIT__ 8CORESIGHT_LSR_SLI (1<<0)LPTIM2_ISR LPTIM_ISR(LPTIM2_BASE)__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX____UINT32_MAX__ 0xffffffffUL__INT_LEAST8_MAX__ 0x7f__GCC_ATOMIC_POINTER_LOCK_FREE 2__ARM_FEATURE_QBIT 1__ARM_FEATURE_CLZ 1__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEX__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024__UINT_LEAST32_MAX__ 0xffffffffUL__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)LIBOPENCM3_LPTIMER_H __INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1__ACCUM_MAX__ 0X7FFFFFFFP-15K__INT8_MAX__ 0x7fBIT14 (1<<14)prescaler__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16__SHRT_WIDTH__ 16BIT20 (1<<20)__ARM_FEATURE_MVE__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intSWPMI1_BASE (PERIPH_BASE_APB1 + 0x8800)SAI1_BASE (PERIPH_BASE_APB2 + 0x5400)INT_FAST32_MINLPTIM_CFGR_TRIGSEL_EXT_TRIG2 (2 << LPTIM_CFGR_TRIGSEL_SHIFT)__FLT_EVAL_METHOD_TS_18661_3__ 0__SCHAR_WIDTH__ 8BIT18 (1<<18)COMP_BASE (PERIPH_BASE_APB2 + 0x0200)SIZE_MAX__UINT_FAST8_TYPE__ unsigned int__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RLPTIM_ICR(tim_base) MMIO32((tim_base) + 0x04)BIT24 (1<<24)__INT32_MAX__ 0x7fffffffLLPTIM_ISR_DOWN (1 << 6)UINTMAX_MAXBIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_BF16_VECTOR_ARITHMETICINFO_BASE (0x1fff0000U)PPBI_BASE (0xE0000000U)__FLT32_MANT_DIG__ 24LPTIM_CFGR_WAVE (1 << 20)INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN____LDBL_EPSILON__ 2.2204460492503131e-16LLPTIM1_ISR LPTIM_ISR(LPTIM1_BASE)BIT28 (1<<28)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2lptimer_disable_irq__DBL_MAX_EXP__ 1024__ATOMIC_RELEASE 3UINT_FAST8_MAX__FLT_MANT_DIG__ 24__UDQ_IBIT__ 0__INT_LEAST32_TYPE__ long intLPTIM_CFGR_PRESC_64 (6 << LPTIM_CFGR_PRESC_SHIFT)__OPTIMIZE_SIZE__ 1__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UKLPTIM1_ARR LPTIM_ARR(LPTIM1_BASE)__FLT64_NORM_MAX__ 1.7976931348623157e+308F64UINTPTR_MAX__LDBL_DENORM_MIN__ 4.9406564584124654e-324L__INT64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_SAT 1__ULLFRACT_IBIT__ 0MMIO16(addr) (*(volatile uint16_t *)(addr))AES_BASE (0x50000000U + 0x60000)DAC_BASE (PERIPH_BASE_APB1 + 0x7400)__GNUC__ 12BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)__FLT32_DIG__ 6WCHAR_MAX__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0UUART5_BASE (PERIPH_BASE_APB1 + 0x5000)__UQQ_IBIT__ 0CORESIGHT_LSR_OFFSET 0xfb4__GCC_ATOMIC_LONG_LOCK_FREE 2__ULACCUM_MIN__ 0.0ULK__LDBL_MAX__ 1.7976931348623157e+308L__ARM_ARCH 7lptimer_get_counter__FLT_RADIX__ 2BIT3 (1<<3)long long intCORESIGHT_LAR_KEY 0xC5ACCE55__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAXLPTIM_CFGR_TRIGSEL_EXT_TRIG0 (0 << LPTIM_CFGR_TRIGSEL_SHIFT)LPTIM_ICR_UPCF (1 << 5)__LDBL_HAS_QUIET_NAN__ 1__LONG_LONG_WIDTH__ 64BIT6 (1<<6)LPTIM_CFGR_TRGFLT_MASK 0x03__UINT_FAST64_MAX__ 0xffffffffffffffffULL__ARM_FP__HA_IBIT__ 8LPTIM_CMP(tim_base) MMIO32((tim_base) + 0x14)__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1BIT9 (1<<9)__FLT32X_MIN__ 2.2250738585072014e-308F32xINTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024LPTIM2_ARR LPTIM_ARR(LPTIM2_BASE)UINT16_MAXLPTIM_CFGR_CKFLT_8 (3 << LPTIM_CFGR_CKFLT_SHIFT)__FLT64_MIN__ 2.2250738585072014e-308F64__INTMAX_C(c) c ## LL__ARM_ARCH_PROFILE__INT64_TYPE__ long long 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1__INT8_TYPE__ signed char__FLT32_MIN__ 1.1754943508222875e-38F32RCC_APB2SMENR_SAI1SMEN (1 << 21)__USACCUM_MIN__ 0.0UHKGPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000)__FLT32_DECIMAL_DIG__ 9__DECIMAL_DIG__ 17__LDBL_MIN_EXP__ (-1021)UINTPTR_MAX __UINTPTR_MAX____LDBL_MANT_DIG__ 53INT64_MIN (-INT64_MAX - 1)RCC_CFGR_STOPWUCK_MSI (0 << 15)RCC_APB2SMENR_SDMMC1SMEN (1 << 10)__UINT8_C(c) c__INT16_TYPE__ short inttrue 1RCC_APB1RSTR1 MMIO32(RCC_BASE + RCC_APB1RSTR1_OFFSET)__FLT64_MAX__ 1.7976931348623157e+308F64RCC_PLLCFGR_PLLN_MASK 0x7fUINT_FAST32_MAXRCC_CFGR_MCO_HSE 0x4RCC_CIER_LSIRDYIE (1 << 0)RCC_APB1RSTR2_OFFSET 0x3cRCC_PLLCFGR_PLLSRC_NONE 0RCC_CCIPR_UARTxSEL_LSE RCC_CCIPR_USARTxSEL_LSEINT_FAST64_MAX __INT_FAST64_MAX__RCC_CR_MSION (1 << 0)__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1RCC_CR_MSIRANGE_48MHZ 11__STDC_HOSTED__ 1rcc_osc_off__SIG_ATOMIC_TYPE__ intRCC_CSR_SFTRSTF (1 << 28)RCC_PLLSAI1_CFGR MMIO32(RCC_BASE + 0x10)RCC_CIFR_CSSF (1 << 8)__INT_FAST64_TYPE__ long long int__WINT_TYPE__ unsigned intGPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800)ST_TSENSE_CAL2_110C MMIO16((INFO_BASE + 0x75ca))RCC_CFGR_MCO_PLL 0x5INT32_MIN (-INT32_MAX - 1)__FLT32_MAX_10_EXP__ 38RCC_CFGR_HPRE_DIV8 0xaRCC_APB1ENR1_TIM3EN (1 << 1)RCC_APB2SMENR_SYSCFGSMEN (1 << 0)RCC_BDCR_LSEDRV_MASK 0x3__USFRACT_MAX__ 0XFFP-8UHRLPTIM1_BASE (PERIPH_BASE_APB1 + 0x7c00)__FP_FAST_FMAF32 1RCC_APB1SMENR1_TIM5SMEN (1 << 3)__UINTPTR_MAX__ 0xffffffffU__FLT32_MIN_EXP__ (-125)RCC_CR_MSIRANGE_4MHZ 6RCC_APB1ENR2_SWPMI1EN (1 << 2)RCC_APB2SMENR_TIM15SMEN (1 << 16)UINT32_MAX __UINT32_MAX____DBL_EPSILON__ ((double)2.2204460492503131e-16L)RCC_APB2RSTR_DFSDMRST (1 << 24)RCC_AHB1ENR MMIO32(RCC_BASE + RCC_AHB1ENR_OFFSET)__ULFRACT_FBIT__ 32INT8_MIN (-INT8_MAX - 1)__FLT64_MIN_10_EXP__ (-307)RCC_APB1SMENR1_LPTIM1SMEN (1 << 31)__GNUC_EXECUTION_CHARSET_NAME "UTF-8"RCC_CIFR MMIO32(RCC_BASE + 0x1c)BIT10 (1<<10)__INT_FAST64_WIDTH__ 64__STDC_VERSION__ 199901LINT_LEAST64_MAX __INT_LEAST64_MAX__SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)RCC_CCIPR_SAI1SEL_SHIFT 22RCC_AHB2SMENR MMIO32(RCC_BASE + RCC_AHB2SMENR_OFFSET)RCC_CFGR_MCOPRE_DIV8 3__SFRACT_EPSILON__ 0x1P-7HRBIT0 (1<<0)__INT32_C(c) c ## Lppre1__ORDER_BIG_ENDIAN__ 4321I2C3_BASE (PERIPH_BASE_APB1 + 0x5c00)SYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000)RCC_APB2SMENR_USART1SMEN (1 << 14)__SQ_FBIT__ 31INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)RCC_CR_MSIRGSEL (1 << 3)RCC_CCIPR MMIO32(RCC_BASE + 0x88)__UHQ_FBIT__ 16RCC_APB1ENR2_LPTIM2EN (1 << 5)__FLT64_MIN_EXP__ (-1021)RCC_AHB1RSTR_CRCRST (1 << 12)__PTRDIFF_WIDTH__ 32__UINT_FAST8_MAX__ 0xffffffffURCC_CFGR_PPRE1_DIV2 0x4RCC_APB1ENR1_OPAMPEN (1 << 30)RTC_BASE (PERIPH_BASE_APB1 + 0x2800)__LACCUM_IBIT__ 32RCC_CCIPR_UARTxSEL_HSI16 RCC_CCIPR_USARTxSEL_HSI16__INT_FAST16_WIDTH__ 32INTMAX_CRCC_CCIPR_I2C2SEL_SHIFT 14__VFP_FP__ 1rcc_set_msi_range__LLFRACT_MIN__ (-0.5LLR-0.5LLR)INT_FAST8_MAX__GCC_ATOMIC_POINTER_LOCK_FREE 2__UINT_FAST16_MAX__ 0xffffffffURCC_APB1SMENR1_TIM6SMEN (1 << 4)__INTPTR_MAX__ 0x7fffffffINT64_C(c) __INT64_C(c)RCC_CIER_LSE_CSSIE (1 << 9)RCC_CCIPR_USART1SEL_SHIFT 0rcc_osc_ready_int_clear__GCC_IEC_559_COMPLEX 0PERIPH_BASE (0x40000000U)RCC_AHB2SMENR_GPIOHSMEN (1 << 7)RCC_CFGR_SWS_PLL 0x3RCC_CFGR_MCO_SHIFT 24WCHAR_MAX __WCHAR_MAX__RCC_APB2SMENR_TIM8SMEN (1 << 13)__FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX__RCC_CSR_MSIRANGE_4MHZ 6__UINT_LEAST8_TYPE__ unsigned charRCC_AHB2ENR_GPIOEEN (1 << 4)RCC_APB1RSTR1_I2C1RST (1 << 21)RCC_APB1RSTR2_LPUART1RST (1 << 0)__ACCUM_FBIT__ 15PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)__UACCUM_IBIT__ 16long intUINT8_MAXIWDG_BASE (PERIPH_BASE_APB1 + 0x3000)SIZE_MAX __SIZE_MAX__RCC_CICR_PLLSAI2RDYC (1 << 7)__INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17RCC_CCIPR_CLK48SEL_SHIFT 26__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1RCC_APB1ENR1_I2C1EN (1 << 21)RCC_CR_MSIRANGE_400KHZ 2__FLT32X_EPSILON__ 2.2204460492503131e-16F32xRCC_ICSCR_MSICAL_MASK 0xffRCC_CCIPR_SAIxSEL_PLLSAI1P 0NVIC_BASE (SCS_BASE + 0x0100)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32USART2_BASE (PERIPH_BASE_APB1 + 0x4400)__UINTMAX_C(c) c ## ULLrcc_enable_rtc_clock__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed charRCC_AHB1RSTR MMIO32(RCC_BASE + RCC_AHB1RSTR_OFFSET)__GCC_ATOMIC_BOOL_LOCK_FREE 2BIT4 (1<<4)UINT_FAST64_MAX__SA_FBIT__ 15INT_FAST32_MAX__ARM_NEON____FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX____THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRRCC_APB1SMENR1_TIM4SMEN (1 << 2)RCC_CSR_MSIRANGE_8MHZ 7rcc_ahb_frequencyshort unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)BIT7 (1<<7)BIT17 (1<<17)__FLT32X_MIN_10_EXP__ (-307)UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)__DBL_IS_IEC_60559__ 2__UINT_FAST32_MAX__ 0xffffffffU__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4RCC_AHB3SMENR_OFFSET 0x70RCC_APB2RSTR_TIM15RST (1 << 16)RCC_AHB2SMENR_ADCSMEN (1 << 13)apb_clkRCC_BDCR_RTCEN (1 << 15)__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32DMA1_BASE (PERIPH_BASE_AHB1 + 0x0000)RCC_BDCR_RTCSEL_NONE 0RCC_CIER_PLLSAI1RDYIE (1 << 6)RCC_AHB1RSTR_TSCRST (1 << 16)GNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsBIT27 (1<<27)SAI1_BASE (PERIPH_BASE_APB2 + 0x5400)RCC_CICR_MSIRDYC (1 << 2)RCC_CCIPR_LPUART1SEL_HSI16 2RCC_APB2ENR_SYSCFGEN (1 << 0)RCC_CCIPR_CLK48SEL_HSI48 0__UTA_FBIT__ 64usartRCC_BDCR_LSESYSDIS (1 << 7)RCC_CIFR_MSIRDYF (1 << 2)__FLT_DECIMAL_DIG__ 9RCC_CRRCR_HSI48RDY (1 << 1)LIBOPENCM3_MEMORYMAP_COMMON_H RCC_LSI__VERSION__ "12.2.1 20221205"RCC_APB1ENR1_OFFSET 0x58uint8_tINT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)__ARM_FEATURE_FMA 1__GNUC_STDC_INLINE__ 1__INT64_C(c) c ## LL__FRACT_FBIT__ 15__LLACCUM_EPSILON__ 0x1P-31LLK__GNUC_PATCHLEVEL__ 1__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2PTRDIFF_MINRCC_AHB2RSTR_GPIOGRST (1 << 6)__UINT_LEAST16_MAX__ 0xffffRCC_APB1SMENR1_OFFSET 0x78RCC_AHB2RSTR_GPIOARST (1 << 0)PPBI_BASE (0xE0000000U)__ARM_ARCH_PROFILE 77RCC_CIFR_PLLRDYF (1 << 5)INT32_MAXGPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000)RCC_APB1ENR1_TIM6EN (1 << 4)__FLT64_MAX_10_EXP__ 308GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400)MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINRCC_PLLCFGR_PLLR_DIV2 0RCC_ICSCR_HSITRIM_MASK 0x1fSDMMC1_BASE (PERIPH_BASE_APB2 + 0x2800)__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)__FRACT_MAX__ 0X7FFFP-15RRCC_CCIPR_LPUART1SEL_LSE 3TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)INT_LEAST32_MAX __INT_LEAST32_MAX__RCC_APB1ENR2_LPUART1EN (1 << 0)__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5RCC_APB1SMENR1_USART2SMEN (1 << 17)rcc_set_clock48_sourceRCC_CIER_PLLRDYIE (1 << 5)RCC_APB1SMENR2_LPUART1SMEN (1 << 0)RCC_APB1ENR1_SPI2EN (1 << 14)RCC_CFGR_SW_HSE 0x2RCC_AHB2SMENR_GPIODSMEN (1 << 3)RCC_CR_MSIRANGE_SHIFT 4__UINT16_MAX__ 0xffff__TQ_FBIT__ 127RCC_AHB2RSTR_ADCRST (1 << 13)LPUART1_BASE (PERIPH_BASE_APB1 + 0x8000)__USQ_FBIT__ 32INT_FAST16_MINRCC_AHB2SMENR_GPIOESMEN (1 << 4)RCC_CSR_IWDGRSTF (1 << 29)__thumb2__ 1__ULLACCUM_FBIT__ 32FMC_QUADSPI_BASE (0xA0000000U)RCC_AHB2SMENR_SRAM2SMEN (1 << 9)_BoolRCC_APB2SMENR_SAI2SMEN (1 << 22)RCC_BDCR_RTCSEL_HSEDIV32 3RCC_CFGR_MCO_MASK 0xf__STRICT_ANSI__ 1rcc_get_usart_clk_freqFMC3_BANK_BASE (0x80000000U)UINT_LEAST8_MAXUINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)TIM8_BASE (PERIPH_BASE_APB2 + 0x3400)RCC_APB1RSTR1_CAN1RST (1 << 25)__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__RCC_AHB1RSTR_DMA2RST (1 << 1)RCC_BDCR_LSECSSON (1 << 5)RCC_APB2ENR_SAI2EN (1 << 22)__USA_IBIT__ 16__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1DBGMCU_BASE (PPBI_BASE + 0x00042000)PTRDIFF_MIN (-PTRDIFF_MAX - 1)UART5_BASE (PERIPH_BASE_APB1 + 0x5000)RCC_BDCR_LSEDRV_HIGH 3__UINT_FAST64_TYPE__ long long unsigned intPERIPH_BASE_AHB2 (0x48000000U)RCC_CR_MSIRANGE_8MHZ 7DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7590)__FLT_MIN__ 1.1754943508222875e-38FRCC_CFGR_MCOPRE_MASK 0x7__HA_FBIT__ 7RCC_CFGR_MCO_HSI48 0x8__FDPIC____UFRACT_MIN__ 0.0URRCC_BDCR_LSERDY (1 << 1)RCC_APB1SMENR2_LPTIM2SMEN (1 << 5)__FLT32_IS_IEC_60559__ 2RCC_AHB1SMENR_DMA1SMEN (1 << 0)GPIO_PORT_G_BASE (PERIPH_BASE_AHB2 + 0x1800)RCC_CSR_PINRSTF (1 << 26)INT_FAST64_MINrcc_osc_ready_int_enablercc_set_msi_range_standbyRCC_CIER_HSI48RDYIE (1 << 10)__LDBL_EPSILON__ 2.2204460492503131e-16LRCC_CCIPR_USART1SEL_APB 0RCC_AHB1RSTR_FLASHRST (1 << 8)__USFRACT_MIN__ 0.0UHRTSC_BASE (PERIPH_BASE_AHB1 + 0x4000)RCC_BDCR_LSEDRV_SHIFT 3__ARM_NEONRCC_PLLCFGR_PLLQ_DIV2 0__UINT8_MAX__ 0xffRCC_CCIPR_LPTIM2SEL_SHIFT 20timer__LDBL_MAX_EXP__ 1024RCC_CFGR_MCOPRE_DIV4 2LIBOPENCM3_MEMORYMAP_H RCC_CFGR_HPRE_MASK 0xfRCC_AHB2SMENR_AESSMEN (1 << 16)__DBL_HAS_DENORM__ 1sourceRCC_CIER_HSERDYIE (1 << 4)RCC_CR_MSIRDY (1 << 1)RCC_APB1RSTR1_OFFSET 0x38QUADSPI_BASE (0xa0001000U)__DA_FBIT__ 31RCC_CCIPR_I2CxSEL_MASK 0x3RCC_CCIPR_UART5SEL_SHIFT 8__GXX_ABI_VERSION 1017GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0c00)__INT_LEAST16_MAX__ 0x7fffRCC_CCIPR_ADCSEL_MASK 0x3__FLT_DENORM_MIN__ 1.4012984643248171e-45FRCC_PLLCFGR_PLLREN (1<<24)RCC_CIFR_HSIRDYF (1 << 3)RCC_CR_MSIRANGE_16MHZ 8INT_LEAST8_MAX __INT_LEAST8_MAX__RCC_CR_MSIRANGE_1MHZ 4rcc_osc_onRCC_APB1RSTR1_SPI2RST (1 << 14)RCC_CICR_PLLSAI1RDYC (1 << 6)__UINT32_C(c) c ## ULRCC_AHB1SMENR_SRAM1SMEN (1 << 9)__UACCUM_MIN__ 0.0UKUINT32_C(c) __UINT32_C(c)__FLT_EPSILON__ 1.1920928955078125e-7FRCC_PLLCFGR_PLLSRC_SHIFT 0TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)RCC_APB2RSTR_SAI1RST (1 << 21)RCC_AHB1SMENR_FLASHSMEN (1 << 8)__PTRDIFF_TYPE__ int__ARM_ARCH_ISA_THUMBRCC_CR_PLLSAI1ON (1 << 26)__UACCUM_EPSILON__ 0x1P-16UK__ARM_FEATURE_MATMUL_INT8RCC_AHB1ENR_DMA2EN (1 << 1)LIBOPENCM3_CM3_MEMORYMAP_H __GCC_ATOMIC_SHORT_LOCK_FREE 2rcc_set_pll_sourceRCC_CCIPR_UARTxSEL_MASK RCC_CCIPR_USARTxSEL_MASKRCC_AHB2SMENR_GPIOGSMEN (1 << 6)RCC_CCIPR_LPUART1SEL_SYS 1__USACCUM_FBIT__ 8RCC_BDCR_LSCOSEL (1 << 25)__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1RCC_APB1ENR1_USART2EN (1 << 17)cm3_assert(expr) do { if (CM3_LIKELY(expr)) { (void)0; } else { cm3_assert_failed(); } } while (0)RCC_APB1SMENR1_UART5SMEN (1 << 20)__LACCUM_FBIT__ 31SCS_BASE (PPBI_BASE + 0xE000)rcc_get_i2c_clk_freqRCC_APB2RSTR_USART1RST (1 << 14)SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)__FLT32_HAS_QUIET_NAN__ 1I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)RCC_APB2SMENR_SPI1SMEN (1 << 12)RCC_CSR_OBLRSTF (1 << 25)RCC_BDCR_LSECSSD (1 << 6)__LDBL_HAS_INFINITY__ 1RCC_CCIPR_LPUART1SEL_APB 0RCC_AHB2RSTR_GPIOERST (1 << 4)__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))__FLT32X_MAX_10_EXP__ 308DWT_BASE (PPBI_BASE + 0x1000)RCC_CCIPR_CLK48SEL_PLLSAI1Q 1RCC_CIER_HSIRDYIE (1 << 3)bool _BoolRCC_APB2ENR_TIM15EN (1 << 16)UINTMAX_MAX __UINTMAX_MAX__RCC_BDCR_RTCSEL_SHIFT 8__SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffRCC_CR_PLLSAI2ON (1 << 28)BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)INT16_MAX __INT16_MAX__RCC_APB1RSTR1_USART2RST (1 << 17)__FP_FAST_FMAF 1RCC_AHB3ENR_OFFSET 0x50__FLT32X_IS_IEC_60559__ 2RCC_APB1RSTR1_USART3RST (1 << 18)PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)RCC_CIER MMIO32(RCC_BASE + 0x18)LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))UINT32_MAXrcc_css_int_flag__INT_LEAST16_WIDTH__ 16__DEC_EVAL_METHOD__ 2RCC_PLLCFGR_PLLSRC_HSE 3__ARM_FEATURE_FP16_FMLRCC_CR_MSIRANGE_2MHZ 5RCC_AHB3ENR_FMCEN (1 << 0)RCC_CCIPR_I2CxSEL_APB 0__USFRACT_EPSILON__ 0x1P-8UHRRCC_APB2ENR_TIM8EN (1 << 13)__USFRACT_FBIT__ 8CORESIGHT_LSR_SLI (1<<0)RCC_APB1ENR1_LCDEN (1 << 9)RCC_CFGR_STOPWUCK_HSI16 (1 << 15)RCC_APB1RSTR1_UART5RST (1 << 20)__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX____ARM_ARCH_7EM__ 1__UINT32_MAX__ 0xffffffffULRCC_CCIPR_ADCSEL_SYS 3RCC_CFGR_HPRE_DIV16 0xb__INT_LEAST8_MAX__ 0x7frcc_osc_ready_int_flag__ARM_FEATURE_QBIT 1__ARM_FEATURE_CLZ 1RCC_HSE__ARM_FEATURE_COMPLEXRCC_AHB3ENR MMIO32(RCC_BASE + RCC_AHB3ENR_OFFSET)BIT15 (1<<15)RCC_ICSCR_HSICAL_MASK 0xffRCC_CFGR_SWS_MASK 0x3__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024RCC_CICR MMIO32(RCC_BASE + 0x20)__UINT_LEAST32_MAX__ 0xffffffffULRCC_MSIINT_FAST8_MIN (-INT_FAST8_MAX - 1)RCC_CFGR_PPRE2_DIV2 0x4RCC_APB2RSTR_OFFSET 0x40__INT_LEAST64_WIDTH__ 64INT_FAST64_MIN (-INT_FAST64_MAX - 1)__ACCUM_MAX__ 0X7FFFFFFFP-15KRCC_APB1RSTR2_SWPMI1RST (1 << 2)__INT8_MAX__ 0x7fBIT14 (1<<14)RCC_CCIPR_USART2SEL_SHIFT 2RCC_APB1RSTR1_TIM6RST (1 << 4)__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16RCC_CIER_PLLSAI2RDYIE (1 << 7)__SHRT_WIDTH__ 16BIT20 (1<<20)__ARM_FEATURE_MVERCC_CFGR_MCO_NOCLK 0x0__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intRCC_CFGR_HPRE_DIV512 0xfrcc_pll_output_enableRCC_APB1RSTR1_TIM4RST (1 << 2)SWPMI1_BASE (PERIPH_BASE_APB1 + 0x8800)UINT_LEAST16_MAX __UINT_LEAST16_MAX__rcc_css_int_clearRCC_CFGR_MCOPRE_DIV16 4__FLT_EVAL_METHOD_TS_18661_3__ 0RCC_CFGR_HPRE_DIV64 0xc__SCHAR_WIDTH__ 8BIT18 (1<<18)shiftSIZE_MAX__UINT_FAST8_TYPE__ unsigned intRCC_CIFR_LSERDYF (1 << 1)__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RRCC_CFGR_MCO_HSI16 0x3BIT24 (1<<24)RCC_PLLCFGR_PLLR_MASK 0x3RCC_CCIPR_I2CxSEL_SYS 1__INT32_MAX__ 0x7fffffffLRCC_APB1ENR1_UART4EN (1 << 19)RCC_PLLCFGR_PLLR_DIV8 3RCC_PLLCFGR_PLLQ_DIV6 2RCC_CFGR_HPRE_DIV256 0xeUINTMAX_MAXRCC_APB1SMENR1_UART4SMEN (1 << 19)BIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLLRCC_CFGR_SW_MASK 0x3__ARM_FEATURE_BF16_VECTOR_ARITHMETICINFO_BASE (0x1fff0000U)__FLT32_MANT_DIG__ 24INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32RCC_AHB2RSTR_GPIOCRST (1 << 2)__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN__RCC_CCIPR_LPUART1SEL_SHIFT 10INT8_MAX __INT8_MAX__RCC_CSR_LSIRDY (1 << 1)BIT28 (1<<28)RCC_BDCR_LSEDRV_MEDHIGH 2cm3_assert_failed__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2INTMAX_C(c) __INTMAX_C(c)RCC_CCIPR_USART1SEL_SYS 1RCC_AHB2SMENR_OFFSET 0x6c__DBL_MAX_EXP__ 1024RCC_AHB2RSTR_AESRST (1 << 16)__ATOMIC_RELEASE 3RCC_PLLCFGR_PLLP_DIV17 RCC_PLLCFGR_PLLPUINT_FAST8_MAX__FLT_MANT_DIG__ 24RCC_APB1ENR1_UART5EN (1 << 20)__UDQ_IBIT__ 0TIM1_BASE (PERIPH_BASE_APB2 + 0x2C00)RCC_CR_HSERDY (1 << 17)__OPTIMIZE_SIZE__ 1__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UKRCC_APB2ENR_SAI1EN (1 << 21)__FLT64_NORM_MAX__ 1.7976931348623157e+308F64RCC_APB1RSTR1_OPAMPRST (1 << 30)UINTPTR_MAX__LDBL_DENORM_MIN__ 4.9406564584124654e-324L__INT64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_SAT 1__ULLFRACT_IBIT__ 0__thumb__ 1RCC_CR_HSIASFS (1 << 11)rcc_wait_for_osc_readyRCC_AHB1ENR_TSCEN (1 << 16)MMIO16(addr) (*(volatile uint16_t *)(addr))RCC_APB2ENR_SPI1EN (1 << 12)AES_BASE (0x50000000U + 0x60000)RCC_CFGR_PPRE2_DIV8 0x6DAC_BASE (PERIPH_BASE_APB1 + 0x7400)__GNUC__ 12BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)WCHAR_MAXRCC_APB1ENR1_USART3EN (1 << 18)RCC_CCIPR_LPTIMxSEL_HSI16 2__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16RCC_CICR_LSIRDYC (1 << 0)__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0URCC_APB2SMENR_DFSDMSMEN (1 << 24)__UQQ_IBIT__ 0RCC_CFGR_SWS_SHIFT 2CORESIGHT_LSR_OFFSET 0xfb4__GCC_ATOMIC_LONG_LOCK_FREE 2rcc_is_osc_ready__LDBL_MAX__ 1.7976931348623157e+308L__ARM_ARCH 7UART4_BASE (PERIPH_BASE_APB1 + 0x4c00)__FLT_RADIX__ 2BIT3 (1<<3)long long intCORESIGHT_LAR_KEY 0xC5ACCE55rcc_css_enableRCC_CCIPR_USART3SEL_SHIFT 4__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAXrcc_apb1_frequencyRCC_AHB2ENR_ADCEN (1 << 13)__LDBL_HAS_QUIET_NAN__ 1RCC_AHB1SMENR_OFFSET 0x68__LONG_LONG_WIDTH__ 64BIT6 (1<<6)RCC_PLLCFGR_PLLN_SHIFT 0x8RCC_CFGR_MCOPRE_SHIFT 28RCC_APB1SMENR1_I2C1SMEN (1 << 21)RCC_CCIPR_LPUART1SEL_MASK 0x3__UINT_FAST64_MAX__ 0xffffffffffffffffULLRCC_APB1RSTR1_I2C3RST (1 << 23)__ARM_FP__HA_IBIT__ 8__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1ppre2BIT9 (1<<9)RCC_AHB2ENR_GPIOHEN (1 << 7)__FLT32X_MIN__ 2.2250738585072014e-308F32xclkselINTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024UINT16_MAXRCC_AHB2RSTR_OTGFSRST (1 << 12)__FLT64_MIN__ 2.2250738585072014e-308F64__INTMAX_C(c) c ## LLRCC_AHB3ENR_QSPIEN (1 << 8)RCC_APB1SMENR2 MMIO32(RCC_BASE + RCC_APB1SMENR2_OFFSET)RCC_CCIPR_USART1SEL_HSI16 2__ARM_ARCH_PROFILE__INT64_TYPE__ long long int__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4RCC_CCIPR_USARTxSEL_APB 0RCC_CR_HSION (1 << 8)RCC_CCIPR_LPTIMxSEL_MASK 0x3RCC_CR_HSIRDY (1 << 10)RCC_APB2SMENR_TIM1SMEN (1 << 11)CRS_BASE (PERIPH_BASE_APB1 + 0x6000)RCC_CCIPR_ADCSEL_PLLSAI1R 1__UFRACT_MAX__ 0XFFFFP-16URRCC_AHB1RSTR_OFFSET 0x28RCC_CR_HSEON (1 << 16)INT64_MAXFPB_BASE (PPBI_BASE + 0x2000)RCC_APB2RSTR_SAI2RST (1 << 22)RCC_CFGR_PPRE2_SHIFT 11RCC_CIFR_PLLSAI2RDYF (1 << 7)RCC_CICR_HSI48RDYC (1 << 10)__INT_LEAST32_MAX__ 0x7fffffffL__SFRACT_IBIT__ 0RCC_BDCR_RTCSEL_LSI 2RCC_CCIPR_USARTxSEL_LSE 3STIR_BASE (SCS_BASE + 0x0F00)RCC_CFGR_SWS_HSE 0x2__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__COMP_BASE (PERIPH_BASE_APB2 + 0x0200)TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)RCC_CSR_BORRSTF (1 << 27)ID_BASE (SCS_BASE + 0x0FD0)SYS_TICK_BASE (SCS_BASE + 0x0010)rcc_oscRCC_BDCR_LSEDRV_MEDLOW 1RCC_PLLCFGR_PLLSRC_HSI16 2RCC_CFGR_SWS_MSI 0x0__UFRACT_FBIT__ 16FMC_BASE (0xa0000000U)__UDQ_FBIT__ 64INT16_MIN (-INT16_MAX - 1)RCC_CCIPR_SAIxSEL_MASK 0x3__LDBL_MAX_10_EXP__ 308RCC_AHB2ENR_GPIOBEN (1 << 1)__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)__INT_FAST32_TYPE__ intRCC_CICR_HSERDYC (1 << 4)unsigned intRCC_CR_MSIRANGE_MASK 0xf__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1RCC_CSR_FWRSTF (1 << 24)__USACCUM_IBIT__ 8RCC_CIER_MSIRDYIE (1 << 2)ITM_BASE (PPBI_BASE + 0x0000)ST_VREFINT_CAL MMIO16((INFO_BASE + 0x75aa))__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6_STDBOOL_H RCC_APB1SMENR2_OFFSET 0x7crcc_system_clock_sourceRCC_CIFR_PLLSAI1RDYF (1 << 6)__FLT_EVAL_METHOD__ 0RCC_AHB3SMENR MMIO32(RCC_BASE + RCC_AHB3SMENR_OFFSET)__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32DFSDM_BASE (PERIPH_BASE_APB2 + 0x6000)RCC_AHB2ENR_GPIOCEN (1 << 2)RCC_BASE (PERIPH_BASE_AHB1 + 0x1000)__ARM_FEATURE_LDREX__UQQ_FBIT__ 8RCC_CFGR_HPRE_SHIFT 4__HQ_FBIT__ 15__ARM_FP16_ARGS__GCC_IEC_559 0RCC_CSR MMIO32(RCC_BASE + 0x94)INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX____LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4__STDC__ 1RCC_AHB2SMENR_RNGSMEN (1 << 18)RCC_CCIPR_CLK48SEL_PLL 2__ARM_FEATURE_IDIV 1RCC_APB2RSTR_SYSCFGRST (1 << 0)__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__rcc_set_rtc_clock_source__UINT8_TYPE__ unsigned charrcc_css_disable__ARM_FEATURE_COPROC 15RCC_AHB1SMENR_TSCSMEN (1 << 16)RCC_CICR_HSIRDYC (1 << 3)UINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"INT8_MINRCC_APB2ENR_DFSDMEN (1 << 24)RCC_PLLCFGR_PLLM_SHIFT 0x4RCC_APB1SMENR1_CAN1SMEN (1 << 25)LIBOPENCM3_RCC_H PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)RCC_AHB1ENR_OFFSET 0x48__ULLFRACT_MIN__ 0.0ULLR__FLT32X_MIN_EXP__ (-1021)RCC_BDCR_LSEON (1 << 0)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1RCC_CFGR_SW_PLL 0x3__GCC_ATOMIC_CHAR_LOCK_FREE 2RCC_AHB2ENR_OFFSET 0x4ccm3_assert_not_reached() cm3_assert_failed()__LFRACT_EPSILON__ 0x1P-31LRFMC1_BANK_BASE (0x60000000U)STM32L4 1RCC_PLLCFGR_PLLQ_MASK 0x3RCC_APB1SMENR1_TIM7SMEN (1 << 5)RCC_APB1SMENR1_OPAMPSMEN (1 << 30)__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX____FLT32X_NORM_MAX__ 1.7976931348623157e+308F32x__arm__ 1RCC_CR MMIO32(RCC_BASE + 0x00)RCC_CCIPR_LPTIMxSEL_APB 0__FLT32_MIN_10_EXP__ (-37)RCC_APB1RSTR2_LPTIM2RST (1 << 5)RCC_APB1ENR1_PWREN (1 << 28)MMIO64(addr) (*(volatile uint64_t *)(addr))__ARM_FP16_FORMAT_ALTERNATIVERCC_APB1SMENR1_TIM3SMEN (1 << 1)RCC_APB1RSTR1_LCDRST (1 << 9)__LDBL_NORM_MAX__ 1.7976931348623157e+308LRCC_PLLCFGR_PLLR_DIV4 1INTPTR_MINDESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)RCC_APB1ENR1_LPTIM1EN (1 << 31)RCC_CCIPR_LPTIMxSEL_LSE 3RCC_CFGR_PPRE2_NODIV 0x0__TA_IBIT__ 64RCC_APB1SMENR1_I2C3SMEN (1 << 23)RCC_LSERCC_AHB2SMENR_GPIOASMEN (1 << 0)RCC_APB1SMENR1_LCDSMEN (1 << 9)__ARM_FEATURE_QRDMXRCC_CFGR_HPRE_NODIV 0x0RCC_CCIPR_LPTIM1SEL_SHIFT 18RCC_APB1ENR1_I2C3EN (1 << 23)__ARM_ARCH_ISA_THUMB 2__LONG_LONG_MAX__ 0x7fffffffffffffffLLRCC_APB1RSTR1_PWRRST (1 << 28)RCC_APB1ENR2_OFFSET 0x5c__WINT_WIDTH__ 32SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__RCC_BDCR_RTCSEL_MASK 0x3RCC_HSI16BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1RCC_AHB2ENR_GPIOFEN (1 << 5)_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN____ULACCUM_MIN__ 0.0ULK__SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__DBL_MIN_EXP__ (-1021)RCC_APB1ENR1_TIM7EN (1 << 5)__LDBL_HAS_DENORM__ 1RCC_CFGR_PPRE1_DIV8 0x6RCC_AHB2RSTR_RNGRST (1 << 18)RCC_PLLCFGR_PLLM_MASK 0x7INT_FAST32_MIN (-INT_FAST32_MAX - 1)RCC_AHB2ENR MMIO32(RCC_BASE + RCC_AHB2ENR_OFFSET)__FLT32_DIG__ 6RCC_AHB3RSTR MMIO32(RCC_BASE + RCC_AHB3RSTR_OFFSET)INT_LEAST16_MAXRCC_APB2RSTR_SDMMC1RST (1 << 10)RCC_CCIPR_USARTxSEL_HSI16 2rcc_apb2_frequencyRCC_AHB2RSTR_OFFSET 0x2cFIREWALL_BASE (PERIPH_BASE_APB2 + 0x1C00)RCC_AHB2RSTR_GPIOBRST (1 << 1)VREFBUF_BASE (PERIPH_BASE_APB2 + 0x0030)BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)rcc_set_sysclk_sourceRCC_APB1ENR1_CAN1EN (1 << 25)RCC_APB2ENR_FWEN (1 << 7)__ACCUM_MIN__ (-0X1P15K-0X1P15K)RCC_ICSCR_MSITRIM_MASK 0xff__ARM_FEATURE_CRYPTO__INT_LEAST32_TYPE__ long intRCC_CFGR_HPRE_DIV4 0x9BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__FRACT_IBIT__ 0__ATOMIC_ACQUIRE 2RCC_CCIPR_USART1SEL_LSE 3UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234ADC1_BASE (0x50000000U + 0x40000)__FLT_NORM_MAX__ 3.4028234663852886e+38FRCC_CFGR_MCOPRE_DIV1 0long long unsigned int__FLT_MIN_10_EXP__ (-37)BIT31 (1<<31)__ULACCUM_IBIT__ 32RCC_CIER_LSERDYIE (1 << 1)__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__ULLACCUM_EPSILON__ 0x1P-32ULLK__APCS_32__ 1__DQ_FBIT__ 63INT_LEAST64_MAX__SACCUM_IBIT__ 8reg32_REG_BIT(base,bit) (((base) << 5) + (bit))__UHQ_IBIT__ 0TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)INT_LEAST8_MINRCC_AHB2ENR_AESEN (1 << 16)BIT29 (1<<29)RCC_APB1RSTR1_I2C2RST (1 << 22)__INT_FAST16_TYPE__ intRCC_APB1ENR1_DAC1EN (1 << 29)INT64_C__ULFRACT_MAX__ 0XFFFFFFFFP-32ULRRCC_CCIPR_I2C1SEL_SHIFT 12__UINT_LEAST16_TYPE__ short unsigned intRCC_APB1RSTR1_UART4RST (1 << 19)RCC_CCIPR_I2C3SEL_SHIFT 16__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned intRCC_CCIPR_USARTxSEL_SYS 1RCC_APB2SMENR_TIM17SMEN (1 << 18)__FLT32X_DIG__ 15RCC_CIFR_LSIRDYF (1 << 0)RCC_CFGR_PPRE2_MASK 0x7__UTQ_FBIT__ 128RCC_APB2ENR_TIM17EN (1 << 18)RCC_BDCR_LSCOEN (1 << 24)__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffffDMA2_BASE (PERIPH_BASE_AHB1 + 0x0400)PTRDIFF_MAX __PTRDIFF_MAX____SIZEOF_SHORT__ 2RCC_CFGR_SWS_HSI16 0x1RCC_CFGR_PPRE2_DIV16 0x7RCC_CR_PLLRDY (1 << 25)UINT_FAST16_MAX__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKRCC_CCIPR_SAIxSEL_PLL 2RCC_PLLCFGR_PLLM(x) ((x)-1)RCC_APB1ENR2 MMIO32(RCC_BASE + RCC_APB1ENR2_OFFSET)UINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRRCC_BDCR_RTCSEL_LSE 1RCC_APB1SMENR1_SPI2SMEN (1 << 14)__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intRCC_AHB2ENR_RNGEN (1 << 18)RCC_AHB2ENR_GPIOGEN (1 << 6)RCC_APB1RSTR1_TIM3RST (1 << 1)RCC_APB1ENR1_TIM4EN (1 << 2)RCC_APB1SMENR1_USART3SMEN (1 << 18)WCHAR_MINRCC_CRRCR MMIO32(RCC_BASE + 0x98)pllsrcBEGIN_DECLS rcc.cRCC_CFGR_PPRE2_DIV4 0x5RCC_AHB2RSTR_GPIOFRST (1 << 5)RCC_APB2RSTR_SPI1RST (1 << 12)RCC_CIFR_HSERDYF (1 << 4)RCC_APB1ENR1_TIM2EN (1 << 0)RCC_AHB1ENR_CRCEN (1 << 12)RCC_HSI48__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX__rcc_uart_i2c_clksel_freq_hz__FLT32X_MAX__ 1.7976931348623157e+308F32xGPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400)__ARM_EABI__ 1RCC_PLLCFGR_PLLQEN (1 << 20)INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1__ARM_FEATURE_DSP 1RCC_CR_MSIPLLEN (1 << 2)RCC_APB1SMENR1_DAC1SMEN (1 << 29)TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)__QQ_IBIT__ 0RCC_AHB2ENR_OTGFSEN (1 << 12)RCC_CR_MSIRANGE_100KHZ 0RCC_CCIPR_DFSDMSEL (1 << 31)RCC_CR_PLLON (1 << 24)__LLACCUM_FBIT__ 31RCC_APB2ENR MMIO32(RCC_BASE + RCC_APB2ENR_OFFSET)__UINTMAX_TYPE__ long long unsigned intLIBOPENCM3_RCC_COMMON_ALL_H DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 0x14)__USQ_IBIT__ 0RCC_ICSCR_HSICAL_SHIFT 16__UINT_LEAST32_TYPE__ long unsigned int__ARM_FEATURE_NUMERIC_MAXMIN__INTMAX_TYPE__ long long int__GCC_ATOMIC_INT_LOCK_FREE 2RCC_APB2RSTR_TIM17RST (1 << 18)RCC_APB1RSTR1_TIM5RST (1 << 3)rcc_disable_rtc_clockINTMAX_MAXRCC_APB1SMENR1_SPI3SMEN (1 << 15)DESIG_PACKAGE MMIO16((INFO_BASE + 0x7500))RCC_PLL__ARM_FEATURE_FP16_SCALAR_ARITHMETICRCC_CFGR_MCO_LSE 0x7__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1RCC_AHB3RSTR_QSPIRST (1 << 8)TIM17_BASE (PERIPH_BASE_APB2 + 0x4800)INT_FAST32_MIN__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_Cmsi_rangeDESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)RCC_PLLCFGR_PLLSRC_MSI 1RCC_PLLPEN (1 << 16)RCC_CCIPR_SAIxSEL_PLLSAI2P 1INT64_MINRCC_APB1RSTR1_LPTIM1RST (1 << 31)__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intRCC_CFGR_SW_MSI 0x0UINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRRCC_APB2ENR_OFFSET 0x60UINT16_C(c) __UINT16_C(c)RCC_PLLCFGR_PLLQ_DIV8 3/build/libopencm3/lib/stm32/l4__SIZEOF_SIZE_T__ 4RCC_APB1ENR1 MMIO32(RCC_BASE + RCC_APB1ENR1_OFFSET)__UINT64_TYPE__ long long unsigned intuint16_t__LDBL_MIN_10_EXP__ (-307)USART1_BASE (PERIPH_BASE_APB2 + 0x3800)USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x6800)RCC_APB2ENR_TIM16EN (1 << 17)RCC_ICSCR MMIO32(RCC_BASE + 0x04)TPIU_BASE (PPBI_BASE + 0x40000)__LDBL_MIN__ 2.2250738585072014e-308LRCC_CSR_WWDGRSTF (1 << 30)RCC_CCIPR_UART4SEL_SHIFT 6__ARM_FEATURE_CDE__ACCUM_IBIT__ 16RCC_CR_MSIRANGE_32MHZ 10RCC_AHB2ENR_GPIOAEN (1 << 0)CORESIGHT_LAR_OFFSET 0xfb0EXTI_BASE (PERIPH_BASE_APB2 + 0x0400)RCC_AHB1RSTR_DMA1RST (1 << 0)RCC_APB2RSTR MMIO32(RCC_BASE + RCC_APB2RSTR_OFFSET)FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000)short intRNG_BASE (0x50000000U + 0x60800)rcc_get_spi_clk_freqRCC_CSR_RESET_FLAGS (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF | RCC_CSR_IWDGRSTF | RCC_CSR_SFTRSTF | RCC_CSR_BORRSTF | RCC_CSR_PINRSTF | RCC_CSR_OBLRSTF | RCC_CSR_FWRSTF)RCC_CSR_LPWRRSTF (1 << 31)RCC_CSR_MSIRANGE_SHIFT 8__UINT16_C(c) c__UDA_IBIT__ 32__FLT_HAS_INFINITY__ 1RCC_PLLCFGR_PLLQ_SHIFT 21UINT_LEAST32_MAXRCC_PLLSAI2_CFGR MMIO32(RCC_BASE + 0x14)BIT2 (1<<2)RCC_PLLCFGR_PLLP (1 << 17)__ATOMIC_RELAXED 0__ARM_FEATURE_COPROCRCC_BDCR_LSEDRV_LOW 0RCC_CCIPR_CLK48SEL_MASK 0x3__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53RCC_CCIPR_UARTxSEL_SYS RCC_CCIPR_USARTxSEL_SYSBIT5 (1<<5)BIT1 (1<<1)INT8_CGPIO_PORT_H_BASE (PERIPH_BASE_AHB2 + 0x1c00)INT_LEAST32_MAX__ARM_ARCH_EXT_IDIV__ 1RCC_PLLCFGR_PLLR_SHIFT 25__DBL_DECIMAL_DIG__ 17RCC_CSR_MSIRANGE_2MHZ 5BIT8 (1<<8)RCC_CRRCR_HSI48ON (1 << 0)__ULACCUM_FBIT__ 32RCC_ICSCR_MSICAL_SHIFT 0INT16_C(c) __INT16_C(c)INT32_C(c) __INT32_C(c)RCC_APB1SMENR1_I2C2SMEN (1 << 22)__INT16_MAX__ 0x7fffRCC_APB1ENR1_TIM5EN (1 << 3)RCC_BDCR_LSEBYP (1 << 2)TIM15_BASE (PERIPH_BASE_APB2 + 0x4000)RCC_AHB2SMENR_GPIOFSMEN (1 << 5)RCC_CIFR_HSI48RDYF (1 << 10)__INT_WIDTH__ 32__ARM_FEATURE_SIMD32 1DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x75e0)RCC_APB1SMENR1_WWDGSMEN (1 << 11)RCC_CR_HSEBYP (1 << 18)__QQ_FBIT__ 7RCC_CR_PLLSAI2RDY (1 << 29)__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64INT16_CRCC_CFGR_PPRE1_SHIFT 8RCC_BDCR_BDRST (1 << 16)__UTA_IBIT__ 64__ULLACCUM_IBIT__ 32RCC_APB1RSTR1_TIM7RST (1 << 5)RCC_CICR_CSSC (1 << 8)__ULLFRACT_EPSILON__ 0x1P-64ULLRfalse 0__INT_LEAST64_TYPE__ long long int__SIZEOF_WINT_T__ 4RCC_APB1ENR1_I2C2EN (1 << 22)INT_LEAST64_MIN__ARM_FEATURE_UNALIGNED 1__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17RCC_CFGR_PPRE1_MASK 0x7__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1__FLT32X_HAS_DENORM__ 1__ULLACCUM_MIN__ 0.0ULLK__INT_FAST32_WIDTH__ 32rcc_set_hpreRCC_CR_MSIRANGE_200KHZ 1RCC_APB1RSTR1_SPI3RST (1 << 15)rcc_get_timer_clk_freqRCC_CCIPR_I2CxSEL_HSI16 2RCC_CCIPR_SWPMI1SEL (1 << 30)__ARM_ASM_SYNTAX_UNIFIED__ 1RCC_BDCR MMIO32(RCC_BASE + 0x90)RCC_APB2ENR_USART1EN (1 << 14)__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODRCC_APB1ENR1_SPI3EN (1 << 15)RCC_APB2SMENR_TIM16SMEN (1 << 17)RCC_CFGR_MCOPRE_DIV2 1__ARM_PCS_VFP 1RCC_AHB2RSTR_GPIODRST (1 << 3)LIBOPENCM3_CM3_ASSERT_H RCC_CCIPR_LPTIMxSEL_LSI 1RCC_CFGR_SW_HSI16 0x1rcc_osc_ready_int_disableRCC_CCIPR_SAI2SEL_SHIFT 24__USES_INITFINI__ 1__GCC_CONSTRUCTIVE_SIZE 64__LLFRACT_IBIT__ 0RCC_APB1SMENR2_SWPMI1SMEN (1 << 2)uint32_tRCC_AHB1SMENR_DMA2SMEN (1 << 1)BIT12 (1<<12)RCC_CFGR_HPRE_DIV128 0xdMPU_BASE (SCS_BASE + 0x0D90)__SACCUM_EPSILON__ 0x1P-7HKRCC_CFGR_PPRE1_DIV4 0x5__GCC_ASM_FLAG_OUTPUTS__ 1ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0x75a8))__ARM_FP 4LPTIM2_BASE (PERIPH_BASE_APB1 + 0x9400)RCC_CCIPR_ADCSEL_SHIFT 28USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6c00)__UINT_FAST16_TYPE__ unsigned int__UHA_IBIT__ 8RCC_CCIPR_CLK48SEL_MSI 3__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULK__LDBL_DIG__ 15POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXBIT16 (1<<16)__WINT_MIN__ 0UINT_LEAST16_MINRCC_AHB1SMENR MMIO32(RCC_BASE + RCC_AHB1SMENR_OFFSET)__FLT64_DIG__ 15RCC_APB2ENR_TIM1EN (1 << 11)__WINT_MAX__ 0xffffffffUBIT22 (1<<22)__INT_LEAST8_WIDTH__ 8RCC_APB1RSTR2 MMIO32(RCC_BASE + RCC_APB1RSTR2_OFFSET)WWDG_BASE (PERIPH_BASE_APB1 + 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%Ó$2Ô§Ő?yÖ‹×%4Ř]}Ů_1ÚĘ^Ű,.áî`âę‘oëăCě—í[[î(ďCIđscń×ňĺ8ó©ôť6őç„ö˝{÷·/řŃXů¸yúŚ<ű’müË=ýýgţâ†?X„+<…˙‹~ ŚćLŤÚ0ŽrmŹÂ‰‘k-’Ł‰“ô”ż„•<^—M'˘ÄDŁ3i¤jĄG¦ĹŻÄg°Ic±=H˛1kł08´ŕgµ\¶ş·‰¸ĆąĹOşrĂŃJÄß7Ń°YŇjÓ«cÔ`XŐĽ_ÖÜZ×EzŘô|ŮCÚÁ?Ű˛EÜÁ2ÝÉ|Ţx$ßÉ8ŕŮ\á!âvZăhäřFĺ”Wî€ďÖđgJúAKű·(ü¨TýUeţ§q˙&5€ä f8‚–h„¦…Ú_†~‹ÝTŚPŤ0Žů0ŹY~p”ÚS•4–0—^yZ&™ĽšD2›Öwś‡ťŞ$žę=źÔ UZ¤©Ą‚©ŞUW«Űj¬PwU®!ZŻWw°ŮH±çq˛5@ł9h´$µăm¶Zg·gx¸`Bą4WşŰ»iĽ]˝•]ľ°JÂ[Ă-~ÄĂaČ—FÉ#eĘíËŐdĚŰ>ÍőÎ˘OĎ ĐŠŃ$LŇ'ÓŇ×kŘ|Ú×‡ŰŃÜŠÝÂ9ŢŞ.ß5áśâ¶4ăćUäŇĺGućÓrčÝéjoę«fëx„ěoOíĚ}îćđ XńÔ%ňŇEóĐYôďKő,öżZřú7ůŹ?úř{űŻeüUdý$ţ1 € 4e2‚§9„űH…~1‡ĆK»d‰]^ŠŻM‹Ĺ†ŚJ+ŤúuŽĐŹy >f‘z{’0r“ůG”p<•p—Ŕ+á™%KšßG›pś … jˇÉ˘—yŁ0!ĄK¦Dg§™M¨‡©`5ŞUj¬áŘ3®ś(°1u±ŃN˛Bł …´5,µţ…·–w¸‚ą2V˝)}ľp9żř%Ŕ¶ÁÉCÂ+Ăľ3ÄÄPĹ¦ŠĆsĎĐvYŃähŇčvÓÔ~×ßAŘË$éÚbcű ../common/usr/lib/gcc/arm-none-eabi/12.2.1/include../../../include/libopencm3/stm32/l4../../../include/libopencm3/stm32../../../include/libopencm3/cm3../../../include/libopencm3/stm32/commonrcc_common_all.cstdint.hrcc.hrcc.hcommon.hstdbool.hmemorymap.hmemorymap.hmemorymap.hrcc_common_all.h. /Ĺ =Űó†X. ./”X. .=ŁX. ./ =˛ÁĎ.E.."ŕZ .=%<LţZ .=%<L1“1= "!0 0rcc_periph_clock_enableRCC_CICR_PLLRDYC (1 << 5)RCC_SWPMI1__UHA_FBIT__ 8USB_OTG_FS_BASE (0x50000000U + 0x00000)RCC_APB2SMENR MMIO32(RCC_BASE + RCC_APB2SMENR_OFFSET)RST_SWPMI1__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64RCC_OTGFSCORESIGHT_LSR_SLK (1<<1)__GCC_ATOMIC_WCHAR_T_LOCK_FREE 2LCD_BASE (PERIPH_BASE_APB1 + 0x2400)__CHAR_UNSIGNED__ 1CORESIGHT_LAR_KEY 0xC5ACCE55USART3_BASE (PERIPH_BASE_APB1 + 0x4800)RCC_AHB2RSTR_GPIOHRST (1 << 7)RCC_AHB2ENR_GPIOCEN (1 << 2)RCC_CFGR_MCO_MSI 0x2RCC_QSPIRCC_USB__FLT64_HAS_INFINITY__ 1rcc_periph_reset_pulse__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GCC_DESTRUCTIVE_SIZE 64__LACCUM_EPSILON__ 0x1P-31LKRCC_CIFR_LSECSSF (1 << 9)__PTRDIFF_MAX__ 0x7fffffffRCC_CR_PLLSAI1RDY (1 << 27)__INTMAX_C(c) c ## LLRCC_CR_MSIRANGE_800KHZ 3RCC_AHB3RSTR_FMCRST (1 << 0)__INTMAX_MAX__ 0x7fffffffffffffffLLMMIO8(addr) (*(volatile uint8_t *)(addr))RST_CAN1__TQ_IBIT__ 0rcc_periph_clken__FLT64_DECIMAL_DIG__ 17WINT_MIN __WINT_MIN__INT_FAST64_MAXOPAMP_BASE (PERIPH_BASE_APB1 + 0x7800)__ATOMIC_CONSUME 1__ULACCUM_FBIT__ 32__WCHAR_MAX__ 0xffffffffURCC_APB1SMENR1_PWRSMEN (1 << 28)RCC_PLLCFGR_PLLR_DIV6 2RCC_AHB2ENR_GPIODEN (1 << 3)RCC_APB2ENR_SDMMC1EN (1 << 10)RCC_AHB1ENR_DMA1EN (1 << 0)RCC_CCIPR_USART1SEL_SYS 1RCC_UART4signed charINT64_MAX __INT64_MAX__INTMAX_MIN__SIZEOF_LONG_LONG__ 8__DBL_MAX_10_EXP__ 308__FRACT_MIN__ (-0.5R-0.5R)__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLKRCC_APB1RSTR1_UART4RST (1 << 19)__USACCUM_MAX__ 0XFFFFP-8UHK__SFRACT_FBIT__ 7__INTMAX_WIDTH__ 64__ARM_FEATURE_BF16_SCALAR_ARITHMETIC__SQ_IBIT__ 0rcc_periph_rst__SIZE_TYPE__ unsigned intRCC_AHB1ENR_FLASHEN (1 << 8)RCC_AHB2SMENR_GPIOESMEN (1 << 4)__FLT_HAS_DENORM__ 1__INT8_TYPE__ signed char__ARM_ARCH_PROFILE 77RCC_APB2SMENR_SAI1SMEN (1 << 21)__USACCUM_MIN__ 0.0UHKGPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000)__FLT32_DECIMAL_DIG__ 9RCC_BDCR_LSCOSEL (1 << 25)__DECIMAL_DIG__ 17__LDBL_MIN_EXP__ (-1021)INT_FAST16_MIN__LDBL_MANT_DIG__ 53SCC_SDMMC1INT64_MIN (-INT64_MAX - 1)BIT6 (1<<6)RCC_CFGR_STOPWUCK_MSI (0 << 15)RCC_APB2SMENR_SDMMC1SMEN (1 << 10)__UINT8_C(c) c__INT16_TYPE__ short intRCC_APB1RSTR1 MMIO32(RCC_BASE + RCC_APB1RSTR1_OFFSET)__FLT64_MAX__ 1.7976931348623157e+308F64RCC_CCIPR_ADCSEL_PLLSAI1R 1UINT8_C(c) __UINT8_C(c)UINT_FAST32_MAXRCC_CFGR_MCO_HSE 0x4RCC_CIER_LSIRDYIE (1 << 0)RCC_APB1RSTR2_OFFSET 0x3cRCC_PLLCFGR_PLLSRC_NONE 0RCC_CCIPR_UARTxSEL_LSE RCC_CCIPR_USARTxSEL_LSEINT_FAST64_MAX __INT_FAST64_MAX__RCC_CR_MSION (1 << 0)__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1__STDC_HOSTED__ 1__ULLFRACT_FBIT__ 64__SIG_ATOMIC_TYPE__ intrcc_peripheral_enable_clockRCC_PLLSAI1_CFGR MMIO32(RCC_BASE + 0x10)RCC_CIFR_CSSF (1 << 8)__INT_FAST64_TYPE__ long long int__WINT_TYPE__ unsigned intGPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800)ST_TSENSE_CAL2_110C MMIO16((INFO_BASE + 0x75ca))RCC_CFGR_MCO_PLL 0x5INT32_MIN (-INT32_MAX - 1)__FLT32_MAX_10_EXP__ 38RCC_CSR_MSIRANGE_MASK 0xfRCC_CFGR_HPRE_DIV8 0xaRCC_CIFR_PLLSAI1RDYF (1 << 6)RCC_APB2SMENR_SYSCFGSMEN (1 << 0)RCC_APB2RSTR_SPI1RST (1 << 12)__USFRACT_MAX__ 0XFFP-8UHRLPTIM1_BASE (PERIPH_BASE_APB1 + 0x7c00)__FP_FAST_FMAF32 1RCC_APB1SMENR1_TIM5SMEN (1 << 3)__UINTPTR_MAX__ 0xffffffffU__FLT32_MIN_EXP__ (-125)RCC_CR_MSIRANGE_4MHZ 6RCC_APB1ENR2_SWPMI1EN (1 << 2)RCC_APB2SMENR_TIM15SMEN (1 << 16)UINT32_MAX __UINT32_MAX__RCC_CCIPR_I2C1SEL_SHIFT 12__DBL_EPSILON__ ((double)2.2204460492503131e-16L)RCC_APB2RSTR_DFSDMRST (1 << 24)RCC_AHB1ENR MMIO32(RCC_BASE + RCC_AHB1ENR_OFFSET)__ULFRACT_FBIT__ 32RCC_APB2ENR_USART1EN (1 << 14)__FLT64_MIN_10_EXP__ (-307)RCC_APB1SMENR1_LPTIM1SMEN (1 << 31)__GNUC_EXECUTION_CHARSET_NAME "UTF-8"RCC_CIFR MMIO32(RCC_BASE + 0x1c)BIT10 (1<<10)__INT_FAST64_WIDTH__ 64__STDC_VERSION__ 199901Lrcc_peripheral_disable_clockRCC_CCIPR_SAI1SEL_SHIFT 22RCC_CFGR_MCOPRE_DIV8 3__SFRACT_EPSILON__ 0x1P-7HR__INT32_C(c) c ## LRCC_SYSCFG__ORDER_BIG_ENDIAN__ 4321SIZE_MAXSYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000)__UINTPTR_TYPE__ unsigned int__SQ_FBIT__ 31RST_SYSCFGDWT_BASE (PPBI_BASE + 0x1000)INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)RCC_CR_MSIRGSEL (1 << 3)SCC_SAI1SCC_SAI2_RCC_REG(i) MMIO32(RCC_BASE + ((i) >> 5))__UHQ_FBIT__ 16RCC_APB1ENR2_LPTIM2EN (1 << 5)__FLT64_MIN_EXP__ (-1021)RCC_AHB1RSTR_CRCRST (1 << 12)ITM_BASE (PPBI_BASE + 0x0000)clear_resetRCC_DFSDMLIBOPENCM3_RCC_H INT8_C(c) __INT8_C(c)__UINT_FAST8_MAX__ 0xffffffffURCC_CFGR_PPRE1_DIV2 0x4RCC_APB1ENR1_OPAMPEN (1 << 30)UINT16_C(c) __UINT16_C(c)__LACCUM_IBIT__ 32RCC_CSR_SFTRSTF (1 << 28)RCC_CCIPR_UARTxSEL_HSI16 RCC_CCIPR_USARTxSEL_HSI16__INT_FAST16_WIDTH__ 32INTMAX_CRCC_CCIPR_I2C2SEL_SHIFT 14__VFP_FP__ 1RCC_ICSCR_MSITRIM_SHIFT 8__LLFRACT_MIN__ (-0.5LLR-0.5LLR)INT_FAST8_MAXCOMP_BASE (PERIPH_BASE_APB2 + 0x0200)__UINT_FAST16_MAX__ 0xffffffffURCC_APB1SMENR1_TIM6SMEN (1 << 4)RCC_CFGR_PPRE2_DIV2 0x4__INTPTR_MAX__ 0x7fffffffINT64_C(c) __INT64_C(c)RCC_CIER_LSE_CSSIE (1 << 9)BIT21 (1<<21)RCC_CCIPR_USART1SEL_SHIFT 0SCC_SPI1SCC_SPI2SCC_SPI3__UFRACT_MIN__ 0.0URRCC_AHB2SMENR_GPIOHSMEN (1 << 7)RCC_CFGR_SWS_PLL 0x3RCC_CFGR_MCO_SHIFT 24WCHAR_MAX __WCHAR_MAX__RCC_APB2SMENR_TIM8SMEN (1 << 13)__FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX__RCC_CSR_MSIRANGE_4MHZ 6__UINT_LEAST8_TYPE__ unsigned charRCC_AHB2ENR_GPIOEEN (1 << 4)RCC_APB1RSTR1_I2C1RST (1 << 21)RCC_PWRRCC_APB1RSTR2_LPUART1RST (1 << 0)__ACCUM_FBIT__ 15PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)__UACCUM_IBIT__ 16long intUINT8_MAXIWDG_BASE (PERIPH_BASE_APB1 + 0x3000)SIZE_MAX __SIZE_MAX__RCC_CICR_PLLSAI2RDYC (1 << 7)__INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17CORESIGHT_LAR_OFFSET 0xfb0__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1RCC_SAI1RST_LCD__FLT32X_EPSILON__ 2.2204460492503131e-16F32xRCC_ICSCR_MSICAL_MASK 0xffRCC_CCIPR_SAIxSEL_PLLSAI1P 0NVIC_BASE (SCS_BASE + 0x0100)__INT_FAST8_TYPE__ intSCC_FLASH__UDA_FBIT__ 32USART2_BASE (PERIPH_BASE_APB1 + 0x4400)__FLT64_MAX_10_EXP__ 308RCC_APB2SMENR_SPI1SMEN (1 << 12)__UINTMAX_C(c) c ## ULLRCC_PLLCFGR_PLLN_MASK 0x7f__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed charRCC_AHB1RSTR MMIO32(RCC_BASE + RCC_AHB1RSTR_OFFSET)RCC_AHB1ENR_DMA2EN (1 << 1)__GCC_ATOMIC_BOOL_LOCK_FREE 2__GCC_HAVE_DWARF2_CFI_ASM 1BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON____FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX____THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRRCC_APB1SMENR1_TIM4SMEN (1 << 2)RCC_CSR_MSIRANGE_8MHZ 7RCC_PLLCFGR_PLLP_DIV17 RCC_PLLCFGR_PLLPshort unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)__GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"UINT_FAST8_MAX __UINT_FAST8_MAX____FLT32X_MIN_10_EXP__ (-307)UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICRCC_SPI2LIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)RCC_CFGR_MCOPRE_SHIFT 28__DBL_IS_IEC_60559__ 2__UINT_FAST32_MAX__ 0xffffffffURCC_AHB3ENR_OFFSET 0x50__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4I2C3_BASE (PERIPH_BASE_APB1 + 0x5c00)RCC_APB2RSTR_TIM15RST (1 << 16)RCC_AHB2SMENR_ADCSMEN (1 << 13)RCC_AHB1SMENR_CRCSMEN (1 << 12)RCC_AHB1SMENR_DMA1SMEN (1 << 0)RCC_CCIPR_LPUART1SEL_HSI16 2__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32RST_CRCRCC_CICR_LSECSSC (1 << 9)DMA1_BASE (PERIPH_BASE_AHB1 + 0x0000)PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)RCC_BDCR_RTCSEL_NONE 0RCC_CIER_PLLSAI1RDYIE (1 << 6)SCC_CAN1GNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsRCC_AHB2SMENR_AESSMEN (1 << 16)BIT27 (1<<27)SCC_PWRRCC_LPUART1RST_CRSRCC_APB2ENR_SYSCFGEN (1 << 0)RCC_CCIPR_CLK48SEL_HSI48 0__UTA_FBIT__ 64INTMAX_C(c) __INTMAX_C(c)RCC_BDCR_LSESYSDIS (1 << 7)RCC_CIFR_MSIRDYF (1 << 2)__FLT_DECIMAL_DIG__ 9RCC_CRRCR_HSI48RDY (1 << 1)LIBOPENCM3_MEMORYMAP_COMMON_H RCC_LSI__INT_LEAST32_MAX__ 0x7fffffffL__VERSION__ "12.2.1 20221205"RCC_APB1ENR1_OFFSET 0x58uint8_tINT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)INT32_C(c) __INT32_C(c)__GNUC_STDC_INLINE__ 1__INT64_C(c) c ## LL__FRACT_FBIT__ 15__FLT_HAS_QUIET_NAN__ 1__GNUC_PATCHLEVEL__ 1__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2RCC_PLLCFGR_PLLP (1 << 17)PTRDIFF_MINRCC_TIM5__UINT_LEAST16_MAX__ 0xffffRCC_TIM6RCC_APB1SMENR1_OFFSET 0x78RCC_TIM7UINTPTR_MAX __UINTPTR_MAX__RCC_BDCR_RTCEN (1 << 15)__LACCUM_FBIT__ 31INT32_MAXRCC_AHB3SMENR_OFFSET 0x70GPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000)RCC_APB1ENR1_TIM6EN (1 << 4)__FLT_DIG__ 6GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400)rcc_set_mcoWINT_MINRCC_PLLCFGR_PLLR_DIV2 0RCC_ICSCR_HSITRIM_MASK 0x1fSDMMC1_BASE (PERIPH_BASE_APB2 + 0x2800)__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)__FRACT_MAX__ 0X7FFFP-15R__GCC_IEC_559 0TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)INT_LEAST32_MAX __INT_LEAST32_MAX__RCC_CIER_LSERDYIE (1 << 1)SCC_DMA1RCC_SDMMC1__INT_FAST32_MAX__ 0x7fffffffRCC_CAN1RCC_APB1SMENR1_USART2SMEN (1 << 17)RCC_PLLCFGR_PLLSRC_HSE 3RCC_CIER_PLLRDYIE (1 << 5)RST_SDMMC1__DQ_IBIT__ 0RCC_APB1ENR1_SPI2EN (1 << 14)RCC_CFGR_SW_HSE 0x2RCC_AHB2SMENR_GPIODSMEN (1 << 3)RCC_CSR_LSION (1 << 0)RCC_CR_MSIRANGE_SHIFT 4__UINT16_MAX__ 0xffff__TQ_FBIT__ 127RCC_AHB2RSTR_ADCRST (1 << 13)LPUART1_BASE (PERIPH_BASE_APB1 + 0x8000)RCC_RNGRCC_AHB2SMENR MMIO32(RCC_BASE + RCC_AHB2SMENR_OFFSET)__USES_INITFINI__ 1RCC_CRRCR_HSI48ON (1 << 0)RCC_CCIPR_LPTIMxSEL_LSI 1WCHAR_MAXRCC_CSR_IWDGRSTF (1 << 29)__SIZEOF_SHORT__ 2__ULLACCUM_FBIT__ 32FMC_QUADSPI_BASE (0xA0000000U)RCC_AHB2SMENR_SRAM2SMEN (1 << 9)USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6c00)RCC_APB1ENR2 MMIO32(RCC_BASE + RCC_APB1ENR2_OFFSET)RST_SPI1INT_FAST32_MIN (-INT_FAST32_MAX - 1)RCC_CFGR_MCO_MASK 0xf__STRICT_ANSI__ 1RST_SPI3RCC_CR_HSION (1 << 8)RCC_APB2RSTR_SYSCFGRST (1 << 0)FMC3_BANK_BASE (0x80000000U)UINT_LEAST8_MAXRST_DMA1RST_DMA2__SIZEOF_LONG_DOUBLE__ 8CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)TIM8_BASE (PERIPH_BASE_APB2 + 0x3400)RCC_APB1RSTR1_CAN1RST (1 << 25)__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__RCC_AHB1RSTR_DMA2RST (1 << 1)RCC_BDCR_LSECSSON (1 << 5)RCC_APB2ENR_SAI2EN (1 << 22)__USA_IBIT__ 16__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1DBGMCU_BASE (PPBI_BASE + 0x00042000)PTRDIFF_MIN (-PTRDIFF_MAX - 1)UART5_BASE (PERIPH_BASE_APB1 + 0x5000)RCC_CFGR_SWS_HSI16 0x1__UINT_FAST64_TYPE__ long long unsigned intPERIPH_BASE_AHB2 (0x48000000U)RCC_CR_MSIRANGE_8MHZ 7DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7590)__FLT_MIN__ 1.1754943508222875e-38FTIM17_BASE (PERIPH_BASE_APB2 + 0x4800)__HA_FBIT__ 7RCC_CFGR_MCO_HSI48 0x8__FDPIC__RST_GPIOARCC_GPIOARST_GPIOCRCC_GPIOCRST_GPIOERCC_GPIOERCC_GPIOFRCC_GPIOGGPIO_PORT_G_BASE (PERIPH_BASE_AHB2 + 0x1800)RCC_CSR_PINRSTF (1 << 26)INT_FAST64_MIN__USFRACT_IBIT__ 0RCC_CCIPR_UARTxSEL_APB RCC_CCIPR_USARTxSEL_APBRCC_CIER_HSI48RDYIE (1 << 10)__LDBL_EPSILON__ 2.2204460492503131e-16LRCC_CCIPR_USART1SEL_APB 0RCC_AHB1RSTR_FLASHRST (1 << 8)__USFRACT_MIN__ 0.0UHRTSC_BASE (PERIPH_BASE_AHB1 + 0x4000)RCC_BDCR_LSEDRV_SHIFT 3__ARM_NEONRCC_PLLCFGR_PLLQ_DIV2 0__UINT8_MAX__ 0xffRCC_CCIPR_LPTIM2SEL_SHIFT 20__LDBL_MAX_EXP__ 1024SCC_LPTIM1SCC_LPTIM2LIBOPENCM3_MEMORYMAP_H RCC_CFGR_HPRE_MASK 0xfRCC_CR_MSIRANGE_400KHZ 2SCC_RNGBIT7 (1<<7)__DBL_HAS_DENORM__ 1DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)RCC_APB2RSTR_USART1RST (1 << 14)RCC_CIER_HSERDYIE (1 << 4)RCC_CR_MSIRDY (1 << 1)RCC_APB1RSTR1_OFFSET 0x38QUADSPI_BASE (0xa0001000U)__DA_FBIT__ 31RCC_ICSCR_MSITRIM_MASK 0xffBIT17 (1<<17)RCC_AHB2RSTR_GPIOARST (1 << 0)__GXX_ABI_VERSION 1017GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0c00)__INT_LEAST16_MAX__ 0x7fffRCC_CCIPR_ADCSEL_MASK 0x3__FLT_DENORM_MIN__ 1.4012984643248171e-45F__LDBL_MAX__ 1.7976931348623157e+308LRCC_PLLCFGR_PLLREN (1<<24)RCC_CIFR_HSIRDYF (1 << 3)RST_GPIOFRST_RNGRCC_CR_MSIRANGE_16MHZ 8RST_GPIOHINT_LEAST8_MAX __INT_LEAST8_MAX__RCC_CR_MSIRANGE_1MHZ 4RCC_APB1RSTR1_SPI2RST (1 << 14)RCC_CICR_PLLSAI1RDYC (1 << 6)__UINT32_C(c) c ## ULRCC_AHB1SMENR_SRAM1SMEN (1 << 9)RCC_CFGR_MCOPRE_DIV4 2__UACCUM_MIN__ 0.0UKUINT32_C(c) __UINT32_C(c)__FLT_EPSILON__ 1.1920928955078125e-7FRCC_PLLCFGR_PLLSRC_SHIFT 0TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)RCC_APB2RSTR_SAI1RST (1 << 21)RCC_AHB1SMENR_FLASHSMEN (1 << 8)__PTRDIFF_TYPE__ int__ARM_ARCH_ISA_THUMBRCC_CR_PLLSAI1ON (1 << 26)RCC_AHB2RSTR_GPIOCRST (1 << 2)RCC_CCIPR_LPUART1SEL_SHIFT 10__ARM_FEATURE_MATMUL_INT8RCC_CFGR_PPRE2_NODIV 0x0RCC_CICR_MSIRDYC (1 << 2)LIBOPENCM3_CM3_MEMORYMAP_H __GCC_ATOMIC_SHORT_LOCK_FREE 2RCC_AHB2RSTR_OTGFSRST (1 << 12)RCC_AHB2SMENR_GPIOGSMEN (1 << 6)RCC_CCIPR_LPUART1SEL_SYS 1__USACCUM_FBIT__ 8RST_GPIOB__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1RCC_APB1ENR1_USART2EN (1 << 17)SCC_DAC1__ELF__ 1SCS_BASE (PPBI_BASE + 0xE000)RCC_CFGR_STOPWUCK_HSI16 (1 << 15)RCC_CICR_LSERDYC (1 << 1)SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)__FLT32_HAS_QUIET_NAN__ 1I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)RST_GPIOGRCC_CSR_OBLRSTF (1 << 25)RCC_BDCR_LSECSSD (1 << 6)__LDBL_HAS_INFINITY__ 1RCC_CCIPR_LPUART1SEL_APB 0RCC_AHB2RSTR_GPIOERST (1 << 4)__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__RCC_LSE_RCC_REG__FLT32X_MAX_10_EXP__ 308__INT_FAST16_MAX__ 0x7fffffffRCC_CCIPR_CLK48SEL_PLLSAI1Q 1RCC_CIER_HSIRDYIE (1 << 3)bool _BoolRST_DFSDMRCC_CRCRCC_CCIPR_ADCSEL_SHIFT 28RCC_APB2ENR_TIM15EN (1 << 16)UINTMAX_MAX __UINTMAX_MAX__RCC_BDCR_RTCSEL_SHIFT 8__SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffBIT13 (1<<13)BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)SCC_TIM1INT16_MAX __INT16_MAX__SCC_TIM3__FP_FAST_FMAF 1SCC_TIM5SCC_TIM6SCC_TIM7SCC_TIM8__FLT32X_IS_IEC_60559__ 2RCC_APB1RSTR1_USART3RST (1 << 18)PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)RST_AESRCC_APB2RSTR_OFFSET 0x40RST_GPIODLIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))UINT32_MAXRCC_OPAMPRST_OTGFS__INT_LEAST16_WIDTH__ 16SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)SCC_CRC__ARM_FEATURE_FP16_FMLRCC_CR_MSIRANGE_2MHZ 5RCC_AHB3ENR_FMCEN (1 << 0)RCC_CCIPR_I2CxSEL_APB 0__USFRACT_EPSILON__ 0x1P-8UHRRCC_AHB2ENR_GPIOHEN (1 << 7)RCC_PLLCFGR_PLLSRC_MSI 1RCC_APB2ENR_TIM8EN (1 << 13)RCC_DAC1__USFRACT_FBIT__ 8__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLKRCC_APB1ENR1_LCDEN (1 << 9)RCC_APB1RSTR1_UART5RST (1 << 20)__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX__RCC_CSR_WWDGRSTF (1 << 30)__UINT32_MAX__ 0xffffffffULRCC_CCIPR_LPUART1SEL_LSE 3RCC_CCIPR_ADCSEL_SYS 3RCC_CFGR_HPRE_DIV16 0xb__INT_LEAST8_MAX__ 0x7f__GCC_ATOMIC_POINTER_LOCK_FREE 2__ARM_FEATURE_QBIT 1__ARM_FEATURE_CLZ 1__ARM_FEATURE_FMA 1__ARM_FEATURE_COMPLEXRCC_AHB3ENR MMIO32(RCC_BASE + RCC_AHB3ENR_OFFSET)RCC_CICR MMIO32(RCC_BASE + 0x20)RCC_ICSCR_HSICAL_MASK 0xffRCC_CFGR_SWS_MASK 0x3__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024RST_TIM16SCC_GPIOHRST_TIM17RCC_TIM1RCC_TIM2RCC_TIM3RCC_TIM4RCC_MSIINT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)RCC_TIM8__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1RCC_CR_MSIRANGE_48MHZ 11__ACCUM_MAX__ 0X7FFFFFFFP-15KRCC_APB1RSTR2_SWPMI1RST (1 << 2)__INT8_MAX__ 0x7fRST_I2C2RST_I2C3RCC_CCIPR_USART2SEL_SHIFT 2RCC_APB1RSTR1_TIM6RST (1 << 4)SCC_WWDG__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16RCC_CIER_PLLSAI2RDYIE (1 << 7)__SHRT_WIDTH__ 16__GCC_IEC_559_COMPLEX 0__ARM_FEATURE_MVERCC_CFGR_MCO_NOCLK 0x0__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intRCC_CFGR_HPRE_DIV64 0xcRCC_APB1RSTR1_TIM4RST (1 << 2)RCC_AHB2SMENR_GPIOCSMEN (1 << 2)SWPMI1_BASE (PERIPH_BASE_APB1 + 0x8800)UINT_LEAST16_MAX __UINT_LEAST16_MAX__INT_FAST32_MIN__FLT_EVAL_METHOD_TS_18661_3__ 0RCC_APB1ENR2_OFFSET 0x5cSCC_ADC1__SCHAR_WIDTH__ 8BIT18 (1<<18)UINT_FAST16_MAXRCC_APB2SMENR_TIM16SMEN (1 << 17)__UINT_FAST8_TYPE__ unsigned intRCC_CIFR_LSERDYF (1 << 1)__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RBIT24 (1<<24)RCC_PLLCFGR_PLLR_MASK 0x3RCC_CCIPR_I2CxSEL_SYS 1__INT32_MAX__ 0x7fffffffLRCC_APB1ENR1_UART4EN (1 << 19)RCC_PLLCFGR_PLLR_DIV8 3RCC_PLLCFGR_PLLQ_DIV6 2RCC_CFGR_HPRE_DIV256 0xeUINTMAX_MAXRCC_APB1SMENR1_UART4SMEN (1 << 19)BIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLLRCC_CFGR_SW_MASK 0x3__ARM_FEATURE_BF16_VECTOR_ARITHMETICINFO_BASE (0x1fff0000U)PPBI_BASE (0xE0000000U)__FLT32_MANT_DIG__ 24INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32rcc_osc_bypass_enable__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN__SCC_GPIOBINT8_MAX __INT8_MAX__RCC_CSR_LSIRDY (1 << 1)BIT28 (1<<28)RCC_BDCR_LSEDRV_MEDHIGH 2RCC_PLLPEN (1 << 16)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2SCC_GPIOFRCC_APB1SMENR1_LCDSMEN (1 << 9)RCC_AHB2SMENR_OFFSET 0x6c__DBL_MAX_EXP__ 1024RCC_AHB2RSTR_AESRST (1 << 16)__ATOMIC_RELEASE 3SCC_TIM2UINT_FAST8_MAX__FLT_MANT_DIG__ 24RCC_APB1ENR1_UART5EN (1 << 20)__UDQ_IBIT__ 0TIM1_BASE (PERIPH_BASE_APB2 + 0x2C00)RCC_CR_HSERDY (1 << 17)__OPTIMIZE_SIZE__ 1__OPTIMIZE__ 1__FLT64_NORM_MAX__ 1.7976931348623157e+308F64RCC_CSR_BORRSTF (1 << 27)RCC_APB1RSTR1_OPAMPRST (1 << 30)UINTPTR_MAXRCC_CIFR_PLLRDYF (1 << 5)__LDBL_DENORM_MIN__ 4.9406564584124654e-324LRCC_ADC1__INT64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_SAT 1__ULLFRACT_IBIT__ 0RCC_CR_HSIASFS (1 << 11)RCC_AHB1ENR_TSCEN (1 << 16)_RCC_BITMMIO16(addr) (*(volatile uint16_t *)(addr))RCC_LPTIM1RCC_LPTIM2AES_BASE (0x50000000U + 0x60000)RCC_CFGR_PPRE2_DIV8 0x6DAC_BASE (PERIPH_BASE_APB1 + 0x7400)__GNUC__ 12RST_LPTIM1RST_LPTIM2mcosrcRCC_APB1ENR1_USART3EN (1 << 18)RCC_CCIPR_LPTIMxSEL_HSI16 2__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16RCC_CICR_LSIRDYC (1 << 0)__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0URCC_APB2SMENR_DFSDMSMEN (1 << 24)__UQQ_IBIT__ 0RCC_CFGR_SWS_SHIFT 2CORESIGHT_LSR_OFFSET 0xfb4RCC_APB1ENR1_TIM3EN (1 << 1)__GCC_ATOMIC_LONG_LOCK_FREE 2__ULACCUM_MIN__ 0.0ULK__INT_MAX__ 0x7fffffff__ARM_ARCH 7UART4_BASE (PERIPH_BASE_APB1 + 0x4c00)__FLT_RADIX__ 2BIT3 (1<<3)long long intTPIU_BASE (PPBI_BASE + 0x40000)RCC_CCIPR_USART1SEL_LSE 3RCC_CCIPR_USART3SEL_SHIFT 4__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAXRCC_AHB2ENR_ADCEN (1 << 13)SCC_GPIOA__LDBL_HAS_QUIET_NAN__ 1SCC_GPIOCSCC_GPIODSCC_GPIOE__LONG_LONG_WIDTH__ 64SCC_GPIOGRST_UART4RST_UART5RCC_UART5RCC_APB1SMENR1_I2C1SMEN (1 << 21)RCC_CCIPR_LPUART1SEL_MASK 0x3__UINT_FAST64_MAX__ 0xffffffffffffffffULLRCC_APB1RSTR1_I2C3RST (1 << 23)__ARM_FP__HA_IBIT__ 8__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1RCC_CFGR_MCOPRE_MASK 0x7BIT9 (1<<9)RCC_CFGR_HPRE_DIV512 0xf__FLT32X_MIN__ 2.2250738585072014e-308F32xINTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024RCC_FWUINT16_MAXBIT20 (1<<20)RCC_APB1ENR2_LPUART1EN (1 << 0)__FLT64_MIN__ 2.2250738585072014e-308F64RCC_APB1SMENR1_TIM2SMEN (1 << 0)RCC_AHB3ENR_QSPIEN (1 << 8)RCC_APB1SMENR2 MMIO32(RCC_BASE + RCC_APB1SMENR2_OFFSET)RCC_CCIPR_USART1SEL_HSI16 2RCC_APB2ENR_DFSDMEN (1 << 24)__ARM_ARCH_PROFILE__INT64_TYPE__ long long int__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4RCC_CCIPR_USARTxSEL_APB 0__USQ_IBIT__ 0RCC_CCIPR_LPTIMxSEL_MASK 0x3RCC_CR_HSIRDY (1 << 10)RCC_APB2SMENR_TIM1SMEN (1 << 11)CRS_BASE (PERIPH_BASE_APB1 + 0x6000)RCC_AES__UFRACT_MAX__ 0XFFFFP-16URRCC_AHB1RSTR_OFFSET 0x28RCC_CR_HSEON (1 << 16)INT64_MAXFPB_BASE (PPBI_BASE + 0x2000)RCC_APB2RSTR_SAI2RST (1 << 22)UINTMAX_CRCC_CFGR_PPRE2_SHIFT 11RCC_CIFR_PLLSAI2RDYF (1 << 7)RCC_CICR_HSI48RDYC (1 << 10)INT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0RCC_BDCR_RTCSEL_LSI 2RCC_CCIPR_USARTxSEL_LSE 3SCC_DFSDMSTIR_BASE (SCS_BASE + 0x0F00)SCC_ADC__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)RST_QSPIRST_TIM15RCC_TIM15RCC_TIM16RCC_TIM17SYS_TICK_BASE (SCS_BASE + 0x0010)rcc_oscRCC_BDCR_LSEDRV_MEDLOW 1RCC_PLLCFGR_PLLSRC_HSI16 2RCC_CFGR_SWS_MSI 0x0__UFRACT_FBIT__ 16FMC_BASE (0xa0000000U)__UDQ_FBIT__ 64INT16_MIN (-INT16_MAX - 1)RCC_CCIPR_SAIxSEL_MASK 0x3__LDBL_MAX_10_EXP__ 308RCC_APB2SMENR_USART1SMEN (1 << 14)RCC_AHB2ENR_GPIOBEN (1 << 1)__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)reset__INT_FAST32_TYPE__ intRCC_CICR_HSERDYC (1 << 4)__ATOMIC_SEQ_CST 5RCC_CR_MSIRANGE_MASK 0xf../common/rcc_common_all.c__FLT_MIN_EXP__ (-125)__DEC_EVAL_METHOD__ 2RCC_CSR_FWRSTF (1 << 24)__USACCUM_IBIT__ 8RCC_CIER_MSIRDYIE (1 << 2)__ARM_ARCH_7EM__ 1ST_VREFINT_CAL MMIO16((INFO_BASE + 0x75aa))__FLT64_HAS_DENORM__ 1__ULLACCUM_IBIT__ 32__UACCUM_EPSILON__ 0x1P-16UK__UTA_IBIT__ 64SCB_BASE (SCS_BASE + 0x0D00)__FLT_EVAL_METHOD__ 0RCC_AHB3SMENR MMIO32(RCC_BASE + RCC_AHB3SMENR_OFFSET)unsigned int__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32DFSDM_BASE (PERIPH_BASE_APB2 + 0x6000)RCC_CR_PLLON (1 << 24)RCC_BASE (PERIPH_BASE_AHB1 + 0x1000)__ARM_FEATURE_LDREXSCC_AES__UQQ_FBIT__ 8RCC_CFGR_HPRE_SHIFT 4INT16_C__ARM_FP16_ARGS__UACCUM_MAX__ 0XFFFFFFFFP-16UKRCC_CSR MMIO32(RCC_BASE + 0x94)INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX____LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4__STDC__ 1RCC_AHB2SMENR_RNGSMEN (1 << 18)SCC_OPAMPRCC_AHB3RSTR_OFFSET 0x30__ARM_FEATURE_IDIV 1SCC_OTGFS__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__WINT_MAXrcc_periph_clock_disable__UINT8_TYPE__ unsigned charRCC_APB2ENR_SAI1EN (1 << 21)__ARM_FEATURE_COPROC 15RCC_AHB1SMENR_TSCSMEN (1 << 16)RCC_CICR_HSIRDYC (1 << 3)UINT64_MAX __UINT64_MAX__false 0INT8_MIN__ORDER_PDP_ENDIAN__ 3412RCC_PLLCFGR_PLLM_SHIFT 0x4RCC_APB1SMENR1_CAN1SMEN (1 << 25)PERIPH_BASE (0x40000000U)true 1__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)RCC_CCIPR_CLK48SEL_PLL 2RCC_AHB1ENR_OFFSET 0x48__FLT32X_MIN_EXP__ (-1021)RCC_BDCR_LSEON (1 << 0)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)RCC_CFGR_SW_PLL 0x3__GCC_ATOMIC_CHAR_LOCK_FREE 2RCC_AHB2ENR_OFFSET 0x4cRCC_CR_PLLSAI2ON (1 << 28)__LFRACT_EPSILON__ 0x1P-31LRFMC1_BANK_BASE (0x60000000U)STM32L4 1RCC_PLLCFGR_PLLQ_MASK 0x3RCC_APB1SMENR1_TIM7SMEN (1 << 5)RCC_APB1SMENR1_OPAMPSMEN (1 << 30)__ARM_SIZEOF_MINIMAL_ENUM 1RCC_APB1ENR1_TIM2EN (1 << 0)__FLT32X_NORM_MAX__ 1.7976931348623157e+308F32x__arm__ 1RCC_CR MMIO32(RCC_BASE + 0x00)RCC_CCIPR_LPTIMxSEL_APB 0__FLT32_MIN_10_EXP__ (-37)RCC_APB1RSTR2_LPTIM2RST (1 << 5)RCC_APB1ENR1_PWREN (1 << 28)MMIO64(addr) (*(volatile uint64_t *)(addr))__ARM_FP16_FORMAT_ALTERNATIVERCC_GPIOBRCC_APB1RSTR1_LCDRST (1 << 9)__LDBL_NORM_MAX__ 1.7976931348623157e+308LRCC_PLLCFGR_PLLR_DIV4 1RCC_GPIODRST_FMCDESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)RCC_CSR_MSIRANGE_SHIFT 8__BIGGEST_ALIGNMENT__ 8RCC_SPI1RCC_APB1ENR1_LPTIM1EN (1 << 31)RCC_CCIPR_LPTIMxSEL_LSE 3RCC_GPIOHRCC_SPI3INT_LEAST64_MAX __INT_LEAST64_MAX__RCC_APB1SMENR1_I2C3SMEN (1 << 23)__SACCUM_IBIT__ 8RCC_AHB2SMENR_GPIOASMEN (1 << 0)RCC_APB1ENR1_TIM5EN (1 << 3)__ARM_FEATURE_QRDMXRCC_CFGR_HPRE_NODIV 0x0RCC_CCIPR_LPTIM1SEL_SHIFT 18RCC_APB1ENR1_I2C3EN (1 << 23)__ARM_ARCH_ISA_THUMB 2RCC_APB1SMENR2_LPTIM2SMEN (1 << 5)__LONG_LONG_MAX__ 0x7fffffffffffffffLLRCC_APB1RSTR1_PWRRST (1 << 28)BIT14 (1<<14)__WINT_WIDTH__ 32SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__RCC_CRSRST_TSCRCC_HSI16BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1RCC_AHB2ENR_GPIOFEN (1 << 5)_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN____SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__DBL_MIN_EXP__ (-1021)RCC_APB1ENR1_TIM7EN (1 << 5)RCC_APB1SMENR2_OFFSET 0x7cRCC_CFGR_PPRE1_DIV8 0x6RCC_AHB2RSTR_RNGRST (1 << 18)RCC_PLLCFGR_PLLM_MASK 0x7INT8_MIN (-INT8_MAX - 1)rcc_peripheral_clear_resetRCC_APB1SMENR1_TIM3SMEN (1 << 1)RCC_AHB2ENR MMIO32(RCC_BASE + RCC_AHB2ENR_OFFSET)__FLT32_DIG__ 6RCC_AHB3RSTR MMIO32(RCC_BASE + RCC_AHB3RSTR_OFFSET)INT_LEAST16_MAXRCC_APB2RSTR_SDMMC1RST (1 << 10)RCC_CCIPR_USARTxSEL_HSI16 2BIT15 (1<<15)RCC_AHB2RSTR_OFFSET 0x2cFIREWALL_BASE (PERIPH_BASE_APB2 + 0x1C00)RCC_AHB2RSTR_GPIOBRST (1 << 1)VREFBUF_BASE (PERIPH_BASE_APB2 + 0x0030)__LDBL_HAS_DENORM__ 1__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)RST_SAI2RCC_APB1ENR1_CAN1EN (1 << 25)RCC_APB2ENR_FWEN (1 << 7)__ACCUM_MIN__ (-0X1P15K-0X1P15K)RCC_LCDRCC_CIER MMIO32(RCC_BASE + 0x18)__ARM_FEATURE_CRYPTO__INT_LEAST32_TYPE__ long intRCC_CFGR_HPRE_DIV4 0x9BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULLRST_SAI1__FRACT_IBIT__ 0__ATOMIC_ACQUIRE 2RCC_AHB3RSTR_QSPIRST (1 << 8)UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234ADC1_BASE (0x50000000U + 0x40000)__FLT_NORM_MAX__ 3.4028234663852886e+38FRCC_CFGR_MCOPRE_DIV1 0RCC_APB1SMENR2_LPUART1SMEN (1 << 0)long long unsigned intSCC_DMA2__FLT_MIN_10_EXP__ (-37)BIT31 (1<<31)__ULACCUM_IBIT__ 32RCC_CFGR_SWS_HSE 0x2__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__ULLACCUM_EPSILON__ 0x1P-32ULLK__APCS_32__ 1__DQ_FBIT__ 63INT_LEAST64_MAXuint16_t_REG_BIT(base,bit) (((base) << 5) + (bit))__UHQ_IBIT__ 0TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)INT_LEAST8_MINRCC_AHB2ENR_AESEN (1 << 16)BIT29 (1<<29)RCC_APB1RSTR1_I2C2RST (1 << 22)__INT_FAST16_TYPE__ intRCC_APB1ENR1_DAC1EN (1 << 29)__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)__ULFRACT_MAX__ 0XFFFFFFFFP-32ULRRST_SPI2__UINT_LEAST16_TYPE__ short unsigned intrcc_periph_reset_holdRCC_CCIPR_I2C3SEL_SHIFT 16__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned intRCC_CCIPR_USARTxSEL_SYS 1RCC_APB2SMENR_TIM17SMEN (1 << 18)__FLT32X_DIG__ 15RCC_CIFR_LSIRDYF (1 << 0)RCC_APB2SMENR_SAI2SMEN (1 << 22)__UTQ_FBIT__ 128RCC_APB2ENR_TIM17EN (1 << 18)__LLACCUM_EPSILON__ 0x1P-31LLK__FINITE_MATH_ONLY__ 0clkenRCC_CCIPR_I2CxSEL_MASK 0x3DMA2_BASE (PERIPH_BASE_AHB1 + 0x0400)PTRDIFF_MAX __PTRDIFF_MAX__rcc_periph_reset_releaseRCC_CFGR_PPRE2_DIV16 0x7RCC_CCIPR_UARTxSEL_MASK RCC_CCIPR_USARTxSEL_MASKRCC_CR_PLLRDY (1 << 25)SCC_LCDRCC_HSESCC_UART4SCC_UART5RCC_CCIPR_SAIxSEL_PLL 2RCC_PLLCFGR_PLLM(x) ((x)-1)__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKUINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRRCC_BDCR_RTCSEL_LSE 1RCC_APB1SMENR1_SPI2SMEN (1 << 14)RCC_DMA1RCC_DMA2__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intRCC_AHB2ENR_RNGEN (1 << 18)RCC_AHB2ENR_GPIOGEN (1 << 6)RCC_APB1RSTR1_TIM3RST (1 << 1)RCC_APB1ENR1_TIM4EN (1 << 2)RCC_APB1SMENR1_USART3SMEN (1 << 18)WCHAR_MINRCC_CRRCR MMIO32(RCC_BASE + 0x98)BEGIN_DECLS RCC_APB2ENR_SPI1EN (1 << 12)RCC_CFGR_PPRE1_DIV16 0x7RCC_CFGR_PPRE2_DIV4 0x5RCC_CSR_MSIRANGE_1MHZ 4RST_TIM2div_valRCC_CIFR_HSERDYF (1 << 4)RST_LPUART1RCC_AHB1ENR_CRCEN (1 << 12)RCC_HSI48__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__LLFRACT_EPSILON__ 0x1P-63LLR__FLT32X_MAX__ 1.7976931348623157e+308F32xGPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400)__FLT32_MIN__ 1.1754943508222875e-38F32RCC_PLLCFGR_PLLQEN (1 << 20)RCC_BDCR_RTCSEL_MASK 0x3INT16_MININTPTR_MIN__FLT_IS_IEC_60559__ 2__THUMBEL__ 1__ARM_FEATURE_DSP 1rcc_osc_bypass_disableRST_ADCRCC_APB1SMENR1_DAC1SMEN (1 << 29)TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)__QQ_IBIT__ 0RCC_AHB2ENR_OTGFSEN (1 << 12)RCC_CR_MSIRANGE_100KHZ 0_RCC_BIT(i) (1 << ((i) & 0x1f))RCC_CCIPR_DFSDMSEL (1 << 31)SCC_TIM15SCC_TIM16SCC_TIM17__LLACCUM_FBIT__ 31RCC_APB2ENR MMIO32(RCC_BASE + RCC_APB2ENR_OFFSET)__UINTMAX_TYPE__ long long unsigned intLIBOPENCM3_RCC_COMMON_ALL_H DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 0x14)__GNUC_MINOR__ 2RCC_ICSCR_HSICAL_SHIFT 16__UINT_LEAST32_TYPE__ long unsigned intRCC_AHB1RSTR_TSCRST (1 << 16)__ARM_FEATURE_NUMERIC_MAXMINTIM4_BASE (PERIPH_BASE_APB1 + 0x0800)__INTMAX_TYPE__ long long int__GCC_ATOMIC_INT_LOCK_FREE 2RCC_APB2RSTR_TIM17RST (1 << 18)RCC_APB1RSTR1_TIM5RST (1 << 3)TIM16_BASE (PERIPH_BASE_APB2 + 0x4400)INTMAX_MAXRCC_APB1SMENR1_SPI3SMEN (1 << 15)rcc_peripheral_resetID_BASE (SCS_BASE + 0x0FD0)DESIG_PACKAGE MMIO16((INFO_BASE + 0x7500))RCC_PLL__ARM_FEATURE_FP16_SCALAR_ARITHMETICRCC_CFGR_MCO_LSE 0x7__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1UINT_FAST64_MAX __UINT_FAST64_MAX____FLT64_HAS_QUIET_NAN__ 1__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CSCC_USART1SCC_USART2SCC_USART3RCC_CCIPR_SAIxSEL_PLLSAI2P 1INT64_MINRCC_APB1RSTR1_LPTIM1RST (1 << 31)__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_CRCC_FMCRCC_CFGR_SW_MSI 0x0UINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRRCC_APB2ENR_OFFSET 0x60RCC_PLLCFGR_PLLQ_DIV8 3/build/libopencm3/lib/stm32/l4__SIZEOF_SIZE_T__ 4RCC_APB1ENR1 MMIO32(RCC_BASE + RCC_APB1ENR1_OFFSET)__UINT64_TYPE__ long long unsigned int__LDBL_MIN_10_EXP__ (-307)USART1_BASE (PERIPH_BASE_APB2 + 0x3800)USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x6800)RCC_APB2ENR_TIM16EN (1 << 17)RCC_ICSCR MMIO32(RCC_BASE + 0x04)RCC_APB1SMENR1_UART5SMEN (1 << 20)__LDBL_MIN__ 2.2250738585072014e-308LRCC_CCIPR_UART4SEL_SHIFT 6__ARM_FEATURE_CDE__ACCUM_IBIT__ 16RCC_CR_MSIRANGE_32MHZ 10RCC_AHB2ENR_GPIOAEN (1 << 0)RCC_TSCEXTI_BASE (PERIPH_BASE_APB2 + 0x0400)RCC_CCIPR_CLK48SEL_SHIFT 26RCC_AHB1RSTR_DMA1RST (1 << 0)RCC_APB2RSTR MMIO32(RCC_BASE + RCC_APB2RSTR_OFFSET)SCC_LPUART1FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000)short intRNG_BASE (0x50000000U + 0x60800)RCC_CSR_RESET_FLAGS (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF | RCC_CSR_IWDGRSTF | RCC_CSR_SFTRSTF | RCC_CSR_BORRSTF | RCC_CSR_PINRSTF | RCC_CSR_OBLRSTF | RCC_CSR_FWRSTF)__FLT32_IS_IEC_60559__ 2RST_OPAMP__UINT16_C(c) c__UDA_IBIT__ 32SCC_SWPMI1RCC_PLLCFGR_PLLQ_SHIFT 21UINT_LEAST32_MAXRCC_PLLSAI2_CFGR MMIO32(RCC_BASE + 0x14)BIT2 (1<<2)INT64_C__ATOMIC_RELAXED 0__ARM_FEATURE_COPROCRCC_BDCR_LSEDRV_LOW 0RCC_CCIPR_CLK48SEL_MASK 0x3__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53RCC_CCIPR_UARTxSEL_SYS RCC_CCIPR_USARTxSEL_SYSCORESIGHT_LSR_SLI (1<<0)BIT5 (1<<5)BIT1 (1<<1)INT8_CGPIO_PORT_H_BASE (PERIPH_BASE_AHB2 + 0x1c00)INT_LEAST32_MAX__ARM_ARCH_EXT_IDIV__ 1SCC_I2C1SCC_I2C2SCC_I2C3__DBL_DECIMAL_DIG__ 17RCC_CSR_MSIRANGE_2MHZ 5BIT8 (1<<8)RST_TIM7SCC_FMCRST_TIM8RCC_ICSCR_MSICAL_SHIFT 0INT16_C(c) __INT16_C(c)RCC_APB1SMENR1_I2C2SMEN (1 << 22)__INT16_MAX__ 0x7fffRST_USBRCC_BDCR_LSEBYP (1 << 2)TIM15_BASE (PERIPH_BASE_APB2 + 0x4000)RCC_AHB2SMENR_GPIOFSMEN (1 << 5)RCC_CIFR_HSI48RDYF (1 << 10)__INT_WIDTH__ 32__ARM_FEATURE_SIMD32 1DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x75e0)RCC_APB1SMENR1_WWDGSMEN (1 << 11)RCC_CR_HSEBYP (1 << 18)SCC_SYSCFG__QQ_FBIT__ 7RCC_CR_PLLSAI2RDY (1 << 29)RTC_BASE (PERIPH_BASE_APB1 + 0x2800)__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64RCC_AHB2RSTR_GPIOGRST (1 << 6)RCC_AHB2SMENR_OTGFSSMEN (1 << 12)RCC_CFGR_PPRE1_SHIFT 8RCC_BDCR_BDRST (1 << 16)SCC_TSCRCC_APB1RSTR1_TIM7RST (1 << 5)RCC_CICR_CSSC (1 << 8)__ULLFRACT_EPSILON__ 0x1P-64ULLR__UINT_LEAST32_MAX__ 0xffffffffUL__SIZEOF_WINT_T__ 4RCC_APB1ENR1_I2C2EN (1 << 22)__ARM_FEATURE_UNALIGNED 1__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17RCC_CFGR_PPRE1_MASK 0x7__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1RCC_USART1__FLT32X_HAS_DENORM__ 1__ULLACCUM_MIN__ 0.0ULLK__INT_FAST32_WIDTH__ 32RCC_CCIPR_UART5SEL_SHIFT 8__TA_IBIT__ 64RCC_CR_MSIRANGE_200KHZ 1RCC_APB1RSTR1_SPI3RST (1 << 15)RCC_I2C1RCC_I2C2RCC_I2C3RCC_CCIPR_I2CxSEL_HSI16 2RCC_CCIPR_SWPMI1SEL (1 << 30)__ARM_ASM_SYNTAX_UNIFIED__ 1RCC_BDCR MMIO32(RCC_BASE + 0x90)SCC_TIM4__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODRCC_APB1ENR1_SPI3EN (1 << 15)__thumb2__ 1RCC_APB1ENR1_I2C1EN (1 << 21)RCC_CFGR_MCOPRE_DIV2 1RCC_CSR_LPWRRSTF (1 << 31)__ARM_PCS_VFP 1RST_I2C1RCC_AHB2RSTR_GPIODRST (1 << 3)__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H RCC_CFGR_SW_HSI16 0x1__PTRDIFF_WIDTH__ 32RCC_CCIPR_SAI2SEL_SHIFT 24INT_LEAST64_MIN__GCC_CONSTRUCTIVE_SIZE 64RCC_ADC__LLFRACT_IBIT__ 0RCC_APB1SMENR2_SWPMI1SMEN (1 << 2)uint32_tRCC_AHB1SMENR_DMA2SMEN (1 << 1)BIT12 (1<<12)RCC_CFGR_HPRE_DIV128 0xdMPU_BASE (SCS_BASE + 0x0D90)__SACCUM_EPSILON__ 0x1P-7HKRCC_CFGR_PPRE1_DIV4 0x5__GCC_ASM_FLAG_OUTPUTS__ 1RST_DAC1ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0x75a8))__ARM_FP 4LPTIM2_BASE (PERIPH_BASE_APB1 + 0x9400)BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)__UINT_FAST16_TYPE__ unsigned int__UHA_IBIT__ 8RCC_CCIPR_CLK48SEL_MSI 3__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULK__LDBL_DIG__ 15POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXRCC_AHB1SMENR_OFFSET 0x68BIT16 (1<<16)__WINT_MIN__ 0UINT_LEAST16_MINRCC_AHB1SMENR MMIO32(RCC_BASE + RCC_AHB1SMENR_OFFSET)__FLT64_DIG__ 15RCC_APB2ENR_TIM1EN (1 << 11)__WINT_MAX__ 0xffffffffUBIT22 (1<<22)__INT_LEAST8_WIDTH__ 8RCC_APB1RSTR2 MMIO32(RCC_BASE + RCC_APB1RSTR2_OFFSET)WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)RCC_AHB2SMENR_GPIOBSMEN (1 << 1)__INT_LEAST16_TYPE__ short intRCC_AHB3SMENR_FMCSMEN (1 << 0)RCC_PLLCFGR MMIO32(RCC_BASE + 0x0c)__DBL_MAX__ ((double)1.7976931348623157e+308L)RCC_ICSCR_HSITRIM_SHIFT 24INT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1RST_TIM1__thumb__ 1RST_TIM3RST_TIM4RST_TIM5RST_TIM6INT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1RST_FLASHRCC_FLASH__HQ_FBIT__ 15__bool_true_false_are_defined 1RCC_BDCR_LSERDY (1 << 1)BIT26 (1<<26)RCC_AHB3SMENR_QSPISMEN (1 << 8)RCC_BDCR_LSCOEN (1 << 24)__SIZE_MAX__ 0xffffffffUSPI2_BASE (PERIPH_BASE_APB1 + 0x3800)RCC_CR_MSIPLLEN (1 << 2)RCC_PLLCFGR_PLLR_SHIFT 25RCC_CFGR_PPRE2_MASK 0x7__ARM_ARCHRCC_CCIPR_SAIxSEL_EXT 3__LONG_MAX__ 0x7fffffffLrcc_get_div_from_hpreRCC_APB2RSTR_TIM1RST (1 << 11)RCC_SAI2RCC_APB1RSTR1_USART2RST (1 << 17)RCC_BDCR_LSEDRV_HIGH 3RCC_CCIPR_USART1SEL_MASK 0x3SAI2_BASE (PERIPH_BASE_APB2 + 0x5800)RCC_AHB2RSTR MMIO32(RCC_BASE + RCC_AHB2RSTR_OFFSET)RCC_CFGR_PPRE1_NODIV 0x0__ARM_FEATURE_LDREX 7PTRDIFF_MAXMMIO32(addr) (*(volatile uint32_t *)(addr))RCC_BDCR_LSEDRV_MASK 0x3RCC_CCIPR MMIO32(RCC_BASE + 0x88)RCC_PLLCFGR_PLLP_DIV7 0RCC_PLLCFGR_PLLN_SHIFT 0x8__USQ_FBIT__ 32RCC_CR_HSIKERON (1 << 9)__SFRACT_MAX__ 0X7FP-7HR__FLT32X_MANT_DIG__ 53RCC_CCIPR_USARTxSEL_MASK 0x3RCC_APB1RSTR1_TIM2RST (1 << 0)__WCHAR_WIDTH__ 32RCC_BDCR_RTCSEL_HSEDIV32 3RCC_CFGR_MCO_LSI 0x6SCC_SRAM1SCC_SRAM2__INT16_C(c) cSAI1_BASE (PERIPH_BASE_APB2 + 0x5400)INT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32RCC_USART2RCC_USART3RCC_CCIPR_ADCSEL_NONE 0SCC_QSPIRST_USART1RST_USART2RST_USART3__ATOMIC_ACQ_REL 4RCC_CR_MSIRANGE_24MHZ 9__HQ_IBIT__ 0__DBL_MIN_10_EXP__ (-307)RCC_CFGR_MCO_HSI16 0x3RCC_CFGR_SW_SHIFT 0RCC_APB1RSTR1_DAC1RST (1 << 29)RCC_CR_CSSON (1 << 19)RST_PWRRCC_PLLCFGR_PLLSRC_MASK 0x3__FLT32_NORM_MAX__ 3.4028234663852886e+38F32RCC_APB1SMENR1 MMIO32(RCC_BASE + RCC_APB1SMENR1_OFFSET)RCC_APB2SMENR_OFFSET 0x80RCC_CFGR_MCO_SYSCLK 0x1UINT64_C(c) __UINT64_C(c)RCC_APB2RSTR_TIM8RST (1 << 13)RCC_APB2RSTR_TIM16RST (1 << 17)__UINTMAX_MAX__ 0xffffffffffffffffULLRCC_CCIPR_ADCSEL_PLLSAI2R 2__DBL_MANT_DIG__ 53RCC_CFGR_HPRE_DIV2 0x8__ULFRACT_IBIT__ 0RCC_PLLCFGR_PLLQ_DIV4 1INT_FAST16_MAXITR_BASE (SCS_BASE + 0x0000)RCC_CSR_RMVF (1 << 23)QUADSPI_BANK_BASE (0x90000000U)__ARM_EABI__ 1__INT_LEAST64_TYPE__ long long intRCC_AHB2RSTR_GPIOFRST (1 << 5)RCC_CFGR MMIO32(RCC_BASE + 0x08)__ARM_FEATURE_CDE_COPROCRST_ADC1UINT32_CRCC_CFGR_MCOPRE_DIV16 4GCC: (15:12.2.rel1-1) 12.2.1 20221205˙˙˙˙| ",,A3aeabi)7E-M M "ń˙ (( "$68&(*,.024:?pˇÓ8l9<š¶ Óč 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int__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1rtc_set_pm_formatRTC_TR_MNT_SHIFT (12)__USACCUM_IBIT__ 8RTC_TR_PM (1 << 22)rtc_unlockITM_BASE (PPBI_BASE + 0x0000)RTC_TAFCR_TAMPPRCH_4RTC (0x2)ST_VREFINT_CAL MMIO16((INFO_BASE + 0x75aa))RTC_TAFCR_TAMPFREQ_RTCDIV8K (0x2)__FLT64_HAS_DENORM__ 1__ULLACCUM_IBIT__ 32__UACCUM_EPSILON__ 0x1P-16UKRTC_TAFCR_TAMPPRCH_SHIFT (13)__UTA_IBIT__ 64__FLT_EVAL_METHOD__ 0__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32RTC_ISR_TSF (1<<11)RCC_BASE (PERIPH_BASE_AHB1 + 0x1000)__ARM_FEATURE_LDREX__UQQ_FBIT__ 8INT16_C__ARM_FP16_ARGS__GCC_IEC_559 0rtc_clear_wakeup_flagINT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX____LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4__STDC__ 1__ARM_FEATURE_IDIV 1__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN____UINT8_TYPE__ unsigned charRTC_TAFCR_TAMP1E (1<<0)RTC_ISR_ALRAF (1<<8)__ARM_FEATURE_COPROC 15RTC_CR_ALRAE (1<<8)UINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"INT8_MINRTC_DR_YU_SHIFT (16)PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)__LDBL_MIN_10_EXP__ (-307)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__GCC_ATOMIC_CHAR_LOCK_FREE 2__LFRACT_EPSILON__ 0x1P-31LRFMC1_BANK_BASE (0x60000000U)STM32L4 1__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX____FLT32X_NORM_MAX__ 1.7976931348623157e+308F32x__arm__ 1RTC_TSDR_DT_SHIFT (4)__FRACT_EPSILON__ 0x1P-15R__FLT32_MIN_10_EXP__ (-37)RTC_TSTR_MNT_SHIFT (12)RTC_TSDR MMIO32(RTC_BASE + 0x34)__ARM_FEATURE_BF16_VECTOR_ARITHMETICbcd_second__LDBL_NORM_MAX__ 1.7976931348623157e+308Lbcd_minuteDESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)bcd_hourRTC_ISR_INIT (1<<7)FMC_QUADSPI_BASE (0xA0000000U)RTC_PRER_PREDIV_A_SHIFT (16)RTC_WPR MMIO32(RTC_BASE + 0x24)rtc_calendar_set_weekdayRTC_CR_SUB1H (1<<17)__ARM_FEATURE_QRDMX__ARM_ARCH_ISA_THUMB 2__LONG_LONG_MAX__ 0x7fffffffffffffffLLRTC_TAFCR_TAMPFREQ_RTCDIV512 (0x6)__WINT_WIDTH__ 32SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__RTC_DR_WDU_SUNBIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN____SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)RTC_TR_HU_SHIFT (16)__DBL_MIN_EXP__ (-1021)__LDBL_HAS_DENORM__ 1INT_FAST32_MIN (-INT_FAST32_MAX - 1)RTC_DR_WDU_SHIFT (13)RTC_SHIFTR_SUBFS_SHIFT (0)__FLT32_DIG__ 6INT_LEAST16_MAXrtc_calendar_set_dateRTC_CR_ALRBIE (1<<13)BIT15 (1<<15)RTC_ISR_SHPF (1<<3)RTC_TSTR_MNU_MASK (0xf)VREFBUF_BASE (PERIPH_BASE_APB2 + 0x0030)BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1INT32_MAX__ACCUM_MIN__ (-0X1P15K-0X1P15K)async__ARM_FEATURE_CRYPTORTC_CALR_CALP (1 << 15)__INT_LEAST32_TYPE__ long intRTC_ALRMXR_WDSEL (1<<30)BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__FRACT_IBIT__ 0UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234ADC1_BASE (0x50000000U + 0x40000)__FLT_NORM_MAX__ 3.4028234663852886e+38Flong long unsigned int__FLT_MIN_10_EXP__ (-37)BIT31 (1<<31)__ULACCUM_IBIT__ 32RTC_TSTR_MNT_MASK (0x7)__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__ULLACCUM_EPSILON__ 0x1P-32ULLK__APCS_32__ 1__DQ_FBIT__ 63INT_LEAST64_MAX__SACCUM_IBIT__ 8RTC_TAFCR_TAMPFLT_MASK (0x3)__UHQ_IBIT__ 0TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)LIBOPENCM3_MEMORYMAP_COMMON_H BIT29 (1<<29)RTC_ISR_TAMP3F (1<<15)__INT_FAST16_TYPE__ intINT64_C__ULFRACT_MAX__ 0XFFFFFFFFP-32ULR__UINT_LEAST16_TYPE__ short unsigned intRTC_CALR MMIO32(RTC_BASE + 0x3c)__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned intRTC_TSTR_ST_SHIFT (4)__FLT32X_DIG__ 15rtc_set_init_flag__UTQ_FBIT__ 128__LLACCUM_EPSILON__ 0x1P-31LLK__FINITE_MATH_ONLY__ 0RTC_ALRMXR_DU_MASK (0xf)__INT_FAST16_MAX__ 0x7fffffffRTC_ISR_WUTF (1<<10)DMA2_BASE (PERIPH_BASE_AHB1 + 0x0400)PTRDIFF_MAX __PTRDIFF_MAX__RTC_CR_REFCKON (1<<4)RTC_TSDR_DT_MASK (0x3)RTC_TAFCR_TAMP2TRG (1<<4)UINT_FAST16_MAX__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKRTC_TAFCR_TAMPPRCH_2RTC (0x1)RTC_DR_MT_SHIFT (12)QUADSPI_BASE (0xa0001000U)RTC_CR_WUCLKSEL_RTC_DIV2 (0x3)UINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRRTC_TSTR_SU_MASK (0xf)__DQ_IBIT__ 0RTC_TAFCR_TAMPTS (1<<7)__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intRTC_TAFCR_TAMPFREQ_RTCDIV4K (0x3)WCHAR_MINBEGIN_DECLS RTC_TR_SU_MASK (0xf)RTC_TR_HT_MASK (0x3)RTC_ALRMBR MMIO32(RTC_BASE + 0x20)RTC_ALRMXSSR_MASKSS_SHIFT (24)__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__FLT32X_MAX__ 1.7976931348623157e+308F32xGPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400)LIBOPENCM3_RTC2_H RTC_TR_HU_MASK (0xf)__ARM_EABI__ 1RTC_TSDR_DU_SHIFT (0)INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1__ARM_FEATURE_DSP 1TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)__QQ_IBIT__ 0RTC_SHIFTR_SUBFS_MASK (0x7fff)__LLACCUM_FBIT__ 31__UINTMAX_TYPE__ long long unsigned intDESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 0x14)__USQ_IBIT__ 0__UINT_LEAST32_TYPE__ long unsigned int__ARM_FEATURE_NUMERIC_MAXMINRTC_TAFCR_TAMPIE (1<<2)__INTMAX_TYPE__ long long int__GCC_ATOMIC_INT_LOCK_FREE 2TIM16_BASE (PERIPH_BASE_APB2 + 0x4400)monthINTMAX_MAXDESIG_PACKAGE MMIO16((INFO_BASE + 0x7500))__ARM_ARCH_7EM__ 1__ARM_FEATURE_FP16_SCALAR_ARITHMETIC__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1/build/libopencm3/lib/stm32/l4TIM17_BASE (PERIPH_BASE_APB2 + 0x4800)RTC_TSTR MMIO32(RTC_BASE + 0x30)__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CINT64_MIN__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intUINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRBIT10 (1<<10)rtc_set_prescaler__SIZEOF_SIZE_T__ 4__UINT64_TYPE__ long long unsigned intuint16_t__INT64_C(c) c ## LLUSART1_BASE (PERIPH_BASE_APB2 + 0x3800)USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x6800)RTC_ALRMXR_MSK1 (1<<7)TPIU_BASE (PPBI_BASE + 0x40000)MPU_BASE (SCS_BASE + 0x0D90)__ARM_FEATURE_CDE__ACCUM_IBIT__ 16CORESIGHT_LAR_OFFSET 0xfb0EXTI_BASE (PERIPH_BASE_APB2 + 0x0400)RTC_ALRMXR_MSK4 (1<<31)FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000)short intRNG_BASE (0x50000000U + 0x60800)RTC_CALR_CALM_SHIFT (0)__UINT16_C(c) c__UDA_IBIT__ 32UINT_LEAST32_MAXRTC_CR_WUCLKSEL_SHIFT (0)BIT2 (1<<2)__ATOMIC_RELAXED 0__ARM_FEATURE_COPROCRTC_ALRMXR_HU_SHIFT (16)RTC_TAFCR_TAMPFLT_EDGE2 (0x1)__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffMMIO64(addr) (*(volatile uint64_t *)(addr))__FLT64_MANT_DIG__ 53BIT5 (1<<5)RTC_CR_OSEL_ALARMB (0x2)BIT1 (1<<1)INT8_CGPIO_PORT_H_BASE (PERIPH_BASE_AHB2 + 0x1c00)INT_LEAST32_MAX__USES_INITFINI__ 1RTC_TSTR_MNU_SHIFT (8)RTC_TSTR_HU_MASK (0xf)__DBL_DECIMAL_DIG__ 17BIT8 (1<<8)RTC_CR_COE (1<<23)RTC_DR_WDU_TUEINT16_C(c) __INT16_C(c)UINT32_MAXRTC_CR_BKP (1<<18)__INT16_MAX__ 0x7fffRTC_ISR_TAMP2F (1<<14)__INT_WIDTH__ 32__ARM_FEATURE_SIMD32 1DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x75e0)RTC_CR_WUTE (1<<10)INT_LEAST8_MIN__QQ_FBIT__ 7RTC_BASE (PERIPH_BASE_APB1 + 0x2800)__SIG_ATOMIC_WIDTH__ 32hourRTC_TSTR_PM (1<<22)LPTIM2_BASE (PERIPH_BASE_APB1 + 0x9400)RTC_CR_OSEL_DISABLED (0x0)__ULLFRACT_EPSILON__ 0x1P-64ULLRfalse 0__SIZEOF_WINT_T__ 4RTC_DR_WDU_MASK (0x7)__ARM_FEATURE_UNALIGNED 1__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17RTC_DR_MT_MASK (1)__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)RTC_TSTR_HU_SHIFT (16)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1__FLT32X_HAS_DENORM__ 1__ULLACCUM_MIN__ 0.0ULLK__INT_FAST32_WIDTH__ 32__TA_IBIT__ 64RTC_ALRMXR_HT_MASK (0x3)rtc_time_set_hourRTC_TAFCR_TAMPPUDIS (1<<15)__ARM_ASM_SYNTAX_UNIFIED__ 1RTC_TSTR_HT_MASK (0x3)RTC_TAFCR_TAMP1TRG (1<<1)__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPROD__thumb2__ 1RTC_TAFCR_TAMPFREQ_RTCDIV1K (0x5)RTC_ALRMXR_DT_SHIFT (28)__ARM_PCS_VFP 1RTC_TAFCR_TAMPPRCH_1RTC (0x0)__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H LPUART1_BASE (PERIPH_BASE_APB1 + 0x8000)rtc_cr_wuckselINT_LEAST64_MIN__GCC_CONSTRUCTIVE_SIZE 64__LLFRACT_IBIT__ 0uint32_tBIT12 (1<<12)DFSDM_BASE (PERIPH_BASE_APB2 + 0x6000)__SACCUM_EPSILON__ 0x1P-7HK__GCC_ASM_FLAG_OUTPUTS__ 1ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0x75a8))__ARM_FP 4RTC_CR_OSEL_MASK (0x3)__UINT_FAST16_TYPE__ unsigned int__UHA_IBIT__ 8RTC_TAFCR_TAMP2E (1<<3)__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULK__LDBL_DIG__ 15POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXBIT16 (1<<16)__WINT_MIN__ 0UINT_LEAST16_MINRTC_ALRMXSSR_SS_SHIFT (0)__FLT64_DIG__ 15rtc_enable_bypass_shadow_registerBIT22 (1<<22)__INT_LEAST8_WIDTH__ 8RTC_DR_WDU_FRIWWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)INT_FAST8_MAX __INT_FAST8_MAX__RTC_ALRMXR_ST_SHIFT (4)__DBL_MAX__ ((double)1.7976931348623157e+308L)INT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1UINTMAX_CINT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1__HQ_FBIT__ 15__bool_true_false_are_defined 1BIT26 (1<<26)__SIZE_MAX__ 0xffffffffUSPI2_BASE (PERIPH_BASE_APB1 + 0x3800)rtc_dr_wdu__ARM_ARCHrtc_lock__LONG_MAX__ 0x7fffffffLRTC_TAFCR_TAMPFREQ_RTCDIV32K (0x0)SAI2_BASE (PERIPH_BASE_APB2 + 0x5800)__ARM_FEATURE_LDREX 7../common/rtc_common_l1f024.cPTRDIFF_MAX__LLFRACT_EPSILON__ 0x1P-63LLR__SFRACT_MAX__ 0X7FP-7HR__FLT32X_MANT_DIG__ 53RTC_CALIBR_DC_MASK (0x1f)__WCHAR_WIDTH__ 32WINT_MAXRTC_TR_MNU_SHIFT (8)__INT16_C(c) cRTC_ALRMXR_DU_SHIFT (24)INT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32__USFRACT_IBIT__ 0__INT_LEAST16_TYPE__ short intRTC_DR_YU_MASK (0xf)RTC_DR_WDU_WED__ATOMIC_ACQ_REL 4bcd_day__DBL_MIN_10_EXP__ (-307)rtc_calendar_set_monthRTC_ALRMBSSR MMIO32(RTC_BASE + 0x48)__FLT32_NORM_MAX__ 3.4028234663852886e+38F32RTC_TR_MNU_MASK (0xf)UINT64_C(c) __UINT64_C(c)__UINTMAX_MAX__ 0xffffffffffffffffULLRTC_ISR_WUTWF (1<<2)__DBL_MANT_DIG__ 53__ULFRACT_IBIT__ 0INT_FAST16_MAXITR_BASE (SCS_BASE + 0x0000)RTC_TSDR_MT (1<<12)QUADSPI_BANK_BASE (0x90000000U)__INT_MAX__ 0x7fffffff__INT_LEAST64_TYPE__ long long int__ARM_FEATURE_CDE_COPROCRTC_ISR_TAMP1F (1<<13)UINT32_CGCC: (15:12.2.rel1-1) 12.2.1 20221205˙˙˙˙| 0DAŽ4 <0 "A„…†ŽNÎĆĹÄP<0 A„…ŽKÎĹÄĂA3aeabi)7E-M M "ń˙ , @08,!!L!""8"##,#$$&()+-/AC13579;=?EBs¤Ö;oDG«˝0 ŇÝćDú"6Me‡ŞĽÎ4ä ý<0)"?P!Q<"e0#y$rtc_common_l1f024.c$t$dwm4.0.c5e6bdb01417bb5a599260a3f8c9cb62wm4.common.h.21.c9066c2f6b12c71b40226ea6107829a4wm4.stdint.h.29.6d480f4ba0f60596e88234283d42444fwm4.stdbool.h.29.4a1c88fe569adb8d03217dd16982ca34wm4.common.h.67.5c568a1f62c8e726909b04e29f9e1fc0wm4.memorymap.h.21.8c90486dae5eea2d8efddd23fe5d09d9wm4.memorymap.h.26.bb1efb6ce36cc052fd0489ef5a3533f5wm4.rtc_common_l1f024.h.39.7a7190ea14301fbce5e958da3e4de6dertc_set_prescalerrtc_wait_for_synchrortc_unlockrtc_lockrtc_set_wakeup_timertc_clear_wakeup_flagrtc_set_init_flagrtc_clear_init_flagrtc_init_flag_is_readyrtc_wait_for_init_readyrtc_enable_bypass_shadow_registerrtc_disable_bypass_shadow_registerrtc_set_am_formatrtc_set_pm_formatrtc_calendar_set_yearrtc_calendar_set_weekdayrtc_calendar_set_monthrtc_calendar_set_dayrtc_calendar_set_datertc_time_set_hourrtc_time_set_minutertc_time_set_secondrtc_time_set_time r x z y{ } ~H NNNK"M&L-N4N;NBNINNN[N`NmNrNN†N’NĄN«N±N·N˝NĂNÉNĐNÖEĺNđIôIůNII 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7RCC_CFGR_MCO_MSI 0x2SPI_CR2_DS_14BIT (0xD << 8)__FLT64_HAS_INFINITY__ 1RCC_APB1SMENR1_USART3SMEN (1 << 18)rcc_periph_reset_pulse__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GNUC_MINOR__ 2__GCC_DESTRUCTIVE_SIZE 64__LACCUM_EPSILON__ 0x1P-31LKRCC_CIFR_LSECSSF (1 << 9)__PTRDIFF_MAX__ 0x7fffffff__ARM_FEATURE_FMA 1SPI2_RXCRCR SPI_RXCRCR(SPI2_BASE)__INTMAX_C(c) c ## LLRCC_CR_MSIRANGE_800KHZ 3RCC_AHB3RSTR_FMCRST (1 << 0)__INTMAX_MAX__ 0x7fffffffffffffffLL__TQ_IBIT__ 0__FLT64_DECIMAL_DIG__ 17__LDBL_MIN__ 2.2250738585072014e-308LINT_FAST64_MAXOPAMP_BASE (PERIPH_BASE_APB1 + 0x7800)SPI1_I2SCFGR SPI_I2SCFGR(SPI1_BASE)__ATOMIC_CONSUME 1__ULACCUM_FBIT__ 32__WCHAR_MAX__ 0xffffffffURCC_APB1SMENR1_PWRSMEN (1 << 28)SPI2_DR SPI_DR(SPI2_BASE)RCC_PLLCFGR_PLLR_DIV6 2RCC_AHB2ENR_GPIODEN (1 << 3)SPI_CR2_DS_12BIT (0xB << 8)RCC_AHB1ENR_DMA1EN (1 << 0)RCC_AHB2SMENR_GPIOCSMEN (1 << 2)RCC_AHB1SMENR_DMA1SMEN (1 << 0)INT64_MAX __INT64_MAX__INTMAX_MIN__SIZEOF_LONG_LONG__ 8spi_enable_rx_dma__DBL_MAX_10_EXP__ 308__FRACT_MIN__ (-0.5R-0.5R)RCC_CR_PLLRDY (1 << 25)__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLK__USACCUM_MAX__ 0XFFFFP-8UHKspi_xfer__INTMAX_WIDTH__ 64__ARM_FEATURE_BF16_SCALAR_ARITHMETIC__SQ_IBIT__ 0rcc_periph_rst__SIZE_TYPE__ unsigned intRCC_AHB1ENR_FLASHEN (1 << 8)SPI_CR1_BR_FPCLK_DIV_8 0x2spi_set_bidirectional_mode__INT8_TYPE__ signed char__ARM_ARCH_PROFILE 77RCC_CFGR_HPRE_NODIV 0x0RCC_CFGR_PPRE2_DIV16 0x7__USACCUM_MIN__ 0.0UHKGPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000)__FLT32_DECIMAL_DIG__ 9SPI_CR2_DS_9BIT (0x8 << 8)__DECIMAL_DIG__ 17__LDBL_MIN_EXP__ (-1021)UINTPTR_MAX __UINTPTR_MAX____LDBL_MANT_DIG__ 53SPI_SR_CRCERR (1 << 4)INT64_MIN (-INT64_MAX - 1)RCC_CFGR_STOPWUCK_MSI (0 << 15)RCC_APB2SMENR_SDMMC1SMEN (1 << 10)__UINT8_C(c) c__INT16_TYPE__ short intRCC_APB1RSTR1 MMIO32(RCC_BASE + RCC_APB1RSTR1_OFFSET)__FLT64_MAX__ 1.7976931348623157e+308F64SPI_CR1_RXONLY (1 << 10)RCC_CCIPR_ADCSEL_PLLSAI1R 1UINT_FAST32_MAXRCC_CFGR_MCO_HSE 0x4SPI_I2SCFGR_I2SCFG_MASTER_RECEIVE 0x3RCC_CIER_LSIRDYIE (1 << 0)RCC_APB1RSTR2_OFFSET 0x3cRCC_PLLCFGR_PLLSRC_NONE 0SPI_I2SPR_ODD (1 << 8)INT_FAST64_MAX __INT_FAST64_MAX__RCC_CR_MSION (1 << 0)__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1RCC_CR_MSIRANGE_48MHZ 11__STDC_HOSTED__ 1__ULLFRACT_FBIT__ 64__SIG_ATOMIC_TYPE__ intRCC_CICR_LSECSSC (1 << 9)RCC_PLLSAI1_CFGR MMIO32(RCC_BASE + 0x10)RCC_CIFR_CSSF (1 << 8)__INT_FAST64_TYPE__ long long int__WINT_TYPE__ unsigned intGPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800)ST_TSENSE_CAL2_110C MMIO16((INFO_BASE + 0x75ca))RCC_CFGR_MCO_PLL 0x5INT32_MIN (-INT32_MAX - 1)spi_set_clock_phase_1__FLT32_MAX_10_EXP__ 38RCC_CSR_MSIRANGE_MASK 0xfRCC_CFGR_HPRE_DIV8 0xaRCC_AHB2SMENR_GPIOHSMEN (1 << 7)RCC_APB1ENR1_TIM3EN (1 << 1)RCC_APB2SMENR_SYSCFGSMEN (1 << 0)RCC_BDCR_LSEDRV_MASK 0x3__USFRACT_MAX__ 0XFFP-8UHRLPTIM1_BASE (PERIPH_BASE_APB1 + 0x7c00)__FP_FAST_FMAF32 1RCC_APB1SMENR1_TIM5SMEN (1 << 3)__UINTPTR_MAX__ 0xffffffffU__FLT32_MIN_EXP__ (-125)SPI_CR2_LDMA_TX (1 << 14)RCC_CFGR_MCOPRE_DIV1 0RCC_APB2SMENR_TIM15SMEN (1 << 16)SPI_I2SCFGR_I2SCFG_LSB 8SPI_CR1_BR_FPCLK_DIV_128 0x6UINT32_MAX __UINT32_MAX__RCC_CCIPR_I2C1SEL_SHIFT 12RCC_CIER_MSIRDYIE (1 << 2)RCC_APB2RSTR_DFSDMRST (1 << 24)RCC_AHB1ENR MMIO32(RCC_BASE + RCC_AHB1ENR_OFFSET)spi_disable_rx_buffer_not_empty_interruptRCC_CFGR_SWS_SHIFT 2RCC_APB2ENR_USART1EN (1 << 14)__FLT64_MIN_10_EXP__ (-307)RCC_APB1SMENR1_LPTIM1SMEN (1 << 31)__GNUC_EXECUTION_CHARSET_NAME "UTF-8"RCC_CIFR MMIO32(RCC_BASE + 0x1c)BIT10 (1<<10)__INT_FAST64_WIDTH__ 64__STDC_VERSION__ 199901LINT_LEAST64_MAX __INT_LEAST64_MAX__RCC_CCIPR_SAI1SEL_SHIFT 22RCC_AHB2SMENR MMIO32(RCC_BASE + RCC_AHB2SMENR_OFFSET)SPI_CR2_DS_15BIT (0xE << 8)RCC_CFGR_MCOPRE_DIV8 3__SFRACT_EPSILON__ 0x1P-7HRSPI_CR2_DS_4BIT (0x3 << 8)__INT32_C(c) c ## LUINT32_C(c) __UINT32_C(c)__ORDER_BIG_ENDIAN__ 4321SIZE_MAXSYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000)RCC_APB2SMENR_USART1SMEN (1 << 14)__SQ_FBIT__ 31RST_SYSCFGDWT_BASE (PPBI_BASE + 0x1000)INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)RCC_CR_MSIRGSEL (1 << 3)SPI_I2SPR_MCKOE (1 << 9)SPI3_CR1 SPI_CR1(SPI3_BASE)__UHQ_FBIT__ 16RCC_APB1ENR2_LPTIM2EN (1 << 5)__FLT64_MIN_EXP__ (-1021)RCC_AHB1RSTR_CRCRST (1 << 12)spi_writeLIBOPENCM3_RCC_H __UINT_FAST8_MAX__ 0xffffffffURCC_CFGR_PPRE1_DIV2 0x4RCC_APB1ENR1_OPAMPEN (1 << 30)RCC_APB2ENR_TIM15EN (1 << 16)UINT16_C(c) __UINT16_C(c)__LACCUM_IBIT__ 32RCC_CSR_SFTRSTF (1 << 28)SPI_CR1_BR_FPCLK_DIV_256 0x7RCC_CCIPR_UARTxSEL_HSI16 RCC_CCIPR_USARTxSEL_HSI16__INT_FAST16_WIDTH__ 32INTMAX_C__VERSION__ "12.2.1 20221205"RCC_CCIPR_I2C2SEL_SHIFT 14__VFP_FP__ 1SPI_CR1_BAUDRATE_FPCLK_DIV_128 (0x06 << 3)__LLFRACT_MIN__ (-0.5LLR-0.5LLR)INT_FAST8_MAXCOMP_BASE (PERIPH_BASE_APB2 + 0x0200)__UINT_FAST16_MAX__ 0xffffffffURCC_APB1SMENR1_TIM6SMEN (1 << 4)RCC_CFGR_PPRE2_DIV2 0x4__INTPTR_MAX__ 0x7fffffffINT64_C(c) __INT64_C(c)RCC_CIER_LSE_CSSIE (1 << 9)SPI_I2SCFGR_I2SSTD_LSB_JUSTIFIED 0x2RCC_CCIPR_USART1SEL_SHIFT 0SPI_I2SCFGR_I2SSTD_I2S_PHILIPS 0x0__GCC_IEC_559_COMPLEX 0__UFRACT_MIN__ 0.0URspi_disable_error_interruptSPI4 SPI4_BASEspi_disableWCHAR_MAX __WCHAR_MAX__RCC_APB2SMENR_TIM8SMEN (1 << 13)__FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX__RCC_CSR_MSIRANGE_4MHZ 6__UINT_LEAST8_TYPE__ unsigned charRCC_AHB2ENR_GPIOEEN (1 << 4)RCC_APB1RSTR1_I2C1RST (1 << 21)SPI_DR(spi_base) MMIO32((spi_base) + 0x0c)spi_set_bidirectional_transmit_only_mode__ACCUM_FBIT__ 15PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)__UACCUM_IBIT__ 16spi_readUINT8_MAXIWDG_BASE (PERIPH_BASE_APB1 + 0x3000)SIZE_MAX __SIZE_MAX__RCC_CICR_PLLSAI2RDYC (1 << 7)__INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17RCC_CCIPR_CLK48SEL_SHIFT 26__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1RCC_APB1ENR1_I2C1EN (1 << 21)RST_LCD__FLT32X_EPSILON__ 2.2204460492503131e-16F32xRCC_ICSCR_MSICAL_MASK 0xffRCC_CCIPR_SAIxSEL_PLLSAI1P 0NVIC_BASE (SCS_BASE + 0x0100)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32USART2_BASE (PERIPH_BASE_APB1 + 0x4400)__UINTMAX_C(c) c ## ULLRCC_PLLCFGR_PLLN_MASK 0x7fUINT8_C(c) __UINT8_C(c)__INT_LEAST8_TYPE__ signed charRCC_AHB1RSTR MMIO32(RCC_BASE + RCC_AHB1RSTR_OFFSET)__GCC_ATOMIC_BOOL_LOCK_FREE 2BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON____FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX____THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRRCC_APB1SMENR1_TIM4SMEN (1 << 2)RCC_CSR_MSIRANGE_8MHZ 7short unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)BIT7 (1<<7)UINT_FAST8_MAX __UINT_FAST8_MAX____FLT32X_MIN_10_EXP__ (-307)GPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400)__ELF__ 1UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)__DBL_IS_IEC_60559__ 2__UINT_FAST32_MAX__ 0xffffffffURCC_APB1SMENR1_LCDSMEN (1 << 9)__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4WINT_MIN __WINT_MIN__RCC_APB2RSTR_TIM15RST (1 << 16)SPI_CR1_BAUDRATE_FPCLK_DIV_8 (0x02 << 3)SPI_CR1_MSBFIRST (0 << 7)RCC_CCIPR_LPUART1SEL_HSI16 2__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32RST_CRCDMA1_BASE (PERIPH_BASE_AHB1 + 0x0000)SPI_I2SCFGR_DATLEN_32BIT 0x2PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)spi_disable_software_slave_managementRCC_BDCR_RTCSEL_NONE 0RCC_CIER_PLLSAI1RDYIE (1 << 6)__LONG_LONG_MAX__ 0x7fffffffffffffffLLGNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsRCC_AHB2SMENR_AESSMEN (1 << 16)BIT27 (1<<27)SAI1_BASE (PERIPH_BASE_APB2 + 0x5400)RCC_CICR_MSIRDYC (1 << 2)RST_CRSRCC_APB2ENR_SYSCFGEN (1 << 0)SPI_DR8(spi_base) MMIO8((spi_base) + 0x0c)SPI_CR2_DS_8BIT (0x7 << 8)__UTA_FBIT__ 64INTMAX_C(c) __INTMAX_C(c)RCC_CFGR_PPRE1_SHIFT 8RCC_CIFR_MSIRDYF (1 << 2)__FLT_DECIMAL_DIG__ 9RCC_CRRCR_HSI48RDY (1 << 1)LIBOPENCM3_MEMORYMAP_COMMON_H spi_disable_rx_dma__INT_LEAST32_MAX__ 0x7fffffffLsigned charRCC_APB1ENR1_DAC1EN (1 << 29)SPI_CR1_CPOL (1 << 1)uint8_tINT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)INT32_C(c) __INT32_C(c)SPI3_I2SCFGR SPI_I2SCFGR(SPI3_BASE)__GNUC_STDC_INLINE__ 1SPI_CR2_DS_13BIT (0xC << 8)SPI_CR1_BIDIMODE (1 << 15)__FRACT_FBIT__ 15RCC_ICSCR_MSICAL_SHIFT 0__LLACCUM_EPSILON__ 0x1P-31LLK__GNUC_PATCHLEVEL__ 1__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2RCC_PLLCFGR_PLLP (1 << 17)PTRDIFF_MINRCC_AHB2RSTR_GPIOGRST (1 << 6)__UINT_LEAST16_MAX__ 0xffffSPI_CR1_BR_FPCLK_DIV_4 0x1RCC_APB1SMENR1_OFFSET 0x78RCC_AHB2RSTR_GPIOARST (1 << 0)PPBI_BASE (0xE0000000U)RCC_BDCR_RTCEN (1 << 15)RCC_CIFR_PLLRDYF (1 << 5)RCC_CCIPR_LPUART1SEL_APB 0RCC_AHB3SMENR_OFFSET 0x70GPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000)RCC_APB1ENR1_TIM6EN (1 << 4)__FLT64_MAX_10_EXP__ 308GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400)MMIO32(addr) (*(volatile uint32_t *)(addr))spi_enable_rx_buffer_not_empty_interruptRCC_PLLCFGR_PLLR_DIV2 0SPI2_I2SCFGR SPI_I2SCFGR(SPI2_BASE)SPI_CR1_LSBFIRST (1 << 7)SDMMC1_BASE (PERIPH_BASE_APB2 + 0x2800)RCC_CSR_BORRSTF (1 << 27)__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38spi_set_full_duplex_modeTIM6_BASE (PERIPH_BASE_APB1 + 0x1000)__FRACT_MAX__ 0X7FFFP-15RRCC_CCIPR_LPUART1SEL_LSE 3TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)INT_LEAST32_MAX __INT_LEAST32_MAX__RCC_APB1ENR2_LPUART1EN (1 << 0)SPI_CR1_BIDIMODE_2LINE_UNIDIR (0 << 15)SPI1_DR SPI_DR(SPI1_BASE)__INT_FAST32_MAX__ 0x7fffffffSPI1_BASE (PERIPH_BASE_APB2 + 0x3000)RCC_APB1SMENR1_USART2SMEN (1 << 17)RCC_PLLCFGR_PLLSRC_HSE 3SPI_SR_TXE (1 << 1)RST_SDMMC1RCC_APB1ENR1_SPI2EN (1 << 14)RCC_CFGR_SW_HSE 0x2SPI_I2SCFGR_DATLEN_24BIT 0x1RCC_AHB2SMENR_GPIODSMEN (1 << 3)__UACCUM_MIN__ 0.0UKRCC_CFGR_MCO_SHIFT 24RCC_CR_MSIRANGE_SHIFT 4__UINT16_MAX__ 0xffff__TQ_FBIT__ 127RCC_AHB2RSTR_ADCRST (1 << 13)__USQ_FBIT__ 32spi_peripheral__USES_INITFINI__ 1RCC_CR_HSIKERON (1 << 9)SPI_SR_UDR (1 << 3)RCC_CSR_IWDGRSTF (1 << 29)__thumb2__ 1__ULLACCUM_FBIT__ 32FMC_QUADSPI_BASE (0xA0000000U)RCC_AHB2SMENR_SRAM2SMEN (1 << 9)USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6c00)SPI_SR_BSY (1 << 7)RCC_BDCR_RTCSEL_HSEDIV32 3RST_SPI1INT_FAST32_MIN (-INT_FAST32_MAX - 1)RCC_CFGR_MCO_MASK 0xf__STRICT_ANSI__ 1RST_SPI3FMC3_BANK_BASE (0x80000000U)UINT_LEAST8_MAXRST_DMA1RST_DMA2__SIZEOF_LONG_DOUBLE__ 8CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)TIM8_BASE (PERIPH_BASE_APB2 + 0x3400)RCC_APB1RSTR1_CAN1RST (1 << 25)__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__RCC_AHB1RSTR_DMA2RST (1 << 1)RCC_BDCR_LSECSSON (1 << 5)SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE (0 << 1)__USA_IBIT__ 16__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1DBGMCU_BASE (PPBI_BASE + 0x00042000)PTRDIFF_MIN (-PTRDIFF_MAX - 1)UART5_BASE (PERIPH_BASE_APB1 + 0x5000)RCC_BDCR_LSEDRV_HIGH 3__UINT_FAST64_TYPE__ long long unsigned intPERIPH_BASE_AHB2 (0x48000000U)RCC_CR_MSIRANGE_8MHZ 7SPI_CR1_BIDIOE (1 << 14)DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7590)__FLT_MIN__ 1.1754943508222875e-38FRCC_CFGR_MCOPRE_MASK 0x7__HA_FBIT__ 7RCC_CFGR_MCO_HSI48 0x8__FDPIC__RST_GPIOARST_GPIOBRST_GPIOCRST_GPIODRST_GPIOERST_GPIOFRST_GPIOGRST_GPIOHRCC_APB2SMENR_SAI1SMEN (1 << 21)GPIO_PORT_G_BASE (PERIPH_BASE_AHB2 + 0x1800)SPI_I2SCFGR(spi_base) MMIO32((spi_base) + 0x1c)SPI_I2SCFGR_I2SE (1 << 10)INT_FAST64_MIN__USFRACT_IBIT__ 0RCC_CCIPR_UARTxSEL_APB RCC_CCIPR_USARTxSEL_APBRCC_CIER_HSI48RDYIE (1 << 10)__LDBL_EPSILON__ 2.2204460492503131e-16LRCC_CCIPR_USART1SEL_APB 0RCC_AHB1RSTR_FLASHRST (1 << 8)__USFRACT_MIN__ 0.0UHRTSC_BASE (PERIPH_BASE_AHB1 + 0x4000)RCC_BDCR_LSEDRV_SHIFT 3__ARM_NEONSPI_CR1_CRCL (1 << 11)RCC_PLLCFGR_PLLQ_DIV2 0__UINT8_MAX__ 0xffSPI_I2SCFGR_DATLEN_16BIT 0x0__LDBL_MAX_EXP__ 1024RCC_CFGR_MCOPRE_DIV4 2LIBOPENCM3_MEMORYMAP_H SPI_CR2_DS_MASK (0xF << 8)LIBOPENCM3_SPI_COMMON_ALL_H SPI_CR2_FRF_TI_MODE (1 << 4)__DBL_HAS_DENORM__ 1DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)RCC_APB2RSTR_USART1RST (1 << 14)SPI_CR2_FRF_MOTOROLA_MODE (0 << 4)RCC_CIER_HSERDYIE (1 << 4)RCC_CR_MSIRDY (1 << 1)RCC_APB1RSTR1_OFFSET 0x38QUADSPI_BASE (0xa0001000U)__DA_FBIT__ 31RCC_CCIPR_I2CxSEL_MASK 0x3BIT17 (1<<17)RCC_CCIPR_UART5SEL_SHIFT 8__GXX_ABI_VERSION 1017GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0c00)__INT_LEAST16_MAX__ 0x7fffRCC_CCIPR_ADCSEL_MASK 0x3__FLT_DENORM_MIN__ 1.4012984643248171e-45F__LDBL_MAX__ 1.7976931348623157e+308LRCC_PLLCFGR_PLLREN (1<<24)RCC_CIFR_HSIRDYF (1 << 3)SPI_CR2_DS_10BIT (0x9 << 8)RST_RNGRCC_CR_MSIRANGE_16MHZ 8RCC_APB1ENR2_OFFSET 0x5cINT_LEAST8_MAX __INT_LEAST8_MAX__RCC_CR_MSIRANGE_1MHZ 4RCC_APB1RSTR1_SPI2RST (1 << 14)RCC_CICR_PLLSAI1RDYC (1 << 6)__UINT32_C(c) c ## ULRCC_AHB1SMENR_SRAM1SMEN (1 << 9)spi_set_receive_only_modespi_set_next_tx_from_crc__FLT_EPSILON__ 1.1920928955078125e-7FRCC_PLLCFGR_PLLSRC_SHIFT 0TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)RCC_APB2RSTR_SAI1RST (1 << 21)RCC_AHB1SMENR_FLASHSMEN (1 << 8)UINT32_MAX__PTRDIFF_TYPE__ int__ARM_ARCH_ISA_THUMBRCC_CR_PLLSAI1ON (1 << 26)__UACCUM_EPSILON__ 0x1P-16UK__ARM_FEATURE_MATMUL_INT8RCC_AHB1ENR_DMA2EN (1 << 1)LIBOPENCM3_CM3_MEMORYMAP_H __GCC_ATOMIC_SHORT_LOCK_FREE 2RCC_CCIPR_UARTxSEL_MASK RCC_CCIPR_USARTxSEL_MASKRCC_AHB2SMENR_GPIOGSMEN (1 << 6)RCC_CCIPR_LPUART1SEL_SYS 1spi_enable_software_slave_management__USACCUM_FBIT__ 8RCC_BDCR_LSCOSEL (1 << 25)__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1RCC_APB1ENR1_USART2EN (1 << 17)RCC_CSR_RMVF (1 << 23)__LACCUM_FBIT__ 31SCS_BASE (PPBI_BASE + 0xE000)RCC_CFGR_STOPWUCK_HSI16 (1 << 15)RCC_CICR_LSERDYC (1 << 1)SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)__FLT32_HAS_QUIET_NAN__ 1I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)SPI3_TXCRCR SPI_TXCRCR(SPI3_BASE)RCC_CSR_OBLRSTF (1 << 25)SPI_SR_FRLVL_HALF_FIFO (0x2 << 9)__LDBL_HAS_INFINITY__ 1RCC_AHB2RSTR_GPIOERST (1 << 4)__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))__FLT32X_MAX_10_EXP__ 308spi_set_nss_highRCC_CCIPR_CLK48SEL_PLLSAI1Q 1RCC_CIER_HSIRDYIE (1 << 3)bool _BoolRST_DFSDMSPI_CR1_BAUDRATE_FPCLK_DIV_32 (0x04 << 3)UINTMAX_MAX __UINTMAX_MAX__RCC_BDCR_RTCSEL_SHIFT 8__SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffRCC_CR_PLLSAI2ON (1 << 28)__GCC_ATOMIC_LONG_LOCK_FREE 2BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)SPI3_RXCRCR SPI_RXCRCR(SPI3_BASE)INT16_MAX __INT16_MAX__RCC_APB1RSTR1_USART2RST (1 << 17)__FP_FAST_FMAF 1RCC_AHB3ENR_OFFSET 0x50SPI2_CR2 SPI_CR2(SPI2_BASE)RCC_CR_MSIRANGE_24MHZ 9__FLT32X_IS_IEC_60559__ 2RCC_APB1RSTR1_USART3RST (1 << 18)PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)RST_AESWINT_MINLIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))RST_OPAMPspi_clean_disable__INT_LEAST16_WIDTH__ 16__ULFRACT_FBIT__ 32__DEC_EVAL_METHOD__ 2__ARM_FEATURE_FP16_FMLRCC_CR_MSIRANGE_2MHZ 5RCC_AHB3ENR_FMCEN (1 << 0)RCC_CCIPR_I2CxSEL_APB 0INT16_MIN (-INT16_MAX - 1)__USFRACT_EPSILON__ 0x1P-8UHRRCC_APB2ENR_TIM8EN (1 << 13)spi_set_unidirectional_mode__USFRACT_FBIT__ 8__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLKRCC_APB1ENR1_LCDEN (1 << 9)SPI_CR2_LDMA_RX (1 << 13)RCC_APB1RSTR1_UART5RST (1 << 20)__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX__RCC_CSR_WWDGRSTF (1 << 30)__UINT32_MAX__ 0xffffffffULRCC_CCIPR_ADCSEL_SYS 3RCC_CFGR_HPRE_DIV16 0xb__INT_LEAST8_MAX__ 0x7f__GCC_ATOMIC_POINTER_LOCK_FREE 2__ARM_FEATURE_QBIT 1__ARM_FEATURE_CLZ 1__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXRCC_AHB3ENR MMIO32(RCC_BASE + RCC_AHB3ENR_OFFSET)BIT15 (1<<15)__ARM_PCS_VFP 1RCC_ICSCR_HSICAL_MASK 0xffRCC_CFGR_SWS_MASK 0x3__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024RCC_BDCR_LSEON (1 << 0)spi_set_standard_modeRCC_CICR MMIO32(RCC_BASE + 0x20)__UINT_LEAST32_MAX__ 0xffffffffUL__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)RCC_APB2RSTR_OFFSET 0x40__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1SPI_CR1_CPHA_CLK_TRANSITION_1 (0 << 0)__ACCUM_MAX__ 0X7FFFFFFFP-15KRCC_APB1RSTR2_SWPMI1RST (1 << 2)__INT8_MAX__ 0x7fRST_I2C2RST_I2C3RCC_CCIPR_USART2SEL_SHIFT 2RCC_APB1RSTR1_TIM6RST (1 << 4)__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16SPI_I2SCFGR_PCMSYNC (1 << 7)__SHRT_WIDTH__ 16BIT20 (1<<20)__ARM_FEATURE_MVERCC_CFGR_MCO_NOCLK 0x0__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intRCC_CFGR_HPRE_DIV64 0xcRCC_APB1RSTR1_TIM4RST (1 << 2)SWPMI1_BASE (PERIPH_BASE_APB1 + 0x8800)UINT_LEAST16_MAX __UINT_LEAST16_MAX__SPI_CR2_FRF (1 << 4)INT_FAST32_MINSPI2_TXCRCR SPI_TXCRCR(SPI2_BASE)__FLT_EVAL_METHOD_TS_18661_3__ 0RCC_AHB3RSTR MMIO32(RCC_BASE + RCC_AHB3RSTR_OFFSET)__SCHAR_WIDTH__ 8RCC_APB2RSTR MMIO32(RCC_BASE + RCC_APB2RSTR_OFFSET)BIT18 (1<<18)UINT_FAST16_MAXspi_disable_tx_buffer_empty_interrupt__UINT_FAST8_TYPE__ unsigned intRCC_CIFR_LSERDYF (1 << 1)__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RSPI_I2SCFGR_I2SCFG_SLAVE_RECEIVE 0x1BIT24 (1<<24)RCC_PLLCFGR_PLLR_MASK 0x3RCC_CCIPR_I2CxSEL_SYS 1__INT32_MAX__ 0x7fffffffLRCC_APB1ENR1_UART4EN (1 << 19)SPI_CR2_RXDMAEN (1 << 0)RCC_PLLCFGR_PLLQ_DIV6 2RCC_CFGR_HPRE_DIV256 0xeUINTMAX_MAXRCC_APB1SMENR1_UART4SMEN (1 << 19)BIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLLRCC_CFGR_SW_MASK 0x3__ARM_FEATURE_BF16_VECTOR_ARITHMETICRCC_CR_MSIRANGE_400KHZ 2INFO_BASE (0x1fff0000U)__FLT32_MANT_DIG__ 24RCC_BDCR_LSEDRV_MEDLOW 1INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32RCC_AHB2ENR_GPIOHEN (1 << 7)__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intRCC_CCIPR_LPUART1SEL_SHIFT 10INT8_MAX __INT8_MAX__RCC_CSR_LSIRDY (1 << 1)BIT28 (1<<28)RCC_BDCR_LSEDRV_MEDHIGH 2RCC_PLLPEN (1 << 16)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2RCC_CCIPR_USART1SEL_SYS 1RCC_AHB2SMENR_OFFSET 0x6c__DBL_MAX_EXP__ 1024RCC_AHB2RSTR_AESRST (1 << 16)__ATOMIC_RELEASE 3RCC_PLLCFGR_PLLP_DIV17 RCC_PLLCFGR_PLLPUINT_FAST8_MAX__FLT_MANT_DIG__ 24RCC_AHB2SMENR_GPIOESMEN (1 << 4)RCC_APB1ENR1_UART5EN (1 << 20)__UDQ_IBIT__ 0RCC_CIFR_LSIRDYF (1 << 0)TIM1_BASE (PERIPH_BASE_APB2 + 0x2C00)RCC_AHB1SMENR MMIO32(RCC_BASE + RCC_AHB1SMENR_OFFSET)RCC_CR_HSERDY (1 << 17)__OPTIMIZE_SIZE__ 1__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UK__FLT64_NORM_MAX__ 1.7976931348623157e+308F64RCC_BDCR_LSESYSDIS (1 << 7)RCC_APB1RSTR1_OPAMPRST (1 << 30)UINTPTR_MAXSPI_I2SCFGR_I2SCFG_MASTER_TRANSMIT 0x2RCC_CR_PLLSAI1RDY (1 << 27)__LDBL_DENORM_MIN__ 4.9406564584124654e-324LRCC_BDCR_LSERDY (1 << 1)__INT64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_SAT 1SPI_CR2_DS_11BIT (0xA << 8)__ULLFRACT_IBIT__ 0__thumb__ 1RCC_CR_HSIASFS (1 << 11)RCC_CCIPR_ADCSEL_NONE 0RCC_AHB1ENR_TSCEN (1 << 16)MMIO16(addr) (*(volatile uint16_t *)(addr))RCC_CSR_LSION (1 << 0)RCC_APB2ENR_SPI1EN (1 << 12)AES_BASE (0x50000000U + 0x60000)SPI_SR_FTLVL_HALF_FIFO (0x2 << 11)DAC_BASE (PERIPH_BASE_APB1 + 0x7400)__GNUC__ 12RST_LPTIM1RST_LPTIM2SPI1_DR8 SPI_DR8(SPI1_BASE)WCHAR_MAXSPI_SR_FTLVL_QUARTER_FIFO (0x1 << 11)RCC_APB1ENR1_USART3EN (1 << 18)RCC_CCIPR_LPTIMxSEL_HSI16 2__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16RCC_CICR_LSIRDYC (1 << 0)__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0URCC_APB2SMENR_DFSDMSMEN (1 << 24)__UQQ_IBIT__ 0I2C3_BASE (PERIPH_BASE_APB1 + 0x5c00)CORESIGHT_LSR_OFFSET 0xfb4spi_enable_tx_dma__ULACCUM_MIN__ 0.0ULK__INT_MAX__ 0x7fffffff__ARM_ARCH 7UART4_BASE (PERIPH_BASE_APB1 + 0x4c00)SPI_CRCPR(spi_base) MMIO32((spi_base) + 0x10)__FLT_RADIX__ 2BIT3 (1<<3)long long intTPIU_BASE (PPBI_BASE + 0x40000)RCC_CCIPR_USART1SEL_LSE 3RCC_CCIPR_USART3SEL_SHIFT 4__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAXRCC_AHB2ENR_ADCEN (1 << 13)__LDBL_HAS_QUIET_NAN__ 1RCC_AHB1SMENR_OFFSET 0x68SPI2_DR8 SPI_DR8(SPI2_BASE)__LONG_LONG_WIDTH__ 64BIT6 (1<<6)RST_UART4RST_UART5RCC_CFGR_MCOPRE_SHIFT 28RCC_APB1SMENR1_I2C1SMEN (1 << 21)RCC_CCIPR_LPUART1SEL_MASK 0x3__UINT_FAST64_MAX__ 0xffffffffffffffffULLRCC_APB1RSTR1_I2C3RST (1 << 23)__ARM_FP__HA_IBIT__ 8__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1BIT9 (1<<9)RCC_CFGR_HPRE_DIV512 0xf__FLT32X_MIN__ 2.2250738585072014e-308F32xINTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024UINT16_MAXRCC_AHB2RSTR_OTGFSRST (1 << 12)SPI_I2SPR(spi_base) MMIO32((spi_base) + 0x20)__FLT64_MIN__ 2.2250738585072014e-308F64RCC_APB1SMENR1_TIM2SMEN (1 << 0)RCC_AHB3ENR_QSPIEN (1 << 8)RCC_APB1SMENR2 MMIO32(RCC_BASE + RCC_APB1SMENR2_OFFSET)RCC_CCIPR_USART1SEL_HSI16 2RCC_APB2ENR_DFSDMEN (1 << 24)__ARM_ARCH_PROFILE__INT64_TYPE__ long long int__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4SPI_CR1_SPE (1 << 6)SPI_CR1_SSM (1 << 9)RCC_CR_HSION (1 << 8)RCC_CSR_PINRSTF (1 << 26)RCC_CCIPR_LPTIMxSEL_MASK 0x3RCC_CR_HSIRDY (1 << 10)RCC_APB2SMENR_TIM1SMEN (1 << 11)CRS_BASE (PERIPH_BASE_APB1 + 0x6000)__UFRACT_MAX__ 0XFFFFP-16URRCC_AHB1RSTR_OFFSET 0x28RCC_CR_HSEON (1 << 16)INT64_MAXFPB_BASE (PPBI_BASE + 0x2000)RCC_APB2RSTR_SAI2RST (1 << 22)RCC_CFGR_PPRE2_SHIFT 11RCC_CIFR_PLLSAI2RDYF (1 << 7)RCC_CICR_HSI48RDYC (1 << 10)spi_enable_ss_output__SFRACT_IBIT__ 0RCC_BDCR_RTCSEL_LSI 2RCC_CCIPR_USARTxSEL_LSE 3STIR_BASE (SCS_BASE + 0x0F00)RCC_CFGR_SWS_HSE 0x2__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)RST_QSPIRST_TIM15RST_TIM16RST_TIM17ID_BASE (SCS_BASE + 0x0FD0)SYS_TICK_BASE (SCS_BASE + 0x0010)RCC_CFGR_HPRE_DIV2 0x8SPI_CR1_CRCL_16BIT (1 << 11)RCC_PLLCFGR_PLLSRC_HSI16 2RCC_AHB2RSTR_GPIODRST (1 << 3)RCC_CFGR_SWS_MSI 0x0__UFRACT_FBIT__ 16FMC_BASE (0xa0000000U)__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)RCC_CCIPR_SAIxSEL_MASK 0x3__LDBL_MAX_10_EXP__ 308spi_set_bidirectional_receive_only_modeRCC_AHB2ENR_GPIOBEN (1 << 1)__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)SPI_CR1_BAUDRATE_FPCLK_DIV_64 (0x05 << 3)__INT_FAST32_TYPE__ intRCC_CICR_HSERDYC (1 << 4)spi_set_next_tx_from_buffer__ATOMIC_SEQ_CST 5SPI1_TXCRCR SPI_TXCRCR(SPI1_BASE)SPI_CR1_MSTR (1 << 2)RCC_APB1RSTR1_TIM7RST (1 << 5)RCC_AHB2RSTR_GPIOCRST (1 << 2)__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1RCC_CSR_FWRSTF (1 << 24)__USACCUM_IBIT__ 8ITM_BASE (PPBI_BASE + 0x0000)ST_VREFINT_CAL MMIO16((INFO_BASE + 0x75aa))__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6_STDBOOL_H RCC_APB1SMENR2_OFFSET 0x7cSPI2_CR1 SPI_CR1(SPI2_BASE)RCC_CIFR_PLLSAI1RDYF (1 << 6)__FLT_EVAL_METHOD__ 0RCC_AHB3SMENR MMIO32(RCC_BASE + RCC_AHB3SMENR_OFFSET)unsigned int__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32RCC_APB2ENR_TIM17EN (1 << 18)RCC_CR_PLLON (1 << 24)RCC_BASE (PERIPH_BASE_AHB1 + 0x1000)__ARM_FEATURE_LDREX__UQQ_FBIT__ 8RCC_CFGR_HPRE_SHIFT 4INT16_C__ARM_FP16_ARGS__GCC_IEC_559 0RCC_CSR MMIO32(RCC_BASE + 0x94)RCC_CR_MSIRANGE_MASK 0xfINT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX____LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4spi_enable_crc__STDC__ 1RCC_AHB2SMENR_RNGSMEN (1 << 18)RCC_CCIPR_CLK48SEL_PLL 2RCC_AHB3RSTR_OFFSET 0x30__ARM_FEATURE_IDIV 1RCC_APB2RSTR_SYSCFGRST (1 << 0)__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN____UINT8_TYPE__ unsigned charSPI_I2SCFGR_I2SCFG_SLAVE_TRANSMIT 0x0SPI_CR1_CRCEN (1 << 13)RCC_BDCR_LSECSSD (1 << 6)RCC_APB2ENR_SAI1EN (1 << 21)__ARM_FEATURE_COPROC 15RCC_AHB1SMENR_TSCSMEN (1 << 16)RCC_CICR_HSIRDYC (1 << 3)UINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"INT8_MIN__ORDER_PDP_ENDIAN__ 3412RCC_PLLCFGR_PLLM_SHIFT 0x4RCC_APB1SMENR1_CAN1SMEN (1 << 25)SPI2_I2SPR SPI_I2SPR(SPI2_BASE)PERIPH_BASE (0x40000000U)true 1spi_send__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)RCC_AHB1ENR_OFFSET 0x48RCC_APB1RSTR2_LPUART1RST (1 << 0)__FLT32X_MIN_EXP__ (-1021)long intINT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1RCC_CFGR_SW_PLL 0x3__GCC_ATOMIC_CHAR_LOCK_FREE 2RCC_CR_CSSON (1 << 19)RCC_AHB2ENR_OFFSET 0x4c__LFRACT_EPSILON__ 0x1P-31LRFMC1_BANK_BASE (0x60000000U)STM32L4 1RCC_PLLCFGR_PLLQ_MASK 0x3RCC_APB1SMENR1_TIM7SMEN (1 << 5)RCC_APB1SMENR1_OPAMPSMEN (1 << 30)SPI_SR_OVR (1 << 6)__ARM_SIZEOF_MINIMAL_ENUM 1RCC_APB1ENR1_TIM2EN (1 << 0)SPI_SR_FRLVL_FIFO_FULL (0x3 << 9)__FLT32X_NORM_MAX__ 1.7976931348623157e+308F32x__arm__ 1RCC_CR MMIO32(RCC_BASE + 0x00)RCC_CCIPR_LPTIMxSEL_APB 0RCC_CFGR_HPRE_MASK 0xf__FLT32_MIN_10_EXP__ (-37)RCC_APB1RSTR2_LPTIM2RST (1 << 5)SPI2 SPI2_BASEMMIO64(addr) (*(volatile uint64_t *)(addr))__ARM_FP16_FORMAT_ALTERNATIVERCC_ICSCR_HSITRIM_MASK 0x1fRCC_APB1RSTR1_LCDRST (1 << 9)__LDBL_NORM_MAX__ 1.7976931348623157e+308LRCC_PLLCFGR_PLLR_DIV4 1INTPTR_MINRST_FMCDESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)RCC_APB1ENR1_LPTIM1EN (1 << 31)RCC_CCIPR_LPTIMxSEL_LSE 3RCC_CCIPR_ADCSEL_SHIFT 28RCC_CFGR_PPRE2_NODIV 0x0__TA_IBIT__ 64RCC_CCIPR_USARTxSEL_APB 0SPI_CR2_TXDMAEN (1 << 1)RCC_APB1SMENR1_I2C3SMEN (1 << 23)SPI_CR2_DS_16BIT (0xF << 8)SPI_CR2_DS_7BIT (0x6 << 8)__SACCUM_IBIT__ 8RCC_AHB2SMENR_GPIOASMEN (1 << 0)RCC_APB1ENR1_TIM5EN (1 << 3)__ARM_FEATURE_QRDMXRCC_CFGR_PPRE2_DIV8 0x6RCC_CCIPR_LPTIM1SEL_SHIFT 18RCC_APB1ENR1_I2C3EN (1 << 23)__ARM_ARCH_ISA_THUMB 2__LDBL_HAS_DENORM__ 1RCC_APB1SMENR2_LPTIM2SMEN (1 << 5)WCHAR_MIN __WCHAR_MIN__RCC_APB1RSTR1_PWRRST (1 << 28)BIT14 (1<<14)__WINT_WIDTH__ 32SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__SPI_I2SCFGR_DATLEN_LSB 1RST_TSCBIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1RCC_AHB2ENR_GPIOFEN (1 << 5)_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN____SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__DBL_MIN_EXP__ (-1021)RCC_APB1ENR1_TIM7EN (1 << 5)spi_disable_crcRCC_CFGR_PPRE1_DIV8 0x6RCC_AHB2RSTR_RNGRST (1 << 18)RCC_PLLCFGR_PLLM_MASK 0x7INT8_MIN (-INT8_MAX - 1)SPI2_CRCPR SPI_CRCPR(SPI2_BASE)RCC_APB1SMENR1_TIM3SMEN (1 << 1)RCC_AHB2ENR MMIO32(RCC_BASE + RCC_AHB2ENR_OFFSET)__FLT32_DIG__ 6SPI_CR1_CPHA (1 << 0)INT_LEAST16_MAXSPI1_SR SPI_SR(SPI1_BASE)RCC_APB2RSTR_SDMMC1RST (1 << 10)RCC_CIER_PLLSAI2RDYIE (1 << 7)INT_FAST64_MIN (-INT_FAST64_MAX - 1)RCC_AHB2RSTR_OFFSET 0x2cFIREWALL_BASE (PERIPH_BASE_APB2 + 0x1C00)SPI_SR_FTLVL_FIFO_FULL (0x3 << 11)RCC_AHB2RSTR_GPIOBRST (1 << 1)VREFBUF_BASE (PERIPH_BASE_APB2 + 0x0030)BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1INT32_MAXRST_SAI2RCC_APB1ENR1_CAN1EN (1 << 25)RCC_APB2ENR_FWEN (1 << 7)__ACCUM_MIN__ (-0X1P15K-0X1P15K)RCC_ICSCR_MSITRIM_MASK 0xffRCC_CIER MMIO32(RCC_BASE + 0x18)__ARM_FEATURE_CRYPTO__INT_LEAST32_TYPE__ long intRCC_CFGR_HPRE_DIV4 0x9BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULLRST_SAI1__FRACT_IBIT__ 0RCC_AHB2RSTR MMIO32(RCC_BASE + RCC_AHB2RSTR_OFFSET)RCC_AHB3RSTR_QSPIRST (1 << 8)UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234RCC_CR_MSIRANGE_4MHZ 6ADC1_BASE (0x50000000U + 0x40000)__FLT_NORM_MAX__ 3.4028234663852886e+38FRST_OTGFSRCC_APB1SMENR2_LPUART1SMEN (1 << 0)long long unsigned int__FLT_MIN_10_EXP__ (-37)BIT31 (1<<31)__ULACCUM_IBIT__ 32RCC_CIER_LSERDYIE (1 << 1)__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__ULLACCUM_EPSILON__ 0x1P-32ULLK__APCS_32__ 1__DQ_FBIT__ 63SPI_CR1_BAUDRATE_FPCLK_DIV_2 (0x00 << 3)INT_LEAST64_MAXuint16_tSPI_CR2_RXNEIE (1 << 6)reg32_REG_BIT(base,bit) (((base) << 5) + (bit))__UHQ_IBIT__ 0TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)INT_LEAST8_MINRCC_AHB2ENR_AESEN (1 << 16)BIT29 (1<<29)RCC_APB1RSTR1_I2C2RST (1 << 22)__INT_FAST16_TYPE__ intSPI3_I2SPR SPI_I2SPR(SPI3_BASE)SPI1 SPI1_BASE__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)__ULFRACT_MAX__ 0XFFFFFFFFP-32ULRRST_SPI2__UINT_LEAST16_TYPE__ short unsigned intRCC_APB1RSTR1_UART4RST (1 << 19)RCC_CCIPR_I2C3SEL_SHIFT 16__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned intRCC_CCIPR_USARTxSEL_SYS 1RCC_APB2SMENR_TIM17SMEN (1 << 18)__FLT32X_DIG__ 15SPI_I2SCFGR_CHLEN (1 << 0)SPI_CR2_SSOE (1 << 2)SPI3_CRCPR SPI_CRCPR(SPI3_BASE)__UTQ_FBIT__ 128spi_send_lsb_firstSPI_CR1_BAUDRATE_FPCLK_DIV_4 (0x01 << 3)__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffffRCC_BDCR_RTCSEL_MASK 0x3DMA2_BASE (PERIPH_BASE_AHB1 + 0x0400)PTRDIFF_MAX __PTRDIFF_MAX____SIZEOF_SHORT__ 2RCC_CFGR_SWS_HSI16 0x1SPI_CR1_BR_FPCLK_DIV_2 0x0SPI_CR2_DS_5BIT (0x4 << 8)../common/spi_common_all.cRCC_AHB1SMENR_CRCSMEN (1 << 12)RCC_APB1ENR1 MMIO32(RCC_BASE + RCC_APB1ENR1_OFFSET)__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKRCC_CCIPR_SAIxSEL_PLL 2RCC_PLLCFGR_PLLM(x) ((x)-1)RCC_APB1ENR2 MMIO32(RCC_BASE + RCC_APB1ENR2_OFFSET)UINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRRCC_BDCR_RTCSEL_LSE 1RCC_APB1SMENR1_SPI2SMEN (1 << 14)__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intRCC_AHB2ENR_RNGEN (1 << 18)RCC_AHB2ENR_GPIOGEN (1 << 6)SPI_CR2_FRXTH (1 << 12)RCC_APB1RSTR1_TIM3RST (1 << 1)RCC_APB1ENR1_TIM4EN (1 << 2)WCHAR_MINRCC_CRRCR MMIO32(RCC_BASE + 0x98)RCC_CFGR_SWS_PLL 0x3BEGIN_DECLS RCC_CFGR_PPRE1_DIV16 0x7RCC_CFGR_PPRE2_DIV4 0x5RST_TIM2RCC_AHB2ENR_GPIOCEN (1 << 2)RCC_APB2RSTR_SPI1RST (1 << 12)RCC_CIFR_HSERDYF (1 << 4)RST_LPUART1RCC_AHB1ENR_CRCEN (1 << 12)SPI1_RXCRCR SPI_RXCRCR(SPI1_BASE)RCC_CCIPR_USARTxSEL_HSI16 2spi_set_slave_mode__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15RCC_APB2SMENR_SPI1SMEN (1 << 12)__FLT32X_MAX__ 1.7976931348623157e+308F32xspi_set_nss_lowRCC_APB1ENR1_OFFSET 0x58SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE (1 << 1)__FLT32_MIN__ 1.1754943508222875e-38F32RCC_PLLCFGR_PLLQEN (1 << 20)INT16_MINspi_disable_tx_dma__FLT_IS_IEC_60559__ 2__THUMBEL__ 1__ARM_FEATURE_DSP 1RST_ADCRCC_APB1SMENR1_DAC1SMEN (1 << 29)TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)__QQ_IBIT__ 0RCC_AHB2ENR_OTGFSEN (1 << 12)RCC_CR_MSIRANGE_100KHZ 0RCC_CCIPR_LPTIM2SEL_SHIFT 20RCC_CCIPR_DFSDMSEL (1 << 31)RST_CAN1SPI_CR1_BAUDRATE_FPCLK_DIV_16 (0x03 << 3)__LLACCUM_FBIT__ 31RCC_APB2ENR MMIO32(RCC_BASE + RCC_APB2ENR_OFFSET)__UINTMAX_TYPE__ long long unsigned intLIBOPENCM3_RCC_COMMON_ALL_H DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 0x14)__USQ_IBIT__ 0SPI_SR_FRLVL_QUARTER_FIFO (0x1 << 9)RCC_ICSCR_HSICAL_SHIFT 16__UINT_LEAST32_TYPE__ long unsigned intRCC_AHB1RSTR_TSCRST (1 << 16)__ARM_FEATURE_NUMERIC_MAXMINTIM4_BASE (PERIPH_BASE_APB1 + 0x0800)__INTMAX_TYPE__ long long int__GCC_ATOMIC_INT_LOCK_FREE 2RCC_APB2RSTR_TIM17RST (1 << 18)RCC_APB1RSTR1_TIM5RST (1 << 3)TIM16_BASE (PERIPH_BASE_APB2 + 0x4400)RCC_ICSCR_HSITRIM_SHIFT 24INTMAX_MAXspi_set_baudrate_prescalerSPI_CR1_CRCNEXT (1 << 12)DESIG_PACKAGE MMIO16((INFO_BASE + 0x7500))__ARM_ARCH_7EM__ 1__ARM_FEATURE_FP16_SCALAR_ARITHMETICRCC_CFGR_MCO_LSE 0x7__USACCUM_EPSILON__ 0x1P-8UHKspi_enable_error_interruptUINT_FAST64_MAX __UINT_FAST64_MAX__TIM17_BASE (PERIPH_BASE_APB2 + 0x4800)__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CSPI2_SR SPI_SR(SPI2_BASE)RCC_CIER_PLLRDYIE (1 << 5)RCC_PLLCFGR_PLLSRC_MSI 1RCC_APB1SMENR1_SPI3SMEN (1 << 15)RCC_CCIPR_SAIxSEL_PLLSAI2P 1INT64_MINSPI_CR2_ERRIE (1 << 5)__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intRCC_CFGR_SW_MSI 0x0UINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRRCC_APB2ENR_OFFSET 0x60RCC_APB2SMENR_SAI2SMEN (1 << 22)RCC_PLLCFGR_PLLQ_DIV8 3/build/libopencm3/lib/stm32/l4__SIZEOF_SIZE_T__ 4RCC_APB2ENR_SDMMC1EN (1 << 10)__UINT64_TYPE__ long long unsigned int__INT64_C(c) c ## LL__LDBL_MIN_10_EXP__ (-307)USART1_BASE (PERIPH_BASE_APB2 + 0x3800)USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x6800)RCC_APB2ENR_TIM16EN (1 << 17)RCC_APB1SMENR1_UART5SMEN (1 << 20)MPU_BASE (SCS_BASE + 0x0D90)RCC_CCIPR_UART4SEL_SHIFT 6__ARM_FEATURE_CDE__ACCUM_IBIT__ 16RCC_CR_MSIRANGE_32MHZ 10RCC_AHB2ENR_GPIOAEN (1 << 0)SPI3_DR SPI_DR(SPI3_BASE)CORESIGHT_LAR_OFFSET 0xfb0EXTI_BASE (PERIPH_BASE_APB2 + 0x0400)RCC_AHB1RSTR_DMA1RST (1 << 0)SPI_CR1_BR_FPCLK_DIV_16 0x3FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000)short intRNG_BASE (0x50000000U + 0x60800)RCC_CSR_RESET_FLAGS (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF | RCC_CSR_IWDGRSTF | RCC_CSR_SFTRSTF | RCC_CSR_BORRSTF | RCC_CSR_PINRSTF | RCC_CSR_OBLRSTF | RCC_CSR_FWRSTF)__FLT32_IS_IEC_60559__ 2RCC_CSR_MSIRANGE_SHIFT 8__UINT16_C(c) cSPI_SR_RXNE (1 << 0)__UDA_IBIT__ 32modeRCC_PLLCFGR_PLLQ_SHIFT 21UINT_LEAST32_MAXRCC_PLLSAI2_CFGR MMIO32(RCC_BASE + 0x14)BIT2 (1<<2)INT64_C__ATOMIC_RELAXED 0__ARM_FEATURE_COPROCRCC_BDCR_LSEDRV_LOW 0RCC_CCIPR_CLK48SEL_MASK 0x3__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53RCC_CCIPR_UARTxSEL_SYS RCC_CCIPR_USARTxSEL_SYSSPI1_CR2 SPI_CR2(SPI1_BASE)CORESIGHT_LSR_SLI (1<<0)BIT5 (1<<5)BIT1 (1<<1)INT8_CGPIO_PORT_H_BASE (PERIPH_BASE_AHB2 + 0x1c00)INT_LEAST32_MAX__ARM_ARCH_EXT_IDIV__ 1SPI_RXCRCR(spi_base) MMIO32((spi_base) + 0x14)SPI_CR1_BIDIMODE_1LINE_BIDIR (1 << 15)SPI_SR_CHSIDE (1 << 2)__DBL_DECIMAL_DIG__ 17RCC_CSR_MSIRANGE_2MHZ 5LIBOPENCM3_SPI_H BIT8 (1<<8)RST_TIM7RCC_CRRCR_HSI48ON (1 << 0)RST_TIM8SPI_CR1_BAUDRATE_FPCLK_DIV_256 (0x07 << 3)INT16_C(c) __INT16_C(c)RCC_CCIPR_CLK48SEL_HSI48 0spi_set_clock_polarity_0spi_set_clock_polarity_1RCC_APB1SMENR1_I2C2SMEN (1 << 22)__INT16_MAX__ 0x7fffRST_USBRCC_BDCR_LSEBYP (1 << 2)TIM15_BASE (PERIPH_BASE_APB2 + 0x4000)RCC_AHB2SMENR_GPIOFSMEN (1 << 5)SPI_CR1_BR_FPCLK_DIV_64 0x5RCC_CIFR_HSI48RDYF (1 << 10)__INT_WIDTH__ 32__ARM_FEATURE_SIMD32 1DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x75e0)spi_resetRCC_APB1SMENR1_WWDGSMEN (1 << 11)RCC_CR_HSEBYP (1 << 18)__QQ_FBIT__ 7RCC_CR_PLLSAI2RDY (1 << 29)RTC_BASE (PERIPH_BASE_APB1 + 0x2800)__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64RCC_AHB2SMENR_OTGFSSMEN (1 << 12)baudrateRCC_BDCR_BDRST (1 << 16)__UTA_IBIT__ 64__ULLACCUM_IBIT__ 32SPI_SR_FRE (1 << 8)RCC_CICR_CSSC (1 << 8)__ULLFRACT_EPSILON__ 0x1P-64ULLRfalse 0SPI_CR2(spi_base) MMIO32((spi_base) + 0x04)SPI_SR_MODF (1 << 5)__SIZEOF_WINT_T__ 4RCC_APB1ENR1_I2C2EN (1 << 22)SPI_CR1_SSI (1 << 8)__ARM_FEATURE_UNALIGNED 1__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17RCC_CFGR_PPRE1_MASK 0x7__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1SPI_I2SCFGR_I2SSTD_MSB_JUSTIFIED 0x1__FLT32X_HAS_DENORM__ 1__ULLACCUM_MIN__ 0.0ULLKSPI5 SPI5_BASE__INT_FAST32_WIDTH__ 32SPI1_CR1 SPI_CR1(SPI1_BASE)SPI_SR_FTLVL_FIFO_EMPTY (0x0 << 11)RCC_APB1RSTR1_SPI3RST (1 << 15)RCC_CCIPR_I2CxSEL_HSI16 2RCC_CCIPR_SWPMI1SEL (1 << 30)__ARM_ASM_SYNTAX_UNIFIED__ 1RCC_BDCR MMIO32(RCC_BASE + 0x90)SPI_I2SCFGR_I2SSTD_PCM 0x3SPI_I2SCFGR_I2SSTD_LSB 4SPI_I2SCFGR_I2SMOD (1 << 11)__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODRCC_APB1ENR1_SPI3EN (1 << 15)RCC_APB2SMENR_TIM16SMEN (1 << 17)RCC_CFGR_MCOPRE_DIV2 1RCC_CSR_LPWRRSTF (1 << 31)__DBL_HAS_QUIET_NAN__ 1RST_I2C1spi_enable_tx_buffer_empty_interrupt__SIZEOF_POINTER__ 4RCC_PLLCFGR MMIO32(RCC_BASE + 0x0c)__ULLFRACT_MIN__ 0.0ULLRRCC_CCIPR_LPTIMxSEL_LSI 1RCC_CFGR_SW_HSI16 0x1LPUART1_BASE (PERIPH_BASE_APB1 + 0x8000)RCC_CCIPR_SAI2SEL_SHIFT 24INT_LEAST64_MIN__GCC_CONSTRUCTIVE_SIZE 64__LLFRACT_IBIT__ 0RCC_APB1SMENR2_SWPMI1SMEN (1 << 2)RCC_AHB2SMENR_ADCSMEN (1 << 13)RCC_ICSCR_MSITRIM_SHIFT 8uint32_tRCC_AHB1SMENR_DMA2SMEN (1 << 1)BIT12 (1<<12)RCC_PLLCFGR_PLLR_DIV8 3RCC_CFGR_HPRE_DIV128 0xdDFSDM_BASE (PERIPH_BASE_APB2 + 0x6000)__SACCUM_EPSILON__ 0x1P-7HKRCC_CFGR_PPRE1_DIV4 0x5__GCC_ASM_FLAG_OUTPUTS__ 1RST_DAC1ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0x75a8))__ARM_FP 4LPTIM2_BASE (PERIPH_BASE_APB1 + 0x9400)BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)SPI3_SR SPI_SR(SPI3_BASE)__UINT_FAST16_TYPE__ unsigned intRCC_CCIPR_UARTxSEL_LSE RCC_CCIPR_USARTxSEL_LSE__UHA_IBIT__ 8RCC_CCIPR_CLK48SEL_MSI 3SPI_TXCRCR(spi_base) MMIO32((spi_base) + 0x18)__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULK__LDBL_DIG__ 15POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXBIT16 (1<<16)SPI1_I2SPR SPI_I2SPR(SPI1_BASE)__WINT_MIN__ 0UINT_LEAST16_MINSPI_I2SCFGR_CKPOL (1 << 3)__FLT64_DIG__ 15RCC_APB2ENR_TIM1EN (1 << 11)__WINT_MAX__ 0xffffffffUBIT22 (1<<22)__INT_LEAST8_WIDTH__ 8RCC_APB1RSTR2 MMIO32(RCC_BASE + RCC_APB1RSTR2_OFFSET)WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)RCC_AHB2SMENR_GPIOBSMEN (1 << 1)__INT_LEAST16_TYPE__ short intRCC_AHB3SMENR_FMCSMEN (1 << 0)__FLT_HAS_DENORM__ 1SPI1_CRCPR SPI_CRCPR(SPI1_BASE)__DBL_MAX__ ((double)1.7976931348623157e+308L)SPI_CR1(spi_base) MMIO32((spi_base) + 0x00)INT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1RST_TIM1UINTMAX_CRST_TIM3RST_TIM4RST_TIM5RST_TIM6INT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1RST_FLASHspi_send_msb_firstRCC_APB2ENR_SAI2EN (1 << 22)__HQ_FBIT__ 15__bool_true_false_are_defined 1BIT26 (1<<26)RCC_AHB3SMENR_QSPISMEN (1 << 8)RCC_CR_MSIRANGE_200KHZ 1RCC_BDCR_LSCOEN (1 << 24)__SIZE_MAX__ 0xffffffffUSPI2_BASE (PERIPH_BASE_APB1 + 0x3800)RCC_CR_MSIPLLEN (1 << 2)RCC_PLLCFGR_PLLR_SHIFT 25RCC_CFGR_PPRE2_MASK 0x7__ARM_ARCHRCC_CCIPR_SAIxSEL_EXT 3__LONG_MAX__ 0x7fffffffLRCC_APB2RSTR_TIM1RST (1 << 11)RCC_APB1RSTR1_LPTIM1RST (1 << 31)SPI_SR_FRLVL_FIFO_EMPTY (0x0 << 9)SPI_CR2_DS_6BIT (0x5 << 8)spi_set_master_modeRCC_CCIPR_USART1SEL_MASK 0x3SAI2_BASE (PERIPH_BASE_APB2 + 0x5800)INT_FAST16_MINRCC_CFGR_PPRE1_NODIV 0x0__ARM_FEATURE_LDREX 7PTRDIFF_MAXRCC_CCIPR MMIO32(RCC_BASE + 0x88)RCC_PLLCFGR_PLLP_DIV7 0RCC_PLLCFGR_PLLN_SHIFT 0x8__LLFRACT_EPSILON__ 0x1P-63LLRSPI3 SPI3_BASE__SFRACT_MAX__ 0X7FP-7HR__FLT32X_MANT_DIG__ 53RCC_CCIPR_USARTxSEL_MASK 0x3RCC_APB1RSTR1_TIM2RST (1 << 0)__WCHAR_WIDTH__ 32RCC_CFGR_MCO_LSI 0x6WINT_MAX__INT16_C(c) cspi_enableRCC_APB1ENR2_SWPMI1EN (1 << 2)INT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32__PTRDIFF_WIDTH__ 32spi_disable_ss_outputRCC_CSR_MSIRANGE_1MHZ 4RST_USART1RST_USART2RST_USART3__ATOMIC_ACQ_REL 4SPI_CR2_TXEIE (1 << 7)SPI6 SPI6_BASE__HQ_IBIT__ 0__DBL_MIN_10_EXP__ (-307)SPI3_DR8 SPI_DR8(SPI3_BASE)dataRCC_CFGR_MCO_HSI16 0x3SPI_CR1_CPHA_CLK_TRANSITION_2 (1 << 0)RCC_CFGR_SW_SHIFT 0RCC_APB1RSTR1_DAC1RST (1 << 29)SPI3_CR2 SPI_CR2(SPI3_BASE)RST_PWRRCC_PLLCFGR_PLLSRC_MASK 0x3spi_set_clock_phase_0__FLT32_NORM_MAX__ 3.4028234663852886e+38F32RCC_APB1SMENR1 MMIO32(RCC_BASE + RCC_APB1SMENR1_OFFSET)RCC_APB2SMENR_OFFSET 0x80RCC_CFGR_MCO_SYSCLK 0x1SPI_CR1_CRCL_8BIT (0 << 11)UINT64_C(c) __UINT64_C(c)RCC_APB2RSTR_TIM8RST (1 << 13)RCC_APB2RSTR_TIM16RST (1 << 17)__UINTMAX_MAX__ 0xffffffffffffffffULLRCC_CCIPR_ADCSEL_PLLSAI2R 2__DBL_MANT_DIG__ 53SPI_CR1_BR_FPCLK_DIV_32 0x4__ULFRACT_IBIT__ 0RCC_PLLCFGR_PLLQ_DIV4 1INT_FAST16_MAXITR_BASE (SCS_BASE + 0x0000)SPI_SR(spi_base) MMIO32((spi_base) + 0x08)QUADSPI_BANK_BASE (0x90000000U)__ARM_EABI__ 1__INT_LEAST64_TYPE__ long long intRCC_AHB2RSTR_GPIOFRST (1 << 5)RCC_CFGR MMIO32(RCC_BASE + 0x08)__ARM_FEATURE_CDE_COPROCRST_ADC1SPI_CR2_NSSP (1 << 3)UINT32_CRCC_CFGR_MCOPRE_DIV16 4GCC: (15:12.2.rel1-1) 12.2.1 20221205˙˙˙˙| 0 & A3aeabi)7E-M M "ń˙ , !!""##$$%%&&''(())**++,,--..//00112233445566778899::;=>@BDZ\FHJLNPRTVX^?pˇÓ8lĄ Ý ]` 0, 7 C&U_ hqz • ±Ů ! = V o ‰ !Ż"Ô #ĺ $ő % &'6 (J )] *v +Ź ,Ą -» .ŕ / 0/ 1Y 2t 3 4Ą 5» 6Í 7ŕ 8ň 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../common/usr/lib/gcc/arm-none-eabi/12.2.1/include../../../include/libopencm3/stm32../../../include/libopencm3/cm3../../../include/libopencm3/stm32/l4../../../include/libopencm3/stm32/commonspi_common_v2.cstdint.hspi.hcommon.hstdbool.hmemorymap.hmemorymap.hmemorymap.hspi.hspi_common_v2.hspi_common_all.hrcc.hrcc.hrcc_common_all.hÍ!#z . . 0=" á 0!é 0 !÷ =‚ =Ť!-3. "™ =¤ =RCC_ICSCR MMIO32(RCC_BASE + 0x04)RCC_CICR_PLLRDYC (1 << 5)SCB_BASE (SCS_BASE + 0x0D00)__UHA_FBIT__ 8USB_OTG_FS_BASE (0x50000000U + 0x00000)RCC_APB2SMENR MMIO32(RCC_BASE + RCC_APB2SMENR_OFFSET)__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64RCC_APB1ENR1_TIM2EN (1 << 0)CORESIGHT_LSR_SLK (1<<1)__GCC_ATOMIC_WCHAR_T_LOCK_FREE 2LCD_BASE (PERIPH_BASE_APB1 + 0x2400)__CHAR_UNSIGNED__ 1RCC_CSR_LSION (1 << 0)USART3_BASE (PERIPH_BASE_APB1 + 0x4800)RCC_AHB2RSTR_GPIOHRST (1 << 7)RCC_AHB2ENR_GPIOCEN (1 << 2)RCC_CFGR_MCO_MSI 0x2SPI_CR2_DS_14BIT (0xD << 8)__FLT64_HAS_INFINITY__ 1RCC_APB1SMENR1_USART3SMEN (1 << 18)spi_init_master__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GNUC_MINOR__ 2__GCC_DESTRUCTIVE_SIZE 64__LACCUM_EPSILON__ 0x1P-31LKRCC_CIFR_LSECSSF (1 << 9)__PTRDIFF_MAX__ 0x7fffffff__ARM_FEATURE_FMA 1SPI2_RXCRCR SPI_RXCRCR(SPI2_BASE)__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)RCC_CR_MSIRANGE_800KHZ 3RCC_AHB3RSTR_FMCRST (1 << 0)__INTMAX_MAX__ 0x7fffffffffffffffLLADC1_BASE (0x50000000U + 0x40000)__FLT64_DECIMAL_DIG__ 17WINT_MIN __WINT_MIN__INT_FAST64_MAXOPAMP_BASE (PERIPH_BASE_APB1 + 0x7800)SPI1_I2SCFGR SPI_I2SCFGR(SPI1_BASE)__ATOMIC_CONSUME 1__ULACCUM_FBIT__ 32__WCHAR_MAX__ 0xffffffffURCC_APB1SMENR1_PWRSMEN (1 << 28)SPI2_DR SPI_DR(SPI2_BASE)RCC_PLLCFGR_PLLR_DIV6 2RCC_AHB2ENR_GPIODEN (1 << 3)SPI_CR2_DS_12BIT (0xB << 8)RCC_AHB1ENR_DMA1EN (1 << 0)RCC_AHB2SMENR_GPIOCSMEN (1 << 2)INT64_MAX __INT64_MAX__INTMAX_MIN__SIZEOF_LONG_LONG__ 8SPI_CR1_MSTR (1 << 2)__DBL_MAX_10_EXP__ 308__FRACT_MIN__ (-0.5R-0.5R)__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLK__USACCUM_MAX__ 0XFFFFP-8UHK__SFRACT_FBIT__ 7__INTMAX_WIDTH__ 64__ARM_FEATURE_BF16_SCALAR_ARITHMETIC__SQ_IBIT__ 0__ORDER_PDP_ENDIAN__ 3412__SIZE_TYPE__ unsigned intRCC_AHB1ENR_FLASHEN (1 << 8)SPI_CR1_BR_FPCLK_DIV_8 0x2__FLT_HAS_DENORM__ 1__INT8_TYPE__ signed char__FLT32_MIN__ 1.1754943508222875e-38F32__USACCUM_MIN__ 0.0UHKRCC_APB1SMENR1_I2C2SMEN (1 << 22)__FLT32_DECIMAL_DIG__ 9SPI_CR2_DS_9BIT (0x8 << 8)__DECIMAL_DIG__ 17__LDBL_MIN_EXP__ (-1021)INT_FAST16_MIN__LDBL_MANT_DIG__ 53SPI_SR_CRCERR (1 << 4)INT64_MIN (-INT64_MAX - 1)RCC_CFGR_STOPWUCK_MSI (0 << 15)RCC_APB2SMENR_SDMMC1SMEN (1 << 10)__UINT8_C(c) c__INT16_TYPE__ short inttrue 1RCC_APB1RSTR1 MMIO32(RCC_BASE + RCC_APB1RSTR1_OFFSET)__FLT64_MAX__ 1.7976931348623157e+308F64SPI_CR1_RXONLY (1 << 10)RCC_CCIPR_ADCSEL_PLLSAI1R 1UINT_FAST32_MAXRCC_CFGR_MCO_HSE 0x4SPI_I2SCFGR_I2SCFG_MASTER_RECEIVE 0x3RCC_CIER_LSIRDYIE (1 << 0)RCC_APB1RSTR2_OFFSET 0x3cRCC_PLLCFGR_PLLSRC_NONE 0SPI_I2SPR_ODD (1 << 8)INT_FAST64_MAX __INT_FAST64_MAX__RCC_CR_MSION (1 << 0)__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1RCC_CR_MSIRANGE_48MHZ 11__UINT_LEAST16_MAX__ 0xffff__STDC_HOSTED__ 1__ULLFRACT_FBIT__ 64__SIG_ATOMIC_TYPE__ intRCC_CICR_LSECSSC (1 << 9)RCC_PLLSAI1_CFGR MMIO32(RCC_BASE + 0x10)RCC_CIFR_CSSF (1 << 8)__INT_FAST64_TYPE__ long long int__WINT_TYPE__ unsigned intGPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800)ST_TSENSE_CAL2_110C MMIO16((INFO_BASE + 0x75ca))RCC_CFGR_MCO_PLL 0x5INT32_MIN (-INT32_MAX - 1)__FLT32_MAX_10_EXP__ 38RCC_CFGR_HPRE_DIV8 0xaRCC_APB1ENR1_TIM3EN (1 << 1)RCC_APB2SMENR_SYSCFGSMEN (1 << 0)RCC_BDCR_LSEDRV_MASK 0x3__USFRACT_MAX__ 0XFFP-8UHRLPTIM1_BASE (PERIPH_BASE_APB1 + 0x7c00)__FP_FAST_FMAF32 1RCC_APB1SMENR1_TIM5SMEN (1 << 3)__UINTPTR_MAX__ 0xffffffffU__FLT32_MIN_EXP__ (-125)SPI_CR2_LDMA_TX (1 << 14)RCC_APB1ENR2_SWPMI1EN (1 << 2)RCC_APB2SMENR_TIM15SMEN (1 << 16)SPI_I2SCFGR_I2SCFG_LSB 8SPI_CR1_BR_FPCLK_DIV_128 0x6UINT32_MAX __UINT32_MAX__RCC_CIER_MSIRDYIE (1 << 2)RCC_APB2RSTR_DFSDMRST (1 << 24)RCC_AHB1ENR MMIO32(RCC_BASE + RCC_AHB1ENR_OFFSET)__ULFRACT_FBIT__ 32RCC_APB2ENR_USART1EN (1 << 14)__FLT64_MIN_10_EXP__ (-307)RCC_APB1SMENR1_LPTIM1SMEN (1 << 31)__GNUC_EXECUTION_CHARSET_NAME "UTF-8"RCC_CIFR MMIO32(RCC_BASE + 0x1c)BIT10 (1<<10)__INT_FAST64_WIDTH__ 64__STDC_VERSION__ 199901LINT_LEAST64_MAX __INT_LEAST64_MAX__RCC_CCIPR_SAI1SEL_SHIFT 22RCC_AHB2SMENR MMIO32(RCC_BASE + RCC_AHB2SMENR_OFFSET)SPI_CR2_DS_15BIT (0xE << 8)cpha__SFRACT_EPSILON__ 0x1P-7HRSPI_CR2_DS_4BIT (0x3 << 8)UINT_LEAST16_MAX __UINT_LEAST16_MAX__UINT32_C(c) __UINT32_C(c)__ORDER_BIG_ENDIAN__ 4321I2C3_BASE (PERIPH_BASE_APB1 + 0x5c00)SYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000)RCC_APB2SMENR_USART1SMEN (1 << 14)__SQ_FBIT__ 31DWT_BASE (PPBI_BASE + 0x1000)INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)RCC_CR_MSIRGSEL (1 << 3)SPI_I2SPR_MCKOE (1 << 9)__TQ_IBIT__ 0SPI3_CR1 SPI_CR1(SPI3_BASE)spi_fifo_reception_threshold_16bitRCC_APB1ENR2_LPTIM2EN (1 << 5)__FLT64_MIN_EXP__ (-1021)RCC_AHB1RSTR_CRCRST (1 << 12)__PTRDIFF_WIDTH__ 32__UINT_FAST8_MAX__ 0xffffffffURCC_CFGR_PPRE1_DIV2 0x4RCC_APB1ENR1_OPAMPEN (1 << 30)RCC_APB2ENR_TIM15EN (1 << 16)UINT16_C(c) __UINT16_C(c)__LACCUM_IBIT__ 32RCC_CSR_SFTRSTF (1 << 28)SPI_CR1_BR_FPCLK_DIV_256 0x7RCC_CCIPR_UARTxSEL_HSI16 RCC_CCIPR_USARTxSEL_HSI16__INT_FAST16_WIDTH__ 32INTMAX_C__VERSION__ "12.2.1 20221205"RCC_CCIPR_I2C2SEL_SHIFT 14__VFP_FP__ 1SPI_CR1_BAUDRATE_FPCLK_DIV_128 (0x06 << 3)__LLFRACT_MIN__ (-0.5LLR-0.5LLR)INT_FAST8_MAX__UINT_FAST16_MAX__ 0xffffffffURCC_APB1SMENR1_TIM6SMEN (1 << 4)RCC_CFGR_PPRE2_DIV2 0x4__INTPTR_MAX__ 0x7fffffffINT64_C(c) __INT64_C(c)RCC_CIER_LSE_CSSIE (1 << 9)SPI_I2SCFGR_I2SSTD_LSB_JUSTIFIED 0x2SPI_I2SCFGR_I2SSTD_I2S_PHILIPS 0x0__GCC_IEC_559_COMPLEX 0PERIPH_BASE (0x40000000U)RCC_AHB2SMENR_GPIOHSMEN (1 << 7)SPI4 SPI4_BASERCC_CFGR_MCO_SHIFT 24WCHAR_MAX __WCHAR_MAX__RCC_APB2SMENR_TIM8SMEN (1 << 13)__FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX__RCC_CSR_MSIRANGE_4MHZ 6__UINT_LEAST8_TYPE__ unsigned charRCC_AHB2ENR_GPIOEEN (1 << 4)RCC_APB1RSTR1_I2C1RST (1 << 21)SPI_DR(spi_base) MMIO32((spi_base) + 0x0c)RCC_APB1RSTR2_LPUART1RST (1 << 0)__ACCUM_FBIT__ 15PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)__UACCUM_IBIT__ 16long intUINT8_MAXIWDG_BASE (PERIPH_BASE_APB1 + 0x3000)SIZE_MAX __SIZE_MAX__RCC_CICR_PLLSAI2RDYC (1 << 7)__INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17RCC_CCIPR_CLK48SEL_SHIFT 26__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1RCC_APB1ENR1_I2C1EN (1 << 21)RCC_CR_MSIRANGE_400KHZ 2__FLT32X_EPSILON__ 2.2204460492503131e-16F32xRCC_ICSCR_MSICAL_MASK 0xffRCC_CCIPR_SAIxSEL_PLLSAI1P 0NVIC_BASE (SCS_BASE + 0x0100)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32USART2_BASE (PERIPH_BASE_APB1 + 0x4400)__UINTMAX_C(c) c ## ULLRCC_PLLCFGR_PLLN_MASK 0x7f__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed charRCC_AHB1RSTR MMIO32(RCC_BASE + RCC_AHB1RSTR_OFFSET)spi_read8__GCC_ATOMIC_BOOL_LOCK_FREE 2BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON____FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX____THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRRCC_APB1SMENR1_TIM4SMEN (1 << 2)RCC_CSR_MSIRANGE_8MHZ 7short unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)BIT7 (1<<7)BIT17 (1<<17)__FLT32X_MIN_10_EXP__ (-307)UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)__DBL_IS_IEC_60559__ 2__UINT_FAST32_MAX__ 0xffffffffU__DEC_EVAL_METHOD__ 2__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4RCC_AHB3SMENR_OFFSET 0x70RCC_APB2RSTR_TIM15RST (1 << 16)SPI_CR1_BAUDRATE_FPCLK_DIV_8 (0x02 << 3)SPI_CR1_MSBFIRST (0 << 7)__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32__FLT32X_MIN_EXP__ (-1021)DMA1_BASE (PERIPH_BASE_AHB1 + 0x0000)SPI_I2SCFGR_DATLEN_32BIT 0x2RCC_BDCR_RTCSEL_NONE 0RCC_CIER_PLLSAI1RDYIE (1 << 6)RCC_AHB1RSTR_TSCRST (1 << 16)GNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsRCC_AHB2SMENR_AESSMEN (1 << 16)BIT27 (1<<27)RCC_AHB2ENR_AESEN (1 << 16)TIM1_BASE (PERIPH_BASE_APB2 + 0x2C00)RCC_CCIPR_LPUART1SEL_HSI16 2../common/spi_common_v2.cRCC_CCIPR_USART2SEL_SHIFT 2SPI_DR8(spi_base) MMIO8((spi_base) + 0x0c)SPI_CR2_DS_8BIT (0x7 << 8)__UTA_FBIT__ 64INTMAX_C(c) __INTMAX_C(c)RCC_BDCR_LSESYSDIS (1 << 7)RCC_CIFR_MSIRDYF (1 << 2)__FLT_DECIMAL_DIG__ 9RCC_CRRCR_HSI48RDY (1 << 1)__thumb__ 1__INT_LEAST32_MAX__ 0x7fffffffLLIBOPENCM3_MEMORYMAP_COMMON_H signed charRCC_APB1ENR1_DAC1EN (1 << 29)SPI_SR_BSY (1 << 7)uint8_tINT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)INT32_C(c) __INT32_C(c)SPI3_I2SCFGR SPI_I2SCFGR(SPI3_BASE)__GNUC_STDC_INLINE__ 1SPI_CR2_DS_13BIT (0xC << 8)SPI_CR1_BIDIMODE (1 << 15)__FRACT_FBIT__ 15RCC_ICSCR_MSICAL_SHIFT 0__LLACCUM_EPSILON__ 0x1P-31LLK__GNUC_PATCHLEVEL__ 1__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2PTRDIFF_MINRCC_AHB2RSTR_GPIOGRST (1 << 6)__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)SPI_CR1_BR_FPCLK_DIV_4 0x1RCC_APB1SMENR1_OFFSET 0x78RCC_AHB2RSTR_GPIOARST (1 << 0)UINTPTR_MAX __UINTPTR_MAX____ARM_ARCH_PROFILE 77RCC_CIFR_PLLRDYF (1 << 5)RCC_CCIPR_LPUART1SEL_APB 0RCC_APB2ENR_SAI2EN (1 << 22)GPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000)RCC_APB1ENR1_TIM6EN (1 << 4)__FLT64_MAX_10_EXP__ 308GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400)MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINRCC_PLLCFGR_PLLR_DIV2 0SPI2_I2SCFGR SPI_I2SCFGR(SPI2_BASE)SPI_CR1_LSBFIRST (1 << 7)SDMMC1_BASE (PERIPH_BASE_APB2 + 0x2800)__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)__FRACT_MAX__ 0X7FFFP-15RRCC_CCIPR_LPUART1SEL_LSE 3TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)INT_LEAST32_MAX __INT_LEAST32_MAX__RCC_APB1ENR2_LPUART1EN (1 << 0)SPI_CR1_BIDIMODE_2LINE_UNIDIR (0 << 15)SPI1_DR SPI_DR(SPI1_BASE)__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5RCC_APB1SMENR1_USART2SMEN (1 << 17)RCC_PLLCFGR_PLLSRC_HSE 3SPI_SR_TXE (1 << 1)RCC_APB1ENR1_SPI2EN (1 << 14)RCC_CFGR_SW_HSE 0x2SPI_I2SCFGR_DATLEN_24BIT 0x1RCC_AHB2SMENR_GPIODSMEN (1 << 3)RCC_CFGR_HPRE_MASK 0xfRCC_CR_MSIRANGE_SHIFT 4__UINT16_MAX__ 0xffff__TQ_FBIT__ 127RCC_AHB2RSTR_ADCRST (1 << 13)__FRACT_IBIT__ 0__USQ_FBIT__ 32uint16_tRCC_CR_HSIKERON (1 << 9)SPI_SR_UDR (1 << 3)RCC_CSR_IWDGRSTF (1 << 29)__thumb2__ 1__ULLACCUM_FBIT__ 32FMC_QUADSPI_BASE (0xA0000000U)RCC_AHB2SMENR_SRAM2SMEN (1 << 9)RCC_APB2SMENR_SAI2SMEN (1 << 22)RCC_BDCR_RTCSEL_HSEDIV32 3INT_FAST32_MIN (-INT_FAST32_MAX - 1)RCC_CFGR_MCO_MASK 0xf__STRICT_ANSI__ 1RCC_CFGR_SWS_PLL 0x3FMC3_BANK_BASE (0x80000000U)UINT_LEAST8_MAXUINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)TIM8_BASE (PERIPH_BASE_APB2 + 0x3400)RCC_APB1RSTR1_CAN1RST (1 << 25)__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__RCC_AHB1RSTR_DMA2RST (1 << 1)RCC_BDCR_LSECSSON (1 << 5)SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE (0 << 1)__USA_IBIT__ 16__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1RCC_APB2SMENR_SAI1SMEN (1 << 21)PTRDIFF_MIN (-PTRDIFF_MAX - 1)USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6c00)RCC_BDCR_LSEDRV_HIGH 3__UINT_FAST64_TYPE__ long long unsigned intDESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 0x14)RCC_CR_MSIRANGE_8MHZ 7SPI_CR1_BIDIOE (1 << 14)DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7590)__FLT_MIN__ 1.1754943508222875e-38FRCC_CFGR_MCOPRE_MASK 0x7__HA_FBIT__ 7RCC_CFGR_MCO_HSI48 0x8__FDPIC__RCC_CSR_MSIRANGE_MASK 0xf__UFRACT_MIN__ 0.0URRCC_BDCR_LSERDY (1 << 1)RCC_APB1SMENR2_LPTIM2SMEN (1 << 5)__FLT32_IS_IEC_60559__ 2RCC_AHB1SMENR_DMA1SMEN (1 << 0)GPIO_PORT_G_BASE (PERIPH_BASE_AHB2 + 0x1800)SPI_I2SCFGR(spi_base) MMIO32((spi_base) + 0x1c)SPI_I2SCFGR_I2SE (1 << 10)INT_FAST64_MIN__USFRACT_IBIT__ 0__INT32_C(c) c ## LRCC_CIER_HSI48RDYIE (1 << 10)__LDBL_EPSILON__ 2.2204460492503131e-16LRCC_CCIPR_USART1SEL_APB 0RCC_CR_MSIRANGE_4MHZ 6__USFRACT_MIN__ 0.0UHRTSC_BASE (PERIPH_BASE_AHB1 + 0x4000)RCC_BDCR_LSEDRV_SHIFT 3__ARM_NEONSPI_CR1_CRCL (1 << 11)RCC_PLLCFGR_PLLQ_DIV2 0__UINT8_MAX__ 0xffSPI_I2SCFGR_DATLEN_16BIT 0x0__LDBL_MAX_EXP__ 1024RCC_CFGR_MCOPRE_DIV4 2LIBOPENCM3_MEMORYMAP_H SPI_CR2_DS_MASK (0xF << 8)LIBOPENCM3_SPI_COMMON_ALL_H SPI_CR2_FRF_TI_MODE (1 << 4)__DBL_HAS_DENORM__ 1DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)SPI_CR2_FRF_MOTOROLA_MODE (0 << 4)RCC_CIER_HSERDYIE (1 << 4)RCC_CR_MSIRDY (1 << 1)RCC_APB1RSTR1_OFFSET 0x38QUADSPI_BASE (0xa0001000U)__DA_FBIT__ 31RCC_ICSCR_MSITRIM_MASK 0xffRCC_CCIPR_UART5SEL_SHIFT 8__GXX_ABI_VERSION 1017GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0c00)__INT_LEAST16_MAX__ 0x7fffRCC_CCIPR_ADCSEL_MASK 0x3__FLT_DENORM_MIN__ 1.4012984643248171e-45FRCC_PLLCFGR_PLLREN (1<<24)RCC_CIFR_HSIRDYF (1 << 3)__ULLACCUM_EPSILON__ 0x1P-32ULLKRCC_CR_MSIRANGE_16MHZ 8INT_LEAST8_MAX __INT_LEAST8_MAX__RCC_CR_MSIRANGE_1MHZ 4RCC_APB1RSTR1_SPI2RST (1 << 14)RCC_CICR_PLLSAI1RDYC (1 << 6)__UINT32_C(c) c ## ULRCC_AHB1SMENR_SRAM1SMEN (1 << 9)__UACCUM_MIN__ 0.0UK__FLT_EPSILON__ 1.1920928955078125e-7Fspi_set_data_sizeTIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)RCC_APB2RSTR_SAI1RST (1 << 21)RCC_AHB1SMENR_FLASHSMEN (1 << 8)SPI3_TXCRCR SPI_TXCRCR(SPI3_BASE)__ARM_ARCH_ISA_THUMBRCC_CR_PLLSAI1ON (1 << 26)__ARM_FEATURE_MATMUL_INT8__UINT8_TYPE__ unsigned charRCC_CICR_MSIRDYC (1 << 2)LIBOPENCM3_CM3_MEMORYMAP_H __GCC_ATOMIC_SHORT_LOCK_FREE 2RCC_AHB2RSTR_OTGFSRST (1 << 12)RCC_AHB2SMENR_GPIOGSMEN (1 << 6)RCC_CCIPR_LPUART1SEL_SYS 1RCC_APB2ENR_TIM1EN (1 << 11)__USACCUM_FBIT__ 8RCC_CCIPR_I2CxSEL_MASK 0x3__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1RCC_APB1ENR1_USART2EN (1 << 17)cpolRCC_APB1SMENR1_UART5SMEN (1 << 20)__LACCUM_FBIT__ 31SCS_BASE (PPBI_BASE + 0xE000)RCC_CFGR_STOPWUCK_HSI16 (1 << 15)RCC_APB2RSTR_USART1RST (1 << 14)SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)__FLT32_HAS_QUIET_NAN__ 1I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)RCC_APB2SMENR_SPI1SMEN (1 << 12)RCC_CSR_OBLRSTF (1 << 25)SPI_SR_FRLVL_HALF_FIFO (0x2 << 9)__LDBL_HAS_INFINITY__ 1RCC_AHB2RSTR_GPIOERST (1 << 4)__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))__FLT32X_MAX_10_EXP__ 308__ARM_ARCH_EXT_IDIV__ 1RCC_CCIPR_CLK48SEL_PLLSAI1Q 1RCC_CIER_HSIRDYIE (1 << 3)bool _BoolRCC_CIER_PLLSAI2RDYIE (1 << 7)SPI_CR1_BAUDRATE_FPCLK_DIV_32 (0x04 << 3)UINTMAX_MAX __UINTMAX_MAX____SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffRCC_CR_PLLSAI2ON (1 << 28)BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)SPI3_RXCRCR SPI_RXCRCR(SPI3_BASE)INT16_MAX __INT16_MAX__RCC_APB1RSTR1_USART2RST (1 << 17)__FP_FAST_FMAF 1RCC_AHB3ENR_OFFSET 0x50SPI2_CR2 SPI_CR2(SPI2_BASE)RCC_CR_MSIRANGE_24MHZ 9__FLT32X_IS_IEC_60559__ 2RCC_APB1RSTR1_USART3RST (1 << 18)PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)RCC_CIER MMIO32(RCC_BASE + 0x18)LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))FIREWALL_BASE (PERIPH_BASE_APB2 + 0x1C00)__INT_LEAST16_WIDTH__ 16RCC_APB1RSTR1_LPTIM1RST (1 << 31)SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)__ARM_FEATURE_FP16_FMLRCC_CR_MSIRANGE_2MHZ 5RCC_AHB3ENR_FMCEN (1 << 0)RCC_CCIPR_I2CxSEL_APB 0INT16_MIN (-INT16_MAX - 1)__USFRACT_EPSILON__ 0x1P-8UHRRCC_AHB2ENR_GPIOHEN (1 << 7)RCC_APB2ENR_TIM8EN (1 << 13)__WINT_MAX__ 0xffffffffU__USFRACT_FBIT__ 8CORESIGHT_LSR_SLI (1<<0)RCC_APB1ENR1_LCDEN (1 << 9)RCC_PLLCFGR_PLLSRC_SHIFT 0SPI_CR2_LDMA_RX (1 << 13)RCC_APB1RSTR1_UART5RST (1 << 20)__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX__RCC_CSR_WWDGRSTF (1 << 30)__UINT32_MAX__ 0xffffffffULRCC_CCIPR_ADCSEL_SYS 3RCC_CFGR_HPRE_DIV16 0xb__INT_LEAST8_MAX__ 0x7f__GCC_ATOMIC_POINTER_LOCK_FREE 2__ARM_FEATURE_QBIT 1__ARM_FEATURE_CLZ 1__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXRCC_AHB3ENR MMIO32(RCC_BASE + RCC_AHB3ENR_OFFSET)SPI_CR2_DS_6BIT (0x5 << 8)RCC_ICSCR_HSICAL_MASK 0xffRCC_CFGR_SWS_MASK 0x3__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024RCC_CICR MMIO32(RCC_BASE + 0x20)__UINT_LEAST32_MAX__ 0xffffffffUL__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)RCC_APB2RSTR_OFFSET 0x40__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1SPI_CR1_CPHA_CLK_TRANSITION_1 (0 << 0)__ACCUM_MAX__ 0X7FFFFFFFP-15KRCC_APB1RSTR2_SWPMI1RST (1 << 2)__INT8_MAX__ 0x7fBIT14 (1<<14)RCC_APB1SMENR1_TIM7SMEN (1 << 5)RCC_APB1RSTR1_TIM6RST (1 << 4)__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16SPI_I2SCFGR_PCMSYNC (1 << 7)__SHRT_WIDTH__ 16BIT20 (1<<20)__ARM_FEATURE_MVERCC_CFGR_MCO_NOCLK 0x0__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intRCC_CFGR_HPRE_DIV64 0xcRCC_APB1RSTR1_TIM4RST (1 << 2)SWPMI1_BASE (PERIPH_BASE_APB1 + 0x8800)SAI1_BASE (PERIPH_BASE_APB2 + 0x5400)SPI_CR2_FRF (1 << 4)INT_FAST32_MINSPI2_TXCRCR SPI_TXCRCR(SPI2_BASE)__FLT_EVAL_METHOD_TS_18661_3__ 0RCC_AHB3RSTR MMIO32(RCC_BASE + RCC_AHB3RSTR_OFFSET)__SCHAR_WIDTH__ 8RCC_APB2RSTR MMIO32(RCC_BASE + RCC_APB2RSTR_OFFSET)BIT18 (1<<18)COMP_BASE (PERIPH_BASE_APB2 + 0x0200)SIZE_MAX__UINT_FAST8_TYPE__ unsigned intRCC_CIFR_LSERDYF (1 << 1)__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RSPI_I2SCFGR_I2SCFG_SLAVE_RECEIVE 0x1BIT24 (1<<24)RCC_PLLCFGR_PLLR_MASK 0x3RCC_CCIPR_I2CxSEL_SYS 1__INT32_MAX__ 0x7fffffffLRCC_APB1ENR1_UART4EN (1 << 19)SPI_CR2_RXDMAEN (1 << 0)RCC_PLLCFGR_PLLQ_DIV6 2RCC_CFGR_HPRE_DIV256 0xeUINTMAX_MAXRCC_APB1SMENR1_UART4SMEN (1 << 19)BIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_BF16_VECTOR_ARITHMETICINFO_BASE (0x1fff0000U)PPBI_BASE (0xE0000000U)__FLT32_MANT_DIG__ 24RCC_BDCR_LSEDRV_MEDLOW 1INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32RCC_AHB2RSTR_GPIOCRST (1 << 2)__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN__RCC_CCIPR_LPUART1SEL_SHIFT 10INT8_MAX __INT8_MAX__RCC_CSR_LSIRDY (1 << 1)BIT28 (1<<28)RCC_BDCR_LSEDRV_MEDHIGH 2RCC_PLLPEN (1 << 16)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2RCC_CCIPR_USART1SEL_SYS 1RCC_AHB2SMENR_OFFSET 0x6c__DBL_MAX_EXP__ 1024RCC_AHB2RSTR_AESRST (1 << 16)__ATOMIC_RELEASE 3RCC_PLLCFGR_PLLP_DIV17 RCC_PLLCFGR_PLLPUINT_FAST8_MAX__FLT_MANT_DIG__ 24RCC_AHB2SMENR_GPIOESMEN (1 << 4)RCC_APB1ENR1_UART5EN (1 << 20)__UDQ_IBIT__ 0RCC_CIFR_LSIRDYF (1 << 0)__INT_LEAST32_TYPE__ long intRCC_AHB1SMENR MMIO32(RCC_BASE + RCC_AHB1SMENR_OFFSET)RCC_CR_HSERDY (1 << 17)__OPTIMIZE_SIZE__ 1__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UK__FLT64_NORM_MAX__ 1.7976931348623157e+308F64RCC_APB1RSTR1_OPAMPRST (1 << 30)UINTPTR_MAXSPI_I2SCFGR_I2SCFG_MASTER_TRANSMIT 0x2RCC_CR_PLLSAI1RDY (1 << 27)__LDBL_DENORM_MIN__ 4.9406564584124654e-324L__INT64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_SAT 1SPI_CR2_DS_11BIT (0xA << 8)__ULLFRACT_IBIT__ 0RCC_CR_HSIASFS (1 << 11)RCC_AHB1ENR_TSCEN (1 << 16)MMIO16(addr) (*(volatile uint16_t *)(addr))RCC_APB2ENR_SPI1EN (1 << 12)AES_BASE (0x50000000U + 0x60000)SPI_SR_FTLVL_HALF_FIFO (0x2 << 11)DAC_BASE (PERIPH_BASE_APB1 + 0x7400)__GNUC__ 12BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)SPI1_DR8 SPI_DR8(SPI1_BASE)WCHAR_MAXSPI_SR_FTLVL_QUARTER_FIFO (0x1 << 11)RCC_APB1ENR1_USART3EN (1 << 18)RCC_CCIPR_LPTIMxSEL_HSI16 2__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16RCC_CICR_LSIRDYC (1 << 0)__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0UUART5_BASE (PERIPH_BASE_APB1 + 0x5000)RCC_APB2SMENR_DFSDMSMEN (1 << 24)__UQQ_IBIT__ 0RCC_CFGR_SWS_SHIFT 2CORESIGHT_LSR_OFFSET 0xfb4__GCC_ATOMIC_LONG_LOCK_FREE 2__ULACCUM_MIN__ 0.0ULK__LDBL_MAX__ 1.7976931348623157e+308L__ARM_ARCH 7RCC_CFGR_SW_MASK 0x3SPI_CRCPR(spi_base) MMIO32((spi_base) + 0x10)__FLT_RADIX__ 2BIT3 (1<<3)long long intCORESIGHT_LAR_KEY 0xC5ACCE55__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAXRCC_AHB2ENR_ADCEN (1 << 13)__LDBL_HAS_QUIET_NAN__ 1RCC_AHB1SMENR_OFFSET 0x68SPI2_DR8 SPI_DR8(SPI2_BASE)__LONG_LONG_WIDTH__ 64BIT6 (1<<6)RCC_PLLCFGR_PLLN_SHIFT 0x8RCC_CFGR_MCOPRE_SHIFT 28RCC_APB1SMENR1_I2C1SMEN (1 << 21)RCC_CCIPR_LPUART1SEL_MASK 0x3__INT_FAST32_TYPE__ intRCC_APB1RSTR1_I2C3RST (1 << 23)__ARM_FP__HA_IBIT__ 8__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1RCC_APB2ENR_SDMMC1EN (1 << 10)BIT9 (1<<9)RCC_CFGR_HPRE_DIV512 0xf__FLT32X_MIN__ 2.2250738585072014e-308F32xINTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024UINT16_MAXPERIPH_BASE_AHB2 (0x48000000U)SPI_I2SPR(spi_base) MMIO32((spi_base) + 0x20)__FLT64_MIN__ 2.2250738585072014e-308F64__INTMAX_C(c) c ## LLRCC_AHB3ENR_QSPIEN (1 << 8)RCC_APB1SMENR2 MMIO32(RCC_BASE + RCC_APB1SMENR2_OFFSET)RCC_CCIPR_USART1SEL_HSI16 2__ARM_ARCH_PROFILE__INT64_TYPE__ long long int__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4SPI_CR1_SPE (1 << 6)SPI_CR1_SSM (1 << 9)RCC_CR_HSION (1 << 8)RCC_CSR_PINRSTF (1 << 26)RCC_CCIPR_LPTIMxSEL_MASK 0x3RCC_CR_HSIRDY (1 << 10)RCC_APB2SMENR_TIM1SMEN (1 << 11)CRS_BASE (PERIPH_BASE_APB1 + 0x6000)RCC_BDCR_RTCEN (1 << 15)__UFRACT_MAX__ 0XFFFFP-16URRCC_AHB1RSTR_OFFSET 0x28RCC_CR_HSEON (1 << 16)INT64_MAXFPB_BASE (PPBI_BASE + 0x2000)RCC_APB2RSTR_SAI2RST (1 << 22)RCC_CFGR_PPRE2_SHIFT 11RCC_CIFR_PLLSAI2RDYF (1 << 7)RCC_CICR_HSI48RDYC (1 << 10)INT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0RCC_BDCR_RTCSEL_LSI 2RCC_CCIPR_USARTxSEL_LSE 3STIR_BASE (SCS_BASE + 0x0F00)RCC_CFGR_SWS_HSE 0x2__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)RCC_CSR_BORRSTF (1 << 27)ID_BASE (SCS_BASE + 0x0FD0)SYS_TICK_BASE (SCS_BASE + 0x0010)RCC_CFGR_HPRE_DIV2 0x8SPI_CR1_CRCL_16BIT (1 << 11)RCC_PLLCFGR_PLLSRC_HSI16 2RCC_CFGR_SWS_MSI 0x0__UFRACT_FBIT__ 16FMC_BASE (0xa0000000U)__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)RCC_CCIPR_SAIxSEL_MASK 0x3__LDBL_MAX_10_EXP__ 308RCC_AHB2ENR_GPIOBEN (1 << 1)RCC_CCIPR_USART3SEL_SHIFT 4SPI_CR1_BAUDRATE_FPCLK_DIV_64 (0x05 << 3)RCC_APB1SMENR1_TIM3SMEN (1 << 1)RCC_CICR_HSERDYC (1 << 4)data_sSPI1_TXCRCR SPI_TXCRCR(SPI1_BASE)RCC_APB1RSTR1_TIM7RST (1 << 5)__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1RCC_CSR_FWRSTF (1 << 24)__USACCUM_IBIT__ 8RCC_APB1SMENR1_WWDGSMEN (1 << 11)ITM_BASE (PPBI_BASE + 0x0000)ST_VREFINT_CAL MMIO16((INFO_BASE + 0x75aa))__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UKRCC_APB1SMENR2_OFFSET 0x7c__UTA_IBIT__ 64RCC_CIFR_PLLSAI1RDYF (1 << 6)__FLT_EVAL_METHOD__ 0RCC_AHB3SMENR MMIO32(RCC_BASE + RCC_AHB3SMENR_OFFSET)unsigned int__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32DFSDM_BASE (PERIPH_BASE_APB2 + 0x6000)RCC_CR_PLLON (1 << 24)RCC_BASE (PERIPH_BASE_AHB1 + 0x1000)__ARM_FEATURE_LDREX__UQQ_FBIT__ 8RCC_CFGR_HPRE_SHIFT 4INT16_C__ARM_FP16_ARGS__GCC_IEC_559 0RCC_CSR MMIO32(RCC_BASE + 0x94)RCC_CR_MSIRANGE_MASK 0xfINT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX____LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4__STDC__ 1RCC_AHB2SMENR_RNGSMEN (1 << 18)RCC_CCIPR_CLK48SEL_PLL 2__ARM_FEATURE_IDIV 1RCC_APB2RSTR_SYSCFGRST (1 << 0)__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__DBGMCU_BASE (PPBI_BASE + 0x00042000)SPI_I2SCFGR_I2SCFG_SLAVE_TRANSMIT 0x0SPI_CR1_CRCEN (1 << 13)RCC_BDCR_LSECSSD (1 << 6)RCC_APB2ENR_SAI1EN (1 << 21)__ARM_FEATURE_COPROC 15RCC_AHB1SMENR_TSCSMEN (1 << 16)RCC_CICR_HSIRDYC (1 << 3)UINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"INT8_MINRCC_APB2ENR_DFSDMEN (1 << 24)RCC_PLLCFGR_PLLM_SHIFT 0x4RCC_APB1SMENR1_CAN1SMEN (1 << 25)LIBOPENCM3_RCC_H PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)RCC_CFGR_PPRE2_DIV8 0x6__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)RCC_AHB1ENR_OFFSET 0x48RCC_CCIPR_LPTIMxSEL_LSI 1__LDBL_MIN_10_EXP__ (-307)RCC_BDCR_LSEON (1 << 0)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1RCC_CFGR_SW_PLL 0x3__GCC_ATOMIC_CHAR_LOCK_FREE 2RCC_CR_CSSON (1 << 19)RCC_AHB2ENR_OFFSET 0x4c__LFRACT_EPSILON__ 0x1P-31LRFMC1_BANK_BASE (0x60000000U)STM32L4 1RCC_PLLCFGR_PLLQ_MASK 0x3spi_set_crcl_16bitRCC_APB1SMENR1_OPAMPSMEN (1 << 30)SPI_SR_OVR (1 << 6)__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX__SPI_SR_FRLVL_FIFO_FULL (0x3 << 9)__FLT32X_NORM_MAX__ 1.7976931348623157e+308F32x__arm__ 1RCC_CR MMIO32(RCC_BASE + 0x00)RCC_CCIPR_LPTIMxSEL_APB 0__FLT32_MIN_10_EXP__ (-37)RCC_APB1RSTR2_LPTIM2RST (1 << 5)SPI2 SPI2_BASEMMIO64(addr) (*(volatile uint64_t *)(addr))__ARM_FP16_FORMAT_ALTERNATIVERCC_ICSCR_HSITRIM_MASK 0x1fRCC_APB1RSTR1_LCDRST (1 << 9)__LDBL_NORM_MAX__ 1.7976931348623157e+308LRCC_PLLCFGR_PLLR_DIV4 1INTPTR_MINspi_send8DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)RCC_APB1ENR1_LPTIM1EN (1 << 31)RCC_CCIPR_LPTIMxSEL_LSE 3RCC_CFGR_PPRE2_NODIV 0x0__TA_IBIT__ 64RCC_CCIPR_USARTxSEL_APB 0SPI_CR2_TXDMAEN (1 << 1)RCC_APB1SMENR1_I2C3SMEN (1 << 23)SPI_CR2_DS_16BIT (0xF << 8)SPI_CR2_DS_7BIT (0x6 << 8)RCC_AHB2SMENR_GPIOASMEN (1 << 0)RCC_APB1SMENR1_LCDSMEN (1 << 9)__ARM_FEATURE_QRDMXRCC_CFGR_HPRE_NODIV 0x0RCC_CCIPR_LPTIM1SEL_SHIFT 18RCC_APB1ENR1_I2C3EN (1 << 23)__ARM_ARCH_ISA_THUMB 2__LONG_LONG_MAX__ 0x7fffffffffffffffLLRCC_APB1RSTR1_PWRRST (1 << 28)RCC_APB1ENR2_OFFSET 0x5c__WINT_WIDTH__ 32SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__SPI_I2SCFGR_DATLEN_LSB 1BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1RCC_AHB2ENR_GPIOFEN (1 << 5)_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN____SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__DBL_MIN_EXP__ (-1021)RCC_APB1ENR1_TIM7EN (1 << 5)__LDBL_HAS_DENORM__ 1RCC_CFGR_PPRE1_DIV8 0x6RCC_AHB2RSTR_RNGRST (1 << 18)RCC_PLLCFGR_PLLM_MASK 0x7INT8_MIN (-INT8_MAX - 1)SPI2_CRCPR SPI_CRCPR(SPI2_BASE)RCC_AHB2ENR MMIO32(RCC_BASE + RCC_AHB2ENR_OFFSET)__FLT32_DIG__ 6SPI_CR1_CPHA (1 << 0)INT_LEAST16_MAXSPI1_SR SPI_SR(SPI1_BASE)RCC_APB2RSTR_SDMMC1RST (1 << 10)RCC_CCIPR_USARTxSEL_HSI16 2BIT15 (1<<15)RCC_AHB2RSTR_OFFSET 0x2cSPI_SR_FTLVL_FIFO_FULL (0x3 << 11)RCC_AHB2RSTR_GPIOBRST (1 << 1)VREFBUF_BASE (PERIPH_BASE_APB2 + 0x0030)BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1INT32_MAXRCC_APB1ENR1_CAN1EN (1 << 25)RCC_APB2ENR_FWEN (1 << 7)__ACCUM_MIN__ (-0X1P15K-0X1P15K)lsbfirst__ARM_FEATURE_CRYPTOUART4_BASE (PERIPH_BASE_APB1 + 0x4c00)RCC_CFGR_HPRE_DIV4 0x9BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__UINT_FAST64_MAX__ 0xffffffffffffffffULLRCC_CCIPR_USART1SEL_SHIFT 0RCC_CCIPR_USART1SEL_LSE 3UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234SPI_CR2_DS_10BIT (0x9 << 8)SPI_CR1_BR_FPCLK_DIV_2 0x0__FLT_NORM_MAX__ 3.4028234663852886e+38FRCC_CFGR_MCOPRE_DIV1 0RCC_APB1SMENR2_LPUART1SMEN (1 << 0)long long unsigned int__FLT_MIN_10_EXP__ (-37)GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000)__ULACCUM_IBIT__ 32RCC_CIER_LSERDYIE (1 << 1)__SHRT_MAX__ 0x7fffspi_set_crcl_8bit__PTRDIFF_TYPE__ int__APCS_32__ 1__DQ_FBIT__ 63SPI_CR1_BAUDRATE_FPCLK_DIV_2 (0x00 << 3)INT_LEAST64_MAX__SACCUM_IBIT__ 8SPI_CR2_RXNEIE (1 << 6)reg32_REG_BIT(base,bit) (((base) << 5) + (bit))__UHQ_IBIT__ 0TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)INT_LEAST8_MINBIT29 (1<<29)RCC_APB1RSTR1_I2C2RST (1 << 22)__INT_FAST16_TYPE__ intSPI3_I2SPR SPI_I2SPR(SPI3_BASE)SPI1 SPI1_BASEINT64_C__ULFRACT_MAX__ 0XFFFFFFFFP-32ULRRCC_CCIPR_I2C1SEL_SHIFT 12__UINT_LEAST16_TYPE__ short unsigned intRCC_APB1RSTR1_UART4RST (1 << 19)__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned intRCC_CCIPR_USARTxSEL_SYS 1RCC_APB2SMENR_TIM17SMEN (1 << 18)__FLT32X_DIG__ 15SPI_I2SCFGR_CHLEN (1 << 0)SPI_CR2_SSOE (1 << 2)SPI3_CRCPR SPI_CRCPR(SPI3_BASE)__UTQ_FBIT__ 128RCC_APB2ENR_TIM17EN (1 << 18)RCC_BDCR_LSCOEN (1 << 24)SPI_CR1_BAUDRATE_FPCLK_DIV_4 (0x01 << 3)__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffffRCC_BDCR_RTCSEL_MASK 0x3RCC_AHB1RSTR_FLASHRST (1 << 8)DMA2_BASE (PERIPH_BASE_AHB1 + 0x0400)PTRDIFF_MAX __PTRDIFF_MAX____SIZEOF_SHORT__ 2RCC_CFGR_SWS_HSI16 0x1RCC_CFGR_PPRE2_DIV16 0x7RCC_CCIPR_UARTxSEL_MASK RCC_CCIPR_USARTxSEL_MASKSPI_CR2_DS_5BIT (0x4 << 8)RCC_CR_PLLRDY (1 << 25)UINT_FAST16_MAX__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKRCC_CCIPR_SAIxSEL_PLL 2RCC_PLLCFGR_PLLM(x) ((x)-1)RCC_APB1ENR2 MMIO32(RCC_BASE + RCC_APB1ENR2_OFFSET)UINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRRCC_BDCR_RTCSEL_LSE 1RCC_APB1SMENR1_SPI2SMEN (1 << 14)__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intRCC_AHB2ENR_RNGEN (1 << 18)RCC_AHB2ENR_GPIOGEN (1 << 6)SPI_CR2_FRXTH (1 << 12)RCC_APB1RSTR1_TIM3RST (1 << 1)RCC_APB1ENR1_TIM4EN (1 << 2)SPI_SR_MODF (1 << 5)WCHAR_MINRCC_CRRCR MMIO32(RCC_BASE + 0x98)BEGIN_DECLS RCC_CFGR_PPRE1_DIV16 0x7RCC_CFGR_PPRE2_DIV4 0x5RCC_AHB2RSTR_GPIOFRST (1 << 5)RCC_APB2RSTR_SPI1RST (1 << 12)RCC_CIFR_HSERDYF (1 << 4)SPI1_CR2 SPI_CR2(SPI1_BASE)RCC_AHB1ENR_CRCEN (1 << 12)SPI1_RXCRCR SPI_RXCRCR(SPI1_BASE)RCC_APB1ENR1_PWREN (1 << 28)__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15RCC_CSR_RMVF (1 << 23)__FLT32X_MAX__ 1.7976931348623157e+308F32xGPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400)RCC_APB1ENR1_OFFSET 0x58SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE (1 << 1)__ARM_EABI__ 1RCC_PLLCFGR_PLLQEN (1 << 20)INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1__ARM_FEATURE_DSP 1RCC_CR_MSIPLLEN (1 << 2)RCC_APB1SMENR1_DAC1SMEN (1 << 29)TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)__QQ_IBIT__ 0RCC_AHB2ENR_OTGFSEN (1 << 12)RCC_CR_MSIRANGE_100KHZ 0RCC_CCIPR_LPTIM2SEL_SHIFT 20RCC_CCIPR_DFSDMSEL (1 << 31)SPI_CR1_BAUDRATE_FPCLK_DIV_16 (0x03 << 3)__LLACCUM_FBIT__ 31RCC_APB2ENR MMIO32(RCC_BASE + RCC_APB2ENR_OFFSET)__UINTMAX_TYPE__ long long unsigned intLIBOPENCM3_RCC_COMMON_ALL_H __USQ_IBIT__ 0SPI_SR_FRLVL_QUARTER_FIFO (0x1 << 9)RCC_ICSCR_HSICAL_SHIFT 16__UINT_LEAST32_TYPE__ long unsigned int__ARM_FEATURE_NUMERIC_MAXMIN__INTMAX_TYPE__ long long int__GCC_ATOMIC_INT_LOCK_FREE 2RCC_APB2RSTR_TIM17RST (1 << 18)RCC_APB1RSTR1_TIM5RST (1 << 3)TIM16_BASE (PERIPH_BASE_APB2 + 0x4400)RCC_ICSCR_HSITRIM_SHIFT 24INTMAX_MAXRCC_APB1SMENR1_SPI3SMEN (1 << 15)SPI_CR1_CRCNEXT (1 << 12)DESIG_PACKAGE MMIO16((INFO_BASE + 0x7500))__ARM_ARCH_7EM__ 1__ARM_FEATURE_FP16_SCALAR_ARITHMETICRCC_CFGR_MCO_LSE 0x7__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1RCC_AHB3RSTR_QSPIRST (1 << 8)TIM17_BASE (PERIPH_BASE_APB2 + 0x4800)spi_fifo_reception_threshold_8bit__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CSPI2_SR SPI_SR(SPI2_BASE)RCC_CIER_PLLRDYIE (1 << 5)RCC_PLLCFGR_PLLSRC_MSI 1RCC_CCIPR_SAIxSEL_PLLSAI2P 1INT64_MINSPI_CR2_ERRIE (1 << 5)__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intRCC_CFGR_SW_MSI 0x0UINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRRCC_APB2ENR_OFFSET 0x60RCC_PLLCFGR_PLLQ_DIV8 3/build/libopencm3/lib/stm32/l4__SIZEOF_SIZE_T__ 4RCC_APB1ENR1 MMIO32(RCC_BASE + RCC_APB1ENR1_OFFSET)__UINT64_TYPE__ long long unsigned int__INT64_C(c) c ## LLSPI2_CR1 SPI_CR1(SPI2_BASE)RCC_APB1RSTR1_SPI3RST (1 << 15)USART1_BASE (PERIPH_BASE_APB2 + 0x3800)USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x6800)RCC_APB2ENR_TIM16EN (1 << 17)TPIU_BASE (PPBI_BASE + 0x40000)__LDBL_MIN__ 2.2250738585072014e-308LRCC_CCIPR_UART4SEL_SHIFT 6__ARM_FEATURE_CDE__ACCUM_IBIT__ 16RCC_CR_MSIRANGE_32MHZ 10RCC_AHB2ENR_GPIOAEN (1 << 0)SPI3_DR SPI_DR(SPI3_BASE)CORESIGHT_LAR_OFFSET 0xfb0EXTI_BASE (PERIPH_BASE_APB2 + 0x0400)RCC_AHB1RSTR_DMA1RST (1 << 0)SPI_CR1_BR_FPCLK_DIV_16 0x3FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000)short intRNG_BASE (0x50000000U + 0x60800)RCC_CSR_RESET_FLAGS (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF | RCC_CSR_IWDGRSTF | RCC_CSR_SFTRSTF | RCC_CSR_BORRSTF | RCC_CSR_PINRSTF | RCC_CSR_OBLRSTF | RCC_CSR_FWRSTF)RCC_CSR_LPWRRSTF (1 << 31)RCC_CSR_MSIRANGE_SHIFT 8__UINT16_C(c) cSPI_SR_RXNE (1 << 0)BIT31 (1<<31)__UDA_IBIT__ 32RCC_PLLCFGR_PLLQ_SHIFT 21UINT_LEAST32_MAXRCC_PLLSAI2_CFGR MMIO32(RCC_BASE + 0x14)BIT2 (1<<2)RCC_PLLCFGR_PLLP (1 << 17)__ATOMIC_RELAXED 0__UHQ_FBIT__ 16__ARM_FEATURE_COPROCRCC_BDCR_LSEDRV_LOW 0RCC_CCIPR_CLK48SEL_MASK 0x3__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53RCC_CCIPR_UARTxSEL_SYS RCC_CCIPR_USARTxSEL_SYSBIT5 (1<<5)BIT1 (1<<1)INT8_CGPIO_PORT_H_BASE (PERIPH_BASE_AHB2 + 0x1c00)INT_LEAST32_MAX__USES_INITFINI__ 1SPI_RXCRCR(spi_base) MMIO32((spi_base) + 0x14)SPI_CR1_BIDIMODE_1LINE_BIDIR (1 << 15)SPI_SR_CHSIDE (1 << 2)__DBL_DECIMAL_DIG__ 17RCC_CSR_MSIRANGE_2MHZ 5LIBOPENCM3_SPI_H BIT8 (1<<8)RCC_CRRCR_HSI48ON (1 << 0)SPI_CR1_BAUDRATE_FPCLK_DIV_256 (0x07 << 3)INT16_C(c) __INT16_C(c)RCC_CCIPR_CLK48SEL_HSI48 0UINT32_MAX__INT16_MAX__ 0x7fffRCC_APB1ENR1_TIM5EN (1 << 3)RCC_BDCR_LSEBYP (1 << 2)RCC_AHB2SMENR_GPIOFSMEN (1 << 5)SPI_CR1_BR_FPCLK_DIV_64 0x5RCC_CIFR_HSI48RDYF (1 << 10)__INT_WIDTH__ 32__ARM_FEATURE_SIMD32 1DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x75e0)RCC_APB2ENR_SYSCFGEN (1 << 0)RCC_CR_HSEBYP (1 << 18)__QQ_FBIT__ 7RCC_CR_PLLSAI2RDY (1 << 29)RTC_BASE (PERIPH_BASE_APB1 + 0x2800)__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64RCC_AHB2SMENR_OTGFSSMEN (1 << 12)RCC_CFGR_PPRE1_SHIFT 8RCC_BDCR_BDRST (1 << 16)LPTIM2_BASE (PERIPH_BASE_APB1 + 0x9400)__ULLACCUM_IBIT__ 32SPI_SR_FRE (1 << 8)RCC_CICR_CSSC (1 << 8)__ULLFRACT_EPSILON__ 0x1P-64ULLRfalse 0SPI_CR2(spi_base) MMIO32((spi_base) + 0x04)RCC_CCIPR_I2C3SEL_SHIFT 16__SIZEOF_WINT_T__ 4RCC_APB1ENR1_I2C2EN (1 << 22)SPI_CR1_SSI (1 << 8)__ARM_FEATURE_UNALIGNED 1__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17RCC_CFGR_PPRE1_MASK 0x7__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1SPI_I2SCFGR_I2SSTD_MSB_JUSTIFIED 0x1__FLT32X_HAS_DENORM__ 1__ULLACCUM_MIN__ 0.0ULLK__INT_FAST32_WIDTH__ 32SPI1_CR1 SPI_CR1(SPI1_BASE)SPI_SR_FTLVL_FIFO_EMPTY (0x0 << 11)__LDBL_IS_IEC_60559__ 2RCC_CCIPR_I2CxSEL_HSI16 2RCC_CCIPR_SWPMI1SEL (1 << 30)__ARM_ASM_SYNTAX_UNIFIED__ 1RCC_BDCR MMIO32(RCC_BASE + 0x90)SPI_I2SCFGR_I2SSTD_PCM 0x3SPI_I2SCFGR_I2SSTD_LSB 4SPI_I2SCFGR_I2SMOD (1 << 11)__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODRCC_APB1ENR1_SPI3EN (1 << 15)RCC_APB2SMENR_TIM16SMEN (1 << 17)RCC_CFGR_MCOPRE_DIV2 1__ARM_PCS_VFP 1RCC_PLLCFGR_PLLR_SHIFT 25RCC_AHB2RSTR_GPIODRST (1 << 3)SPI_CR1_CPOL (1 << 1)RCC_PLLCFGR MMIO32(RCC_BASE + 0x0c)__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H RCC_CFGR_SW_HSI16 0x1LPUART1_BASE (PERIPH_BASE_APB1 + 0x8000)RCC_CCIPR_SAI2SEL_SHIFT 24INT_LEAST64_MIN__GCC_CONSTRUCTIVE_SIZE 64__LLFRACT_IBIT__ 0RCC_APB1SMENR2_SWPMI1SMEN (1 << 2)RCC_AHB2SMENR_ADCSMEN (1 << 13)RCC_ICSCR_MSITRIM_SHIFT 8uint32_tRCC_AHB1SMENR_DMA2SMEN (1 << 1)BIT12 (1<<12)RCC_PLLCFGR_PLLR_DIV8 3RCC_CFGR_HPRE_DIV128 0xdMPU_BASE (SCS_BASE + 0x0D90)__SACCUM_EPSILON__ 0x1P-7HKRCC_CFGR_PPRE1_DIV4 0x5__GCC_ASM_FLAG_OUTPUTS__ 1RCC_BDCR_LSCOSEL (1 << 25)ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0x75a8))__ARM_FP 4RCC_CCIPR_ADCSEL_SHIFT 28SPI3_SR SPI_SR(SPI3_BASE)__UINT_FAST16_TYPE__ unsigned intRCC_CCIPR_UARTxSEL_LSE RCC_CCIPR_USARTxSEL_LSE__UHA_IBIT__ 8RCC_CCIPR_CLK48SEL_MSI 3SPI_TXCRCR(spi_base) MMIO32((spi_base) + 0x18)__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULK__LDBL_DIG__ 15POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXBIT16 (1<<16)SPI1_I2SPR SPI_I2SPR(SPI1_BASE)__WINT_MIN__ 0UINT_LEAST16_MINSPI_I2SCFGR_CKPOL (1 << 3)__FLT64_DIG__ 15RCC_BDCR_RTCSEL_SHIFT 8TIM15_BASE (PERIPH_BASE_APB2 + 0x4000)BIT22 (1<<22)__INT_LEAST8_WIDTH__ 8RCC_APB1RSTR2 MMIO32(RCC_BASE + RCC_APB1RSTR2_OFFSET)WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)RCC_AHB2SMENR_GPIOBSMEN (1 << 1)__INT_LEAST16_TYPE__ short intRCC_AHB3SMENR_FMCSMEN (1 << 0)RCC_CFGR_MCOPRE_DIV8 3SPI1_CRCPR SPI_CRCPR(SPI1_BASE)__DBL_MAX__ ((double)1.7976931348623157e+308L)SPI_CR1(spi_base) MMIO32((spi_base) + 0x00)INT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1UINTMAX_CRCC_CFGR_SW_SHIFT 0INT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1__HQ_FBIT__ 15__bool_true_false_are_defined 1BIT26 (1<<26)RCC_AHB3SMENR_QSPISMEN (1 << 8)RCC_CR_MSIRANGE_200KHZ 1RCC_CCIPR_UARTxSEL_APB RCC_CCIPR_USARTxSEL_APB__SIZE_MAX__ 0xffffffffUSPI2_BASE (PERIPH_BASE_APB1 + 0x3800)RCC_APB1SMENR1_TIM2SMEN (1 << 0)RCC_CFGR_PPRE2_MASK 0x7__ARM_ARCHRCC_CCIPR_SAIxSEL_EXT 3__LONG_MAX__ 0x7fffffffLRCC_APB2RSTR_TIM1RST (1 << 11)SPI_SR_FRLVL_FIFO_EMPTY (0x0 << 9)RCC_CCIPR_USART1SEL_MASK 0x3SAI2_BASE (PERIPH_BASE_APB2 + 0x5800)RCC_AHB2RSTR MMIO32(RCC_BASE + RCC_AHB2RSTR_OFFSET)RCC_CFGR_PPRE1_NODIV 0x0__ARM_FEATURE_LDREX 7PTRDIFF_MAXRCC_CCIPR MMIO32(RCC_BASE + 0x88)RCC_PLLCFGR_PLLP_DIV7 0__LLFRACT_EPSILON__ 0x1P-63LLRSPI3 SPI3_BASE__SFRACT_MAX__ 0X7FP-7HR__FLT32X_MANT_DIG__ 53RCC_CCIPR_USARTxSEL_MASK 0x3RCC_APB1RSTR1_TIM2RST (1 << 0)__WCHAR_WIDTH__ 32RCC_CFGR_MCO_LSI 0x6WINT_MAX__INT16_C(c) cSPI5 SPI5_BASEINT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32RCC_AHB3RSTR_OFFSET 0x30RCC_CCIPR_ADCSEL_NONE 0RCC_CSR_MSIRANGE_1MHZ 4SPI2_I2SPR SPI_I2SPR(SPI2_BASE)__ATOMIC_ACQ_REL 4SPI_CR2_TXEIE (1 << 7)SPI6 SPI6_BASE__HQ_IBIT__ 0__DBL_MIN_10_EXP__ (-307)SPI3_DR8 SPI_DR8(SPI3_BASE)dataRCC_CFGR_MCO_HSI16 0x3SPI_CR1_CPHA_CLK_TRANSITION_2 (1 << 0)RCC_APB1RSTR1_DAC1RST (1 << 29)SPI3_CR2 SPI_CR2(SPI3_BASE)RCC_PLLCFGR_PLLSRC_MASK 0x3__FLT32_NORM_MAX__ 3.4028234663852886e+38F32RCC_APB1SMENR1 MMIO32(RCC_BASE + RCC_APB1SMENR1_OFFSET)RCC_APB2SMENR_OFFSET 0x80RCC_CFGR_MCO_SYSCLK 0x1SPI_CR1_CRCL_8BIT (0 << 11)UINT64_C(c) __UINT64_C(c)RCC_APB2RSTR_TIM8RST (1 << 13)RCC_APB2RSTR_TIM16RST (1 << 17)__UINTMAX_MAX__ 0xffffffffffffffffULLRCC_CCIPR_ADCSEL_PLLSAI2R 2__DBL_MANT_DIG__ 53SPI_CR1_BR_FPCLK_DIV_32 0x4__ULFRACT_IBIT__ 0RCC_PLLCFGR_PLLQ_DIV4 1INT_FAST16_MAXITR_BASE (SCS_BASE + 0x0000)SPI_SR(spi_base) MMIO32((spi_base) + 0x08)QUADSPI_BANK_BASE (0x90000000U)__INT_MAX__ 0x7fffffff__INT_LEAST64_TYPE__ long long intRCC_AHB1SMENR_CRCSMEN (1 << 12)RCC_AHB1ENR_DMA2EN (1 << 1)RCC_CFGR MMIO32(RCC_BASE + 0x08)__ARM_FEATURE_CDE_COPROCRCC_CICR_LSERDYC (1 << 1)SPI_CR2_NSSP (1 << 3)UINT32_CRCC_CFGR_MCOPRE_DIV16 4GCC: (15:12.2.rel1-1) 12.2.1 20221205˙˙˙˙| $A„…Ž A3aeabi)7E-M M "ń˙ 57!#%')+-/139;lťĎ4hˇ Ů 8; $ ! + = Pb „ spi_common_v2.c$twm4.0.c5e6bdb01417bb5a599260a3f8c9cb62wm4.common.h.21.c9066c2f6b12c71b40226ea6107829a4wm4.stdint.h.29.6d480f4ba0f60596e88234283d42444fwm4.stdbool.h.29.4a1c88fe569adb8d03217dd16982ca34wm4.common.h.67.5c568a1f62c8e726909b04e29f9e1fc0wm4.memorymap.h.21.8c90486dae5eea2d8efddd23fe5d09d9wm4.memorymap.h.26.bb1efb6ce36cc052fd0489ef5a3533f5wm4.spi_common_all.h.33.9ea0c3889826c83e4c563d215a234fb7wm4.spi_common_v2.h.34.10c1122c4818b128f05bb1e70d3ba8d7wm4.rcc.h.40.e8c13f444ba606cb63a83dcc96231a47spi_init_masterspi_send8spi_read8spi_set_crcl_8bitspi_set_crcl_16bitspi_set_data_sizespi_fifo_reception_threshold_8bitspi_fifo_reception_threshold_16bit "&-4;BGTYfkxŤ’—´ąÖŰ÷ -2OZ sw}‚›ź¤®˛¸ĂŘÜíú &*( =HUlŤ (0 8@H % +17' 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Ô „ .!n ? ? ? ? ? ˙ „ .!n ? ? ? ? ? ¨ „!"!"!"!Ď =ŕ =ň =„ =” =¤ =´ =Ä =Ř =ë =ý =Ž =ˇ /ąĚ /Ú !č!üh = 2! = ? = 2! = ť h = 2! = ? = 2! = É 0+ ?1 = s<+.?1 = q<> = $!" = $!î , % ./ú - & .=Ś = =› = =¨!0"¸ = !Ĺ = !TIM_SMCR_ETPS_ETRP_DIV_8 (0x3 << 12)LIBOPENCM3_CM3_MEMORYMAP_H __LACCUM_EPSILON__ 0x1P-31LK__thumb__ 1UINT16_C(c) __UINT16_C(c)RCC_APB2ENR_DFSDMEN (1 << 24)__UACCUM_FBIT__ 16__APCS_32__ 1timer_ic_set_filter__LFRACT_EPSILON__ 0x1P-31LR__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__TIM6 TIM6_BASERCC_AHB2ENR_GPIOGEN (1 << 6)eventtimer_set_enabled_off_state_in_idle_mode__FLT_NORM_MAX__ 3.4028234663852886e+38FRCC_APB1ENR2 MMIO32(RCC_BASE + RCC_APB1ENR2_OFFSET)TIM_CCMR2_IC3F_DTF_DIV_8_N_8 (0x9 << 4)__USACCUM_MIN__ 0.0UHK__ARM_FEATURE_MATMUL_INT8RCC_APB1SMENR2_OFFSET 0x7cTIM_CCMR1_IC2F_DTF_DIV_16_N_6 (0xB << 12)__FLT32_DIG__ 6__DBL_EPSILON__ ((double)2.2204460492503131e-16L)__FLT32X_MAX__ 1.7976931348623157e+308F32x__UACCUM_IBIT__ 16RCC_APB2ENR_TIM15EN (1 << 16)INTPTR_MIN (-INTPTR_MAX - 1)TIM_CCMR2(tim_base) MMIO32((tim_base) + 0x1C)oc_modeTIM_IC_OFFTIM_CCMR1_OC2M_ACTIVE (0x1 << 12)WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)TIM_BDTR_OSSR (1 << 11)__INT_FAST16_MAX__ 0x7fffffffRCC_AHB2ENR_OTGFSEN (1 << 12)TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)RCC_CFGR_HPRE_DIV512 0xf__FLT64_MANT_DIG__ 53UINT_LEAST16_MAXUINT_LEAST8_MAX __UINT_LEAST8_MAX__UINT_FAST16_MAX __UINT_FAST16_MAX____SIG_ATOMIC_MAX__ 0x7fffffffTIM_SMCR(tim_base) MMIO32((tim_base) + 0x08)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)TIM_ARR(tim_base) MMIO32((tim_base) + 0x2C)RCC_CICR MMIO32(RCC_BASE + 0x20)RCC_APB2ENR MMIO32(RCC_BASE + RCC_APB2ENR_OFFSET)alignment__ARM_PCS_VFP 1__ARM_FEATURE_UNALIGNED 1__FLT32_HAS_INFINITY__ 1timer_disable_preload__USQ_IBIT__ 0__PTRDIFF_MAX__ 0x7fffffffRCC_CFGR_HPRE_DIV2 0x8RCC_APB2SMENR_OFFSET 0x80INT64_MIN (-INT64_MAX - 1)RCC_CFGR_PPRE2_DIV16 0x7timer_set_alignmentRCC_CICR_CSSC (1 << 8)UINT_FAST32_MAXTIM1_CCER TIM_CCER(TIM1)TIM15_EGR TIM_EGR(TIM15)TIM_CCMR2_IC3F_DTF_DIV_4_N_8 (0x7 << 4)RCC_AHB2RSTR_GPIOFRST (1 << 5)BIT10 (1<<10)UINT_FAST64_MAXTIM3_CCER TIM_CCER(TIM3)__STDC__ 1_BoolTIM2_CCR3 TIM_CCR3(TIM2)__ULLFRACT_IBIT__ 0__FLT32_MAX_EXP__ 128__CHAR32_TYPE__ long unsigned intRCC_CCIPR_LPTIMxSEL_HSI16 2__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__UDA_FBIT__ 32RCC_CRRCR_HSI48ON (1 << 0)TIM_CR2_CCDS (1 << 3)RCC_AHB1SMENR_DMA1SMEN (1 << 0)TIM_SMCR_ETF_MASK (0xF << 8)__DBL_MAX_10_EXP__ 308RCC_APB1ENR2_LPUART1EN (1 << 0)INT_LEAST32_MINRCC_APB1SMENR1_TIM6SMEN (1 << 4)__UINT_FAST64_MAX__ 0xffffffffffffffffULLTIM_DIER_TIE (1 << 6)RCC_APB1SMENR1_OPAMPSMEN (1 << 30)__ARM_FEATURE_IDIV 1RCC_PLLCFGR_PLLP (1 << 17)RCC_AHB1SMENR_CRCSMEN (1 << 12)TIM_CCMR1_OC2M_FROZEN (0x0 << 12)__WCHAR_TYPE__ unsigned int__SA_IBIT__ 16__UDA_IBIT__ 32tim_ic_id__ELF__ 1RCC_CIER_HSI48RDYIE (1 << 10)__SIZEOF_LONG__ 4DWT_BASE (PPBI_BASE + 0x1000)TIM_CCMR1_IC2F_DTF_DIV_16_N_8 (0xC << 12)DESIG_PACKAGE MMIO16((INFO_BASE + 0x7500))TIM1_SR TIM_SR(TIM1)RCC_CFGR_SWS_SHIFT 2BIT11 (1<<11)TIM2_CCMR1 TIM_CCMR1(TIM2)RCC_AHB2RSTR MMIO32(RCC_BASE + RCC_AHB2RSTR_OFFSET)LIBOPENCM3_MEMORYMAP_H RCC_CR_MSIRANGE_16MHZ 8RCC_APB2RSTR_SDMMC1RST (1 << 10)BIT3 (1<<3)timer_enable_preloadWCHAR_MAXTIM17_CCER TIM_CCER(TIM17)TIM_CCMR2_IC4F_DTF_DIV_16_N_6 (0xB << 12)RCC_PLLCFGR_PLLQ_MASK 0x3RCC_CSR_PINRSTF (1 << 26)__DBL_DECIMAL_DIG__ 17__UINT_LEAST64_TYPE__ long long unsigned intTIM1_CCMR2 TIM_CCMR2(TIM1)RCC_CFGR_HPRE_DIV4 0x9_STDBOOL_H clock_divSIG_ATOMIC_MIN__SHRT_WIDTH__ 16__STRICT_ANSI__ 1TIM10_CNT TIM_CNT(TIM10)WINT_MINRCC_APB2ENR_TIM17EN (1 << 18)TIM_SMCR_SMS_RM (0x4 << 0)timer_set_oc_value__DQ_FBIT__ 63__UACCUM_EPSILON__ 0x1P-16UKRCC_CCIPR MMIO32(RCC_BASE + 0x88)__INT_FAST16_WIDTH__ 32TIM_SMCR_SMS_TM (0x6 << 0)timer_set_oc_idle_state_set__FLT_HAS_INFINITY__ 1RCC_APB1RSTR1_TIM4RST (1 << 2)TIM8_CNT TIM_CNT(TIM8)BIT1 (1<<1)TIM8_ARR TIM_ARR(TIM8)RCC_APB1SMENR1_SPI2SMEN (1 << 14)RCC_AHB1SMENR MMIO32(RCC_BASE + RCC_AHB1SMENR_OFFSET)TIM_SMCR_SMS_ECM1 (0x7 << 0)INT_FAST64_MAX __INT_FAST64_MAX__TIM_CCR1(tim_base) MMIO32((tim_base) + 0x34)TIM7_DIER TIM_DIER(TIM7)TIM4_CCMR2 TIM_CCMR2(TIM4)TIM_CCMR2_IC4PSC_2 (0x1 << 10)RCC_APB1RSTR1_PWRRST (1 << 28)RCC_CFGR_MCO_HSE 0x4RCC_APB1SMENR1_LPTIM1SMEN (1 << 31)TIM13_PSC TIM_PSC(TIM13)TIM4_CCR2 TIM_CCR2(TIM4)TIM12_CCMR1 TIM_CCMR1(TIM12)ITM_BASE (PPBI_BASE + 0x0000)__FP_FAST_FMAF32 1__ARM_ARCH_ISA_THUMB 2__GCC_ATOMIC_INT_LOCK_FREE 2TIM_SMCR_ETPS_OFF (0x0 << 12)RCC_APB2ENR_SPI1EN (1 << 12)RCC_CFGR_MCO_LSI 0x6TIM_CR1_CEN (1 << 0)RCC_CIFR_LSIRDYF (1 << 0)TIM_CCMR2_IC3F_DTF_DIV_16_N_8 (0xC << 4)TIM11_CCER TIM_CCER(TIM11)TIM_CCMR1_IC1F_DTF_DIV_32_N_6 (0xE << 4)__USFRACT_MIN__ 0.0UHRRCC_APB1ENR2_SWPMI1EN (1 << 2)UINT64_MAX __UINT64_MAX__TIM_IC_CK_INT_N_2__INT_LEAST32_TYPE__ long intTIM_IC_CK_INT_N_4__DBL_HAS_INFINITY__ 1TIM_IC_CK_INT_N_8TIM_CCER_CC1NE (1 << 2)GPIO_PORT_G_BASE (PERIPH_BASE_AHB2 + 0x1800)RCC_CFGR_SW_HSI16 0x1BIT13 (1<<13)RCC_CCIPR_USART1SEL_APB 0RCC_APB1RSTR1_I2C3RST (1 << 23)__SHRT_MAX__ 0x7fffRCC_CFGR_PPRE2_NODIV 0x0TIM_CCMR2_IC4F_DTF_DIV_16_N_8 (0xC << 12)BIT4 (1<<4)POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)timer_set_oc_slow_modeRCC_CSR_RMVF (1 << 23)TIM_CR1_ARPE (1 << 7)TIM_CCMR1_IC1F_MASK (0xF << 4)RCC_CCIPR_SAIxSEL_MASK 0x3TIM_CCMR1_IC1F_DTF_DIV_32_N_5 (0xD << 4)RCC_CSR_MSIRANGE_SHIFT 8RCC_BDCR_LSECSSON (1 << 5)timer_set_clock_divisionRCC_CFGR_MCO_PLL 0x5TIM_CCMR1_CC2S_IN_TI2 (0x1 << 8)__INT_FAST64_MAX__ 0x7fffffffffffffffLL__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)RCC_APB1RSTR1_CAN1RST (1 << 25)__GCC_ATOMIC_CHAR_LOCK_FREE 2__UINT_FAST16_TYPE__ unsigned intRCC_CCIPR_USARTxSEL_HSI16 2GNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsRCC_BDCR MMIO32(RCC_BASE + 0x90)MMIO8(addr) (*(volatile uint8_t *)(addr))__UINT64_MAX__ 0xffffffffffffffffULLTIM_EGR_CC2G (1 << 2)RCC_CIER_HSIRDYIE (1 << 3)RCC_APB1ENR1_TIM6EN (1 << 4)TIM_CR2_OIS_MASK (0x7f << 8)TIM_SMCR_MSM (1 << 7)__ARMEL__ 1TIM_CCMR2_IC4PSC_4 (0x2 << 10)__FLT32X_MAX_10_EXP__ 308TIM4_CR2 TIM_CR2(TIM4)BIT14 (1<<14)TIM4_CCR1 TIM_CCR1(TIM4)RCC_AHB1ENR MMIO32(RCC_BASE + RCC_AHB1ENR_OFFSET)__WCHAR_WIDTH__ 32TIM_CCMR1_OC1M_ACTIVE (0x1 << 4)__SIG_ATOMIC_TYPE__ int__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1RCC_AHB2ENR_AESEN (1 << 16)RCC_APB1RSTR1_TIM6RST (1 << 4)TIM_CCMR2_OC4M_MASK (0x7 << 12)RCC_CIFR_MSIRDYF (1 << 2)RCC_CR_MSIRGSEL (1 << 3)TIM_CCMR1_OC1M_FORCE_LOW (0x4 << 4)TIM6_ARR TIM_ARR(TIM6)TIM_DIER_BIE (1 << 7)__UINT16_C(c) c__PRAGMA_REDEFINE_EXTNAME 1__INT_LEAST64_TYPE__ long long intTIM8_SMCR TIM_SMCR(TIM8)RCC_CCIPR_UARTxSEL_APB RCC_CCIPR_USARTxSEL_APBtimer_set_counterLPUART1_BASE (PERIPH_BASE_APB1 + 0x8000)TIM_CCMR2_OC4M_TOGGLE (0x3 << 12)RCC_PLLCFGR_PLLSRC_MASK 0x3RCC_APB2SMENR_SDMMC1SMEN (1 << 10)timer_disable_irqUINTMAX_MAXRCC_AHB2SMENR_GPIODSMEN (1 << 3)TIM_CCMR2_OC4FE (1 << 10)__HAVE_SPECULATION_SAFE_VALUE 1I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)UINTMAX_C(c) __UINTMAX_C(c)__QQ_FBIT__ 7timer_enable_breakBIT15 (1<<15)TIM_CCMR2_IC3F_MASK (0xF << 4)__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xINT8_CTIM_CCER_CC1E (1 << 0)RCC_AHB1SMENR_TSCSMEN (1 << 16)TIM_CCMR2_OC4CE (1 << 15)BIT22 (1<<22)BIT5 (1<<5)USB_OTG_FS_BASE (0x50000000U + 0x00000)__BIGGEST_ALIGNMENT__ 8__ARM_ARCH__UINT8_TYPE__ unsigned charTIM8_CCER TIM_CCER(TIM8)RCC_AHB2RSTR_GPIOARST (1 << 0)RCC_CFGR_STOPWUCK_HSI16 (1 << 15)TIM5_CR1 TIM_CR1(TIM5)__FLT32_MIN_10_EXP__ (-37)RCC_CSR_MSIRANGE_8MHZ 7TIM15_BDTR TIM_BDTR(TIM15)RCC_APB1ENR1_UART4EN (1 << 19)TIM_IC_DTF_DIV_4_N_6TIM_IC_DTF_DIV_4_N_8__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLKRCC_PLLCFGR_PLLQ_DIV4 1__INT_LEAST16_MAX__ 0x7fffRCC_APB2ENR_TIM8EN (1 << 13)BIT12 (1<<12)TIM_CCER_CC3P (1 << 9)TIM9_CNT TIM_CNT(TIM9)RCC_CICR_PLLSAI2RDYC (1 << 7)TIM9_ARR TIM_ARR(TIM9)TIM_CCMR2_CC3S_IN_TRC (0x3 << 0)TIM_CCMR1_IC2PSC_MASK (0x3 << 10)TIM_CCMR2_IC4F_DTF_DIV_8_N_8 (0x9 << 12)RCC_CCIPR_UART5SEL_SHIFT 8TIM16_RCR TIM_RCR(TIM16)TIM12_SR TIM_SR(TIM12)RCC_CR_PLLON (1 << 24)BIT16 (1<<16)__SACCUM_IBIT__ 8TIM_CCMR2_OC4M_ACTIVE (0x1 << 12)RCC_AHB2SMENR_GPIOFSMEN (1 << 5)TIM2_SMCR TIM_SMCR(TIM2)TIM_SR_CC1IF (1 << 1)__SIZEOF_WCHAR_T__ 4TIM4_SMCR TIM_SMCR(TIM4)RCC_CFGR_MCOPRE_DIV8 3__FLT32_NORM_MAX__ 3.4028234663852886e+38F32timer_clear_flag__FLT32X_HAS_INFINITY__ 1FMC_BASE (0xa0000000U)TIM_CCMR2_OC3FE (1 << 2)TIM_CCMR2_IC4PSC_8 (0x3 << 10)RCC_BDCR_LSEDRV_MASK 0x3__INT8_C(c) cRCC_APB2ENR_SDMMC1EN (1 << 10)INFO_BASE (0x1fff0000U)__ARM_EABI__ 1RCC_PLLCFGR_PLLR_DIV4 1RCC_AHB2SMENR_GPIOASMEN (1 << 0)UINT64_C(c) __UINT64_C(c)TIM_CR2_MMS_COMPARE_OC3REF (0x6 << 4)__FLT32_EPSILON__ 1.1920928955078125e-7F32TIM7_PSC TIM_PSC(TIM7)TIM_CCMR2_IC3PSC_4 (0x2 << 2)TIM11_SR TIM_SR(TIM11)INT_LEAST8_MAX __INT_LEAST8_MAX__false 0__FLT_MAX_EXP__ 128RCC_AHB2ENR_GPIOBEN (1 << 1)__INT64_MAX__ 0x7fffffffffffffffLLRCC_BDCR_LSEBYP (1 << 2)BIT17 (1<<17)__ATOMIC_SEQ_CST 5RCC_CCIPR_LPUART1SEL_LSE 3RCC_APB1SMENR1_TIM7SMEN (1 << 5)DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7590)RCC_APB2RSTR_TIM15RST (1 << 16)RCC_CR_MSIPLLEN (1 << 2)RCC_CR MMIO32(RCC_BASE + 0x00)TIM_SMCR_TS_MASK (0x7 << 4)TIM17_BDTR TIM_BDTR(TIM17)TIM_SMCR_ECE (1 << 14)__FLT32X_MAX_EXP__ 1024SDMMC1_BASE (PERIPH_BASE_APB2 + 0x2800)__FLT32_MANT_DIG__ 24RCC_ICSCR_MSICAL_MASK 0xff__UINT_FAST8_TYPE__ unsigned intRCC_BDCR_RTCSEL_SHIFT 8TIM_CR2_MMS_MASK (0x7 << 4)__UTA_FBIT__ 64DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)__DBL_DIG__ 15INTPTR_MAX __INTPTR_MAX__TIM9_CCR2 TIM_CCR2(TIM9)TIM_CCMR1_OC1CE (1 << 7)__DECIMAL_DIG__ 17TIM12_DIER TIM_DIER(TIM12)INT_FAST16_MINTIM_CCMR2_OC3M_FORCE_HIGH (0x5 << 4)RCC_CFGR_HPRE_MASK 0xfTIM17_PSC TIM_PSC(TIM17)TIM15_CR2 TIM_CR2(TIM15)__ARM_BF16_FORMAT_ALTERNATIVETIM16_CR1 TIM_CR1(TIM16)TIM_SMCR_ETF_DTS_DIV_2_N_8 (0x5 << 8)TIM3_DMAR TIM_DMAR(TIM3)UINT64_CTIM_CCMR1_IC2F_DTF_DIV_32_N_6 (0xE << 12)__UINT64_TYPE__ long long unsigned intRCC_APB1ENR1_LPTIM1EN (1 << 31)TIM5_CR2 TIM_CR2(TIM5)TIM5_DMAR TIM_DMAR(TIM5)TIM_BDTR_DBL_MASK (0x1F << 8)RCC_PLLCFGR_PLLP_DIV17 RCC_PLLCFGR_PLLPBIT18 (1<<18)__LFRACT_IBIT__ 0long long unsigned intRCC_BDCR_BDRST (1 << 16)__USER_LABEL_PREFIX__ RCC_PLLCFGR_PLLM_SHIFT 0x4TIM_SMCR_TS_ETRF (0x7 << 4)RCC_APB1RSTR1_SPI3RST (1 << 15)TIM3_DIER TIM_DIER(TIM3)timer_enable_break_automatic_outputINT64_MAX __INT64_MAX__TIM_EGR_UG (1 << 0)__QQ_IBIT__ 0TIM_CCMR1_OC2M_TOGGLE (0x3 << 12)RCC_AHB3ENR_FMCEN (1 << 0)UINT_LEAST64_MAXSPI2_BASE (PERIPH_BASE_APB1 + 0x3800)RCC_CR_HSIRDY (1 << 10)__DBL_MIN__ ((double)2.2250738585072014e-308L)RCC_CFGR_STOPWUCK_MSI (0 << 15)TIM_OC2NTIM_CCMR1_IC2F_MASK (0xF << 12)__INT_FAST8_MAX__ 0x7fffffff__INT16_MAX__ 0x7fffRCC_APB1SMENR1_TIM3SMEN (1 << 1)RCC_CR_PLLSAI2ON (1 << 28)TIM2_CCMR2 TIM_CCMR2(TIM2)__INT_FAST8_WIDTH__ 32RCC_CCIPR_I2CxSEL_HSI16 2RCC_AHB3SMENR_OFFSET 0x70TIM8_RCR TIM_RCR(TIM8)TIM_CCMR1_IC1PSC_2 (0x1 << 2)__LDBL_MAX__ 1.7976931348623157e+308LINT_FAST32_MAXRCC_AHB3RSTR_OFFSET 0x30__ARM_FP16_ARGS__FLT32_MIN_EXP__ (-125)ST_VREFINT_CAL MMIO16((INFO_BASE + 0x75aa))CORESIGHT_LSR_SLK (1<<1)TIM16_CCR1 TIM_CCR1(TIM16)__UINT32_C(c) c ## UL__LDBL_MIN_EXP__ (-1021)__DBL_MIN_10_EXP__ (-307)IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)BIT7 (1<<7)GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000)TIM8_BDTR TIM_BDTR(TIM8)TIM_CR2_MMS_COMPARE_OC4REF (0x7 << 4)TIM6_CR1 TIM_CR1(TIM6)RCC_PLLCFGR_PLLSRC_NONE 0TIM_CCMR2_IC4F_DTF_DIV_2_N_6 (0x4 << 12)TIM17_CCMR1 TIM_CCMR1(TIM17)RCC_CCIPR_USART2SEL_SHIFT 2TIM_CCMR1_IC2F_OFF (0x0 << 12)timer_peripheralRCC_APB1SMENR1_OFFSET 0x78INT_LEAST64_MAX __INT_LEAST64_MAX__INT64_CTIM_PSC(tim_base) MMIO32((tim_base) + 0x28)__UDQ_IBIT__ 0AES_BASE (0x50000000U + 0x60000)RCC_CCIPR_USART1SEL_HSI16 2__DBL_MANT_DIG__ 53__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)TIM1_CCR4 TIM_CCR4(TIM1)TIM_CCMR2_IC4F_MASK (0xF << 12)__PTRDIFF_WIDTH__ 32TIM_CCMR1_IC2F_DTF_DIV_32_N_8 (0xF << 12)RCC_AHB1SMENR_OFFSET 0x68INT8_MAX __INT8_MAX____ULLACCUM_MIN__ 0.0ULLKTIM15_DIER TIM_DIER(TIM15)TIM3_CCR4 TIM_CCR4(TIM3)TIM_SMCR_ETF_DTS_DIV_4_N_6 (0x6 << 8)RCC_APB1SMENR1_TIM2SMEN (1 << 0)RCC_APB1SMENR1_USART2SMEN (1 << 17)INT_FAST64_MAXRCC_CICR_LSIRDYC (1 << 0)timer_set_oc_modeTIM12_CCR2 TIM_CCR2(TIM12)timer_set_prescalerDESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)RCC_APB2SMENR_SYSCFGSMEN (1 << 0)TIM_CCMR2_IC4F_DTF_DIV_32_N_6 (0xE << 12)TIM_SR_CC3OF (1 << 11)RCC_APB2ENR_SAI1EN (1 << 21)__WINT_MAX__ 0xffffffffUTIM_SMCR_ETF_DTS_DIV_16_N_5 (0xA << 8)TIM_CCMR2_IC3F_CK_INT_N_2 (0x1 << 4)TIM_CCMR2_CC3S_IN_TI3 (0x1 << 0)__ARM_FP16_FORMAT_ALTERNATIVEmodeRCC_CCIPR_I2C2SEL_SHIFT 14TIM_CCMR2_CC4S_IN_TRC (0x3 << 8)UINTPTR_MAXRCC_CCIPR_LPTIMxSEL_APB 0INT32_C(c) __INT32_C(c)_REG_BIT(base,bit) (((base) << 5) + (bit))RCC_AHB1SMENR_SRAM1SMEN (1 << 9)__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1__UINT32_TYPE__ long unsigned int__FLT_EPSILON__ 1.1920928955078125e-7FTIM_CCER_CC4P (1 << 13)RCC_PLLCFGR_PLLR_MASK 0x3__UINT8_C(c) cLIBOPENCM3_RCC_COMMON_ALL_H TIM_SR_UIF (1 << 0)RCC_CFGR_SWS_HSE 0x2__ARM_FEATURE_NUMERIC_MAXMINRCC_CFGR_MCOPRE_MASK 0x7RCC_AHB3SMENR MMIO32(RCC_BASE + RCC_AHB3SMENR_OFFSET)INT8_C(c) __INT8_C(c)UINT16_MAX __UINT16_MAX__RCC_AHB2RSTR_GPIOGRST (1 << 6)__ULLFRACT_MIN__ 0.0ULLRdirectionRCC_CCIPR_ADCSEL_NONE 0TIM_CCMR2_OC3M_PWM2 (0x7 << 4)TIM17 TIM17_BASEunsigned charTIM_CCMR1_IC2F_DTF_DIV_8_N_6 (0x8 << 12)TIM_CCMR2_IC3PSC_OFF (0x0 << 2)__LDBL_DIG__ 15__ARM_FEATURE_QRDMXRCC_CCIPR_LPTIMxSEL_LSE 3BIT8 (1<<8)__SFRACT_IBIT__ 0TIM_CCMR2_IC3F_DTF_DIV_8_N_6 (0x8 << 4)RCC_CIFR_HSIRDYF (1 << 3)TIM2_CCER TIM_CCER(TIM2)FMC3_BANK_BASE (0x80000000U)TIM_IC3TIM_IC4TIM9_SMCR TIM_SMCR(TIM9)RCC_APB1RSTR1_LPTIM1RST (1 << 31)RCC_APB1ENR1_CAN1EN (1 << 25)timer_set_break_lockTIM4_CCER TIM_CCER(TIM4)__FLT_DIG__ 6TIM14_EGR TIM_EGR(TIM14)TIM3_CCR3 TIM_CCR3(TIM3)RCC_CR_PLLSAI1RDY (1 << 27)__DBL_MAX_EXP__ 1024TIM_CCMR2_OC3M_PWM1 (0x6 << 4)TIM_CR2_MMS_ENABLE (0x1 << 4)__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULK__LLFRACT_IBIT__ 0__UINT_LEAST16_MAX__ 0xffffTIM6_CR2 TIM_CR2(TIM6)__SIZE_WIDTH__ 32TIM_CR1_CKD_CK_INT_MASK (0x3 << 8)__ARM_FEATURE_FP16_FMLTIM5_CCR2 TIM_CCR2(TIM5)TIM_CCMR2_IC4F_DTF_DIV_32_N_8 (0xF << 12)__ULFRACT_FBIT__ 32RCC_APB1RSTR1_TIM3RST (1 << 1)BIT2 (1<<2)TIM_CR1_CMS_CENTER_1 (0x1 << 5)TIM17_DMAR TIM_DMAR(TIM17)RCC_CCIPR_CLK48SEL_PLL 2TIM_CCMR1_OC1M_FORCE_HIGH (0x5 << 4)TIM12_CCR1 TIM_CCR1(TIM12)RCC_AHB2ENR_ADCEN (1 << 13)TIM_CCMR1_OC2M_INACTIVE (0x2 << 12)INT_LEAST16_MAX __INT_LEAST16_MAX____UINT_LEAST64_MAX__ 0xffffffffffffffffULLRCC_APB1SMENR1_WWDGSMEN (1 << 11)TIM_SR_CC1OF (1 << 9)TIM15_DCR TIM_DCR(TIM15)RCC_CCIPR_USART1SEL_LSE 3TIM_BDTR_BKP (1 << 13)BEGIN_DECLS tim_et_pol__SFRACT_FBIT__ 7DMA2_BASE (PERIPH_BASE_AHB1 + 0x0400)__LLACCUM_EPSILON__ 0x1P-31LLKTIM12_SMCR TIM_SMCR(TIM12)RCC_CSR_OBLRSTF (1 << 25)PTRDIFF_MIN (-PTRDIFF_MAX - 1)TIM_IC_IN_TI1TIM1_CCMR1 TIM_CCMR1(TIM1)TIM14_ARR TIM_ARR(TIM14)__SIZEOF_LONG_LONG__ 8TIM_CCMR1_IC2F_DTF_DIV_8_N_8 (0x9 << 12)FIREWALL_BASE (PERIPH_BASE_APB2 + 0x1C00)SIZE_MAXRCC_CR_MSIRANGE_200KHZ 1WCHAR_MAX __WCHAR_MAX__RCC_AHB1RSTR_FLASHRST (1 << 8)__FLT32_DECIMAL_DIG__ 9TIM_CCMR2_OC3M_MASK (0x7 << 4)QUADSPI_BANK_BASE (0x90000000U)TIM_EGR(tim_base) MMIO32((tim_base) + 0x14)TIM7_CR1 TIM_CR1(TIM7)GPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000)RCC_PLLCFGR_PLLSRC_MSI 1BIT9 (1<<9)TIM_SMCR_TS_TI1F_ED (0x4 << 4)TIM14_CCER TIM_CCER(TIM14)RCC_CR_MSIRANGE_SHIFT 4timer_set_output_idle_state__FLT32X_MANT_DIG__ 53TIM3 TIM3_BASERCC_CR_HSIKERON (1 << 9)TIM8_DIER TIM_DIER(TIM8)__WINT_TYPE__ unsigned intTIM_EGR_BG (1 << 7)UINT_LEAST32_MAX __UINT_LEAST32_MAX__RCC_CFGR_MCO_MSI 0x2SCB_BASE (SCS_BASE + 0x0D00)RCC_APB1ENR1_OFFSET 0x58TIM5_SR TIM_SR(TIM5)TIM_CR2_OIS3 (1 << 12)RCC_PLLCFGR_PLLSRC_HSI16 2RCC_AHB3SMENR_FMCSMEN (1 << 0)TIM12_PSC TIM_PSC(TIM12)__FLT_MANT_DIG__ 24RCC_AHB2ENR_RNGEN (1 << 18)__ULACCUM_FBIT__ 32TIM1_BASE (PERIPH_BASE_APB2 + 0x2C00)RCC_APB2RSTR_SAI2RST (1 << 22)RCC_CCIPR_LPUART1SEL_HSI16 2timer_set_disabled_off_state_in_idle_modeTIM2_DCR TIM_DCR(TIM2)TIM1_RCR TIM_RCR(TIM1)RCC_BDCR_RTCSEL_NONE 0RCC_CRRCR_HSI48RDY (1 << 1)__ARM_ARCH_PROFILE 77timer_update_on_anyTIM14_CNT TIM_CNT(TIM14)TIM10_SR TIM_SR(TIM10)__ARM_FEATURE_COPROC 15BIT20 (1<<20)STM32L4 1TIM_CCMR1_CC1S_IN_TI1 (0x1 << 0)RCC_CCIPR_UARTxSEL_LSE RCC_CCIPR_USARTxSEL_LSE__INT_LEAST8_MAX__ 0x7ftimer_get_flag__FLT_MIN_EXP__ (-125)TIM_CCMR1_IC1F_DTF_DIV_2_N_8 (0x5 << 4)oc_idRCC_ICSCR_HSITRIM_SHIFT 24__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__RCC_CFGR_PPRE2_SHIFT 11__UINT64_C(c) c ## ULL__FRACT_IBIT__ 0__FLT_RADIX__ 2__USA_FBIT__ 16TIM_DCR(tim_base) MMIO32((tim_base) + 0x48)__LDBL_IS_IEC_60559__ 2TIM_CCMR1_IC1F_CK_INT_N_2 (0x1 << 4)__FLT32X_DIG__ 15UINT_FAST8_MAX __UINT_FAST8_MAX____LDBL_EPSILON__ 2.2204460492503131e-16LTIM1_CR2 TIM_CR2(TIM1)TIM_CCMR2_IC4F_DTF_DIV_2_N_8 (0x5 << 12)TIM16_CCER TIM_CCER(TIM16)TIM_CCMR2_IC3F_DTF_DIV_16_N_6 (0xB << 4)__FLT_EVAL_METHOD_TS_18661_3__ 0TIM8_CCR4 TIM_CCR4(TIM8)__SQ_FBIT__ 31timer_set_oc_polarity_high__UINTMAX_MAX__ 0xffffffffffffffffULLTIM_DIER_CC4IE (1 << 4)RCC_APB1ENR1_I2C2EN (1 << 22)__USA_IBIT__ 16__ACCUM_EPSILON__ 0x1P-15KTIM16_CR2 TIM_CR2(TIM16)RCC_PLLSAI2_CFGR MMIO32(RCC_BASE + 0x14)RCC_CCIPR_USART1SEL_MASK 0x3__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LKRCC_CFGR_HPRE_DIV16 0xbTIM12_ARR TIM_ARR(TIM12)BIT21 (1<<21)RCC_PLLCFGR_PLLQEN (1 << 20)TIM5_CCR1 TIM_CCR1(TIM5)RCC_APB2ENR_SYSCFGEN (1 << 0)RCC_CCIPR_I2CxSEL_APB 0TIM15_SR TIM_SR(TIM15)RCC_CCIPR_UART4SEL_SHIFT 6INT_FAST32_MIN__FRACT_EPSILON__ 0x1P-15RTIM_CCMR2_CC4S_IN_TI3 (0x2 << 8)RCC_PLLCFGR_PLLQ_DIV6 2__FLT_MIN_10_EXP__ (-37)timer_disable_compare_control_update_on_triggerTIM_CCMR2_IC3F_DTF_DIV_16_N_5 (0xA << 4)BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)RCC_PLLCFGR_PLLSRC_HSE 3TIM7_CR2 TIM_CR2(TIM7)TIM11_CCMR1 TIM_CCMR1(TIM11)__INT_WIDTH__ 32I2C3_BASE (PERIPH_BASE_APB1 + 0x5c00)TIM_CCMR1_IC2F_DTF_DIV_4_N_6 (0x6 << 12)TIM_CCMR2_IC3F_DTF_DIV_2_N_8 (0x5 << 4)TIM_CCMR2_IC4F_DTF_DIV_8_N_6 (0x8 << 12)RCC_CFGR_SW_SHIFT 0PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)TIM_DMAR(tim_base) MMIO32((tim_base) + 0x4C)RCC_BDCR_LSERDY (1 << 1)RCC_CFGR_MCO_HSI16 0x3RCC_AHB2ENR_GPIOAEN (1 << 0)CORESIGHT_LAR_KEY 0xC5ACCE55NVIC_BASE (SCS_BASE + 0x0100)__UDQ_FBIT__ 64RCC_CCIPR_I2C3SEL_SHIFT 16__FLT64_DIG__ 15__ARM_NEON__INT_LEAST16_WIDTH__ 16RCC_AHB2SMENR_AESSMEN (1 << 16)__ARM_ARCH_7EM__ 1timer_get_counter__INT16_C(c) cINT_FAST8_MAXRCC_CIFR_PLLRDYF (1 << 5)RCC_APB1RSTR1_OFFSET 0x38__FLT32X_DECIMAL_DIG__ 17timer_enable_irqTIM9_SR TIM_SR(TIM9)__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2TIM10_CCER TIM_CCER(TIM10)__INT16_TYPE__ short intRCC_APB2RSTR_DFSDMRST (1 << 24)TIM_CR2_OIS1N (1 << 9)UINTMAX_CRCC_CFGR_SWS_MSI 0x0__bool_true_false_are_defined 1RCC_CCIPR_ADCSEL_PLLSAI1R 1__FRACT_MIN__ (-0.5R-0.5R)SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)TIM10_CR1 TIM_CR1(TIM10)SWPMI1_BASE (PERIPH_BASE_APB1 + 0x8800)RCC_CCIPR_LPUART1SEL_SHIFT 10TIM_CCMR2_OC3M_ACTIVE (0x1 << 4)RCC_CIER_PLLSAI2RDYIE (1 << 7)TIM_CCMR1_CC2S_IN_TRC (0x3 << 8)TIM_CCMR1_IC1F_DTF_DIV_4_N_6 (0x6 << 4)RCC_PLLCFGR_PLLR_DIV6 2__GCC_ATOMIC_LONG_LOCK_FREE 2_GCC_STDINT_H TIM_SMCR_ETPS_ETRP_DIV_2 (0x1 << 12)PTRDIFF_MAX __PTRDIFF_MAX____GXX_TYPEINFO_EQUALITY_INLINE 0RCC_CIER_MSIRDYIE (1 << 2)__UHQ_FBIT__ 16uint8_tINT16_C(c) __INT16_C(c)INTMAX_MIN (-INTMAX_MAX - 1)timer_one_shot_modeRCC_BDCR_LSCOSEL (1 << 25)TIM_CR1_DIR_UP (0 << 4)TIM8_CR1 TIM_CR1(TIM8)RCC_CFGR_SWS_PLL 0x3RCC_CSR_MSIRANGE_1MHZ 4RCC_CFGR_MCOPRE_DIV16 4__INT_MAX__ 0x7fffffffRCC_BDCR_LSEDRV_LOW 0TIM16_BASE (PERIPH_BASE_APB2 + 0x4400)TIM_BDTR_LOCK_LEVEL_1 (0x1 << 8)BIT23 (1<<23)TIM5_CCMR1 TIM_CCMR1(TIM5)__FP_FAST_FMAF 1RCC_AHB1ENR_FLASHEN (1 << 8)TIM3_SMCR TIM_SMCR(TIM3)__WCHAR_MIN__ 0URCC_APB2SMENR_TIM16SMEN (1 << 17)RCC_CIFR MMIO32(RCC_BASE + 0x1c)TIM_DIER_TDE (1 << 14)TIM5_SMCR TIM_SMCR(TIM5)TIM_CCMR1_IC2F_DTF_DIV_4_N_8 (0x7 << 12)RCC_CSR_MSIRANGE_MASK 0xfTIM_CCMR1_IC1PSC_OFF (0x0 << 2)RCC_BDCR_LSEDRV_MEDHIGH 2RCC_APB2ENR_FWEN (1 << 7)TIM10_ARR TIM_ARR(TIM10)timer_set_dma_on_update_eventRCC_APB2ENR_OFFSET 0x60RCC_CFGR_HPRE_NODIV 0x0__LLFRACT_EPSILON__ 0x1P-63LLR__INT_FAST64_WIDTH__ 64__FRACT_FBIT__ 15TIM_CCMR1_OC1M_FROZEN (0x0 << 4)RCC_CFGR_PPRE1_DIV8 0x6TIM_CCMR1_OC1M_INACTIVE (0x2 << 4)__ATOMIC_ACQ_REL 4__INT32_MAX__ 0x7fffffffLTIM_CCMR2_CC4S_MASK (0x3 << 8)TIM_CR2_OIS2 (1 << 10)__CHAR_UNSIGNED__ 1TIM_BDTR_LOCK_LEVEL_3 (0x3 << 8)RCC_CR_MSIRANGE_400KHZ 2BIT24 (1<<24)RCC_CFGR_SW_MSI 0x0TIM_CCMR1_IC2PSC_2 (0x1 << 10)TIM4_CR1 TIM_CR1(TIM4)__SCHAR_MAX__ 0x7f__GCC_HAVE_DWARF2_CFI_ASM 1TIM13_ARR TIM_ARR(TIM13)TIM13_CNT TIM_CNT(TIM13)INT16_MAX __INT16_MAX____TA_IBIT__ 64TPIU_BASE (PPBI_BASE + 0x40000)TIM_IC_DTF_DIV_8_N_6TIM_IC_DTF_DIV_8_N_8RCC_CCIPR_ADCSEL_SHIFT 28DAC_BASE (PERIPH_BASE_APB1 + 0x7400)timer_disable_counter__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRRCC_CR_MSIRANGE_48MHZ 11tim_ic_pscTIM15_CCR1 TIM_CCR1(TIM15)RCC_AHB2SMENR_OFFSET 0x6cTIM2_CR2 TIM_CR2(TIM2)__ULFRACT_EPSILON__ 0x1P-32ULRTIM_BDTR_LOCK_LEVEL_2 (0x2 << 8)TIM8_SR TIM_SR(TIM8)RCC_ICSCR_MSICAL_SHIFT 0INT_LEAST32_MAX __INT_LEAST32_MAX__TIM_IC_PSC_4TIM16_PSC TIM_PSC(TIM16)TIM_CR1_UDIS (1 << 1)TIM_CCMR1_IC1PSC_8 (0x3 << 2)__FLT_HAS_QUIET_NAN__ 1TIM_CCMR2_OC4PE (1 << 11)UINT_FAST64_MAX __UINT_FAST64_MAX__TIM15_CR1 TIM_CR1(TIM15)BIT25 (1<<25)__FLT32X_NORM_MAX__ 1.7976931348623157e+308F32xRCC_PLLCFGR_PLLP_DIV7 0TIM_SR_CC2IF (1 << 2)TIM_CCMR2_OC4M_PWM2 (0x7 << 12)TIM2_DIER TIM_DIER(TIM2)USART1_BASE (PERIPH_BASE_APB2 + 0x3800)STIR_BASE (SCS_BASE + 0x0F00)TIM5_CCMR2 TIM_CCMR2(TIM5)RCC_AHB1ENR_DMA2EN (1 << 1)TIM8_CR2 TIM_CR2(TIM8)RCC_AHB2SMENR_SRAM2SMEN (1 << 9)TIM4_DIER TIM_DIER(TIM4)TIM1_PSC TIM_PSC(TIM1)RCC_CR_MSIRANGE_24MHZ 9__SCHAR_WIDTH__ 8__ORDER_PDP_ENDIAN__ 3412__ATOMIC_ACQUIRE 2timer_set_disabled_off_state_in_run_mode__INT_FAST32_WIDTH__ 32__INT_FAST64_TYPE__ long long inttimer_set_master_mode__ACCUM_FBIT__ 15RCC_AHB2SMENR_GPIOHSMEN (1 << 7)__INT_LEAST64_MAX__ 0x7fffffffffffffffLLTIM_CCMR1_IC1F_DTF_DIV_16_N_8 (0xC << 4)__ARM_FEATURE_QBIT 1CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)TIM_SR_CC2OF (1 << 10)UINT32_C(c) __UINT32_C(c)TIM_CCMR1_IC2F_DTF_DIV_2_N_6 (0x4 << 12)deadtimeRCC_CR_MSION (1 << 0)TIM_CCMR1_IC2PSC_4 (0x2 << 10)__SACCUM_MAX__ 0X7FFFP-7HKTIM_CCMR1_CC1S_IN_TI2 (0x2 << 0)INTMAX_MAXTIM_CR1_OPM (1 << 3)TIM2 TIM2_BASETIM3_EGR TIM_EGR(TIM3)__ACCUM_IBIT__ 16TIM_CCMR2_IC3F_DTF_DIV_32_N_5 (0xD << 4)TIM6_CNT TIM_CNT(TIM6)__INTMAX_WIDTH__ 64RCC_BDCR_LSCOEN (1 << 24)TIM_CCR2(tim_base) MMIO32((tim_base) + 0x38)timer_disable_break_automatic_outputDBGMCU_BASE (PPBI_BASE + 0x00042000)__INT_LEAST64_WIDTH__ 64valueTIM_CCER(tim_base) MMIO32((tim_base) + 0x20)RCC_CIFR_HSI48RDYF (1 << 10)RCC_ICSCR_HSICAL_SHIFT 16RCC_APB1ENR1_USART2EN (1 << 17)RCC_CCIPR_USARTxSEL_LSE 3TIM_DIER_CC1DE (1 << 9)TIM_SMCR_ETPS_ETRP_DIV_4 (0x2 << 12)__ARM_32BIT_STATE 1__ATOMIC_RELAXED 0TIM9_CR1 TIM_CR1(TIM9)RCC_CFGR_PPRE1_MASK 0x7__LFRACT_MAX__ 0X7FFFFFFFP-31LR__LDBL_MIN__ 2.2250738585072014e-308LRCC_CCIPR_USART1SEL_SHIFT 0RCC_APB1RSTR2_LPTIM2RST (1 << 5)__ULACCUM_IBIT__ 32TIM_SMCR_SMS_EM3 (0x3 << 0)RCC_CIFR_PLLSAI2RDYF (1 << 7)__THUMB_INTERWORK__ 1TIM_CCMR2_CC4S_IN_TI4 (0x1 << 8)PPBI_BASE (0xE0000000U)TIM4_CCR4 TIM_CCR4(TIM4)BIT27 (1<<27)TIM_CR2_MMS_UPDATE (0x2 << 4)__FRACT_MAX__ 0X7FFFP-15RRCC_CFGR_HPRE_DIV64 0xcTIM_BDTR_LOCK_MASK (0x3 << 8)RCC_APB1RSTR1_UART4RST (1 << 19)__GCC_IEC_559 0__FLT_IS_IEC_60559__ 2__FLT32X_EPSILON__ 2.2204460492503131e-16F32xTIM_CCMR2_OC3CE (1 << 7)__UFRACT_IBIT__ 0RCC_CCIPR_SAI2SEL_SHIFT 24TIM_SMCR_SMS_EM2 (0x2 << 0)TIM_CCR4(tim_base) MMIO32((tim_base) + 0x40)TIM_CCMR2_OC4M_FROZEN (0x0 << 12)TIM9_CCMR1 TIM_CCMR1(TIM9)MMIO32(addr) (*(volatile uint32_t *)(addr))TIM_CR2_OIS3N (1 << 13)TIM_CCMR1_IC1F_DTF_DIV_2_N_6 (0x4 << 4)RCC_APB1RSTR2_OFFSET 0x3cRCC_AHB1ENR_CRCEN (1 << 12)TIM_CCMR1_IC2F_DTF_DIV_2_N_8 (0x5 << 12)TIM_DIER_UDE (1 << 8)TIM_CCMR1_IC1F_DTF_DIV_16_N_6 (0xB << 4)TIM_EGR_CC4G (1 << 4)__SIZE_MAX__ 0xffffffffUtimer_disable_break_main_output__ATOMIC_RELEASE 3BIT28 (1<<28)RCC_APB1RSTR1_I2C1RST (1 << 21)__INT_LEAST8_WIDTH__ 8TIM_CCMR1_CC1S_IN_TRC (0x3 << 0)__GNUC__ 12RCC_CCIPR_SAIxSEL_PLLSAI1P 0TIM_SMCR_SMS_MASK (0x7 << 0)__ARM_FEATURE_COPROCUINTMAX_MAX __UINTMAX_MAX__RCC_ICSCR MMIO32(RCC_BASE + 0x04)__INT_FAST16_TYPE__ intTIM4_SR TIM_SR(TIM4)TIM_SR_CC4OF (1 << 12)TIM16_DCR TIM_DCR(TIM16)RCC_CFGR_SWS_MASK 0x3__INT_LEAST32_WIDTH__ 32RCC_AHB1RSTR_TSCRST (1 << 16)__FLT32_IS_IEC_60559__ 2__UTQ_IBIT__ 0TIM_BDTR_DTG_MASK 0x00FFTIM_CCMR1_IC1F_DTF_DIV_16_N_5 (0xA << 4)__DBL_IS_IEC_60559__ 2TIM_CCMR1_IC2PSC_8 (0x3 << 10)__UTA_IBIT__ 64TIM16_CCMR1 TIM_CCMR1(TIM16)__SIZEOF_WINT_T__ 4RCC_CFGR_HPRE_DIV256 0xeRCC_AHB1RSTR_DMA2RST (1 << 1)TIM5_CCER TIM_CCER(TIM5)RCC_CCIPR_CLK48SEL_MSI 3INT_FAST8_MINRCC_APB1ENR1_DAC1EN (1 << 29)RCC_APB1RSTR1_USART2RST (1 << 17)TIM_CCMR2_IC3PSC_8 (0x3 << 2)RCC_CFGR_PPRE2_DIV2 0x4TIM_CCMR2_IC4PSC_OFF (0x0 << 10)__ARM_FEATURE_SAT 1RCC_APB1ENR1_PWREN (1 << 28)INT16_MIN (-INT16_MAX - 1)TIM13_EGR TIM_EGR(TIM13)__FLT_MAX__ 3.4028234663852886e+38F__INT_LEAST8_TYPE__ signed char__GXX_ABI_VERSION 1017BIT29 (1<<29)INT32_CTIM_CCMR1_IC1PSC_MASK (0x3 << 2)TIM_IC_PSC_OFFTIM_SMCR_SMS_OFF (0x0 << 0)__ARM_ARCH_ISA_THUMB../common/timer_common_all.c__FLT64_IS_IEC_60559__ 2timer_disable_oc_preloadTIM16 TIM16_BASETIM11_DIER TIM_DIER(TIM11)INTMAX_CTIM2_PSC TIM_PSC(TIM2)__USACCUM_MAX__ 0XFFFFP-8UHKRCC_AHB2ENR_GPIOEEN (1 << 4)__WINT_MIN__ 0U__INT8_MAX__ 0x7fRCC_AHB2ENR_OFFSET 0x4ctimer_slave_set_filterTIM_CCER_CC2NP (1 << 7)__INT_LEAST32_MAX__ 0x7fffffffLTIM_CCMR2_CC3S_OUT (0x0 << 0)TIM_SR_CC3IF (1 << 3)TIM17_ARR TIM_ARR(TIM17)TIM_CCER_CC2NE (1 << 6)TIM17_CNT TIM_CNT(TIM17)RCC_CCIPR_USARTxSEL_MASK 0x3__USACCUM_EPSILON__ 0x1P-8UHKRCC_AHB2SMENR_GPIOBSMEN (1 << 1)RCC_CFGR MMIO32(RCC_BASE + 0x08)period__USFRACT_EPSILON__ 0x1P-8UHRRCC_CFGR_MCOPRE_SHIFT 28__INTMAX_C(c) c ## LL__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)SAI1_BASE (PERIPH_BASE_APB2 + 0x5400)__UINT_FAST16_MAX__ 0xffffffffU__ARM_ARCH_EXT_IDIV__ 1__UINT_FAST64_TYPE__ long long unsigned intCOMP_BASE (PERIPH_BASE_APB2 + 0x0200)RCC_AHB2RSTR_OTGFSRST (1 << 12)TIM_CCMR2_OC3M_INACTIVE (0x2 << 4)BIT0 (1<<0)TIM4_EGR TIM_EGR(TIM4)TIM_RCR(tim_base) MMIO32((tim_base) + 0x30)TIM_CR2_MMS_COMPARE_OC2REF (0x5 << 4)RCC_CFGR_PPRE1_DIV2 0x4__UINT_LEAST32_MAX__ 0xffffffffULRTC_BASE (PERIPH_BASE_APB1 + 0x2800)__UFRACT_EPSILON__ 0x1P-16URTIM17_CCR1 TIM_CCR1(TIM17)RCC_APB2SMENR_TIM8SMEN (1 << 13)UART4_BASE (PERIPH_BASE_APB1 + 0x4c00)RCC_CSR_SFTRSTF (1 << 28)TIM_OCM_FORCE_HIGH__ULACCUM_MIN__ 0.0ULKTIM_CCMR1_OC1M_TOGGLE (0x3 << 4)RCC_APB2RSTR_SAI1RST (1 << 21)__SIZEOF_SIZE_T__ 4LIBOPENCM3_MEMORYMAP_COMMON_H TIM_IC_IN_TI2TIM_IC_IN_TI3TIM_IC_IN_TI4BIT19 (1<<19)timer_slave_set_polarity__UINT_FAST8_MAX__ 0xffffffffUTIM_IC_DTF_DIV_2_N_6TIM9_DIER TIM_DIER(TIM9)TIM_IC_DTF_DIV_2_N_8TIM_CCMR2_OC4M_FORCE_LOW (0x4 << 12)RCC_CIFR_HSERDYF (1 << 4)__SQ_IBIT__ 0LCD_BASE (PERIPH_BASE_APB1 + 0x2400)flagINT_FAST16_MIN (-INT_FAST16_MAX - 1)RCC_APB1RSTR1_TIM2RST (1 << 0)TIM_BDTR_DBA_MASK (0x1F << 0)TIM3_SR TIM_SR(TIM3)RCC_PLLCFGR_PLLSRC_SHIFT 0RCC_CCIPR_CLK48SEL_SHIFT 26__UHQ_IBIT__ 0TIM1_CCR3 TIM_CCR3(TIM1)ST_TSENSE_CAL2_110C MMIO16((INFO_BASE + 0x75ca))RCC_APB2SMENR_TIM15SMEN (1 << 16)RCC_AHB3SMENR_QSPISMEN (1 << 8)__SFRACT_MIN__ (-0.5HR-0.5HR)__thumb2__ 1__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1RCC_AHB2ENR MMIO32(RCC_BASE + RCC_AHB2ENR_OFFSET)__LACCUM_FBIT__ 31LPTIM2_BASE (PERIPH_BASE_APB1 + 0x9400)TIM_IC_DTF_DIV_16_N_5TIM_IC_DTF_DIV_16_N_6TIM_CCMR1_OC2M_MASK (0x7 << 12)TIM_IC_DTF_DIV_16_N_8RCC_CFGR_MCOPRE_DIV1 0RCC_CCIPR_I2CxSEL_MASK 0x3RCC_CR_MSIRANGE_4MHZ 6RCC_CFGR_SW_HSE 0x2TIM_BDTR(tim_base) MMIO32((tim_base) + 0x44)RCC_PLLCFGR_PLLQ_DIV8 3RCC_CCIPR_CLK48SEL_MASK 0x3TIM_CCMR1_IC1PSC_4 (0x2 << 2)RCC_PLLCFGR_PLLN_SHIFT 0x8__LONG_MAX__ 0x7fffffffLTIM16_DMAR TIM_DMAR(TIM16)timer_set_dma_on_compare_event__INT32_C(c) c ## LVREFBUF_BASE (PERIPH_BASE_APB2 + 0x0030)TIM_SMCR_ETF_DTS_DIV_8_N_6 (0x8 << 8)__FLT64_NORM_MAX__ 1.7976931348623157e+308F64TIM_DIER_CC3IE (1 << 3)WINT_MAX __WINT_MAX__TIM_CCMR1_OC2M_PWM2 (0x7 << 12)triggerINT_FAST16_MAX __INT_FAST16_MAX__RCC_APB1SMENR1_I2C3SMEN (1 << 23)TIM_CR2(tim_base) MMIO32((tim_base) + 0x04)RCC_ICSCR_HSICAL_MASK 0xffRCC_CICR_LSECSSC (1 << 9)RCC_PLLPEN (1 << 16)__FLT32X_IS_IEC_60559__ 2timer_set_mode__SACCUM_EPSILON__ 0x1P-7HKRCC_APB1SMENR1_TIM5SMEN (1 << 3)RNG_BASE (0x50000000U + 0x60800)timer_direction_downUINT_FAST32_MAX __UINT_FAST32_MAX__TIM_CCMR1_CC2S_IN_TI1 (0x2 << 8)RCC_CIER_LSE_CSSIE (1 << 9)TIM1_CNT TIM_CNT(TIM1)UINT32_CTIM2_BASE (PERIPH_BASE_APB1 + 0x0000)TIM1_ARR TIM_ARR(TIM1)short unsigned intRCC_AHB2RSTR_AESRST (1 << 16)__LDBL_DECIMAL_DIG__ 17signed charRCC_CFGR_PPRE2_DIV4 0x5LIBOPENCM3_RCC_H TIM_CCER_CC3NP (1 << 11)RCC_APB2SMENR_SAI2SMEN (1 << 22)TIM_CCMR2_CC3S_MASK (0x3 << 0)TIM_CCMR2_IC4PSC_MASK (0x3 << 10)INTMAX_C(c) __INTMAX_C(c)timer_generate_eventTIM9_PSC TIM_PSC(TIM9)TIM_SR_CC4IF (1 << 4)DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 0x14)__CHAR_BIT__ 8INTMAX_MINTIM_CCMR2_IC3F_CK_INT_N_4 (0x2 << 4)RCC_CR_MSIRANGE_2MHZ 5TIM13_CCER TIM_CCER(TIM13)TIM14_CCMR1 TIM_CCMR1(TIM14)TIM_CCMR2_CC4S_OUT (0x0 << 8)RCC_CFGR_PPRE1_SHIFT 8countTIM_BDTR_AOE (1 << 14)timer_disable_break__ARM_FEATURE_DOTPRODTIM_CCMR1_OC1M_PWM2 (0x7 << 4)timer_set_periodTIM1 TIM1_BASETIM_SR_TIF (1 << 6)TIM3_PSC TIM_PSC(TIM3)RCC_CFGR_PPRE2_DIV8 0x6TIM_CR1_CKD_CK_INT_MUL_2 (0x1 << 8)TIM_IC2__CHAR16_TYPE__ short unsigned intRCC_CCIPR_USARTxSEL_APB 0__FLT64_MIN__ 2.2250738585072014e-308F64__INTPTR_MAX__ 0x7fffffff__UINT16_TYPE__ short unsigned intINTPTR_MAXFLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000)RCC_CCIPR_ADCSEL_PLLSAI2R 2__GCC_ATOMIC_POINTER_LOCK_FREE 2RCC_CSR_FWRSTF (1 << 24)timer_interrupt_source__DBL_MAX__ ((double)1.7976931348623157e+308L)RCC_CFGR_MCOPRE_DIV2 1TIM_CCMR1_OC1M_PWM1 (0x6 << 4)__FLT32_MAX_10_EXP__ 38__ORDER_LITTLE_ENDIAN__ 1234TIM_CCMR2_IC3F_DTF_DIV_2_N_6 (0x4 << 4)INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)TIM3_CCR1 TIM_CCR1(TIM3)TIM_CCMR2_OC4M_INACTIVE (0x2 << 12)TIM5_EGR TIM_EGR(TIM5)ITR_BASE (SCS_BASE + 0x0000)INT_LEAST8_MAX__WINT_WIDTH__ 32RCC_APB1RSTR2_SWPMI1RST (1 << 2)timer_set_enabled_off_state_in_run_modePERIPH_BASE (0x40000000U)__SIZEOF_INT__ 4tim_ic_filter__LDBL_HAS_DENORM__ 1TIM5 TIM5_BASEtimer_disable_oc_output__ARM_FP16_FORMAT_IEEETIM_CCMR2_OC4M_FORCE_HIGH (0x5 << 12)TIM17_EGR TIM_EGR(TIM17)RCC_CCIPR_ADCSEL_SYS 3RCC_CIFR_CSSF (1 << 8)RCC_APB1ENR1_TIM3EN (1 << 1)RCC_AHB2ENR_GPIOFEN (1 << 5)__USES_INITFINI__ 1BIT30 (1<<30)__FLT64_MAX_EXP__ 1024RCC_APB1ENR1_LCDEN (1 << 9)RCC_CR_PLLSAI2RDY (1 << 29)RCC_CFGR_PPRE1_DIV16 0x7__INTPTR_TYPE__ int__REGISTER_PREFIX__ RCC_CFGR_PPRE2_MASK 0x7RCC_BDCR_RTCSEL_LSE 1__USFRACT_MAX__ 0XFFP-8UHRTIM4_DCR TIM_DCR(TIM4)PERIPH_BASE_AHB2 (0x48000000U)CRS_BASE (PERIPH_BASE_APB1 + 0x6000)RCC_CRRCR MMIO32(RCC_BASE + 0x98)WCHAR_MIN __WCHAR_MIN____FLT32_MAX__ 3.4028234663852886e+38F32TIM10_CCMR1 TIM_CCMR1(TIM10)TIM4_CCMR1 TIM_CCMR1(TIM4)TIM_CR2_CCPC (1 << 0)INT_FAST8_MAX __INT_FAST8_MAX__TIM_CCMR2_OC4M_PWM1 (0x6 << 12)timer_ic_disableRCC_AHB2SMENR_OTGFSSMEN (1 << 12)RCC_AHB2SMENR_RNGSMEN (1 << 18)TIM1_CCR2 TIM_CCR2(TIM1)TIM_CCMR1_OC1M_MASK (0x7 << 4)TIM_CCMR1_OC1PE (1 << 3)__USQ_FBIT__ 32TIM_CCMR1_OC2M_FORCE_LOW (0x4 << 12)__INT_FAST8_TYPE__ intTIM_ET_RISINGUINT8_C(c) __UINT8_C(c)UINT32_MAXRCC_APB1SMENR1_SPI3SMEN (1 << 15)__ARM_FEATURE_BF16_SCALAR_ARITHMETIC__FLT_MIN__ 1.1754943508222875e-38FRCC_CSR MMIO32(RCC_BASE + 0x94)__STDC_HOSTED__ 1__UINTMAX_C(c) c ## ULLTIM_CCER_CC4E (1 << 12)RCC_APB2RSTR_SYSCFGRST (1 << 0)GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400)TIM16_SR TIM_SR(TIM16)__UACCUM_MAX__ 0XFFFFFFFFP-16UKTIM12_CNT TIM_CNT(TIM12)RCC_CSR_LPWRRSTF (1 << 31)FMC1_BANK_BASE (0x60000000U)TIM_OCM_FROZENlong intRCC_CFGR_MCO_SYSCLK 0x1TIM_ET_FALLINGTIM2_CNT TIM_CNT(TIM2)__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)TIM2_ARR TIM_ARR(TIM2)INT16_MAX__DBL_HAS_DENORM__ 1TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1__FLT64_MAX_10_EXP__ 308__PTRDIFF_TYPE__ intTIM8_CCR1 TIM_CCR1(TIM8)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2TIM_CCMR2_OC3M_FROZEN (0x0 << 4)TIM_CCMR1_OC2M_FORCE_HIGH (0x5 << 12)__USACCUM_FBIT__ 8RCC_AHB1RSTR_CRCRST (1 << 12)__GNUC_STDC_INLINE__ 1TIM5_CNT TIM_CNT(TIM5)UINT64_MAXTIM7 TIM7_BASERCC_APB2RSTR_TIM8RST (1 << 13)TIM15_PSC TIM_PSC(TIM15)RCC_CCIPR_LPTIMxSEL_MASK 0x3__ARM_FPGPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800)RCC_APB2ENR_TIM1EN (1 << 11)RCC_CICR_PLLRDYC (1 << 5)TIM14_CR1 TIM_CR1(TIM14)RCC_CICR_LSERDYC (1 << 1)RCC_CSR_BORRSTF (1 << 27)TIM_CR2_MMS_COMPARE_OC1REF (0x4 << 4)UINT_FAST8_MAXTIM_CCMR1_IC2F_CK_INT_N_8 (0x3 << 12)RCC_APB1SMENR1_UART5SMEN (1 << 20)TIM5_DIER TIM_DIER(TIM5)RCC_PLLCFGR_PLLR_DIV8 3RCC_APB2SMENR MMIO32(RCC_BASE + RCC_APB2SMENR_OFFSET)__UTQ_FBIT__ 128LIBOPENCM3_CM3_COMMON_H RCC_AHB2SMENR MMIO32(RCC_BASE + RCC_AHB2SMENR_OFFSET)TIM_SMCR_ETF_CK_INT_N_2 (0x1 << 8)RCC_CCIPR_CLK48SEL_HSI48 0RCC_APB1SMENR1_I2C1SMEN (1 << 21)RCC_CIFR_PLLSAI1RDYF (1 << 6)TIM9_EGR TIM_EGR(TIM9)TIM11_CCR1 TIM_CCR1(TIM11)__ARM_FEATURE_CRYPTOTIM4_PSC TIM_PSC(TIM4)TIM_OCM_TOGGLETIM_CCER_CC2E (1 << 4)RCC_CCIPR_LPTIM2SEL_SHIFT 20RCC_CICR_MSIRDYC (1 << 2)__FLT32_HAS_DENORM__ 1TIM12_CR1 TIM_CR1(TIM12)__UINT_FAST32_TYPE__ unsigned intRCC_CFGR_MCO_MASK 0xfRCC_AHB2RSTR_GPIOHRST (1 << 7)INT32_MIN (-INT32_MAX - 1)__ARM_FEATURE_FP16_SCALAR_ARITHMETICRCC_BDCR_LSEDRV_SHIFT 3__SACCUM_FBIT__ 7__HQ_FBIT__ 15TIM_CCMR1_IC1F_CK_INT_N_4 (0x2 << 4)__LLACCUM_IBIT__ 32uint32_tRCC_APB1SMENR2_LPTIM2SMEN (1 << 5)RCC_APB2SMENR_SPI1SMEN (1 << 12)__LLFRACT_FBIT__ 63timer_enable_compare_control_update_on_triggertimer_set_repetition_counterTIM_EGR_CC1G (1 << 1)RCC_APB1SMENR2 MMIO32(RCC_BASE + RCC_APB1SMENR2_OFFSET)SIG_ATOMIC_MIN __SIG_ATOMIC_MIN__TIM_CCER_CC1NP (1 << 3)RCC_CFGR_SW_PLL 0x3__GCC_ATOMIC_SHORT_LOCK_FREE 2RCC_CFGR_PPRE1_NODIV 0x0TIM_BDTR_BKE (1 << 12)tim_oc_mode__ULFRACT_MAX__ 0XFFFFFFFFP-32ULRTIM6_EGR TIM_EGR(TIM6)__SIZEOF_POINTER__ 4RCC_CCIPR_LPUART1SEL_APB 0__GCC_ASM_FLAG_OUTPUTS__ 1RCC_APB1SMENR1_CAN1SMEN (1 << 25)RCC_CR_MSIRANGE_32MHZ 10TIM_CCMR2_IC4F_CK_INT_N_2 (0x1 << 12)UINT_LEAST64_MAX __UINT_LEAST64_MAX____UINTMAX_TYPE__ long long unsigned intTIM_OCM_FORCE_LOWRCC_APB2SMENR_TIM17SMEN (1 << 18)timer_set_oc_polarity_low__INTPTR_WIDTH__ 32TIM_IC_IN_TRCINT_LEAST64_MIN (-INT_LEAST64_MAX - 1)INT_FAST16_MAXGPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0c00)USART3_BASE (PERIPH_BASE_APB1 + 0x4800)INTPTR_MINTIM5_CCR4 TIM_CCR4(TIM5)RCC_CR_MSIRANGE_MASK 0xfTIM_CCMR1_IC1F_DTF_DIV_8_N_6 (0x8 << 4)RCC_AHB1RSTR MMIO32(RCC_BASE + RCC_AHB1RSTR_OFFSET)__FLT64_HAS_INFINITY__ 1TIM_CR2_OIS2N (1 << 11)__GCC_DESTRUCTIVE_SIZE 64RCC_PLLCFGR_PLLREN (1<<24)RCC_BDCR_LSECSSD (1 << 6)TIM5_DCR TIM_DCR(TIM5)RCC_CR_MSIRANGE_1MHZ 4__LONG_LONG_MAX__ 0x7fffffffffffffffLLRCC_CR_PLLRDY (1 << 25)TIM10_DIER TIM_DIER(TIM10)timer_ic_set_prescalerTIM2_CCR1 TIM_CCR1(TIM2)__ULLACCUM_EPSILON__ 0x1P-32ULLK__GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"TIM1_BDTR TIM_BDTR(TIM1)MMIO64(addr) (*(volatile uint64_t *)(addr))__STDC_VERSION__ 199901L__LFRACT_MIN__ (-0.5LR-0.5LR)TIM_DIER(tim_base) MMIO32((tim_base) + 0x0C)PTRDIFF_MAXRCC_CFGR_MCO_NOCLK 0x0TIM_CNT(tim_base) MMIO32((tim_base) + 0x24)__LLFRACT_MIN__ (-0.5LLR-0.5LLR)RCC_CCIPR_ADCSEL_MASK 0x3INT64_C(c) __INT64_C(c)__GCC_ATOMIC_LLONG_LOCK_FREE 1__ULACCUM_EPSILON__ 0x1P-32ULKPERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)TIM_SMCR_ETF_OFF (0x0 << 8)TIM_IC_DTF_DIV_32_N_5TIM_IC_DTF_DIV_32_N_6TIM_IC_DTF_DIV_32_N_8TIM17_RCR TIM_RCR(TIM17)TIM_CCMR1_IC1F_DTF_DIV_4_N_8 (0x7 << 4)__LONG_LONG_WIDTH__ 64INT_LEAST64_MINRCC_AHB3ENR_OFFSET 0x50TIM8_CCMR1 TIM_CCMR1(TIM8)__VERSION__ "12.2.1 20221205"BIT26 (1<<26)__FLT64_EPSILON__ 2.2204460492503131e-16F64TIM_CCMR1_IC1F_CK_INT_N_8 (0x3 << 4)RCC_APB1SMENR1_PWRSMEN (1 << 28)TIM_CR1(tim_base) MMIO32((tim_base) + 0x00)GPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400)__ULLACCUM_FBIT__ 32TIM_CCER_CC1P (1 << 1)TIM3_CNT TIM_CNT(TIM3)__LDBL_HAS_QUIET_NAN__ 1TIM_CCMR2_IC4F_CK_INT_N_4 (0x2 << 12)TIM3_ARR TIM_ARR(TIM3)RCC_CR_CSSON (1 << 19)TIM2_CCR4 TIM_CCR4(TIM2)__WCHAR_MAX__ 0xffffffffUUART5_BASE (PERIPH_BASE_APB1 + 0x5000)TIM14_DIER TIM_DIER(TIM14)RCC_BDCR_LSEON (1 << 0)RCC_AHB1SMENR_FLASHSMEN (1 << 8)TIM_CCMR1_IC2F_CK_INT_N_2 (0x1 << 12)TIM5_CCR3 TIM_CCR3(TIM5)TIM_CCMR1_CC2S_MASK (0x3 << 8)__ULLACCUM_IBIT__ 32RCC_APB2SMENR_SAI1SMEN (1 << 21)__LDBL_MANT_DIG__ 53RCC_APB2ENR_USART1EN (1 << 14)__ULLFRACT_FBIT__ 64RCC_AHB2RSTR_OFFSET 0x2c__DQ_IBIT__ 0TIM12_EGR TIM_EGR(TIM12)__FLT64_MAX__ 1.7976931348623157e+308F64TIM_SMCR_ETF_DTS_DIV_16_N_8 (0xC << 8)INT_LEAST8_MINTIM_SMCR_TS_TI2FP2 (0x6 << 4)TIM_CR1_URS (1 << 2)CORESIGHT_LSR_SLI (1<<0)__UQQ_IBIT__ 0RCC_AHB2RSTR_GPIOCRST (1 << 2)LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))TIM_SMCR_ETF_DTS_DIV_16_N_6 (0xB << 8)DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x75e0)timer_enable_preload_complementry_enable_bitsTIM_CR1_CKD_CK_INT (0x0 << 8)TIM17_SR TIM_SR(TIM17)__ARM_FEATURE_CDETIM5_PSC TIM_PSC(TIM5)TIM_CCMR2_IC3F_DTF_DIV_32_N_8 (0xF << 4)TIM1_EGR TIM_EGR(TIM1)RCC_AHB2ENR_GPIODEN (1 << 3)RCC_CCIPR_USART1SEL_SYS 1TIM10_EGR TIM_EGR(TIM10)SYS_TICK_BASE (SCS_BASE + 0x0010)TIM_BDTR_OSSI (1 << 10)RCC_APB1ENR2_LPTIM2EN (1 << 5)__ARM_FEATURE_LDREXTIM16_ARR TIM_ARR(TIM16)TIM_OCM_PWM1TIM16_CNT TIM_CNT(TIM16)TIM4 TIM4_BASETIM_CR2_CCUS (1 << 2)__ACCUM_MIN__ (-0X1P15K-0X1P15K)__ORDER_BIG_ENDIAN__ 4321__ARM_FEATURE_CMSE/build/libopencm3/lib/stm32/l4PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)__UFRACT_MAX__ 0XFFFFP-16URRCC_AHB1RSTR_DMA1RST (1 << 0)TIM_CCMR1_OC2M_PWM1 (0x6 << 12)I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)TIM15 TIM15_BASERCC_AHB1ENR_OFFSET 0x48TIM_CCMR2_IC3PSC_MASK (0x3 << 2)__SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)TIM7_EGR TIM_EGR(TIM7)RCC_CSR_MSIRANGE_2MHZ 5RCC_APB1ENR1_SPI3EN (1 << 15)timer_enable_oc_outputtrue 1timer_enable_break_main_outputTIM_DIER_COMIE (1 << 5)RCC_APB1ENR1_TIM5EN (1 << 3)TIM_EGR_COMG (1 << 5)TIM17_CR2 TIM_CR2(TIM17)lockTIM_CCMR1_IC2F_CK_INT_N_4 (0x2 << 12)TIM15_CCMR1 TIM_CCMR1(TIM15)USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6c00)__FLT_DECIMAL_DIG__ 9TIM_OCM_ACTIVEBIT31 (1<<31)__INT32_TYPE__ long int__USACCUM_IBIT__ 8TIM14_CCR1 TIM_CCR1(TIM14)GPIO_PORT_H_BASE (PERIPH_BASE_AHB2 + 0x1c00)TIM8 TIM8_BASEtimer_enable_oc_preloadRCC_AHB3ENR MMIO32(RCC_BASE + RCC_AHB3ENR_OFFSET)RCC_CCIPR_I2CxSEL_SYS 1__ULFRACT_MIN__ 0.0ULRRCC_APB2RSTR_TIM16RST (1 << 17)tim_ic_inputTIM1_DMAR TIM_DMAR(TIM1)TIM_CCMR2_IC4F_CK_INT_N_8 (0x3 << 12)TIM_DIER_CC2IE (1 << 2)RCC_APB1RSTR1_DAC1RST (1 << 29)__ARM_FEATURE_SIMD32 1TIM_CCER_CC2P (1 << 5)__UINTPTR_TYPE__ unsigned intTIM_SMCR_ETP (1 << 15)__FINITE_MATH_ONLY__ 0UINT8_MAX __UINT8_MAX__TIM_DIER_CC3DE (1 << 11)TIM10_PSC TIM_PSC(TIM10)RCC_APB1RSTR1 MMIO32(RCC_BASE + RCC_APB1RSTR1_OFFSET)RCC_CFGR_PPRE1_DIV4 0x5__LFRACT_FBIT__ 31__ARM_FEATURE_DSP 1__ARM_FEATURE_BF16_VECTOR_ARITHMETICRCC_CFGR_MCO_SHIFT 24TIM15_RCR TIM_RCR(TIM15)UINT8_MAXTIM17_DIER TIM_DIER(TIM17)RCC_CFGR_HPRE_SHIFT 4RCC_AHB3ENR_QSPIEN (1 << 8)TIM_SMCR_ETF_DTS_DIV_32_N_8 (0xF << 8)__ARM_SIZEOF_MINIMAL_ENUM 1RCC_APB2RSTR_OFFSET 0x40RCC_AHB1RSTR_OFFSET 0x28__INT64_C(c) c ## LL__ARM_FEATURE_CRC32INT_LEAST16_MAXRCC_APB1ENR1 MMIO32(RCC_BASE + RCC_APB1ENR1_OFFSET)__DA_FBIT__ 31__FLT32_MIN__ 1.1754943508222875e-38F32TIM_CCMR1_OC2CE (1 << 15)SIZE_MAX __SIZE_MAX__timer_set_oc_idle_state_unsetINT8_MINTIM_CCMR2_IC4F_DTF_DIV_4_N_6 (0x6 << 12)TIM_CCMR1(tim_base) MMIO32((tim_base) + 0x18)__GCC_ATOMIC_BOOL_LOCK_FREE 2INT_FAST64_MINRCC_AHB2SMENR_ADCSMEN (1 << 13)RCC_CSR_MSIRANGE_4MHZ 6__INT_FAST32_MAX__ 0x7fffffffRCC_CFGR_MCOPRE_DIV4 2__FLT_MAX_10_EXP__ 38TIM_CCMR1_IC2F_DTF_DIV_16_N_5 (0xA << 12)RCC_APB2RSTR_SPI1RST (1 << 12)TIM4_CNT TIM_CNT(TIM4)WINT_MIN __WINT_MIN__TIM4_ARR TIM_ARR(TIM4)SIG_ATOMIC_MAX __SIG_ATOMIC_MAX____GCC_IEC_559_COMPLEX 0__TQ_FBIT__ 127__VFP_FP__ 1TIM_CR2_OIS4 (1 << 14)__ARM_ASM_SYNTAX_UNIFIED__ 1TIM_IC_OUTRCC_PLLCFGR_PLLQ_SHIFT 21TIM_CR2_OIS1 (1 << 8)RCC_CICR_HSIRDYC (1 << 3)INT32_MAXTIM9_CCR1 TIM_CCR1(TIM9)__ARM_FP 4RCC_CSR_WWDGRSTF (1 << 30)RCC_PLLCFGR_PLLM_MASK 0x7__UFRACT_MIN__ 0.0UR__ULFRACT_IBIT__ 0RCC_APB1ENR2_OFFSET 0x5cRCC_APB2SMENR_DFSDMSMEN (1 << 24)RCC_BDCR_RTCSEL_HSEDIV32 3TIM_CCMR2_CC3S_IN_TI4 (0x2 << 0)TIM_BDTR_MOE (1 << 15)__ARM_SIZEOF_WCHAR_T 4__ARM_FEATURE_LDREX 7RCC_APB1RSTR1_TIM7RST (1 << 5)RCC_AHB1ENR_TSCEN (1 << 16)TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)__SIZEOF_DOUBLE__ 8__UINT_FAST32_MAX__ 0xffffffffU__LDBL_MAX_EXP__ 1024RCC_BDCR_RTCSEL_MASK 0x3RCC_PLLCFGR_PLLQ_DIV2 0TIM_SR(tim_base) MMIO32((tim_base) + 0x10)QUADSPI_BASE (0xa0001000U)RCC_CR_HSERDY (1 << 17)__ARM_FEATURE_FP16_VECTOR_ARITHMETICTIM6_PSC TIM_PSC(TIM6)TIM2_EGR TIM_EGR(TIM2)RCC_APB1RSTR1_USART3RST (1 << 18)RCC_CFGR_MCO_HSI48 0x8RCC_AHB2RSTR_GPIOERST (1 << 4)TIM_IC1__INTMAX_MAX__ 0x7fffffffffffffffLLINT64_MAXRCC_APB1ENR1_TIM2EN (1 << 0)RCC_BDCR_RTCEN (1 << 15)TIM15_DMAR TIM_DMAR(TIM15)UINT_LEAST16_MAX __UINT_LEAST16_MAX__RCC_CR_HSIASFS (1 << 11)__LONG_WIDTH__ 32RCC_CICR_HSERDYC (1 << 4)__OPTIMIZE__ 1TIM_BDTR_LOCK_OFF (0x0 << 8)TIM_CCMR1_IC2PSC_OFF (0x0 << 10)TIM_CCMR2_IC4F_DTF_DIV_4_N_8 (0x7 << 12)TIM10_CCR1 TIM_CCR1(TIM10)USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x6800)RCC_CIER_PLLRDYIE (1 << 5)RCC_CCIPR_LPUART1SEL_MASK 0x3__arm__ 1PTRDIFF_MINRCC_APB1RSTR1_UART5RST (1 << 20)TIM8_EGR TIM_EGR(TIM8)ADC1_BASE (0x50000000U + 0x40000)TIM1_DCR TIM_DCR(TIM1)RCC_CR_HSEBYP (1 << 18)UINT32_MAX __UINT32_MAX____OPTIMIZE_SIZE__ 1TIM1_CR1 TIM_CR1(TIM1)TIM16_EGR TIM_EGR(TIM16)TIM_CR2_MMS_RESET (0x0 << 4)TIM_CCMR2_IC4F_DTF_DIV_16_N_5 (0xA << 12)TIM1_CCR1 TIM_CCR1(TIM1)RCC_AHB2SMENR_GPIOCSMEN (1 << 2)timer_set_ti1_ch1INT_FAST32_MIN (-INT_FAST32_MAX - 1)RCC_PLLCFGR_PLLN_MASK 0x7f__INT8_TYPE__ signed char__LDBL_DENORM_MIN__ 4.9406564584124654e-324LRCC_CCIPR_I2C1SEL_SHIFT 12timer_set_ti1_ch123_xorRCC_CCIPR_USARTxSEL_SYS 1SYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000)RCC_CR_MSIRANGE_100KHZ 0RCC_APB1RSTR1_OPAMPRST (1 << 30)RCC_APB2RSTR_USART1RST (1 << 14)RCC_APB1SMENR2_SWPMI1SMEN (1 << 2)TIM_CR2_MMS_COMPARE_PULSE (0x3 << 4)TIM_CR1_CMS_EDGE (0x0 << 5)TIM13_CCMR1 TIM_CCMR1(TIM13)UINT_LEAST32_MAXTIM_SMCR_TS_ITR3 (0x3 << 4)__ACCUM_MAX__ 0X7FFFFFFFP-15K__DBL_HAS_QUIET_NAN__ 1RCC_CIFR_LSECSSF (1 << 9)RCC_APB1SMENR1_LCDSMEN (1 << 9)__FLT64_MIN_EXP__ (-1021)__INT_FAST32_TYPE__ intTIM_CR1_DIR_DOWN (1 << 4)RCC_APB1ENR1_TIM7EN (1 << 5)TIM12_CCER TIM_CCER(TIM12)RCC_APB1RSTR1_LCDRST (1 << 9)RCC_APB2ENR_TIM16EN (1 << 17)__FLT64_HAS_QUIET_NAN__ 1__ARM_NEON__USART2_BASE (PERIPH_BASE_APB1 + 0x4400)RCC_CIER_LSERDYIE (1 << 1)TIM3_CCMR1 TIM_CCMR1(TIM3)TIM17_DCR TIM_DCR(TIM17)INT8_MAXRCC_CIER_LSIRDYIE (1 << 0)TIM_SMCR_TS_ITR2 (0x2 << 4)RCC_CSR_LSIRDY (1 << 1)CORESIGHT_LAR_OFFSET 0xfb0RCC_CFGR_MCO_LSE 0x7RCC_APB1RSTR2 MMIO32(RCC_BASE + RCC_APB1RSTR2_OFFSET)TIM8_CCMR2 TIM_CCMR2(TIM8)WCHAR_MIN__FLT32X_MIN_EXP__ (-1021)TIM_OC1TIM_OC2TIM_OC3TIM_OC4timer_set_oc_fast_mode__ARM_ARCH_PROFILETIM_SMCR_ETF_CK_INT_N_8 (0x3 << 8)TIM_OCM_INACTIVE__LACCUM_IBIT__ 32RCC_CCIPR_LPTIM1SEL_SHIFT 18RCC_CICR_HSI48RDYC (1 << 10)TIM11_ARR TIM_ARR(TIM11)TIM11_CNT TIM_CNT(TIM11)MMIO16(addr) (*(volatile uint16_t *)(addr))SCS_BASE (PPBI_BASE + 0xE000)TIM_CCMR2_IC3PSC_2 (0x1 << 2)INT16_MINTIM_SMCR_TS_ITR1 (0x1 << 4)TIM_SMCR_ETF_DTS_DIV_32_N_6 (0xE << 8)__SA_FBIT__ 15RCC_CCIPR_UARTxSEL_MASK RCC_CCIPR_USARTxSEL_MASKTIM5_ARR TIM_ARR(TIM5)__SIZEOF_SHORT__ 2UINTPTR_MAX __UINTPTR_MAX__timer_enable_counterTIM8_DMAR TIM_DMAR(TIM8)RCC_PLLCFGR_PLLM(x) ((x)-1)timer_set_break_polarity_low__UINT8_MAX__ 0xffRCC_AHB2SMENR_GPIOGSMEN (1 << 6)TIM_CCMR1_IC1F_DTF_DIV_32_N_8 (0xF << 4)TIM_EGR_TG (1 << 6)TIM14_PSC TIM_PSC(TIM14)timer_continuous_modeoutputsTIM13_CR1 TIM_CR1(TIM13)TIM_SMCR_TS_ITR0 (0x0 << 4)TIM_CCMR1_CC1S_OUT (0x0 << 0)TIM_SMCR_ETF_DTS_DIV_32_N_5 (0xD << 8)TIM3_CCR2 TIM_CCR2(TIM3)RCC_CFGR_SW_MASK 0x3RCC_AHB2SMENR_GPIOESMEN (1 << 4)TIM_SMCR_ETF_DTS_DIV_2_N_6 (0x4 << 8)TIM_CCMR1_OC1FE (1 << 2)RCC_CR_MSIRANGE_800KHZ 3TIM_SMCR_ETF_DTS_DIV_8_N_8 (0x9 << 8)TIM_SMCR_SMS_GM (0x5 << 0)timer_enable_oc_clearUINT_FAST16_MAXRCC_APB1RSTR1_I2C2RST (1 << 22)__FLT64_DECIMAL_DIG__ 17__UINTPTR_MAX__ 0xffffffffU__ARM_FEATURE_COMPLEX__UACCUM_MIN__ 0.0UKTIM2_SR TIM_SR(TIM2)RCC_AHB1ENR_DMA1EN (1 << 0)TIM_CCMR2_OC3M_TOGGLE (0x3 << 4)RCC_APB1ENR1_I2C1EN (1 << 21)TIM4_CCR3 TIM_CCR3(TIM4)__SFRACT_EPSILON__ 0x1P-7HR__ATOMIC_CONSUME 1TIM11_CR1 TIM_CR1(TIM11)__INT_LEAST16_TYPE__ short intTIM_CCMR1_CC1S_MASK (0x3 << 0)END_DECLS TIM_CCMR2_IC3F_CK_INT_N_8 (0x3 << 4)INT32_MAX __INT32_MAX__TIM13_DIER TIM_DIER(TIM13)__USFRACT_FBIT__ 8RCC_CSR_IWDGRSTF (1 << 29)RCC_CR_MSIRDY (1 << 1)RCC_CCIPR_UARTxSEL_HSI16 RCC_CCIPR_USARTxSEL_HSI16__GCC_ATOMIC_WCHAR_T_LOCK_FREE 2RCC_CCIPR_SAIxSEL_PLLSAI2P 1RCC_APB2RSTR_TIM17RST (1 << 18)RCC_APB1RSTR1_TIM5RST (1 << 3)TIM16_BDTR TIM_BDTR(TIM16)__SIZEOF_PTRDIFF_T__ 4TIM1_DIER TIM_DIER(TIM1)RCC_APB1ENR1_USART3EN (1 << 18)__DA_IBIT__ 32timer_disable_update_eventTIM_SMCR_ETPS_MASK (0X3 << 12)FMC_QUADSPI_BASE (0xA0000000U)RCC_APB1ENR1_UART5EN (1 << 20)RCC_APB1ENR1_I2C3EN (1 << 23)DMA1_BASE (PERIPH_BASE_AHB1 + 0x0000)RCC_APB1RSTR1_SPI2RST (1 << 14)RCC_AHB2RSTR_GPIOBRST (1 << 1)RCC_CFGR_HPRE_DIV8 0xa__FLT32X_HAS_QUIET_NAN__ 1__GNUC_EXECUTION_CHARSET_NAME "UTF-8"RCC_AHB3RSTR MMIO32(RCC_BASE + RCC_AHB3RSTR_OFFSET)timer_set_deadtimeRCC_CCIPR_SAIxSEL_PLL 2RCC_CSR_RESET_FLAGS (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF | RCC_CSR_IWDGRSTF | RCC_CSR_SFTRSTF | RCC_CSR_BORRSTF | RCC_CSR_PINRSTF | RCC_CSR_OBLRSTF | RCC_CSR_FWRSTF)__SIG_ATOMIC_WIDTH__ 32__DBL_MIN_EXP__ (-1021)TIM_CCR3(tim_base) MMIO32((tim_base) + 0x3C)TIM_SMCR_TS_TI1FP1 (0x5 << 4)TIM7_SR TIM_SR(TIM7)RCC_BASE (PERIPH_BASE_AHB1 + 0x1000)MPU_BASE (SCS_BASE + 0x0D90)TIM_CR2_TI1S (1 << 7)TIM15_BASE (PERIPH_BASE_APB2 + 0x4000)RCC_APB2RSTR_TIM1RST (1 << 11)UINT16_MAXINT_LEAST16_MINTIM_CR1_CKD_CK_INT_MUL_4 (0x2 << 8)__LDBL_MAX_10_EXP__ 308SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)RCC_AHB3RSTR_FMCRST (1 << 0)RCC_ICSCR_MSITRIM_SHIFT 8TIM_CCMR1_OC2PE (1 << 11)TIM8_DCR TIM_DCR(TIM8)__INT64_TYPE__ long long intRCC_CFGR_SWS_HSI16 0x1INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)TIM_CCMR1_IC1F_OFF (0x0 << 4)__TA_FBIT__ 63__LDBL_NORM_MAX__ 1.7976931348623157e+308Lbool _Bool__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64RCC_ICSCR_HSITRIM_MASK 0x1f__UINT_LEAST32_TYPE__ long unsigned inttimer_disable_preload_complementry_enable_bitsRCC_APB1SMENR1_TIM4SMEN (1 << 2)SAI2_BASE (PERIPH_BASE_APB2 + 0x5800)TIM_CCMR2_IC4F_OFF (0x0 << 12)RCC_AHB2RSTR_RNGRST (1 << 18)TIM_SMCR_SMS_EM1 (0x1 << 0)RCC_APB1ENR1_OPAMPEN (1 << 30)INT32_MIN__HA_IBIT__ 8TIM_IC_PSC_2TIM_CR1_CMS_CENTER_3 (0x3 << 5)TIM_CCMR2_OC3PE (1 << 3)TIM_IC_PSC_8INT8_MIN (-INT8_MAX - 1)__FLT32X_HAS_DENORM__ 1TSC_BASE (PERIPH_BASE_AHB1 + 0x4000)INT16_CRCC_CR_MSIRANGE_8MHZ 7TIM_DIER_COMDE (1 << 13)__FLT32_HAS_QUIET_NAN__ 1RCC_PLLCFGR MMIO32(RCC_BASE + 0x0c)__HQ_IBIT__ 0long long int__FLT_EVAL_METHOD__ 0RCC_AHB3RSTR_QSPIRST (1 << 8)RCC_AHB2RSTR_ADCRST (1 << 13)timer_slave_set_prescalerRCC_CCIPR_UARTxSEL_SYS RCC_CCIPR_USARTxSEL_SYSTIM2_CR1 TIM_CR1(TIM2)RCC_APB2ENR_SAI2EN (1 << 22)__UHA_FBIT__ 8timer_reset_output_idle_state__ARM_FEATURE_CLZ 1TIM_CR1_CMS_CENTER_2 (0x2 << 5)__FLT64_MIN_10_EXP__ (-307)RCC_APB2SMENR_TIM1SMEN (1 << 11)__ARM_FEATURE_FMA 1RCC_BDCR_LSESYSDIS (1 << 7)timer_disable_oc_clearTIM6_DIER TIM_DIER(TIM6)TIM_CCMR1_CC2S_OUT (0x0 << 8)TIM8_CCR3 TIM_CCR3(TIM8)__FDPIC__CORESIGHT_LSR_OFFSET 0xfb4INT64_MIN__UINT16_MAX__ 0xffffOPAMP_BASE (PERIPH_BASE_APB1 + 0x7800)RCC_AHB2ENR_GPIOCEN (1 << 2)__ARM_ARCH 7RCC_CR_HSION (1 << 8)RCC_CCIPR_SAI1SEL_SHIFT 22RCC_APB1SMENR2_LPUART1SMEN (1 << 0)BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)tim_oc_idTIM_CCER_CC3NE (1 << 10)TIM11_EGR TIM_EGR(TIM11)TIM1_SMCR TIM_SMCR(TIM1)__LDBL_MIN_10_EXP__ (-307)RCC_BDCR_LSEDRV_HIGH 3BIT6 (1<<6)RCC_CCIPR_SWPMI1SEL (1 << 30)SIG_ATOMIC_MAX__USFRACT_IBIT__ 0TIM6_SR TIM_SR(TIM6)__FLT32X_MIN_10_EXP__ (-307)WINT_MAXtimer_enable_update_eventTIM17_BASE (PERIPH_BASE_APB2 + 0x4800)__DEC_EVAL_METHOD__ 2TIM3_CR2 TIM_CR2(TIM3)INT_LEAST64_MAX__LDBL_HAS_INFINITY__ 1TIM_CCMR1_IC2F_DTF_DIV_32_N_5 (0xD << 12)long unsigned intDFSDM_BASE (PERIPH_BASE_APB2 + 0x6000)RCC_AHB2ENR_GPIOHEN (1 << 7)RCC_APB1SMENR1_USART3SMEN (1 << 18)TIM8_PSC TIM_PSC(TIM8)__SFRACT_MAX__ 0X7FP-7HRRCC_APB1ENR1_TIM4EN (1 << 2)TIM_OC1NTIM15_ARR TIM_ARR(TIM15)TIM15_CCER TIM_CCER(TIM15)TIM15_CNT TIM_CNT(TIM15)TIM_DIER_CC2DE (1 << 10)TIM_CCMR2_IC3F_DTF_DIV_4_N_6 (0x6 << 4)RCC_CR_PLLSAI1ON (1 << 26)RCC_CIER_PLLSAI1RDYIE (1 << 6)TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)TIM_CCER_CC3E (1 << 8)TIM_SR_BIF (1 << 7)__SIZEOF_LONG_DOUBLE__ 8RCC_APB1ENR1_SPI2EN (1 << 14)LPTIM1_BASE (PERIPH_BASE_APB1 + 0x7c00)__FLT64_HAS_DENORM__ 1TIM_CCMR2_IC3F_DTF_DIV_32_N_6 (0xE << 4)RCC_CCIPR_CLK48SEL_PLLSAI1Q 1__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)__FLT_HAS_DENORM__ 1__LLACCUM_FBIT__ 31UINT_LEAST8_MAX__THUMBEL__ 1TIM_DIER_CC1IE (1 << 1)RCC_BDCR_LSEDRV_MEDLOW 1RCC_PLLCFGR_PLLR_SHIFT 25RCC_APB2RSTR MMIO32(RCC_BASE + RCC_APB2RSTR_OFFSET)__GCC_CONSTRUCTIVE_SIZE 64TIM3_DCR TIM_DCR(TIM3)timer_direction_upTIM8_CCR2 TIM_CCR2(TIM8)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__TQ_IBIT__ 0TIM16_DIER TIM_DIER(TIM16)TIM11_PSC TIM_PSC(TIM11)__FLT32X_MIN__ 2.2250738585072014e-308F32xTIM17_CR1 TIM_CR1(TIM17)RCC_ICSCR_MSITRIM_MASK 0xffRCC_CCIPR_LPTIMxSEL_LSI 1TIM_SR_COMIF (1 << 5)__SIZEOF_FLOAT__ 4RCC_APB1SMENR1_I2C2SMEN (1 << 22)FPB_BASE (PPBI_BASE + 0x2000)TIM_SMCR_ETF_CK_INT_N_4 (0x2 << 8)__SIZE_TYPE__ unsigned intRCC_CCIPR_LPUART1SEL_SYS 1TIM2_DMAR TIM_DMAR(TIM2)timer_slave_set_trigger__UINT_LEAST8_TYPE__ unsigned chartimer_update_on_overflowUINT16_CTIM4_DMAR TIM_DMAR(TIM4)RCC_APB1SMENR1_DAC1SMEN (1 << 29)__ARM_NEON_FPTIM_CCMR2_IC3F_OFF (0x0 << 4)EXTI_BASE (PERIPH_BASE_APB2 + 0x0400)TIM_CCER_CC4NP (1 << 15)RCC_PLLCFGR_PLLR_DIV2 0__UFRACT_FBIT__ 16unsigned intID_BASE (SCS_BASE + 0x0FD0)TIM3_CCMR2 TIM_CCMR2(TIM3)TIM15_SMCR TIM_SMCR(TIM15)TIM_OC3NRCC_CICR_PLLSAI1RDYC (1 << 6)TIM_DIER_UIE (1 << 0)RCC_CIFR_LSERDYF (1 << 1)__ARM_FEATURE_MVE__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0x75a8))INT_LEAST32_MAXTIM9_CCER TIM_CCER(TIM9)RCC_APB2SMENR_USART1SMEN (1 << 14)RCC_CIER_HSERDYIE (1 << 4)RCC_BDCR_RTCSEL_LSI 2TIM_CCMR2_IC4F_DTF_DIV_32_N_5 (0xD << 12)__UHA_IBIT__ 8__ARM_FEATURE_CDE_COPROC__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRtimer_set_break_polarity_highTIM_CR1_CMS_MASK (0x3 << 5)RCC_APB1SMENR1 MMIO32(RCC_BASE + RCC_APB1SMENR1_OFFSET)timer_ic_enableshort int__UQQ_FBIT__ 8timer_slave_set_modeTIM2_CCR2 TIM_CCR2(TIM2)__GNUC_MINOR__ 2TIM14_SR TIM_SR(TIM14)RCC_CIER MMIO32(RCC_BASE + 0x18)BBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)TIM_CCMR2_OC3M_FORCE_LOW (0x4 << 4)TIM_SMCR_ETF_DTS_DIV_4_N_8 (0x7 << 8)TIM3_CR1 TIM_CR1(TIM3)INTMAX_MAX __INTMAX_MAX__RCC_AHB2RSTR_GPIODRST (1 << 3)RCC_CR_HSEON (1 << 16)__INTMAX_TYPE__ long long intRCC_APB1RSTR2_LPUART1RST (1 << 0)__UINT_LEAST16_TYPE__ short unsigned intTIM_DIER_CC4DE (1 << 12)__ULLFRACT_EPSILON__ 0x1P-64ULLRRCC_CCIPR_USART3SEL_SHIFT 4TIM_CCMR1_IC1F_DTF_DIV_8_N_8 (0x9 << 4)RCC_PLLSAI1_CFGR MMIO32(RCC_BASE + 0x10)RCC_CSR_LSION (1 << 0)RCC_APB1SMENR1_UART4SMEN (1 << 19)TIM15_CCR2 TIM_CCR2(TIM15)TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)TIM7_CNT TIM_CNT(TIM7)TIM7_ARR TIM_ARR(TIM7)__FLT_DENORM_MIN__ 1.4012984643248171e-45FRCC_AHB1SMENR_DMA2SMEN (1 << 1)INT_FAST32_MAX __INT_FAST32_MAX__RCC_CCIPR_SAIxSEL_EXT 3TIM8_BASE (PERIPH_BASE_APB2 + 0x3400)UINT8_CRCC_CCIPR_DFSDMSEL (1 << 31)INT_FAST64_MIN (-INT_FAST64_MAX - 1)__UINT_LEAST8_MAX__ 0xff__HA_FBIT__ 7__UINT32_MAX__ 0xffffffffULRCC_CFGR_HPRE_DIV128 0xdtimer_ic_set_inputTIM_EGR_CC3G (1 << 3)TIM13_SR TIM_SR(TIM13)TIM13_CCR1 TIM_CCR1(TIM13)TIM_OCM_PWM2TIM_CCMR1_OC2FE (1 << 10)__GNUC_PATCHLEVEL__ 1GCC: (15:12.2.rel1-1) 12.2.1 20221205˙˙˙˙| A„Ž 4444Ś44JJJJJJ PPfA3aeabi)7E-M M "ń˙ !!""##$$%%&&''(())**++,,--..///000111222333,343Š3’3ę3ň3H3P3444555666777888999:::;;;<<<==>>??@@AABBCCDDEEFFGGHHIIJJLLMMNNOOOOPPPPQQRRSSTTUUVVWWXXY[\^`bvx//00112233445566778899::;;<<dfhjlnprtzArŁŐ:n© y| × č ú 1@Y n „ « Ŕ Ô ę ţ 1 L a w!“"± #É $Ű%ń & '. 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../common/usr/lib/gcc/arm-none-eabi/12.2.1/include../../../include/libopencm3/stm32/l4../../../include/libopencm3/stm32/common../../../include/libopencm3/stm32../../../include/libopencm3/cm3usart_common_all.cstdint.hrcc.husart_common_all.husart.hcommon.hstdbool.hmemorymap.hmemorymap.hmemorymap.husart.husart_common_v2.hrcc.hrcc_common_all.h5$###k.% ( .y.=J(..-" ă!>>ö!.!!‰!.!!ś!.!!Ż!.!!ż =Í =Ý ///-.í !0 ! -. =Ť =ź =« =· =Ä =Đ =Ü =é =ö = =Ť =™ =Ą =RCC_ICSCR MMIO32(RCC_BASE + 0x04)RCC_CICR_PLLRDYC (1 << 5)USART_CR1_DEAT (0x1F << USART_CR1_DEAT_SHIFT)baudSCB_BASE (SCS_BASE + 0x0D00)__UHA_FBIT__ 8USB_OTG_FS_BASE (0x50000000U + 0x00000)usart_set_parity__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64CORESIGHT_LSR_SLK (1<<1)__GCC_ATOMIC_WCHAR_T_LOCK_FREE 2LCD_BASE (PERIPH_BASE_APB1 + 0x2400)__CHAR_UNSIGNED__ 1__UINTPTR_MAX__ 0xffffffffUUSART_CR3_DEP (1 << 15)USART3_BASE (PERIPH_BASE_APB1 + 0x4800)USART_RTOR_BLEN_MASK (0xFF << USART_RTOR_BLEN_SHIFT)RCC_CCIPR_I2CxSEL_MASK 0x3RCC_CFGR_MCO_MSI 0x2RCC_AHB1SMENR_SRAM1SMEN (1 << 9)RCC_CICR_LSECSSC (1 << 9)__FLT64_HAS_INFINITY__ 1RCC_AHB1RSTR_FLASHRST (1 << 8)RCC_CCIPR_UARTxSEL_MASK RCC_CCIPR_USARTxSEL_MASK__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GNUC_MINOR__ 2__GCC_DESTRUCTIVE_SIZE 64__LACCUM_EPSILON__ 0x1P-31LKRCC_CIFR_LSECSSF (1 << 9)__PTRDIFF_MAX__ 0x7fffffffUSART_CR1_DEDT_VAL(x) ((x) << USART_CR1_DEDT_SHIFT)__ARM_FEATURE_FMA 1__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)RCC_CR_MSIRANGE_800KHZ 3RCC_AHB3RSTR_FMCRST (1 << 0)__INTMAX_MAX__ 0x7fffffffffffffffLL__TQ_IBIT__ 0__FLT64_DECIMAL_DIG__ 17RCC_AHB2ENR_GPIODEN (1 << 3)WINT_MIN __WINT_MIN__INT_FAST64_MAXOPAMP_BASE (PERIPH_BASE_APB1 + 0x7800)RCC_ICSCR_MSICAL_SHIFT 0__ATOMIC_CONSUME 1__ULACCUM_FBIT__ 32__WCHAR_MAX__ 0xffffffffURCC_APB1SMENR1_PWRSMEN (1 << 28)RCC_PLLCFGR_PLLR_DIV6 2USART_ISR_EOBF (1 << 12)RCC_APB2ENR_SDMMC1EN (1 << 10)RCC_AHB1ENR_DMA1EN (1 << 0)UART5_GTPR USART_GTPR(UART5_BASE)RCC_AHB2SMENR_GPIOCSMEN (1 << 2)USART2_BRR USART_BRR(USART2_BASE)USART3_ISR USART_ISR(USART3_BASE)INT64_MAX __INT64_MAX__INTMAX_MIN__SIZEOF_LONG_LONG__ 8__DBL_MAX_10_EXP__ 308__FRACT_MIN__ (-0.5R-0.5R)__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLKRCC_APB1RSTR1_UART4RST (1 << 19)__USACCUM_MAX__ 0XFFFFP-8UHK__SFRACT_FBIT__ 7__INTMAX_WIDTH__ 64RCC_APB1ENR1_SPI2EN (1 << 14)__ARM_FEATURE_BF16_SCALAR_ARITHMETIC__SQ_IBIT__ 0__ORDER_PDP_ENDIAN__ 3412__SIZE_TYPE__ unsigned intRCC_AHB1ENR_FLASHEN (1 << 8)RCC_AHB2SMENR_GPIOESMEN (1 << 4)__FLT_HAS_DENORM__ 1__INT8_TYPE__ signed char__FLT32_MIN__ 1.1754943508222875e-38F32USART_ISR_LBDF (1 << 8)__USACCUM_MIN__ 0.0UHKRCC_APB1SMENR1_I2C2SMEN (1 << 22)__FLT32_DECIMAL_DIG__ 9RCC_CIER_HSERDYIE (1 << 4)__DECIMAL_DIG__ 17__LDBL_MIN_EXP__ (-1021)INT_FAST16_MIN__LDBL_MANT_DIG__ 53INT64_MIN (-INT64_MAX - 1)../common/usart_common_all.cRCC_CFGR_STOPWUCK_MSI (0 << 15)RCC_APB2SMENR_SDMMC1SMEN (1 << 10)__UINT8_C(c) c__INT16_TYPE__ short inttrue 1RCC_APB1ENR1_TIM5EN (1 << 3)__FLT64_MAX__ 1.7976931348623157e+308F64UART5_RTOR USART_RTOR(UART5_BASE)UINT_FAST32_MAXUSART_GTPR_GT_SHIFT 8RCC_CFGR_MCO_HSE 0x4RCC_CIER_LSIRDYIE (1 << 0)USART1_RTOR USART_RTOR(USART1_BASE)RCC_APB1RSTR2_OFFSET 0x3cRCC_PLLCFGR_PLLSRC_NONE 0RCC_CCIPR_UARTxSEL_LSE RCC_CCIPR_USARTxSEL_LSEINT_FAST64_MAX __INT_FAST64_MAX__RCC_CR_MSION (1 << 0)__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1usart_enable_idle_interruptusart_sendUSART_ICR_EOBCF (1 << 12)RCC_CR_MSIRANGE_48MHZ 11__UINT_LEAST16_MAX__ 0xffff__STDC_HOSTED__ 1__ULLFRACT_FBIT__ 64__SIG_ATOMIC_TYPE__ intRCC_CICR_MSIRDYC (1 << 2)RCC_PLLSAI1_CFGR MMIO32(RCC_BASE + 0x10)USART_CR3_DDRE (1 << 13)RCC_CIFR_CSSF (1 << 8)__INT_FAST64_TYPE__ long long int__WINT_TYPE__ unsigned intGPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800)USART3_CR2 USART_CR2(USART3_BASE)ST_TSENSE_CAL2_110C MMIO16((INFO_BASE + 0x75ca))usart_disable_rx_interruptRCC_CFGR_MCO_PLL 0x5INT32_MIN (-INT32_MAX - 1)__FLT32_MAX_10_EXP__ 38USART_CR2_ADDM7 (1 << 4)RCC_CFGR_HPRE_DIV8 0xaRCC_APB1ENR1_TIM3EN (1 << 1)usart_enable_rx_interruptRCC_APB2RSTR_SPI1RST (1 << 12)__USFRACT_MAX__ 0XFFP-8UHRLPTIM1_BASE (PERIPH_BASE_APB1 + 0x7c00)__FP_FAST_FMAF32 1RCC_APB1SMENR1_TIM5SMEN (1 << 3)TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)USART_CR3_SCARCNT_SHIFT 17__FLT32_MIN_EXP__ (-125)usart_disable_tx_dmaUSART3_BRR USART_BRR(USART3_BASE)UART5_CR1 USART_CR1(UART5_BASE)RCC_PLLCFGR_PLLREN (1<<24)UINT32_MAX __UINT32_MAX__RCC_CIER_MSIRDYIE (1 << 2)USART_GTPR_PSC_VAL(x) ((x) << USART_GTPR_PSC_SHIFT)RCC_AHB1ENR MMIO32(RCC_BASE + RCC_AHB1ENR_OFFSET)__ULFRACT_FBIT__ 32INT8_MIN (-INT8_MAX - 1)__FLT64_MIN_10_EXP__ (-307)RCC_APB1SMENR1_LPTIM1SMEN (1 << 31)__GNUC_EXECUTION_CHARSET_NAME "UTF-8"RCC_CIFR MMIO32(RCC_BASE + 0x1c)BIT10 (1<<10)__INT_FAST64_WIDTH__ 64__STDC_VERSION__ 199901LINT_LEAST64_MAX __INT_LEAST64_MAX__RCC_PLLCFGR_PLLSRC_MASK 0x3RCC_CCIPR_SAI1SEL_SHIFT 22RCC_AHB2SMENR MMIO32(RCC_BASE + RCC_AHB2SMENR_OFFSET)RCC_CFGR_MCOPRE_DIV8 3__SFRACT_EPSILON__ 0x1P-7HRUSART_CR2_STOPBITS_MASK (0x03 << 12)USART_CR2_ABRMOD_FRAME_0x7F (0x2 << USART_CR2_ABRMOD_SHIFT)UINT_LEAST16_MAX __UINT_LEAST16_MAX__UINT32_C(c) __UINT32_C(c)__ORDER_BIG_ENDIAN__ 4321I2C3_BASE (PERIPH_BASE_APB1 + 0x5c00)SYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000)__UINTPTR_TYPE__ unsigned int__SQ_FBIT__ 31INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)RCC_CR_MSIRGSEL (1 << 3)USART_ISR_RXNE (1 << 5)RCC_CCIPR MMIO32(RCC_BASE + 0x88)UART4 UART4_BASE__UHQ_FBIT__ 16RCC_APB1ENR2_LPTIM2EN (1 << 5)USART_CR1_DEDT_SHIFT 16__FLT64_MIN_EXP__ (-1021)RCC_AHB1RSTR_CRCRST (1 << 12)__PTRDIFF_WIDTH__ 32USART_CR1_WAKE (1 << 11)RCC_APB1SMENR1_DAC1SMEN (1 << 29)__UINT_FAST8_MAX__ 0xffffffffUUART4_CR2 USART_CR2(UART4_BASE)RCC_APB1ENR1_OPAMPEN (1 << 30)RTC_BASE (PERIPH_BASE_APB1 + 0x2800)UART5_TDR USART_TDR(UART5_BASE)__LACCUM_IBIT__ 32RCC_CSR_SFTRSTF (1 << 28)RCC_CCIPR_UARTxSEL_HSI16 RCC_CCIPR_USARTxSEL_HSI16__INT_FAST16_WIDTH__ 32INTMAX_C__VERSION__ "12.2.1 20221205"RCC_CCIPR_I2C2SEL_SHIFT 14__VFP_FP__ 1RCC_ICSCR_MSITRIM_SHIFT 8__LLFRACT_MIN__ (-0.5LLR-0.5LLR)INT_FAST8_MAX__UINT_FAST16_MAX__ 0xffffffffURCC_APB1SMENR1_TIM6SMEN (1 << 4)RCC_CFGR_PPRE2_DIV2 0x4__INTPTR_MAX__ 0x7fffffffINT64_C(c) __INT64_C(c)RCC_CIER_LSE_CSSIE (1 << 9)RCC_CCIPR_USART1SEL_SHIFT 0RCC_APB1RSTR1 MMIO32(RCC_BASE + RCC_APB1RSTR1_OFFSET)__GCC_IEC_559_COMPLEX 0PERIPH_BASE (0x40000000U)RCC_AHB2SMENR_GPIOHSMEN (1 << 7)USART_MODE_RX USART_CR1_RERCC_CFGR_MCO_SHIFT 24WCHAR_MAX __WCHAR_MAX__RCC_APB2SMENR_TIM8SMEN (1 << 13)__FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX__USART_ICR_WUCF (1 << 20)USART_CR3_DMAT (1 << 7)USART_CR3_IRLP (1 << 2)__UINT_LEAST8_TYPE__ unsigned charRCC_AHB2ENR_GPIOEEN (1 << 4)RCC_APB1RSTR1_I2C1RST (1 << 21)RCC_APB1RSTR2_LPUART1RST (1 << 0)__ACCUM_FBIT__ 15PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)USART1_CR1 USART_CR1(USART1_BASE)__UACCUM_IBIT__ 16long intUINT8_MAXIWDG_BASE (PERIPH_BASE_APB1 + 0x3000)SIZE_MAX __SIZE_MAX__RCC_CICR_PLLSAI2RDYC (1 << 7)__INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17UART4_TDR USART_TDR(UART4_BASE)__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1RCC_APB1ENR1_I2C1EN (1 << 21)RCC_CR_MSIRANGE_400KHZ 2__FLT32X_EPSILON__ 2.2204460492503131e-16F32xRCC_ICSCR_MSICAL_MASK 0xffRCC_CCIPR_SAIxSEL_PLLSAI1P 0NVIC_BASE (SCS_BASE + 0x0100)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32LIBOPENCM3_USART_COMMON_ALL_H USART2_BASE (PERIPH_BASE_APB1 + 0x4400)RCC_APB1SMENR1_TIM2SMEN (1 << 0)RCC_AHB2ENR_GPIOFEN (1 << 5)__UINTMAX_C(c) c ## ULLRCC_PLLCFGR_PLLN_MASK 0x7f__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed charRCC_AHB1RSTR MMIO32(RCC_BASE + RCC_AHB1RSTR_OFFSET)__GCC_ATOMIC_BOOL_LOCK_FREE 2BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON____FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX__usart_enable_tx_complete_interrupt__THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRRCC_APB1SMENR1_TIM4SMEN (1 << 2)USART_GTPR_PSC_SHIFT 0USART1_CR2 USART_CR2(USART1_BASE)short unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)BIT7 (1<<7)BIT17 (1<<17)__FLT32X_MIN_10_EXP__ (-307)usart_set_baudrateUINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)__DBL_IS_IEC_60559__ 2__UINT_FAST32_MAX__ 0xffffffffU__DEC_EVAL_METHOD__ 2__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4RCC_AHB3SMENR_OFFSET 0x70RCC_APB2RSTR_TIM15RST (1 << 16)USART_CR2_STOPBITS_2 (0x02 << 12)USART_CR2_ABREN (1 << 20)USART_MODE_TX USART_CR1_TERCC_CFGR_PPRE1_DIV2 0x4USART_CR2_CPHA (1 << 9)RCC_BDCR_RTCEN (1 << 15)__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32USART_PARITY_EVEN USART_CR1_PCE__FLT32X_MIN_EXP__ (-1021)DMA1_BASE (PERIPH_BASE_AHB1 + 0x0000)RCC_BDCR_RTCSEL_NONE 0RCC_CIER_PLLSAI1RDYIE (1 << 6)USART_ISR_RWU (1 << 19)GNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsRCC_AHB2SMENR_AESSMEN (1 << 16)BIT27 (1<<27)RCC_AHB2ENR_AESEN (1 << 16)TIM1_BASE (PERIPH_BASE_APB2 + 0x2C00)RCC_CCIPR_LPUART1SEL_HSI16 2RCC_APB2ENR_SYSCFGEN (1 << 0)USART_CR1_TCIE (1 << 6)__UTA_FBIT__ 64usartRCC_BDCR_LSESYSDIS (1 << 7)RCC_CIFR_MSIRDYF (1 << 2)__FLT_DECIMAL_DIG__ 9RCC_CRRCR_HSI48RDY (1 << 1)__thumb__ 1__INT_LEAST32_MAX__ 0x7fffffffLLIBOPENCM3_MEMORYMAP_COMMON_H signed charRCC_APB1ENR1_OFFSET 0x58INT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)INT32_C(c) __INT32_C(c)__GNUC_STDC_INLINE__ 1usart_recv__FRACT_FBIT__ 15__LLACCUM_EPSILON__ 0x1P-31LLK__GNUC_PATCHLEVEL__ 1__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2PTRDIFF_MINRCC_AHB2RSTR_GPIOGRST (1 << 6)__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)RCC_APB1SMENR1_OFFSET 0x78RCC_AHB2RSTR_GPIOARST (1 << 0)UINTPTR_MAX __UINTPTR_MAX____ARM_ARCH_PROFILE 77RCC_CIFR_PLLRDYF (1 << 5)RCC_CCIPR_LPUART1SEL_APB 0RCC_APB2ENR_SAI2EN (1 << 22)GPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000)RCC_APB1RSTR1_TIM3RST (1 << 1)__FLT64_MAX_10_EXP__ 308GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400)MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINRCC_PLLCFGR_PLLR_DIV2 0RCC_ICSCR_HSITRIM_MASK 0x1fSDMMC1_BASE (PERIPH_BASE_APB2 + 0x2800)__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)__FRACT_MAX__ 0X7FFFP-15RRCC_CCIPR_LPUART1SEL_LSE 3TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)INT_LEAST32_MAX __INT_LEAST32_MAX__RCC_CIER_LSERDYIE (1 << 1)USART3_ICR USART_ICR(USART3_BASE)__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5RCC_APB1SMENR1_USART2SMEN (1 << 17)RCC_PLLCFGR_PLLSRC_HSE 3RCC_CIER_PLLRDYIE (1 << 5)USART_CR3_SCARCNT_MASK 0x7USART_CR1_DEDT (0x1F << USART_CR1_DEDT_SHIFT)USART2_CR3 USART_CR3(USART2_BASE)RCC_AHB2SMENR_GPIODSMEN (1 << 3)RCC_CSR_LSION (1 << 0)RCC_CR_MSIRANGE_SHIFT 4__UINT16_MAX__ 0xffff__TQ_FBIT__ 127RCC_AHB2RSTR_ADCRST (1 << 13)usart_set_stopbitsUSART_CR3_WUFIE (1 << 22)USART_TDR_MASK (0x1FF << 0)__USQ_FBIT__ 32USART_CR1(usart_base) MMIO32((usart_base) + 0x00)__USES_INITFINI__ 1USART_ISR_CTSIF (1 << 9)USART_RQR(usart_base) MMIO32((usart_base) + 0x18)__thumb2__ 1__ULLACCUM_FBIT__ 32FMC_QUADSPI_BASE (0xA0000000U)RCC_AHB2SMENR_SRAM2SMEN (1 << 9)RCC_APB2SMENR_SAI2SMEN (1 << 22)RCC_BDCR_RTCSEL_HSEDIV32 3UART5_CR2 USART_CR2(UART5_BASE)RCC_CFGR_MCO_MASK 0xf__STRICT_ANSI__ 1RCC_CFGR_SWS_PLL 0x3FMC3_BANK_BASE (0x80000000U)UINT_LEAST8_MAXRCC_BDCR_LSCOEN (1 << 24)UINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)TIM8_BASE (PERIPH_BASE_APB2 + 0x3400)RCC_APB1RSTR1_CAN1RST (1 << 25)__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__RCC_AHB1RSTR_DMA2RST (1 << 1)RCC_BDCR_LSECSSON (1 << 5)USART_CR2_ADD_VAL(x) ((x) << USART_CR2_ADD_SHIFT)__USA_IBIT__ 16__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1DBGMCU_BASE (PPBI_BASE + 0x00042000)PTRDIFF_MIN (-PTRDIFF_MAX - 1)USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6c00)RCC_BDCR_LSEDRV_HIGH 3__UINT_FAST64_TYPE__ long long unsigned intPERIPH_BASE_AHB2 (0x48000000U)RCC_CR_MSIRANGE_8MHZ 7RCC_APB1ENR1_TIM4EN (1 << 2)DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7590)__FLT_MIN__ 1.1754943508222875e-38Fusart_set_flow_control__HA_FBIT__ 7RCC_CFGR_MCO_HSI48 0x8__FDPIC__RCC_APB1RSTR1_LCDRST (1 << 9)__UFRACT_MIN__ 0.0URRCC_BDCR_LSERDY (1 << 1)RCC_APB1SMENR2_LPTIM2SMEN (1 << 5)__FLT32_IS_IEC_60559__ 2RCC_AHB1SMENR_DMA1SMEN (1 << 0)USART_CR3_WUS_START_BIT (0x2 << 20)GPIO_PORT_G_BASE (PERIPH_BASE_AHB2 + 0x1800)RCC_CSR_IWDGRSTF (1 << 29)INT_FAST64_MIN__USFRACT_IBIT__ 0__INT32_C(c) c ## LRCC_CIER_HSI48RDYIE (1 << 10)__LDBL_EPSILON__ 2.2204460492503131e-16LRCC_CCIPR_USART1SEL_APB 0USART_CR2(usart_base) MMIO32((usart_base) + 0x04)USART_CR3_SCEN (1 << 5)__USFRACT_MIN__ 0.0UHRTSC_BASE (PERIPH_BASE_AHB1 + 0x4000)RCC_APB1ENR1_TIM6EN (1 << 4)__ARM_NEONRCC_PLLCFGR_PLLQ_DIV2 0__UINT8_MAX__ 0xffUSART_ICR_IDLECF (1 << 4)USART3_CR3 USART_CR3(USART3_BASE)__LDBL_MAX_EXP__ 1024RCC_CFGR_MCOPRE_DIV4 2LIBOPENCM3_MEMORYMAP_H RCC_CFGR_HPRE_MASK 0xfUSART_FLAG_ORE USART_ISR_OREUSART1_ICR USART_ICR(USART1_BASE)__DBL_HAS_DENORM__ 1DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)RCC_APB2RSTR_USART1RST (1 << 14)USART_ISR_RTOF (1 << 11)USART_FLAG_TC USART_ISR_TCRCC_BDCR MMIO32(RCC_BASE + 0x90)USART1_BRR USART_BRR(USART1_BASE)RCC_APB1RSTR1_OFFSET 0x38QUADSPI_BASE (0xa0001000U)__DA_FBIT__ 31RCC_CFGR_SW_HSE 0x2RCC_CCIPR_UART5SEL_SHIFT 8__GXX_ABI_VERSION 1017GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0c00)__INT_LEAST16_MAX__ 0x7fffRCC_CCIPR_ADCSEL_MASK 0x3USART_ISR_ABRE (1 << 14)__FLT_DENORM_MIN__ 1.4012984643248171e-45FUSART_FLAG_PE USART_ISR_PEusart_disable_tx_complete_interruptRCC_CIFR_HSIRDYF (1 << 3)usart_enableRCC_CR_MSIRANGE_16MHZ 8INT_LEAST8_MAX __INT_LEAST8_MAX__USART_FLAG_NF USART_ISR_NFRCC_APB2SMENR_TIM1SMEN (1 << 11)RCC_APB1RSTR1_SPI2RST (1 << 14)RCC_CICR_PLLSAI1RDYC (1 << 6)__UINT32_C(c) c ## ULUSART_CR2_CLKEN (1 << 11)USART_CR1_UE (1 << 0)__UACCUM_MIN__ 0.0UKUSART_CR3_WUS_RXNE (0x3 << 20)__FLT_EPSILON__ 1.1920928955078125e-7FUSART_CR1_RTOIE (1 << 26)USART_ISR_ABRF (1 << 15)RCC_PLLCFGR_PLLSRC_SHIFT 0TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)RCC_APB2RSTR_SAI1RST (1 << 21)RCC_AHB1SMENR_FLASHSMEN (1 << 8)UART5_ICR USART_ICR(UART5_BASE)RCC_APB1ENR1_UART5EN (1 << 20)__ARM_ARCH_ISA_THUMBRCC_CR_PLLSAI1ON (1 << 26)USART_ISR_CMF (1 << 17)USART_STOPBITS_0_5 USART_CR2_STOPBITS_0_5__ARM_FEATURE_MATMUL_INT8USART_ISR_REACK (1 << 22)RCC_AHB1ENR_DMA2EN (1 << 1)LIBOPENCM3_CM3_MEMORYMAP_H __GCC_ATOMIC_SHORT_LOCK_FREE 2RCC_AHB2RSTR_OTGFSRST (1 << 12)RCC_AHB2SMENR_GPIOGSMEN (1 << 6)RCC_CCIPR_LPUART1SEL_SYS 1USART_GTPR(usart_base) MMIO32((usart_base) + 0x10)__USACCUM_FBIT__ 8usart_recv_blocking__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1RCC_APB1ENR1_USART2EN (1 << 17)USART_ICR_RTOCF (1 << 11)RCC_APB1SMENR1_UART5SMEN (1 << 20)__LACCUM_FBIT__ 31SCS_BASE (PPBI_BASE + 0xE000)RCC_APB2SMENR MMIO32(RCC_BASE + RCC_APB2SMENR_OFFSET)RCC_CFGR_STOPWUCK_HSI16 (1 << 15)USART_CR3_OVRDIS (1 << 12)SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)__FLT32_HAS_QUIET_NAN__ 1I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)USART_CR1_RE (1 << 2)RCC_CSR_OBLRSTF (1 << 25)USART_ISR_TXE (1 << 7)__LDBL_HAS_INFINITY__ 1RCC_AHB2RSTR_GPIOERST (1 << 4)__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))__FLT32X_MAX_10_EXP__ 308USART_ISR_TC (1 << 6)DWT_BASE (PPBI_BASE + 0x1000)RCC_CCIPR_CLK48SEL_PLLSAI1Q 1RCC_CIER_HSIRDYIE (1 << 3)bool _BoolRCC_APB2ENR_TIM15EN (1 << 16)UINTMAX_MAX __UINTMAX_MAX__RCC_BDCR_RTCSEL_SHIFT 8__SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)RCC_APB1ENR1_SPI3EN (1 << 15)__UINT_LEAST8_MAX__ 0xffUSART_CR2_LINEN (1 << 14)RCC_CCIPR_CLK48SEL_SHIFT 26BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)USART_CR1_MME (1 << 13)INT16_MAX __INT16_MAX__RCC_AHB1ENR_OFFSET 0x48__FP_FAST_FMAF 1RCC_AHB3ENR_OFFSET 0x50USART_CR3_DEM (1 << 14)__FLT32X_IS_IEC_60559__ 2RCC_APB1RSTR1_USART3RST (1 << 18)PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)RCC_CIER MMIO32(RCC_BASE + 0x18)RCC_APB2RSTR_OFFSET 0x40LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))FIREWALL_BASE (PERIPH_BASE_APB2 + 0x1C00)__INT_LEAST16_WIDTH__ 16SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)__ARM_FEATURE_FP16_FMLRCC_CR_MSIRANGE_2MHZ 5RCC_AHB3ENR_FMCEN (1 << 0)RCC_CCIPR_I2CxSEL_APB 0INT16_MIN (-INT16_MAX - 1)__USFRACT_EPSILON__ 0x1P-8UHRRCC_AHB2ENR_GPIOHEN (1 << 7)RCC_APB2ENR_TIM8EN (1 << 13)__WINT_MAX__ 0xffffffffU__USFRACT_FBIT__ 8CORESIGHT_LSR_SLI (1<<0)RCC_APB1ENR1_LCDEN (1 << 9)USART1 USART1_BASEUSART_CR3_WUS_ADDRMATCH (0x0 << 20)USART_CR2_ABRMOD_SHIFT 21RCC_APB1RSTR1_UART5RST (1 << 20)__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX__RCC_CSR_WWDGRSTF (1 << 30)__UINT32_MAX__ 0xffffffffULRCC_CCIPR_ADCSEL_SYS 3RCC_CFGR_HPRE_DIV16 0xbflowcontrol__INT_LEAST8_MAX__ 0x7f__GCC_ATOMIC_POINTER_LOCK_FREE 2__ARM_FEATURE_QBIT 1__ARM_FEATURE_CLZ 1__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXRCC_BDCR_LSEDRV_MASK 0x3RCC_AHB3ENR MMIO32(RCC_BASE + RCC_AHB3ENR_OFFSET)BIT15 (1<<15)RCC_APB2ENR_TIM16EN (1 << 17)RCC_ICSCR_HSICAL_MASK 0xffRCC_CFGR_SWS_MASK 0x3__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024USART3 USART3_BASEUSART_CR1_PS (1 << 9)__UINT_LEAST32_MAX__ 0xffffffffUL__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1RCC_CICR MMIO32(RCC_BASE + 0x20)__ACCUM_MAX__ 0X7FFFFFFFP-15KRCC_APB1RSTR2_SWPMI1RST (1 << 2)__INT8_MAX__ 0x7fUART5_RDR USART_RDR(UART5_BASE)BIT14 (1<<14)RCC_CCIPR_USART2SEL_SHIFT 2RCC_APB1RSTR1_TIM6RST (1 << 4)__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16RCC_CIER_PLLSAI2RDYIE (1 << 7)__SHRT_WIDTH__ 16BIT20 (1<<20)__ARM_FEATURE_MVEUSART_ICR_LBDCF (1 << 8)USART_CR2_LBDIE (1 << 6)__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intUSART_CR2_CPOL (1 << 10)USART_GTPR_GT (0xFF << USART_GTPR_GT_SHIFT)RCC_APB1RSTR1_TIM4RST (1 << 2)USART1_CR3 USART_CR3(USART1_BASE)SWPMI1_BASE (PERIPH_BASE_APB1 + 0x8800)SAI1_BASE (PERIPH_BASE_APB2 + 0x5400)RCC_CSR_MSIRANGE_4MHZ 6INT_FAST32_MINUART5_CR3 USART_CR3(UART5_BASE)__FLT_EVAL_METHOD_TS_18661_3__ 0RCC_CFGR_HPRE_DIV64 0xc__SCHAR_WIDTH__ 8BIT18 (1<<18)COMP_BASE (PERIPH_BASE_APB2 + 0x0200)RCC_APB1SMENR1 MMIO32(RCC_BASE + RCC_APB1SMENR1_OFFSET)SIZE_MAX__UINT_FAST8_TYPE__ unsigned intUSART_RQR_RXFRQ (1 << 3)__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RBIT24 (1<<24)RCC_PLLCFGR_PLLR_MASK 0x3RCC_CCIPR_I2CxSEL_SYS 1__INT32_MAX__ 0x7fffffffLRCC_APB1ENR1_UART4EN (1 << 19)RCC_PLLCFGR_PLLR_DIV8 3RCC_PLLCFGR_PLLQ_DIV6 2RCC_CFGR_HPRE_DIV256 0xeUINTMAX_MAXRCC_APB1SMENR1_UART4SMEN (1 << 19)BIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_BF16_VECTOR_ARITHMETICINFO_BASE (0x1fff0000U)PPBI_BASE (0xE0000000U)__FLT32_MANT_DIG__ 24INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32RCC_AHB1SMENR_DMA2SMEN (1 << 1)RCC_AHB2RSTR_GPIOCRST (1 << 2)__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN__RCC_CCIPR_LPUART1SEL_SHIFT 10INT8_MAX __INT8_MAX__RCC_CSR_LSIRDY (1 << 1)BIT28 (1<<28)RCC_BDCR_LSEDRV_MEDHIGH 2RCC_PLLPEN (1 << 16)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2INTMAX_C(c) __INTMAX_C(c)RCC_APB1SMENR1_LCDSMEN (1 << 9)RCC_AHB2SMENR_OFFSET 0x6c__DBL_MAX_EXP__ 1024RCC_AHB2RSTR_AESRST (1 << 16)__ATOMIC_RELEASE 3RCC_PLLCFGR_PLLP_DIV17 RCC_PLLCFGR_PLLPUINT_FAST8_MAX__FLT_MANT_DIG__ 24clock__UDQ_IBIT__ 0RCC_CIFR_LSIRDYF (1 << 0)__INT_LEAST32_TYPE__ long intRCC_AHB1SMENR MMIO32(RCC_BASE + RCC_AHB1SMENR_OFFSET)RCC_CR_HSERDY (1 << 17)__OPTIMIZE_SIZE__ 1__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UK__FLT64_NORM_MAX__ 1.7976931348623157e+308F64RCC_APB1RSTR1_OPAMPRST (1 << 30)UINTPTR_MAXLIBOPENCM3_USART_H RCC_CR_PLLSAI1RDY (1 << 27)__LDBL_DENORM_MIN__ 4.9406564584124654e-324L__INT64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_SAT 1USART_CR3_DMAR (1 << 6)__ULLFRACT_IBIT__ 0RCC_PLLCFGR_PLLQ_SHIFT 21USART_FLAG_FE USART_ISR_FERCC_AHB1ENR_TSCEN (1 << 16)MMIO16(addr) (*(volatile uint16_t *)(addr))USART_CR3_EIE (1 << 0)USART_FLOWCONTROL_NONE 0x00AES_BASE (0x50000000U + 0x60000)USART_RDR(usart_base) MMIO32((usart_base) + 0x24)DAC_BASE (PERIPH_BASE_APB1 + 0x7400)__GNUC__ 12BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)WCHAR_MAXRCC_APB1ENR1_USART3EN (1 << 18)RCC_CCIPR_LPTIMxSEL_HSI16 2__LONG_WIDTH__ 32UART5_RQR USART_RQR(UART5_BASE)__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16RCC_CICR_LSIRDYC (1 << 0)__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0UUART5_BASE (PERIPH_BASE_APB1 + 0x5000)RCC_APB2SMENR_DFSDMSMEN (1 << 24)__UQQ_IBIT__ 0RCC_CFGR_SWS_SHIFT 2CORESIGHT_LSR_OFFSET 0xfb4__GCC_ATOMIC_LONG_LOCK_FREE 2__ULACCUM_MIN__ 0.0ULK__LDBL_MAX__ 1.7976931348623157e+308L__ARM_ARCH 7RCC_CFGR_SW_MASK 0x3__FLT_RADIX__ 2BIT3 (1<<3)long long intCORESIGHT_LAR_KEY 0xC5ACCE55UART5_BRR USART_BRR(UART5_BASE)RCC_CCIPR_USART3SEL_SHIFT 4__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAXrcc_apb1_frequencyRCC_AHB2ENR_ADCEN (1 << 13)__LDBL_HAS_QUIET_NAN__ 1RCC_AHB1SMENR_OFFSET 0x68__LONG_LONG_WIDTH__ 64BIT6 (1<<6)USART1_RDR USART_RDR(USART1_BASE)RCC_CFGR_MCOPRE_SHIFT 28RCC_APB1SMENR1_I2C1SMEN (1 << 21)RCC_CCIPR_LPUART1SEL_MASK 0x3__UINT_FAST64_MAX__ 0xffffffffffffffffULLRCC_APB1RSTR1_I2C3RST (1 << 23)__ARM_FP__HA_IBIT__ 8RCC_CSR_RMVF (1 << 23)__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1RCC_CFGR_MCOPRE_MASK 0x7BIT9 (1<<9)RCC_CFGR_HPRE_DIV512 0xf__FLT32X_MIN__ 2.2250738585072014e-308F32xUART4_RQR USART_RQR(UART4_BASE)INTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024UINT16_MAXUSART_STOPBITS_1 USART_CR2_STOPBITS_1RCC_APB1ENR2_LPUART1EN (1 << 0)__FLT64_MIN__ 2.2250738585072014e-308F64__INTMAX_C(c) c ## LLUSART_CR1_CMIE (1 << 14)RCC_APB1SMENR2 MMIO32(RCC_BASE + RCC_APB1SMENR2_OFFSET)RCC_CCIPR_USART1SEL_HSI16 2RCC_CCIPR_DFSDMSEL (1 << 31)__ARM_ARCH_PROFILE__INT64_TYPE__ long long intRCC_CR_MSIRANGE_1MHZ 4__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4RCC_APB2SMENR_TIM15SMEN (1 << 16)RCC_CR_HSION (1 << 8)USART_ISR_NF (1 << 2)RCC_CSR_PINRSTF (1 << 26)UART4_BRR USART_BRR(UART4_BASE)RCC_CCIPR_LPTIMxSEL_MASK 0x3RCC_CR_HSIRDY (1 << 10)USART_ICR_NCF (1 << 2)CRS_BASE (PERIPH_BASE_APB1 + 0x6000)RCC_CCIPR_ADCSEL_PLLSAI1R 1__UFRACT_MAX__ 0XFFFFP-16URUSART_CR3_HDSEL (1 << 3)RCC_AHB1RSTR_OFFSET 0x28usart_disable_rx_dmaINT64_MAXFPB_BASE (PPBI_BASE + 0x2000)RCC_APB2RSTR_SAI2RST (1 << 22)RCC_CFGR_PPRE2_SHIFT 11RCC_CIFR_PLLSAI2RDYF (1 << 7)RCC_CICR_HSI48RDYC (1 << 10)INT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0RCC_BDCR_RTCSEL_LSI 2RCC_CCIPR_USARTxSEL_LSE 3USART_STOPBITS_1_5 USART_CR2_STOPBITS_1_5STIR_BASE (SCS_BASE + 0x0F00)RCC_CFGR_SWS_HSE 0x2__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__RCC_CSR_BORRSTF (1 << 27)ID_BASE (SCS_BASE + 0x0FD0)SYS_TICK_BASE (SCS_BASE + 0x0010)RCC_CSR_MSIRANGE_MASK 0xfRCC_BDCR_LSEDRV_MEDLOW 1RCC_PLLCFGR_PLLSRC_HSI16 2RCC_CFGR_SWS_MSI 0x0USART_ISR_PE (1 << 0)__UFRACT_FBIT__ 16usart_enable_tx_dma__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)RCC_CCIPR_SAIxSEL_MASK 0x3USART_CR2_STOPBITS_1 (0x00 << 12)__LDBL_MAX_10_EXP__ 308RCC_APB2SMENR_USART1SMEN (1 << 14)RCC_AHB2ENR_GPIOBEN (1 << 1)LPUART1 LPUART1_BASERCC_PLLCFGR_PLLQ_DIV4 1USART_RQR_MMRQ (1 << 2)FMC_BASE (0xa0000000U)__INT_FAST32_TYPE__ intRCC_CICR_HSERDYC (1 << 4)USART_CR2_ABRMOD_FALL_EDGE (0x1 << USART_CR2_ABRMOD_SHIFT)unsigned intRCC_CR_MSIRANGE_MASK 0xfRCC_CR_HSIASFS (1 << 11)USART_CR2_LBCL (1 << 8)RCC_CCIPR_SAIxSEL_PLLSAI2P 1__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1USART_FLAG_RXNE USART_ISR_RXNEUSART2_CR1 USART_CR1(USART2_BASE)RCC_CSR_FWRSTF (1 << 24)__USACCUM_IBIT__ 8ITM_BASE (PPBI_BASE + 0x0000)ST_VREFINT_CAL MMIO16((INFO_BASE + 0x75aa))RCC_CIFR_HSERDYF (1 << 4)__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UKRCC_APB1SMENR2_OFFSET 0x7cRCC_APB2SMENR_SYSCFGSMEN (1 << 0)USART_MODE_TX_RX (USART_CR1_RE | USART_CR1_TE)__UTA_IBIT__ 64USART_CR2_ABRMOD_STARTBIT (0x0 << USART_CR2_ABRMOD_SHIFT)RCC_CIFR_PLLSAI1RDYF (1 << 6)__FLT_EVAL_METHOD__ 0USART_CR2_ABRMOD_MASK 3RCC_AHB3SMENR MMIO32(RCC_BASE + RCC_AHB3SMENR_OFFSET)__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32DFSDM_BASE (PERIPH_BASE_APB2 + 0x6000)RCC_AHB2ENR_GPIOCEN (1 << 2)RCC_BASE (PERIPH_BASE_AHB1 + 0x1000)__ARM_FEATURE_LDREXUSART_RQR_TXFRQ (1 << 4)__UQQ_FBIT__ 8RCC_CFGR_HPRE_SHIFT 4INT16_C__ARM_FP16_ARGS__GCC_IEC_559 0RCC_CSR MMIO32(RCC_BASE + 0x94)RCC_CFGR_PPRE2_DIV8 0x6INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX__UART4_ICR USART_ICR(UART4_BASE)__LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4bits__STDC__ 1RCC_AHB2SMENR_RNGSMEN (1 << 18)RCC_CCIPR_CLK48SEL_PLL 2RCC_APB1ENR1_I2C3EN (1 << 23)__ARM_FEATURE_IDIV 1RCC_APB2RSTR_SYSCFGRST (1 << 0)__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN____UINT8_TYPE__ unsigned charRCC_BDCR_LSECSSD (1 << 6)RCC_APB2ENR_SAI1EN (1 << 21)__ARM_FEATURE_COPROC 15RCC_AHB1SMENR_TSCSMEN (1 << 16)RCC_CICR_HSIRDYC (1 << 3)UINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"INT8_MINRCC_APB2ENR_DFSDMEN (1 << 24)RCC_PLLCFGR_PLLM_SHIFT 0x4RCC_APB1SMENR1_CAN1SMEN (1 << 25)RCC_PLLCFGR_PLLQEN (1 << 20)LIBOPENCM3_RCC_H PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)USART_RTOR_BLEN_VAL(x) ((x) << USART_RTOR_BLEN_SHIFT)__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)UART4_RTOR USART_RTOR(UART4_BASE)USART_ISR_TEACK (1 << 21)RCC_CCIPR_LPTIMxSEL_LSI 1__LDBL_MIN_10_EXP__ (-307)RCC_BDCR_LSEON (1 << 0)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1RCC_CFGR_SW_PLL 0x3__GCC_ATOMIC_CHAR_LOCK_FREE 2RCC_AHB2ENR_OFFSET 0x4cRCC_CR_PLLSAI2ON (1 << 28)USART_CR1_OVER8 (1 << 15)__LFRACT_EPSILON__ 0x1P-31LRFMC1_BANK_BASE (0x60000000U)STM32L4 1USART_CR1_M1 (1 << 28)RCC_APB1SMENR1_TIM7SMEN (1 << 5)RCC_APB1SMENR1_OPAMPSMEN (1 << 30)__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX____FLT32X_NORM_MAX__ 1.7976931348623157e+308F32xUSART3_CR1 USART_CR1(USART3_BASE)__arm__ 1usart_disable_tx_interruptRCC_CCIPR_LPTIMxSEL_APB 0USART2_RQR USART_RQR(USART2_BASE)__FLT32_MIN_10_EXP__ (-37)RCC_APB1RSTR2_LPTIM2RST (1 << 5)RCC_APB1ENR1_PWREN (1 << 28)MMIO64(addr) (*(volatile uint64_t *)(addr))RCC_APB1ENR1_I2C2EN (1 << 22)__ARM_FP16_FORMAT_ALTERNATIVERCC_APB1SMENR1_TIM3SMEN (1 << 1)USART_CR3_RTSE (1 << 8)__LDBL_NORM_MAX__ 1.7976931348623157e+308LRCC_PLLCFGR_PLLR_DIV4 1INTPTR_MINRCC_CFGR_HPRE_DIV2 0x8DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)RCC_APB1ENR1_LPTIM1EN (1 << 31)RCC_CCIPR_LPTIMxSEL_LSE 3USART_FLOWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)__TA_IBIT__ 64RCC_CCIPR_USARTxSEL_APB 0RCC_APB1SMENR1_I2C3SMEN (1 << 23)RCC_AHB2SMENR_GPIOASMEN (1 << 0)UART4_ISR USART_ISR(UART4_BASE)__ARM_FEATURE_QRDMXRCC_CFGR_HPRE_NODIV 0x0RCC_CCIPR_LPTIM1SEL_SHIFT 18UART5_ISR USART_ISR(UART5_BASE)__ARM_ARCH_ISA_THUMB 2USART_ISR_SBKF (1 << 18)USART_ICR_FECF (1 << 1)__LONG_LONG_MAX__ 0x7fffffffffffffffLLRCC_APB1RSTR1_PWRRST (1 << 28)RCC_APB1ENR2_OFFSET 0x5c__WINT_WIDTH__ 32SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__USART_CR2_MSBFIRST (1 << 19)UART4_RDR USART_RDR(UART4_BASE)USART_CR3(usart_base) MMIO32((usart_base) + 0x08)BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1USART_GTPR_GT_VAL(x) ((x) << USART_GTPR_GT_SHIFT)_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN____SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__DBL_MIN_EXP__ (-1021)RCC_APB1ENR1_TIM7EN (1 << 5)__LDBL_HAS_DENORM__ 1RCC_CFGR_PPRE1_DIV8 0x6USART_CR1_TE (1 << 3)RCC_AHB2RSTR_RNGRST (1 << 18)USART2_ICR USART_ICR(USART2_BASE)INT_FAST32_MIN (-INT_FAST32_MAX - 1)USART_CR3_CTSE (1 << 9)RCC_AHB2ENR MMIO32(RCC_BASE + RCC_AHB2ENR_OFFSET)__FLT32_DIG__ 6RCC_AHB3RSTR MMIO32(RCC_BASE + RCC_AHB3RSTR_OFFSET)INT_LEAST16_MAXRCC_APB2RSTR_SDMMC1RST (1 << 10)RCC_CCIPR_USARTxSEL_HSI16 2rcc_apb2_frequencyRCC_AHB2RSTR_OFFSET 0x2cUART5 UART5_BASEUSART_CR1_IDLEIE (1 << 4)RCC_AHB2RSTR_GPIOBRST (1 << 1)VREFBUF_BASE (PERIPH_BASE_APB2 + 0x0030)BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1INT32_MAXUSART_CR3_SCARCNT_DISABLE (0 << USART_CR3_SCARCNT_SHIFT)USART_STOPBITS_2 USART_CR2_STOPBITS_2USART3_RQR USART_RQR(USART3_BASE)__ACCUM_MIN__ (-0X1P15K-0X1P15K)RCC_ICSCR_MSITRIM_MASK 0xffusart_enable_error_interrupt__ARM_FEATURE_CRYPTORCC_AHB2RSTR_GPIOHRST (1 << 7)UART4_BASE (PERIPH_BASE_APB1 + 0x4c00)RCC_CFGR_HPRE_DIV4 0x9USART_CR1_RXNEIE (1 << 5)BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__FRACT_IBIT__ 0USART2_RDR USART_RDR(USART2_BASE)RCC_CICR_LSERDYC (1 << 1)UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234RCC_CR_MSIRANGE_4MHZ 6ADC1_BASE (0x50000000U + 0x40000)__FLT_NORM_MAX__ 3.4028234663852886e+38FUSART_ICR_CTSCF (1 << 9)RCC_APB1SMENR2_LPUART1SMEN (1 << 0)long long unsigned intUSART_TDR(usart_base) MMIO32((usart_base) + 0x28)__FLT_MIN_10_EXP__ (-37)GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000)__ULACCUM_IBIT__ 32RCC_APB2ENR_OFFSET 0x60__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__PTRDIFF_TYPE__ int__APCS_32__ 1__DQ_FBIT__ 63USART_CR2_STOPBITS_1_5 (0x03 << 12)INT_LEAST64_MAX__SACCUM_IBIT__ 8USART_CR2_STOPBITS_0_5 (0x01 << 12)reg32_REG_BIT(base,bit) (((base) << 5) + (bit))__UHQ_IBIT__ 0TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)INT_LEAST8_MINUSART_CR2_RTOEN (1 << 23)BIT29 (1<<29)RCC_APB1RSTR1_I2C2RST (1 << 22)__INT_FAST16_TYPE__ intRCC_APB1ENR1_DAC1EN (1 << 29)INT64_C__ULFRACT_MAX__ 0XFFFFFFFFP-32ULRRCC_CCIPR_I2C1SEL_SHIFT 12__UINT_LEAST16_TYPE__ short unsigned intUSART_FLAG_IDLE USART_ISR_IDLEUSART1_TDR USART_TDR(USART1_BASE)__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned intRCC_CCIPR_USARTxSEL_SYS 1usart_disable_error_interruptRCC_APB2SMENR_TIM17SMEN (1 << 18)__FLT32X_DIG__ 15USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x6800)USART_ICR_CMCF (1 << 17)RCC_CFGR_PPRE2_MASK 0x7__UTQ_FBIT__ 128RCC_APB2ENR_TIM17EN (1 << 18)USART_CR3_ONEBIT (1 << 11)usart_wait_send_ready__FINITE_MATH_ONLY__ 0RCC_CFGR_MCO_NOCLK 0x0__INT_FAST16_MAX__ 0x7fffffffRCC_APB2RSTR_DFSDMRST (1 << 24)USART_CR1_PEIE (1 << 8)DMA2_BASE (PERIPH_BASE_AHB1 + 0x0400)PTRDIFF_MAX __PTRDIFF_MAX____SIZEOF_SHORT__ 2RCC_CFGR_SWS_HSI16 0x1RCC_CFGR_PPRE2_DIV16 0x7RCC_CCIPR_CLK48SEL_MASK 0x3RCC_CR_PLLRDY (1 << 25)RCC_CFGR_PPRE2_NODIV 0x0USART_CR2_LBDL (1 << 5)UINT_FAST16_MAX__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKRCC_CCIPR_SAIxSEL_PLL 2RCC_PLLCFGR_PLLM(x) ((x)-1)RCC_APB1ENR2 MMIO32(RCC_BASE + RCC_APB1ENR2_OFFSET)UINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRRCC_BDCR_RTCSEL_LSE 1RCC_APB1SMENR1_SPI2SMEN (1 << 14)__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intRCC_AHB2ENR_RNGEN (1 << 18)RCC_AHB2ENR_GPIOGEN (1 << 6)USART_ICR_ORECF (1 << 3)USART3_RDR USART_RDR(USART3_BASE)usart_disable_idle_interruptWCHAR_MINRCC_CRRCR MMIO32(RCC_BASE + 0x98)usart_disableBEGIN_DECLS USART_CR1_M USART_CR1_M0RCC_CFGR_PPRE1_DIV16 0x7RCC_CFGR_PPRE2_DIV4 0x5RCC_AHB2RSTR_GPIOFRST (1 << 5)USART_CR2_STOPBITS_SHIFT 12USART_ICR_TCCF (1 << 6)RCC_APB1ENR1_TIM2EN (1 << 0)RCC_AHB1ENR_CRCEN (1 << 12)RCC_APB2ENR_FWEN (1 << 7)__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15RCC_APB2SMENR_SPI1SMEN (1 << 12)__FLT32X_MAX__ 1.7976931348623157e+308F32xGPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400)USART2_RTOR USART_RTOR(USART2_BASE)USART_ISR_CTS (1 << 10)__ARM_EABI__ 1UART4_CR3 USART_CR3(UART4_BASE)RCC_BDCR_RTCSEL_MASK 0x3INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1__ARM_FEATURE_DSP 1USART_RQR_SBKRQ (1 << 1)RCC_CR_MSIPLLEN (1 << 2)USART2_TDR USART_TDR(USART2_BASE)TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)__QQ_IBIT__ 0USART_ICR_PECF (1 << 0)RCC_CR_MSIRANGE_100KHZ 0RCC_CCIPR_LPTIM2SEL_SHIFT 20USART_FLOWCONTROL_RTS USART_CR3_RTSEUSART_CR2_SWAP (1 << 15)RCC_CR_PLLON (1 << 24)__LLACCUM_FBIT__ 31RCC_APB2ENR MMIO32(RCC_BASE + RCC_APB2ENR_OFFSET)__UINTMAX_TYPE__ long long unsigned intLIBOPENCM3_RCC_COMMON_ALL_H DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 0x14)__USQ_IBIT__ 0RCC_ICSCR_HSICAL_SHIFT 16__UINT_LEAST32_TYPE__ long unsigned intRCC_AHB1RSTR_TSCRST (1 << 16)__ARM_FEATURE_NUMERIC_MAXMINUSART_CR1_TXEIE (1 << 7)__INTMAX_TYPE__ long long intUSART_FLAG_TXE USART_ISR_TXE__GCC_ATOMIC_INT_LOCK_FREE 2RCC_APB2RSTR_TIM17RST (1 << 18)RCC_APB1RSTR1_TIM5RST (1 << 3)TIM16_BASE (PERIPH_BASE_APB2 + 0x4400)INTMAX_MAXRCC_APB1SMENR1_SPI3SMEN (1 << 15)USART_RTOR_RTO_SHIFT 0DESIG_PACKAGE MMIO16((INFO_BASE + 0x7500))__ARM_ARCH_7EM__ 1__ARM_FEATURE_FP16_SCALAR_ARITHMETICRCC_CFGR_MCO_LSE 0x7__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1RCC_AHB3RSTR_QSPIRST (1 << 8)TIM17_BASE (PERIPH_BASE_APB2 + 0x4800)__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CRCC_PLLCFGR_PLLSRC_MSI 1USART2 USART2_BASEINT64_MINRCC_APB1RSTR1_LPTIM1RST (1 << 31)__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_Cusart_wait_recv_readyRCC_CFGR_SW_MSI 0x0UINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRUSART1_GTPR USART_GTPR(USART1_BASE)UINT16_C(c) __UINT16_C(c)RCC_PLLCFGR_PLLQ_DIV8 3/build/libopencm3/lib/stm32/l4__SIZEOF_SIZE_T__ 4RCC_APB1ENR1 MMIO32(RCC_BASE + RCC_APB1ENR1_OFFSET)__UINT64_TYPE__ long long unsigned intuint16_t__INT64_C(c) c ## LLUSART1_BASE (PERIPH_BASE_APB2 + 0x3800)usart_enable_tx_interruptUSART_CR2_ADD (0xFF << USART_CR2_ADD_SHIFT)TPIU_BASE (PPBI_BASE + 0x40000)__LDBL_MIN__ 2.2250738585072014e-308LRCC_CCIPR_UART4SEL_SHIFT 6__ARM_FEATURE_CDE__ACCUM_IBIT__ 16RCC_CR_MSIRANGE_32MHZ 10USART_CR2_DATAINV (1 << 18)RCC_AHB2ENR_GPIOAEN (1 << 0)CORESIGHT_LAR_OFFSET 0xfb0EXTI_BASE (PERIPH_BASE_APB2 + 0x0400)USART_ISR_FE (1 << 1)USART3_TDR USART_TDR(USART3_BASE)RCC_AHB1RSTR_DMA1RST (1 << 0)RCC_APB2RSTR MMIO32(RCC_BASE + RCC_APB2RSTR_OFFSET)RCC_CIFR_LSERDYF (1 << 1)FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000)short intRNG_BASE (0x50000000U + 0x60800)USART_RDR_MASK (0x1FF << 0)RCC_CSR_RESET_FLAGS (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF | RCC_CSR_IWDGRSTF | RCC_CSR_SFTRSTF | RCC_CSR_BORRSTF | RCC_CSR_PINRSTF | RCC_CSR_OBLRSTF | RCC_CSR_FWRSTF)RCC_CSR_LPWRRSTF (1 << 31)RCC_CSR_MSIRANGE_SHIFT 8__UINT16_C(c) cBIT31 (1<<31)__UDA_IBIT__ 32modeUSART_CR1_EOBIE (1 << 27)USART_FLOWCONTROL_CTS USART_CR3_CTSEUINT_LEAST32_MAXRCC_CSR_MSIRANGE_8MHZ 7RCC_PLLSAI2_CFGR MMIO32(RCC_BASE + 0x14)BIT2 (1<<2)RCC_PLLCFGR_PLLP (1 << 17)__ATOMIC_RELAXED 0__ARM_FEATURE_COPROCUSART_ISR(usart_base) MMIO32((usart_base) + 0x1C)RCC_BDCR_LSEDRV_LOW 0RCC_AHB2ENR_OTGFSEN (1 << 12)__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53RCC_CCIPR_UARTxSEL_SYS RCC_CCIPR_USARTxSEL_SYSUSART_CR1_M0 (1 << 12)usart_set_databitsBIT5 (1<<5)BIT1 (1<<1)INT8_CGPIO_PORT_H_BASE (PERIPH_BASE_AHB2 + 0x1c00)INT_LEAST32_MAX__ARM_ARCH_EXT_IDIV__ 1USART_CR3_CTSIE (1 << 10)RCC_CCIPR_USART1SEL_SYS 1RCC_PLLCFGR_PLLR_SHIFT 25__DBL_DECIMAL_DIG__ 17RCC_CSR_MSIRANGE_2MHZ 5BIT8 (1<<8)RCC_CRRCR_HSI48ON (1 << 0)USART_CR3_IREN (1 << 1)INT16_C(c) __INT16_C(c)RCC_CCIPR_CLK48SEL_HSI48 0UINT32_MAXRCC_APB1SMENR1_USART3SMEN (1 << 18)__INT16_MAX__ 0x7fffUSART3_GTPR USART_GTPR(USART3_BASE)RCC_BDCR_LSEBYP (1 << 2)RCC_CFGR_MCOPRE_DIV16 4RCC_AHB2SMENR_GPIOFSMEN (1 << 5)USART_RTOR(usart_base) MMIO32((usart_base) + 0x14)RCC_CIFR_HSI48RDYF (1 << 10)__INT_WIDTH__ 32__ARM_FEATURE_SIMD32 1DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x75e0)RCC_APB1SMENR1_WWDGSMEN (1 << 11)RCC_CR_HSEBYP (1 << 18)__QQ_FBIT__ 7RCC_CR_PLLSAI2RDY (1 << 29)USART_CR2_ABRMOD_FRAME_0x55 (0x3 << USART_CR2_ABRMOD_SHIFT)__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64RCC_AHB2SMENR_OTGFSSMEN (1 << 12)RCC_CFGR_PPRE1_SHIFT 8RCC_BDCR_BDRST (1 << 16)LPTIM2_BASE (PERIPH_BASE_APB1 + 0x9400)__ULLACCUM_IBIT__ 32RCC_APB1RSTR1_TIM7RST (1 << 5)RCC_CICR_CSSC (1 << 8)__ULLFRACT_EPSILON__ 0x1P-64ULLRfalse 0RCC_APB1RSTR1_TIM2RST (1 << 0)RCC_CCIPR_I2C3SEL_SHIFT 16__SIZEOF_WINT_T__ 4USART_ISR_IDLE (1 << 4)__ARM_FEATURE_UNALIGNED 1__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17RCC_CFGR_PPRE1_MASK 0x7USART_GTPR_PSC (0xFF << USART_GTPR_PSC_SHIFT)__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1USART_BRR(usart_base) MMIO32((usart_base) + 0x0C)__FLT32X_HAS_DENORM__ 1USART_CR2_ADD_SHIFT 24__ULLACCUM_MIN__ 0.0ULLK__INT_FAST32_WIDTH__ 32RCC_CR_MSIRANGE_200KHZ 1RCC_APB1RSTR1_SPI3RST (1 << 15)USART_CR1_DEAT_SHIFT 21RCC_CCIPR_I2CxSEL_HSI16 2RCC_CCIPR_SWPMI1SEL (1 << 30)__ARM_ASM_SYNTAX_UNIFIED__ 1RCC_CR MMIO32(RCC_BASE + 0x00)RCC_APB2ENR_USART1EN (1 << 14)RCC_CFGR_MCOPRE_DIV1 0USART_CR3_NACK (1 << 4)__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODUSART1_RQR USART_RQR(USART1_BASE)RCC_APB2SMENR_TIM16SMEN (1 << 17)UART4_GTPR USART_GTPR(UART4_BASE)RCC_CFGR_MCOPRE_DIV2 1__ARM_PCS_VFP 1RCC_CCIPR_USART1SEL_LSE 3RCC_AHB2RSTR_GPIODRST (1 << 3)USART1_ISR USART_ISR(USART1_BASE)usart_set_mode__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H RCC_CFGR_SW_HSI16 0x1LPUART1_BASE (PERIPH_BASE_APB1 + 0x8000)RCC_CCIPR_SAI2SEL_SHIFT 24USART_CR3_SCARCNT_VAL(x) ((x) << USART_CR3_SCARCNT_SHIFT)INT_LEAST64_MIN__GCC_CONSTRUCTIVE_SIZE 64__LLFRACT_IBIT__ 0RCC_APB1SMENR2_SWPMI1SMEN (1 << 2)RCC_AHB2SMENR_ADCSMEN (1 << 13)uint32_tUSART2_CR2 USART_CR2(USART2_BASE)BIT12 (1<<12)RCC_CFGR_HPRE_DIV128 0xdMPU_BASE (SCS_BASE + 0x0D90)__SACCUM_EPSILON__ 0x1P-7HKRCC_CFGR_PPRE1_DIV4 0x5__GCC_ASM_FLAG_OUTPUTS__ 1USART_PARITY_NONE 0x00RCC_BDCR_LSCOSEL (1 << 25)ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0x75a8))USART_FLOWCONTROL_MASK (USART_CR3_RTSE | USART_CR3_CTSE)__ARM_FP 4RCC_CCIPR_ADCSEL_SHIFT 28RCC_AHB3ENR_QSPIEN (1 << 8)__UINT_FAST16_TYPE__ unsigned intUSART_CR1_UESM (1 << 1)__UHA_IBIT__ 8RCC_CCIPR_CLK48SEL_MSI 3__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULKUSART_RTOR_RTO_MASK (0xFFFFF << USART_RTOR_RTO_SHIFT)__LDBL_DIG__ 15POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXUSART_CR2_RXINV (1 << 16)BIT16 (1<<16)__WINT_MIN__ 0UINT_LEAST16_MINUSART_ISR_ORE (1 << 3)__FLT64_DIG__ 15RCC_APB2ENR_TIM1EN (1 << 11)TIM15_BASE (PERIPH_BASE_APB2 + 0x4000)BIT22 (1<<22)__INT_LEAST8_WIDTH__ 8RCC_APB1RSTR2 MMIO32(RCC_BASE + RCC_APB1RSTR2_OFFSET)WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)RCC_AHB2SMENR_GPIOBSMEN (1 << 1)__INT_LEAST16_TYPE__ short intRCC_AHB3SMENR_FMCSMEN (1 << 0)__ULLACCUM_EPSILON__ 0x1P-32ULLKRCC_PLLCFGR MMIO32(RCC_BASE + 0x0c)__DBL_MAX__ ((double)1.7976931348623157e+308L)RCC_ICSCR_HSITRIM_SHIFT 24INT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1UINTMAX_CRCC_CFGR_SW_SHIFT 0stopbitsINT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1__HQ_FBIT__ 15__bool_true_false_are_defined 1USART3_RTOR USART_RTOR(USART3_BASE)BIT26 (1<<26)RCC_AHB3SMENR_QSPISMEN (1 << 8)RCC_CCIPR_UARTxSEL_APB RCC_CCIPR_USARTxSEL_APB__SIZE_MAX__ 0xffffffffUSPI2_BASE (PERIPH_BASE_APB1 + 0x3800)RCC_CR_HSEON (1 << 16)RCC_APB2SMENR_SAI1SMEN (1 << 21)USART_ICR(usart_base) MMIO32((usart_base) + 0x20)usart_send_blocking__ARM_ARCHRCC_CCIPR_SAIxSEL_EXT 3__LONG_MAX__ 0x7fffffffLRCC_APB2RSTR_TIM1RST (1 << 11)RCC_CR_MSIRDY (1 << 1)RCC_APB1RSTR1_USART2RST (1 << 17)RCC_PLLCFGR_PLLM_MASK 0x7RCC_CCIPR_USART1SEL_MASK 0x3SAI2_BASE (PERIPH_BASE_APB2 + 0x5800)RCC_AHB2RSTR MMIO32(RCC_BASE + RCC_AHB2RSTR_OFFSET)RCC_CFGR_PPRE1_NODIV 0x0__ARM_FEATURE_LDREX 7PTRDIFF_MAXUSART_PARITY_ODD (USART_CR1_PS | USART_CR1_PCE)RCC_BDCR_LSEDRV_SHIFT 3RCC_PLLCFGR_PLLP_DIV7 0RCC_PLLCFGR_PLLN_SHIFT 0x8__LLFRACT_EPSILON__ 0x1P-63LLRRCC_CR_HSIKERON (1 << 9)__SFRACT_MAX__ 0X7FP-7HR__FLT32X_MANT_DIG__ 53RCC_CCIPR_USARTxSEL_MASK 0x3RCC_PLLCFGR_PLLQ_MASK 0x3__WCHAR_WIDTH__ 32RCC_CFGR_MCO_LSI 0x6USART_MODE_MASK (USART_CR1_RE | USART_CR1_TE)WINT_MAX__INT16_C(c) cRCC_APB1ENR2_SWPMI1EN (1 << 2)INT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32RCC_AHB3RSTR_OFFSET 0x30RCC_CCIPR_ADCSEL_NONE 0USART_CR1_PCE (1 << 10)RCC_CSR_MSIRANGE_1MHZ 4USART_RTOR_BLEN_SHIFT 24parity__ATOMIC_ACQ_REL 4RCC_CR_MSIRANGE_24MHZ 9__HQ_IBIT__ 0__DBL_MIN_10_EXP__ (-307)dataRCC_CFGR_MCO_HSI16 0x3RCC_APB1RSTR1_DAC1RST (1 << 29)RCC_CR_CSSON (1 << 19)RCC_APB2ENR_SPI1EN (1 << 12)USART_ISR_WUF (1 << 20)USART2_ISR USART_ISR(USART2_BASE)__FLT32_NORM_MAX__ 3.4028234663852886e+38F32USART2_GTPR USART_GTPR(USART2_BASE)RCC_APB2SMENR_OFFSET 0x80RCC_CFGR_MCO_SYSCLK 0x1UINT64_C(c) __UINT64_C(c)RCC_APB2RSTR_TIM8RST (1 << 13)RCC_APB2RSTR_TIM16RST (1 << 17)USART_CR1_DEAT_VAL(x) ((x) << USART_CR1_DEAT_SHIFT)__UINTMAX_MAX__ 0xffffffffffffffffULLRCC_CCIPR_ADCSEL_PLLSAI2R 2__DBL_MANT_DIG__ 53UART4_CR1 USART_CR1(UART4_BASE)__ULFRACT_IBIT__ 0USART_CR2_TXINV (1 << 17)USART_RQR_ABKRQ (1 << 0)INT_FAST16_MAXITR_BASE (SCS_BASE + 0x0000)USART_RTOR_RTO_VAL(x) ((x) << USART_RTOR_RTO_SHIFT)QUADSPI_BANK_BASE (0x90000000U)__INT_MAX__ 0x7fffffff__INT_LEAST64_TYPE__ long long intusart_enable_rx_dmaRCC_AHB1SMENR_CRCSMEN (1 << 12)RCC_APB1ENR1_CAN1EN (1 << 25)RCC_CFGR MMIO32(RCC_BASE + 0x08)__ARM_FEATURE_CDE_COPROCUSART_ISR_BUSY (1 << 16)UINT32_CUSART_PARITY_MASK (USART_CR1_PS | USART_CR1_PCE)GCC: (15:12.2.rel1-1) 12.2.1 20221205˙˙˙˙| LA„Ž A„…ŽHÎĹÄĂA„ŽFÎÄ A3aeabi)7E-M M "ń˙ < !!""##$$%%&&''(())*,-/13KM579;=?ACEGIOArŁŐ:n© ă NQ ALTgzŤ ±Ŕ× ä ň';Q\ p … ™ ® Č !ă "ý # $; %_ &{ ' (µ )usart_common_all.c$t$dwm4.0.c5e6bdb01417bb5a599260a3f8c9cb62wm4.common.h.21.c9066c2f6b12c71b40226ea6107829a4wm4.stdint.h.29.6d480f4ba0f60596e88234283d42444fwm4.stdbool.h.29.4a1c88fe569adb8d03217dd16982ca34wm4.common.h.67.5c568a1f62c8e726909b04e29f9e1fc0wm4.memorymap.h.21.8c90486dae5eea2d8efddd23fe5d09d9wm4.memorymap.h.26.bb1efb6ce36cc052fd0489ef5a3533f5wm4.usart_common_all.h.35.bd3c3b47d5858b45f68435b934dd532ewm4.usart_common_v2.h.33.21f0272ea673e54352d1eeaaf4506f64wm4.usart.h.37.2d48e96b821a9920058e758acb058711wm4.rcc.h.40.e8c13f444ba606cb63a83dcc96231a47usart_set_baudratercc_apb1_frequencyrcc_apb2_frequencyusart_set_databitsusart_set_stopbitsusart_set_parityusart_set_modeusart_set_flow_controlusart_enableusart_disableusart_send_blockingusart_wait_send_readyusart_sendusart_recv_blockingusart_wait_recv_readyusart_recvusart_enable_rx_dmausart_disable_rx_dmausart_enable_tx_dmausart_disable_tx_dmausart_enable_rx_interruptusart_disable_rx_interruptusart_enable_tx_interruptusart_disable_tx_interruptusart_enable_tx_complete_interruptusart_disable_tx_complete_interruptusart_enable_idle_interruptusart_disable_idle_interruptusart_enable_error_interruptusart_disable_error_interrupt@cDd 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0x2400)__CHAR_UNSIGNED__ 1__UINTPTR_MAX__ 0xffffffffUUSART_CR3_DEP (1 << 15)USART3_BASE (PERIPH_BASE_APB1 + 0x4800)USART_RTOR_BLEN_MASK (0xFF << USART_RTOR_BLEN_SHIFT)__FLT64_HAS_INFINITY__ 1__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GCC_DESTRUCTIVE_SIZE 64__LACCUM_EPSILON__ 0x1P-31LK__PTRDIFF_MAX__ 0x7fffffffUSART_CR1_DEDT_VAL(x) ((x) << USART_CR1_DEDT_SHIFT)__ARM_FEATURE_FMA 1__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)__INTMAX_MAX__ 0x7fffffffffffffffLLADC1_BASE (0x50000000U + 0x40000)__FLT32X_MIN_EXP__ (-1021)WINT_MIN __WINT_MIN__INT_FAST64_MAXOPAMP_BASE (PERIPH_BASE_APB1 + 0x7800)__ATOMIC_CONSUME 1__ULACCUM_FBIT__ 32__WCHAR_MAX__ 0xffffffffUUSART_ISR_EOBF (1 << 12)UART5_GTPR USART_GTPR(UART5_BASE)USART2_BRR USART_BRR(USART2_BASE)USART3_ISR USART_ISR(USART3_BASE)INT64_MAX __INT64_MAX__INTMAX_MIN__SIZEOF_LONG_LONG__ 8__DBL_MAX_10_EXP__ 308__FRACT_MIN__ (-0.5R-0.5R)__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLK__USACCUM_MAX__ 0XFFFFP-8UHK__SFRACT_FBIT__ 7__INTMAX_WIDTH__ 64__ARM_FEATURE_BF16_SCALAR_ARITHMETIC__SQ_IBIT__ 0__ORDER_PDP_ENDIAN__ 3412__SIZE_TYPE__ unsigned int__FLT_HAS_DENORM__ 1__INT8_TYPE__ signed char__FLT32_MIN__ 1.1754943508222875e-38F32usart_enable_halfduplex__USACCUM_MIN__ 0.0UHK__FLT32_DECIMAL_DIG__ 9__DECIMAL_DIG__ 17__LDBL_MIN_EXP__ (-1021)INT_FAST16_MIN__LDBL_MANT_DIG__ 53INT64_MIN (-INT64_MAX - 1)__UINT8_C(c) c__INT16_TYPE__ short inttrue 1__FLT64_MAX__ 1.7976931348623157e+308F64UART5_RTOR USART_RTOR(UART5_BASE)UINT_FAST32_MAXUSART_GTPR_GT_SHIFT 8USART_GTPR_PSC_SHIFT 0USART1_RTOR USART_RTOR(USART1_BASE)INT_FAST64_MAX __INT_FAST64_MAX____GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1USART_CR3_SCARCNT_VAL(x) ((x) << USART_CR3_SCARCNT_SHIFT)usart_sendUSART_ICR_EOBCF (1 << 12)__UINT_LEAST16_MAX__ 0xffff__STDC_HOSTED__ 1__ULLFRACT_FBIT__ 64__SIG_ATOMIC_TYPE__ intUSART_CR3_DDRE (1 << 13)__INT_FAST64_TYPE__ long long int__WINT_TYPE__ unsigned intGPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800)USART3_CR2 USART_CR2(USART3_BASE)ST_TSENSE_CAL2_110C MMIO16((INFO_BASE + 0x75ca))INT32_MIN (-INT32_MAX - 1)__FLT32_MAX_10_EXP__ 38USART_CR2_ADDM7 (1 << 4)__USFRACT_MAX__ 0XFFP-8UHRLPTIM1_BASE (PERIPH_BASE_APB1 + 0x7c00)__FP_FAST_FMAF32 1TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)USART_CR3_SCARCNT_SHIFT 17__FLT32_MIN_EXP__ (-125)USART3_BRR USART_BRR(USART3_BASE)UART5_CR1 USART_CR1(UART5_BASE)UINT32_MAX __UINT32_MAX__usart_disable_tx_inversionUSART_GTPR_PSC_VAL(x) ((x) << USART_GTPR_PSC_SHIFT)__ULFRACT_FBIT__ 32INT8_MIN (-INT8_MAX - 1)__FLT64_MIN_10_EXP__ (-307)__GNUC_EXECUTION_CHARSET_NAME "UTF-8"BIT10 (1<<10)__INT_FAST64_WIDTH__ 64__STDC_VERSION__ 199901LINT_LEAST64_MAX __INT_LEAST64_MAX____SFRACT_EPSILON__ 0x1P-7HRUSART_CR2_STOPBITS_MASK (0x03 << 12)USART_CR2_ABRMOD_FRAME_0x7F (0x2 << USART_CR2_ABRMOD_SHIFT)UINT_LEAST16_MAX __UINT_LEAST16_MAX__UINT32_C(c) __UINT32_C(c)__ORDER_BIG_ENDIAN__ 4321SIZE_MAXSYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000)__UINTPTR_TYPE__ unsigned int__SQ_FBIT__ 31INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)USART_ISR_RXNE (1 << 5)__TQ_IBIT__ 0UART4 UART4_BASE__UHQ_FBIT__ 16USART_CR1_DEDT_SHIFT 16__FLT64_MIN_EXP__ (-1021)__PTRDIFF_WIDTH__ 32USART_CR1_WAKE (1 << 11)TIM8_BASE (PERIPH_BASE_APB2 + 0x3400)__UINT_FAST8_MAX__ 0xffffffffUUART4_CR2 USART_CR2(UART4_BASE)UINT16_C(c) __UINT16_C(c)UART5_TDR USART_TDR(UART5_BASE)__LACCUM_IBIT__ 32__INT_FAST16_WIDTH__ 32INTMAX_C__VERSION__ "12.2.1 20221205"__VFP_FP__ 1__LLFRACT_MIN__ (-0.5LLR-0.5LLR)INT_FAST8_MAX__UINT_FAST16_MAX__ 0xffffffffU__INTPTR_MAX__ 0x7fffffffINT64_C(c) __INT64_C(c)__GCC_IEC_559_COMPLEX 0PERIPH_BASE (0x40000000U)USART_MODE_RX USART_CR1_REWCHAR_MAX __WCHAR_MAX____FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX__USART_ICR_WUCF (1 << 20)USART_CR3_DMAT (1 << 7)USART_CR3_IRLP (1 << 2)__UINT_LEAST8_TYPE__ unsigned char__ACCUM_FBIT__ 15PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)__UACCUM_IBIT__ 16long intUINT8_MAXIWDG_BASE (PERIPH_BASE_APB1 + 0x3000)SIZE_MAX __SIZE_MAX____INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17UART4_TDR USART_TDR(UART4_BASE)__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1__FLT32X_EPSILON__ 2.2204460492503131e-16F32xNVIC_BASE (SCS_BASE + 0x0100)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32LIBOPENCM3_USART_COMMON_ALL_H USART2_BASE (PERIPH_BASE_APB1 + 0x4400)__UINTMAX_C(c) c ## ULL__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed char__GCC_ATOMIC_BOOL_LOCK_FREE 2BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON____FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX____THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLR__FLT64_DECIMAL_DIG__ 17USART1_CR2 USART_CR2(USART1_BASE)short unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)BIT7 (1<<7)BIT17 (1<<17)__FLT32X_MIN_10_EXP__ (-307)UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)__DBL_IS_IEC_60559__ 2__UINT_FAST32_MAX__ 0xffffffffU__DEC_EVAL_METHOD__ 2__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4I2C3_BASE (PERIPH_BASE_APB1 + 0x5c00)USART_CR2_STOPBITS_2 (0x02 << 12)USART_CR2_ABREN (1 << 20)USART_MODE_TX USART_CR1_TEUSART_CR2_CPHA (1 << 9)__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32USART_PARITY_EVEN USART_CR1_PCEDMA1_BASE (PERIPH_BASE_AHB1 + 0x0000)USART_ISR_RWU (1 << 19)GNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsBIT27 (1<<27)TIM1_BASE (PERIPH_BASE_APB2 + 0x2C00)__LFRACT_MAX__ 0X7FFFFFFFP-31LRUSART_CR1_TCIE (1 << 6)__UTA_FBIT__ 64usart__FLT_DECIMAL_DIG__ 9__thumb__ 1__INT_LEAST32_MAX__ 0x7fffffffLLIBOPENCM3_MEMORYMAP_COMMON_H signed charINT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)INT32_C(c) __INT32_C(c)__GNUC_STDC_INLINE__ 1usart_recv__FRACT_FBIT__ 15__LLACCUM_EPSILON__ 0x1P-31LLK__GNUC_PATCHLEVEL__ 1__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2PTRDIFF_MIN__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)UINTPTR_MAX __UINTPTR_MAX____ARM_ARCH_PROFILE 77GPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000)__FLT64_MAX_10_EXP__ 308GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400)MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINSDMMC1_BASE (PERIPH_BASE_APB2 + 0x2800)__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)__FRACT_MAX__ 0X7FFFP-15RTIM3_BASE (PERIPH_BASE_APB1 + 0x0400)INT_LEAST32_MAX __INT_LEAST32_MAX__USART_ICR_IDLECF (1 << 4)__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5USART_CR3_SCARCNT_MASK 0x7USART_CR1_DEDT (0x1F << USART_CR1_DEDT_SHIFT)USART2_CR3 USART_CR3(USART2_BASE)__UINT16_MAX__ 0xffffUSART_STOPBITS_1 USART_CR2_STOPBITS_1__TQ_FBIT__ 127USART_CR3_WUFIE (1 << 22)USART_TDR_MASK (0x1FF << 0)__USQ_FBIT__ 32USART_CR1(usart_base) MMIO32((usart_base) + 0x00)__USES_INITFINI__ 1USART_ISR_CTSIF (1 << 9)USART_RQR(usart_base) MMIO32((usart_base) + 0x18)__thumb2__ 1__ULLACCUM_FBIT__ 32FMC_QUADSPI_BASE (0xA0000000U)_BoolUART5_CR2 USART_CR2(UART5_BASE)__STRICT_ANSI__ 1usart_enable_tx_inversionFMC3_BANK_BASE (0x80000000U)valueUINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__USART_CR2_ADD_VAL(x) ((x) << USART_CR2_ADD_SHIFT)__USA_IBIT__ 16__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1PTRDIFF_MIN (-PTRDIFF_MAX - 1)USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6c00)__UINT_FAST64_TYPE__ long long unsigned intDESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 0x14)DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7590)__FLT_MIN__ 1.1754943508222875e-38F__HA_FBIT__ 7__FDPIC____UFRACT_MIN__ 0.0UR__FLT32_IS_IEC_60559__ 2USART_CR3_WUS_START_BIT (0x2 << 20)GPIO_PORT_G_BASE (PERIPH_BASE_AHB2 + 0x1800)INT_FAST64_MIN__USFRACT_IBIT__ 0__INT32_C(c) c ## L__LDBL_EPSILON__ 2.2204460492503131e-16LUSART_CR2(usart_base) MMIO32((usart_base) + 0x04)USART_CR3_SCEN (1 << 5)__USFRACT_MIN__ 0.0UHRTSC_BASE (PERIPH_BASE_AHB1 + 0x4000)__ARM_NEON__UINT8_MAX__ 0xffUSART3_CR3 USART_CR3(USART3_BASE)__LDBL_MAX_EXP__ 1024LIBOPENCM3_MEMORYMAP_H USART_FLAG_ORE USART_ISR_OREUSART1_ICR USART_ICR(USART1_BASE)__DBL_HAS_DENORM__ 1DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)USART_ISR_RTOF (1 << 11)USART_FLAG_TC USART_ISR_TCUSART1_BRR USART_BRR(USART1_BASE)QUADSPI_BASE (0xa0001000U)__DA_FBIT__ 31__GXX_ABI_VERSION 1017GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0c00)__INT_LEAST16_MAX__ 0x7fffUSART_ISR_ABRE (1 << 14)__FLT_DENORM_MIN__ 1.4012984643248171e-45FUSART_FLAG_PE USART_ISR_PE__ULLACCUM_EPSILON__ 0x1P-32ULLKINT_LEAST8_MAX __INT_LEAST8_MAX__USART_FLAG_NF USART_ISR_NF__UINT32_C(c) c ## ULUSART_CR2_CLKEN (1 << 11)USART_CR1_UE (1 << 0)__UACCUM_MIN__ 0.0UK__FLT_EPSILON__ 1.1920928955078125e-7FUSART_CR3_WUS_ADDRMATCH (0x0 << 20)USART_ISR_ABRF (1 << 15)TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)USART_CR2_ADD (0xFF << USART_CR2_ADD_SHIFT)__ARM_ARCH_ISA_THUMBUSART_ISR_CMF (1 << 17)USART_STOPBITS_0_5 USART_CR2_STOPBITS_0_5__ARM_FEATURE_MATMUL_INT8__UINT8_TYPE__ unsigned charLIBOPENCM3_CM3_MEMORYMAP_H __GCC_ATOMIC_SHORT_LOCK_FREE 2usart_enable_rx_timeout_interrupt__USACCUM_FBIT__ 8__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1USART_ISR_REACK (1 << 22)__LACCUM_FBIT__ 31SCS_BASE (PPBI_BASE + 0xE000)USART_CR3_OVRDIS (1 << 12)usart_disable_data_inversion__FLT32_HAS_QUIET_NAN__ 1I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)USART_CR1_RE (1 << 2)USART_ISR_TXE (1 << 7)__LDBL_HAS_INFINITY__ 1__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))__FLT32X_MAX_10_EXP__ 308USART_ISR_TC (1 << 6)DWT_BASE (PPBI_BASE + 0x1000)bool _BoolUINTMAX_MAX __UINTMAX_MAX____SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffUSART_CR2_LINEN (1 << 14)BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)USART_CR1_MME (1 << 13)INT16_MAX __INT16_MAX____FP_FAST_FMAF 1USART_CR3_DEM (1 << 14)__FLT32X_IS_IEC_60559__ 2USART_RQR_ABKRQ (1 << 0)PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))FIREWALL_BASE (PERIPH_BASE_APB2 + 0x1C00)__INT_LEAST16_WIDTH__ 16SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)__ARM_FEATURE_FP16_FMLINT16_MIN (-INT16_MAX - 1)__USFRACT_EPSILON__ 0x1P-8UHR__WINT_MAX__ 0xffffffffU__USFRACT_FBIT__ 8CORESIGHT_LSR_SLI (1<<0)USART1 USART1_BASEUSART_CR2_ABRMOD_SHIFT 21__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX____UINT32_MAX__ 0xffffffffULUSART_RTOR_RTO_VAL(x) ((x) << USART_RTOR_RTO_SHIFT)__INT_LEAST8_MAX__ 0x7f__GCC_ATOMIC_POINTER_LOCK_FREE 2__ARM_FEATURE_QBIT 1__ARM_FEATURE_CLZ 1__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXUSART_CR3_WUS_RXNE (0x3 << 20)usart_enable_rx_inversion__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024USART3 USART3_BASEUSART_CR1_PS (1 << 9)__UINT_LEAST32_MAX__ 0xffffffffUL__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1__ACCUM_MAX__ 0X7FFFFFFFP-15K__INT8_MAX__ 0x7fUART5_RDR USART_RDR(UART5_BASE)BIT14 (1<<14)__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16__SHRT_WIDTH__ 16BIT20 (1<<20)__ARM_FEATURE_MVEUSART_ICR_LBDCF (1 << 8)USART_CR2_LBDIE (1 << 6)__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intUSART_CR2_CPOL (1 << 10)USART_GTPR_GT (0xFF << USART_GTPR_GT_SHIFT)USART1_CR3 USART_CR3(USART1_BASE)SWPMI1_BASE (PERIPH_BASE_APB1 + 0x8800)SAI1_BASE (PERIPH_BASE_APB2 + 0x5400)INT_FAST32_MINUART5_CR3 USART_CR3(UART5_BASE)__FLT_EVAL_METHOD_TS_18661_3__ 0__SCHAR_WIDTH__ 8BIT18 (1<<18)COMP_BASE (PERIPH_BASE_APB2 + 0x0200)__UINT_FAST8_TYPE__ unsigned int__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RBIT24 (1<<24)__INT32_MAX__ 0x7fffffffL__INT64_C(c) c ## LLUINTMAX_MAXBIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__APCS_32__ 1__ARM_FEATURE_BF16_VECTOR_ARITHMETICINFO_BASE (0x1fff0000U)PPBI_BASE (0xE0000000U)__FLT32_MANT_DIG__ 24INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN__INT8_MAX __INT8_MAX__BIT28 (1<<28)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2INTMAX_C(c) __INTMAX_C(c)__DBL_MAX_EXP__ 1024__ATOMIC_RELEASE 3UINT_FAST8_MAX__FLT_MANT_DIG__ 24USART_CR1_RTOIE (1 << 26)__UDQ_IBIT__ 0__INT_LEAST32_TYPE__ long int__OPTIMIZE_SIZE__ 1__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UK__FLT64_NORM_MAX__ 1.7976931348623157e+308F64UINTPTR_MAXLIBOPENCM3_USART_H __LDBL_DENORM_MIN__ 4.9406564584124654e-324L__INT64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_SAT 1USART_CR3_DMAR (1 << 6)__ULLFRACT_IBIT__ 0USART_FLAG_FE USART_ISR_FEMMIO16(addr) (*(volatile uint16_t *)(addr))USART_CR3_EIE (1 << 0)USART_FLOWCONTROL_NONE 0x00AES_BASE (0x50000000U + 0x60000)USART_RDR(usart_base) MMIO32((usart_base) + 0x24)DAC_BASE (PERIPH_BASE_APB1 + 0x7400)__GNUC__ 12BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)WCHAR_MAX__LONG_WIDTH__ 32UART5_RQR USART_RQR(UART5_BASE)__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0UUART5_BASE (PERIPH_BASE_APB1 + 0x5000)__UQQ_IBIT__ 0CORESIGHT_LSR_OFFSET 0xfb4__GCC_ATOMIC_LONG_LOCK_FREE 2__ULACCUM_MIN__ 0.0ULK__LDBL_MAX__ 1.7976931348623157e+308L__ARM_ARCH 7__FLT_RADIX__ 2BIT3 (1<<3)long long intCORESIGHT_LAR_KEY 0xC5ACCE55UART5_BRR USART_BRR(UART5_BASE)__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAX__LDBL_HAS_QUIET_NAN__ 1__LONG_LONG_WIDTH__ 64BIT6 (1<<6)USART1_RDR USART_RDR(USART1_BASE)__UINT_FAST64_MAX__ 0xffffffffffffffffULL__ARM_FP__HA_IBIT__ 8__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1BIT9 (1<<9)__FLT32X_MIN__ 2.2250738585072014e-308F32xUART4_RQR USART_RQR(UART4_BASE)INTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024UINT16_MAXPERIPH_BASE_AHB2 (0x48000000U)__FLT64_MIN__ 2.2250738585072014e-308F64__INTMAX_C(c) c ## LLUSART_CR1_CMIE (1 << 14)__ARM_ARCH_PROFILE__INT64_TYPE__ long long int__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4USART_ISR_NF (1 << 2)UART4_BRR USART_BRR(UART4_BASE)USART_ICR_NCF (1 << 2)CRS_BASE (PERIPH_BASE_APB1 + 0x6000)__UFRACT_MAX__ 0XFFFFP-16URINT64_MAXFPB_BASE (PPBI_BASE + 0x2000)INT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0USART_STOPBITS_1_5 USART_CR2_STOPBITS_1_5STIR_BASE (SCS_BASE + 0x0F00)__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__ID_BASE (SCS_BASE + 0x0FD0)SYS_TICK_BASE (SCS_BASE + 0x0010)usart_enable_rx_timeoutUSART_ISR_PE (1 << 0)__UFRACT_FBIT__ 16FMC_BASE (0xa0000000U)__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)USART_CR2_STOPBITS_1 (0x00 << 12)__LDBL_MAX_10_EXP__ 308LPUART1 LPUART1_BASEUSART_RQR_MMRQ (1 << 2)UART5_ICR USART_ICR(UART5_BASE)__INT_FAST32_TYPE__ int../common/usart_common_v2.cunsigned int__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1USART_FLAG_RXNE USART_ISR_RXNEUSART2_CR1 USART_CR1(USART2_BASE)__USACCUM_IBIT__ 8ITM_BASE (PPBI_BASE + 0x0000)ST_VREFINT_CAL MMIO16((INFO_BASE + 0x75aa))__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UKUSART_MODE_TX_RX (USART_CR1_RE | USART_CR1_TE)__UTA_IBIT__ 64USART_CR2_ABRMOD_STARTBIT (0x0 << USART_CR2_ABRMOD_SHIFT)__FLT_EVAL_METHOD__ 0USART_CR2_ABRMOD_MASK 3__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32DFSDM_BASE (PERIPH_BASE_APB2 + 0x6000)RCC_BASE (PERIPH_BASE_AHB1 + 0x1000)__ARM_FEATURE_LDREXUSART_RQR_TXFRQ (1 << 4)__UQQ_FBIT__ 8INT16_Cflag__ARM_FP16_ARGS__GCC_IEC_559 0INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX__UART4_ICR USART_ICR(UART4_BASE)usart_disable_rx_inversion__SIZEOF_PTRDIFF_T__ 4__STDC__ 1__ARM_FEATURE_IDIV 1__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__DBGMCU_BASE (PPBI_BASE + 0x00042000)__ARM_FEATURE_COPROC 15usart_disable_rx_timeout__GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"INT8_MINPERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)USART_RTOR_BLEN_VAL(x) ((x) << USART_RTOR_BLEN_SHIFT)__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)UART4_RTOR USART_RTOR(UART4_BASE)USART_ISR_TEACK (1 << 21)__LDBL_MIN_10_EXP__ (-307)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1USART_CR2_ABRMOD_FRAME_0x55 (0x3 << USART_CR2_ABRMOD_SHIFT)__GCC_ATOMIC_CHAR_LOCK_FREE 2USART_CR1_OVER8 (1 << 15)__LFRACT_EPSILON__ 0x1P-31LRFMC1_BANK_BASE (0x60000000U)STM32L4 1USART_CR1_M1 (1 << 28)__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX____FLT32X_NORM_MAX__ 1.7976931348623157e+308F32xUSART3_CR1 USART_CR1(USART3_BASE)__arm__ 1USART2_RQR USART_RQR(USART2_BASE)__FLT32_MIN_10_EXP__ (-37)MMIO64(addr) (*(volatile uint64_t *)(addr))__ARM_FP16_FORMAT_ALTERNATIVEUSART_CR3_RTSE (1 << 8)__LDBL_NORM_MAX__ 1.7976931348623157e+308LINTPTR_MINDESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)USART_FLOWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)__TA_IBIT__ 64UART4_ISR USART_ISR(UART4_BASE)__ARM_FEATURE_QRDMXUART5_ISR USART_ISR(UART5_BASE)__ARM_ARCH_ISA_THUMB 2USART_ISR_SBKF (1 << 18)USART_ICR_FECF (1 << 1)__LONG_LONG_MAX__ 0x7fffffffffffffffLL__WINT_WIDTH__ 32SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__USART_CR2_MSBFIRST (1 << 19)UART4_RDR USART_RDR(UART4_BASE)__USQ_IBIT__ 0USART_CR3(usart_base) MMIO32((usart_base) + 0x08)BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1USART_GTPR_GT_VAL(x) ((x) << USART_GTPR_GT_SHIFT)_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN____SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__DBL_MIN_EXP__ (-1021)__LDBL_HAS_DENORM__ 1USART_CR1_TE (1 << 3)USART2_ICR USART_ICR(USART2_BASE)INT_FAST32_MIN (-INT_FAST32_MAX - 1)USART_CR3_CTSE (1 << 9)__FLT32_DIG__ 6INT_LEAST16_MAXBIT15 (1<<15)UART5 UART5_BASEUSART_CR1_IDLEIE (1 << 4)VREFBUF_BASE (PERIPH_BASE_APB2 + 0x0030)BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1INT32_MAXUSART_CR3_SCARCNT_DISABLE (0 << USART_CR3_SCARCNT_SHIFT)USART_STOPBITS_2 USART_CR2_STOPBITS_2USART3_RQR USART_RQR(USART3_BASE)__ACCUM_MIN__ (-0X1P15K-0X1P15K)__ARM_FEATURE_CRYPTOUART4_BASE (PERIPH_BASE_APB1 + 0x4c00)USART_CR1_RXNEIE (1 << 5)BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__FRACT_IBIT__ 0USART2_RDR USART_RDR(USART2_BASE)UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234__FLT_NORM_MAX__ 3.4028234663852886e+38FUSART_ICR_CTSCF (1 << 9)long long unsigned intUSART_TDR(usart_base) MMIO32((usart_base) + 0x28)__FLT_MIN_10_EXP__ (-37)GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000)__ULACCUM_IBIT__ 32__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__PTRDIFF_TYPE__ intusart_get_flag__DQ_FBIT__ 63USART_CR2_STOPBITS_1_5 (0x03 << 12)INT_LEAST64_MAX__SACCUM_IBIT__ 8usart_disable_halfduplex__UHQ_IBIT__ 0TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)INT_LEAST8_MINUSART_CR2_RTOEN (1 << 23)BIT29 (1<<29)__INT_FAST16_TYPE__ intINT64_C__ULFRACT_MAX__ 0XFFFFFFFFP-32ULR__UINT_LEAST16_TYPE__ short unsigned intUSART_FLAG_IDLE USART_ISR_IDLEUSART1_TDR USART_TDR(USART1_BASE)__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned int__FLT32X_DIG__ 15USART3_ICR USART_ICR(USART3_BASE)USART_ICR_CMCF (1 << 17)__UTQ_FBIT__ 128USART_CR3_ONEBIT (1 << 11)usart_wait_send_ready__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffffUSART_CR1_PEIE (1 << 8)DMA2_BASE (PERIPH_BASE_AHB1 + 0x0400)PTRDIFF_MAX __PTRDIFF_MAX____SIZEOF_SHORT__ 2USART_CR2_LBDL (1 << 5)UINT_FAST16_MAX__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKUINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRUSART_CR2_ABRMOD_FALL_EDGE (0x1 << USART_CR2_ABRMOD_SHIFT)__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intUSART_ICR_ORECF (1 << 3)USART3_RDR USART_RDR(USART3_BASE)WCHAR_MINUSART_CR2_LBCL (1 << 8)BEGIN_DECLS USART_CR1_M USART_CR1_M0USART_CR2_STOPBITS_SHIFT 12USART_ICR_TCCF (1 << 6)__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__FLT32X_MAX__ 1.7976931348623157e+308F32xGPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400)USART2_RTOR USART_RTOR(USART2_BASE)USART_ISR_CTS (1 << 10)UINT_LEAST8_MAX__ARM_EABI__ 1UART4_CR3 USART_CR3(UART4_BASE)INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1__ARM_FEATURE_DSP 1USART_RQR_SBKRQ (1 << 1)USART2_TDR USART_TDR(USART2_BASE)TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)__QQ_IBIT__ 0USART_ICR_PECF (1 << 0)USART_FLOWCONTROL_RTS USART_CR3_RTSEUSART_CR2_SWAP (1 << 15)__LLACCUM_FBIT__ 31__UINTMAX_TYPE__ long long unsigned int__GNUC_MINOR__ 2__UINT_LEAST32_TYPE__ long unsigned int__ARM_FEATURE_NUMERIC_MAXMINUSART_CR1_TXEIE (1 << 7)__INTMAX_TYPE__ long long intUSART_FLAG_TXE USART_ISR_TXE__GCC_ATOMIC_INT_LOCK_FREE 2TIM16_BASE (PERIPH_BASE_APB2 + 0x4400)INTMAX_MAXUSART_RTOR_RTO_SHIFT 0DESIG_PACKAGE MMIO16((INFO_BASE + 0x7500))__ARM_ARCH_7EM__ 1__ARM_FEATURE_FP16_SCALAR_ARITHMETIC__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1TIM17_BASE (PERIPH_BASE_APB2 + 0x4800)__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CUSART2 USART2_BASEINT64_MIN__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_Cusart_wait_recv_readyUINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRUSART1_GTPR USART_GTPR(USART1_BASE)UART4_CR1 USART_CR1(UART4_BASE)/build/libopencm3/lib/stm32/l4__SIZEOF_SIZE_T__ 4__UINT64_TYPE__ long long unsigned intuint16_tUSART1_BASE (PERIPH_BASE_APB2 + 0x3800)USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x6800)TPIU_BASE (PPBI_BASE + 0x40000)__LDBL_MIN__ 2.2250738585072014e-308LUSART_ICR_RTOCF (1 << 11)__ARM_FEATURE_CDE__ACCUM_IBIT__ 16USART_CR2_DATAINV (1 << 18)CORESIGHT_LAR_OFFSET 0xfb0EXTI_BASE (PERIPH_BASE_APB2 + 0x0400)USART_ISR_FE (1 << 1)USART3_TDR USART_TDR(USART3_BASE)FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000)short intRNG_BASE (0x50000000U + 0x60800)USART_RDR_MASK (0x1FF << 0)usart_disable_rx_timeout_interrupt__UINT16_C(c) cBIT31 (1<<31)__UDA_IBIT__ 32USART_CR1_EOBIE (1 << 27)USART_FLOWCONTROL_CTS USART_CR3_CTSEUINT_LEAST32_MAXBIT2 (1<<2)__ATOMIC_RELAXED 0__ARM_FEATURE_COPROCUSART_ISR(usart_base) MMIO32((usart_base) + 0x1C)__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53USART_CR1_M0 (1 << 12)USART1_CR1 USART_CR1(USART1_BASE)BIT5 (1<<5)BIT1 (1<<1)INT8_CGPIO_PORT_H_BASE (PERIPH_BASE_AHB2 + 0x1c00)INT_LEAST32_MAX__ARM_ARCH_EXT_IDIV__ 1USART_CR3_CTSIE (1 << 10)__DBL_DECIMAL_DIG__ 17BIT8 (1<<8)USART_CR3_IREN (1 << 1)INT16_C(c) __INT16_C(c)UINT32_MAX__INT16_MAX__ 0x7fffUSART3_GTPR USART_GTPR(USART3_BASE)USART_RTOR(usart_base) MMIO32((usart_base) + 0x14)USART2_GTPR USART_GTPR(USART2_BASE)__INT_WIDTH__ 32__ARM_FEATURE_SIMD32 1DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x75e0)__QQ_FBIT__ 7RTC_BASE (PERIPH_BASE_APB1 + 0x2800)__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64LPTIM2_BASE (PERIPH_BASE_APB1 + 0x9400)__ULLACCUM_IBIT__ 32__ULLFRACT_EPSILON__ 0x1P-64ULLRfalse 0__SIZEOF_WINT_T__ 4USART_ISR_IDLE (1 << 4)__ARM_FEATURE_UNALIGNED 1__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17USART_GTPR_PSC (0xFF << USART_GTPR_PSC_SHIFT)__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1USART_BRR(usart_base) MMIO32((usart_base) + 0x0C)__FLT32X_HAS_DENORM__ 1USART_CR2_ADD_SHIFT 24__ULLACCUM_MIN__ 0.0ULLK__INT_FAST32_WIDTH__ 32USART_CR1_DEAT_SHIFT 21__ARM_ASM_SYNTAX_UNIFIED__ 1USART_CR3_NACK (1 << 4)__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODUSART1_RQR USART_RQR(USART1_BASE)UART4_GTPR USART_GTPR(UART4_BASE)__ARM_PCS_VFP 1USART1_ISR USART_ISR(USART1_BASE)__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H LPUART1_BASE (PERIPH_BASE_APB1 + 0x8000)INT_LEAST64_MIN__GCC_CONSTRUCTIVE_SIZE 64__LLFRACT_IBIT__ 0uint32_tUSART2_CR2 USART_CR2(USART2_BASE)BIT12 (1<<12)MPU_BASE (SCS_BASE + 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0x42000000 + (bit) * 4)I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)BIT7 (1<<7)BIT17 (1<<17)__FLT32X_MIN_10_EXP__ (-307)UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)__DBL_IS_IEC_60559__ 2__UINT_FAST32_MAX__ 0xffffffffU__DEC_EVAL_METHOD__ 2__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4WINT_MIN __WINT_MIN____SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32__FLT32X_MIN_EXP__ (-1021)DMA1_BASE (PERIPH_BASE_AHB1 + 0x0000)QUADSPI_CCR_DCYC_SHIFT 18GNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsBIT27 (1<<27)TIM1_BASE (PERIPH_BASE_APB2 + 0x2C00)__UTA_FBIT__ 64INTMAX_C(c) __INTMAX_C(c)__FLT_DECIMAL_DIG__ 9__thumb__ 1__INT_LEAST32_MAX__ 0x7fffffffLLIBOPENCM3_MEMORYMAP_COMMON_H signed charINT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)INT32_C(c) __INT32_C(c)__GNUC_STDC_INLINE__ 1../common/quadspi_common_v1.c__FRACT_FBIT__ 15__LLACCUM_EPSILON__ 0x1P-31LLK__GNUC_PATCHLEVEL__ 1__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2PTRDIFF_MIN__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)UINTPTR_MAX __UINTPTR_MAX____ARM_ARCH_PROFILE 77GPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000)__FLT64_MAX_10_EXP__ 308GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400)MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINSDMMC1_BASE (PERIPH_BASE_APB2 + 0x2800)__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)__FRACT_MAX__ 0X7FFFP-15RTIM3_BASE (PERIPH_BASE_APB1 + 0x0400)INT_LEAST32_MAX __INT_LEAST32_MAX__QUADSPI_BYTE_DR MMIO8(QUADSPI_BASE + 0x20U)__ATOMIC_SEQ_CST 5QUADSPI_CCR_FMODE_SHIFT 26QUADSPI_CR_ABORT (1 << 1)__UINT16_MAX__ 0xffff__TQ_FBIT__ 127__USQ_FBIT__ 32INT_FAST16_MINQUADSPI_CR_FTIE (1 << 18)__thumb2__ 1__ULLACCUM_FBIT__ 32FMC_QUADSPI_BASE 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1)USB_FEAT_ENDPOINT_HALT 0INT32_C(c) __INT32_C(c)__ptr_t void *__GNUC_STDC_INLINE__ 1_REENT_RAND48_ADD(ptr) ((ptr)->_new._reent._r48._add)__FRACT_FBIT__ 15__LLACCUM_EPSILON__ 0x1P-31LLK__GNUC_PATCHLEVEL__ 1__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2__alloc_align(x) __attribute__((__alloc_align__(x)))__UINT_LEAST16_MAX__ 0xffffUINTPTR_MAX __UINTPTR_MAX___REENT_MP_RESULT_K(ptr) ((ptr)->_result_k)__predict_true(exp) __builtin_expect((exp), 1)_STDBOOL_H _REENT_WCSRTOMBS_STATE(ptr) ((ptr)->_new._reent._wcsrtombs_state)USB_CONFIG_ATTR_SELF_POWERED 0x40__FLT64_MAX_10_EXP__ 308MMIO32(addr) (*(volatile uint32_t *)(addr))__SIZEOF_LONG__ 4bcdDeviceusb_interface_descriptor_BSD_SIZE_T_DEFINED_ ___int32_t_defined 1__UINT_FAST32_TYPE__ unsigned int___int_size_t_h bmRequestType__SIZEOF_FLOAT__ 4__SACCUM_IBIT__ 8__GNUCLIKE_MATH_BUILTIN_RELOPS __FLT_MAX_10_EXP__ 38__PMT(args) argsUSB_REQ_GET_INTERFACE 10__FRACT_MAX__ 0X7FFFP-15R__GCC_IEC_559 0__DBL_MIN_10_EXP__ (-307)INT_LEAST32_MAX __INT_LEAST32_MAX___REENT_SMALL_CHECK_INIT(ptr) __INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5_READ_WRITE_RETURN_TYPE int__DEFINED_size_t USB_REQ_SET_CONFIGURATION 9BIT8 (1<<8)__need_wint_tBEGIN_DECLS __sym_default(sym,impl,verid) __asm__(".symver " #impl ", " #sym "@@" #verid)__alloc_size2(n,x) __attribute__((__alloc_size__(n, x)))__UINT16_MAX__ 0xffffusb_config_descriptormax_size__POSIX_VISIBLE 0_HAVE_LONG_DOUBLE 1_Alignas(x) __aligned(x)__GNUCLIKE_BUILTIN_CONSTANT_P 1__thumb2__ 1__ULLACCUM_FBIT__ 32_Bool__DECONST(type,var) ((type)(__uintptr_t)(const void *)(var))__STRICT_ANSI__ 1_SYS_FEATURES_H user_callback_set_configUINT_LEAST8_MAXUINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__LAST_DATA_OUTchar__USA_IBIT__ 16__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1PTRDIFF_MIN (-PTRDIFF_MAX - 1)__hidden __attribute__((__visibility__("hidden")))USB_CONFIG_ATTR_DEFAULT 0x80__UINT_FAST64_TYPE__ long long unsigned intUSB_ENDPOINT_ATTR_ASYNC 0x04_REENT_MBRTOWC_STATE(ptr) ((ptr)->_new._reent._mbrtowc_state)_WINT_T __lock_close(lock) ((void) 0)__FLT_MIN__ 1.1754943508222875e-38F__need_size_t __HA_FBIT__ 7BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)__FDPIC__USB_CONFIG_ATTR_REMOTE_WAKEUP 0x20USB_DT_INTERFACE_SIZE 9__FLT_MAX__ 3.4028234663852886e+38F__FLT32_IS_IEC_60559__ 2__noinline __attribute__ ((__noinline__))_REENT_CHECK_SIGNAL_BUF(ptr) iface_assocINT_FAST64_MIN__USFRACT_IBIT__ 0__weak_symbol __attribute__((__weak__))USB_REQ_SET_DESCRIPTOR 7__USFRACT_MIN__ 0.0UHR__used __attribute__((__used__))UINT16_C__ARM_NEON_REENT_EMERGENCY(ptr) ((ptr)->_emergency)__GNUCLIKE_CTOR_SECTION_HANDLING 1__UINT8_MAX__ 0xff___int16_t_defined 1UINTMAX_C(c) __UINTMAX_C(c)_REENT _impure_ptr__LDBL_MAX_EXP__ 1024USB_REQ_TYPE_VENDOR 0x40__SVID_VISIBLE 0__exported __attribute__((__visibility__("default")))__SCCSID(s) struct __hackBIT7 (1<<7)__DBL_HAS_DENORM__ 1__OPTIMIZE_SIZE__ 1__CC_SUPPORTS___INLINE 1_MB_LEN_MAX 1extra_string_idxcontrol_buffer__GXX_TYPEINFO_EQUALITY_INLINE 0BIT17 (1<<17)USB_ENDPOINT_ATTR_NOSYNC 0x00__GXX_ABI_VERSION 1017__ULACCUM_IBIT__ 32iInterface__FLT_DENORM_MIN__ 1.4012984643248171e-45F__TQ_FBIT__ 127__returns_twice __attribute__((__returns_twice__))__requires_shared(...) __lock_annotate(shared_locks_required(__VA_ARGS__))_END_STD_C bDescriptorType_T_SIZE __UINT32_C(c) c ## UL__UACCUM_MIN__ 0.0UKUINT32_C(c) __UINT32_C(c)_Null_unspecified __FLT_EPSILON__ 1.1920928955078125e-7F__XSTRING(x) __STRING(x)usbd_register_reset_callback__ACCUM_IBIT__ 16USB_DT_ENDPOINT 5UINT32_MAX__PTRDIFF_TYPE__ int__ARM_ARCH_ISA_THUMBUINT32_CUSB_FEAT_TEST_MODE 2__GNUCLIKE_BUILTIN_VARARGS 1__UACCUM_EPSILON__ 0x1P-16UK__ARM_FEATURE_MATMUL_INT8__UINT8_TYPE__ unsigned char_REENT_SIGNGAM(ptr) ((ptr)->_new._reent._gamma_signgam)USB_ENDPOINT_ATTR_ADAPTIVE 0x08__GCC_ATOMIC_SHORT_LOCK_FREE 2__USACCUM_FBIT__ 8_ELIDABLE_INLINE static __inline____NULLABILITY_PRAGMA_POP __MISC_VISIBLE 0__LACCUM_FBIT__ 31USB_ENDPOINT_ATTR_INTERRUPT 0x03__INT_LEAST16_WIDTH__ 16__FLT32_HAS_QUIET_NAN__ 1__OBSOLETE_MATH __OBSOLETE_MATH_DEFAULTUSB_DT_INTERFACE 4__LDBL_HAS_INFINITY__ 1__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))usb_device_descriptor__FLT32X_MAX_10_EXP__ 308USB_TRANSACTION_OUT__ARM_ARCH_EXT_IDIV__ 1bool _Bool__offsetof(type,field) offsetof(type, field)UINTMAX_MAX __UINTMAX_MAX____SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffBIT13 (1<<13)_BSD_WCHAR_T_ _REENT_TM(ptr) (&(ptr)->_new._reent._localtime_buf)INT16_MAX __INT16_MAX____FP_FAST_FMAF 1USB_DT_CONFIGURATION_SIZE 9__FLT32X_IS_IEC_60559__ 2endpointWINT_MINLIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))__UINTPTR_MAX__ 0xffffffffU_REENT_CHECK_EMERGENCY(ptr) USBD_REQ_HANDLED__ARM_FEATURE_FP16_FML__containerof(x,s,m) ({ const volatile __typeof(((s *)0)->m) *__x = (x); __DEQUALIFY(s *, (const volatile char *)__x - __offsetof(s, m));})__restrict restrict__USFRACT_EPSILON__ 0x1P-8UHRNULL ((void *)0)_Thread_local __threadbNumInterfaces___int_least32_t_defined 1__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__need_NULLUINT64_Cinterface__UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX__USB_REQ_TYPE_STANDARD 0x00__UINT32_MAX__ 0xffffffffULiFunctionset_address_before_status_REENT_MBTOWC_STATE(ptr) ((ptr)->_new._reent._mbtowc_state)USB_REQ_CLEAR_FEATURE 1_REENT_MBLEN_STATE(ptr) ((ptr)->_new._reent._mblen_state)__trylocks_shared(...) __lock_annotate(shared_trylock_function(__VA_ARGS__))__INT_LEAST8_MAX__ 0x7f__GCC_ATOMIC_POINTER_LOCK_FREE 2__ARM_FEATURE_QBIT 1__ARM_FEATURE_CLZ 1__ARM_FEATURE_FMA 1__ARM_FEATURE_COMPLEX__ARM_EABI__ 1unsigned signedctrl_buf_len__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024__bounded BIT21 (1<<21)__UINT_LEAST32_MAX__ 0xffffffffUL__DBL_EPSILON__ ((double)2.2204460492503131e-16L)__lock_acquire(lock) ((void) 0)__LFRACT_MIN__ (-0.5LR-0.5LR)__has_feature(x) 0__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1__ACCUM_MAX__ 0X7FFFFFFFP-15K__INT8_MAX__ 0x7fBIT14 (1<<14)UINT_FAST64_MAX__GCC_HAVE_DWARF2_CFI_ASM 1___int8_t_defined 1__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16__UINT_FAST16_TYPE__ unsigned int__SHRT_WIDTH__ 16__GCC_IEC_559_COMPLEX 0__ARM_FEATURE_MVEbMaxPacketSize0__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intUSB_DT_DEVICE_QUALIFIER 6iSerialNumber__attribute_format_strfmon__(a,b) UINT_LEAST16_MAX __UINT_LEAST16_MAX__INT_FAST32_MIN_T_SIZE_ __FLT_EVAL_METHOD_TS_18661_3__ 0__attribute_malloc__ __SCHAR_WIDTH__ 8INT_LEAST16_MAXBIT18 (1<<18)UINT_FAST16_MAX__lock_acquire_recursive(lock) ((void) 0)SIZE_MAX__UINT_FAST8_TYPE__ unsigned int__LLACCUM_IBIT__ 32bNumEndpointsusbd_deviceBIT24 (1<<24)__INT32_MAX__ 0x7fffffffL__min_size(x) static (x)_TIMER_T_ unsigned longUINTMAX_MAXBIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__APCS_32__ 1__ARM_FEATURE_BF16_VECTOR_ARITHMETIC__need_NULL USB_DEV_STATUS_REMOTE_WAKEUP 0x02__FLT32_MANT_DIG__ 24INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32__section(x) __attribute__((__section__(x)))offsetof(TYPE,MEMBER) __builtin_offsetof (TYPE, MEMBER)__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN__usb_interface__USFRACT_FBIT__ 8__LDBL_EPSILON__ 2.2204460492503131e-16LBIT28 (1<<28)__pure2 __attribute__((__const__))__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2INTMAX_C(c) __INTMAX_C(c)__NULLABILITY_PRAGMA_PUSH __DBL_MAX_EXP__ 1024__ATOMIC_RELEASE 3__FLT32X_HAS_DENORM__ 1__FLT_MANT_DIG__ 24_RAND48_SEED_1 (0xabcd)__UDQ_IBIT__ 0ep_read_packet__OPTIMIZE__ 1usbd_register_sof_callback__CC_SUPPORTS___FUNC__ 1__FLT64_NORM_MAX__ 1.7976931348623157e+308F64__GNUCLIKE_MATH_BUILTIN_CONSTANTS __asserts_exclusive(...) __lock_annotate(assert_exclusive_lock(__VA_ARGS__))UINTPTR_MAX_T_PTRDIFF_ __USBSTD_H __LDBL_DENORM_MIN__ 4.9406564584124654e-324L__ULLFRACT_IBIT__ 0__INT64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_SAT 1__FLT32X_MIN_10_EXP__ (-307)_ANSI_STDDEF_H _PTRDIFF_T_ MMIO16(addr) (*(volatile uint16_t *)(addr))USB_ENDPOINT_ADDR_OUT(x) (x)UINT16_C(c) __UINT16_C(c)STALLEDcurrent_config__GNUC__ 12bmAttributesWCHAR_MAX__const const__alloc_size(x) __attribute__((__alloc_size__(x)))__LONG_WIDTH__ 32_T_WCHAR_ INT32_MAX __INT32_MAX____UACCUM_FBIT__ 16__warn_references(sym,msg) __asm__(".section .gnu.warning." #sym); __asm__(".asciz \"" msg "\""); __asm__(".previous")__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0U__UQQ_IBIT__ 0_NEWLIB_VERSION_H__ 1__GCC_ATOMIC_LONG_LOCK_FREE 2_usbd_control_in_ATEXIT_DYNAMIC_ALLOC 1__need_size_t__LDBL_MAX__ 1.7976931348623157e+308L__ARM_ARCH 7_SIZE_T_ USB_REQ_SET_FEATURE 3__FLT_RADIX__ 2BIT3 (1<<3)long long int_REENT_RAND48_MULT(ptr) ((ptr)->_new._reent._r48._mult)BIT29 (1<<29)MIN(a,b) ((a) < (b) ? (a) : (b))__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAX__wchar_t__ __LDBL_HAS_QUIET_NAN__ 1usbd_poll__LONG_LONG_WIDTH__ 64BIT6 (1<<6)_PTRDIFF_T force_nak__UINT_FAST64_MAX__ 0xffffffffffffffffULL__ARM_FP__HA_IBIT__ 8__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1BIT9 (1<<9)__FLT32X_MIN__ 2.2250738585072014e-308F32xINT_FAST8_MIN (-INT_FAST8_MAX - 1)__strftimelike(fmtarg,firstvararg) __attribute__((__format__ (__strftime__, fmtarg, firstvararg)))__FLT64_MAX_EXP__ 1024__WCHAR_T __SYS_CONFIG_H__ __FLT64_MIN__ 2.2250738585072014e-308F64wMaxPacketSize__INT_WIDTH__ 32_HAVE_CC_INHIBIT_LOOP_TO_LIBCALL 1__FLT_MIN_EXP__ (-125)__ARM_ARCH_PROFILE__INT64_TYPE__ long long int__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4set_address__predict_false(exp) __builtin_expect((exp), 0)__unused __attribute__((__unused__))__nonnull_all __attribute__((__nonnull__))_REENT_MBSRTOWCS_STATE(ptr) ((ptr)->_new._reent._mbsrtowcs_state)MAX_USER_CONTROL_CALLBACK 4__UFRACT_MAX__ 0XFFFFP-16UR___int_least64_t_defined 1_Alignof(x) __alignof(x)iManufacturer__THROW UINTMAX_Cuser_control_callbackINT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0_REENT_L64A_BUF(ptr) ((ptr)->_new._reent._l64a_buf)__EXP(x) __ ##x ##__complete__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__usbd_driver_REENT_CHECK_ASCTIME_BUF(ptr) _ANSIDECL_H_ __USER_LABEL_PREFIX__ __UFRACT_FBIT__ 16__ACCUM_EPSILON__ 0x1P-15K__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)__GNUCLIKE_BUILTIN_MEMCPY 1_usbd_control_outUSB_REQ_TYPE_IN 0x80__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)USB_CLASS_VENDOR 0xFF__INT_FAST32_TYPE__ int__SIZEOF_LONG_LONG__ 8unsigned int_SIZE_T_DEFINED_ USB_DT_INTERFACE_ASSOCIATION_SIZE sizeof(struct usb_iface_assoc_descriptor)usb_control_state_SIZET_ __DEC_EVAL_METHOD__ 2usbd_ep_setup__USACCUM_IBIT__ 8__ARM_ARCH_7EM__ 1__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UINTMAX_TYPE__ long long unsigned int_WCHAR_T_DECLARED usbd_register_extra_stringep_stall_setINT_LEAST8_MAX __INT_LEAST8_MAX___SYS_REENT_H_ __FLT_EVAL_METHOD__ 0UINT_FAST32_MAXbInterfaceClass__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32bConfigurationValueUINT64_C(c) __UINT64_C(c)__ARM_FEATURE_LDREX_T_PTRDIFF __UQQ_FBIT__ 8INT16_C__ARM_FP16_ARGS__UACCUM_MAX__ 0XFFFFFFFFP-16UK__FLT32X_DIG__ 15__requires_unlocked(...) __lock_annotate(locks_excluded(__VA_ARGS__))usbd_ep_nak_set__LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4__WCHAR_T__ USB_REQ_TYPE_OUT 0x0___int_least8_t_defined 1__ARM_FEATURE_IDIV 1__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN___GCC_WCHAR_T usbd_ep_stall_setcontrol_buffer_size__unlocks(...) __lock_annotate(unlock_function(__VA_ARGS__))__EXPORT __ARM_FEATURE_COPROC 15__OBSOLETE_MATH_DEFAULT 1_Noreturn __dead2extralenstringiConfigurationbRequest_UNBUF_STREAM_OPT 1__IMPORT _RAND48_SEED_2 (0x1234)poll__USA_FBIT__ 16__volatile volatile_MACHINE__TYPES_H __IEEE_LITTLE_ENDIAN __LDBL_MIN_10_EXP__ (-307)INT64_MAXINT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1__ATFILE_VISIBLE 0__GCC_ATOMIC_CHAR_LOCK_FREE 2control_state__LFRACT_EPSILON__ 0x1P-31LRSTM32L4 1__malloc_like __attribute__((__malloc__))bFunctionSubClassBIT20 (1<<20)__ARM_SIZEOF_MINIMAL_ENUM 1USB_REQ_TYPE_OTHER 0x03_POINTER_INT long__FLT32X_NORM_MAX__ 1.7976931348623157e+308F32x_PTRDIFF_T_DECLARED INT_FAST64_MAXUSB_DT_INTERFACE_POWER 8__FRACT_EPSILON__ 0x1P-15R__FLT32_MIN_10_EXP__ (-37)__RAND_MAX 0x7fffffff__lock_try_acquire(lock) ((void) 0)__STRING(x) #x_WCHAR_T INT8_MAX __INT8_MAX____ARM_FP16_FORMAT_ALTERNATIVEUSB_DT_OTHER_SPEED_CONFIGURATION 7__FBSDID(s) struct __hack_usbd_deviceINTPTR_MIN__DA_FBIT__ 31_MACHINE__DEFAULT_TYPES_H __BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)USB_REQ_TYPE_DEVICE 0x00_GCC_PTRDIFF_T __GNUCLIKE_BUILTIN_NEXT_ARG 1__TA_IBIT__ 64usbd_ep_write_packet__LOCK_INIT(class,lock) static int lock = 0;_SIZE_T _WCHAR_T_H __ARM_FEATURE_QRDMX__ARM_ARCH_ISA_THUMB 2__LONG_LONG_MAX__ 0x7fffffffffffffffLL_FSEEK_OPTIMIZATION 1__WINT_WIDTH__ 32__arg_type_tag(arg_kind,arg_idx,type_tag_idx) _REENT_INIT_PTR(var) { memset((var), 0, sizeof(*(var))); _REENT_INIT_PTR_ZEROED(var); }BIT11 (1<<11)__COPYRIGHT(s) struct __hack__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1_REENT_MBRLEN_STATE(ptr) ((ptr)->_new._reent._mbrlen_state)_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0usbd_request_return_codes__ULACCUM_MIN__ 0.0ULK_STDDEF_H_ INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__DBL_MIN_EXP__ (-1021)__SIZE_T bFunctionClassUSB_DT_INTERFACE_ASSOCIATION 11INT8_MIN (-INT8_MAX - 1)__printf0like(fmtarg,firstvararg) __FLT32_DIG__ 6DATA_IN__dead2 __attribute__((__noreturn__))BIT15 (1<<15)disconnectUSB_REQ_TYPE_ENDPOINT 0x02__EXPusbd_init___int64_t_defined 1__LDBL_HAS_DENORM__ 1__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1INT32_MAX__BEGIN_DECLS __ACCUM_MIN__ (-0X1P15K-0X1P15K)__GNUC_VA_LIST_COMPATIBILITY 1__ARM_FEATURE_CRYPTOINT16_MIN (-INT16_MAX - 1)__INT_LEAST32_TYPE__ long intUSB_REQ_SET_ADDRESS 5UINT_LEAST16_MAXBIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__FRACT_IBIT__ 0__ATOMIC_ACQUIRE 2UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2__NEWLIB_PATCHLEVEL__ 0bLength__ORDER_LITTLE_ENDIAN__ 1234__size_t__FLT_NORM_MAX__ 3.4028234663852886e+38Fuser_callback_set_altsettinglong long unsigned int__FLT_MIN_10_EXP__ (-37)BIT31 (1<<31)wIndex__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__ULLACCUM_EPSILON__ 0x1P-32ULLK_SIZE_T_DEFINED __DQ_FBIT__ 63__GNU_VISIBLE 0INT_LEAST64_MAXuint16_t__PTRDIFF_T __UHQ_IBIT__ 0INT_LEAST8_MIN_REENT_WCTOMB_STATE(ptr) ((ptr)->_new._reent._wctomb_state)usbd_dev__INT_FAST16_TYPE__ intextra__USBD_H __SACCUM_MIN__ (-0X1P7HK-0X1P7HK)__ULFRACT_MAX__ 0XFFFFFFFFP-32ULR__UINT_LEAST16_TYPE__ short unsigned intUINT16_MAX__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned intSTATUS_INusbd_control_complete_callback__signed signedSTATUS_OUTbNumConfigurations_REENT_ASCTIME_BUF(ptr) ((ptr)->_new._reent._asctime_buf)__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffff__have_longlong64 1INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)PTRDIFF_MAX __PTRDIFF_MAX____SIZEOF_SHORT__ 2bFunctionProtocolINT8_MIN__size_t _WCHAR_T_DEFINED idProduct__trylocks_exclusive(...) __lock_annotate(exclusive_trylock_function(__VA_ARGS__))USB_REQ_TYPE_TYPE 0x60ep_write_packetUINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRBIT26 (1<<26)__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long int__always_inline __inline__ __attribute__((__always_inline__))_ATEXIT_SIZE 32USBD_REQ_NOTSUPPidVendor_BSD_SIZE_T_ WCHAR_MIN__no_lock_analysis __lock_annotate(no_thread_safety_analysis)_WCHAR_T_ true 1_REENT_STDIO_STREAM(var,index) &(var)->__sf[index]desc_T_WCHAR _BEGIN_STD_C ../../usb/usb.cusb_iface_assoc_descriptor_TIME_T_ __int_least64_t_CLOCKID_T_ unsigned long_REENT_CHECK_TM(ptr) __arm__ 1__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__INT_WCHAR_T_H __FLT32X_MAX__ 1.7976931348623157e+308F32x_usbd_resetwValue__FLT32_MIN__ 1.1754943508222875e-38F32INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1__ARM_FEATURE_DSP 1WINT_MIN __WINT_MIN__USB_DT_DEVICE_SIZE sizeof(struct usb_device_descriptor)USB_ENDPOINT_ATTR_SYNC 0x0C__QQ_IBIT__ 0__LLACCUM_FBIT__ 31USB_FEAT_DEVICE_REMOTE_WAKEUP 1bInterfaceSubClass__USQ_IBIT__ 0USB_REQ_TYPE_DIRECTION 0x80__lock_release_recursive(lock) ((void) 0)__UINT_LEAST32_TYPE__ long unsigned intinit__ARM_FEATURE_NUMERIC_MAXMIN_RAND48_MULT_1 (0xdeec)__INTMAX_TYPE__ long long intUSB_REQ_TYPE_INTERFACE 0x01__GCC_ATOMIC_INT_LOCK_FREE 2_RAND48_SEED_0 (0x330e)INTMAX_MAXbFirstInterface__ARM_FEATURE_FP16_SCALAR_ARITHMETICUSB_TRANSACTION_SETUP__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1UINT_LEAST32_MAX__FLT64_HAS_QUIET_NAN__ 1__ptrvalue _NOINLINE_STATIC _NOINLINE static__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_C__CC_SUPPORTS_VARADIC_XXX 1INT64_MIN__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intMMIO64(addr) (*(volatile uint64_t *)(addr))bDeviceClass__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRdriverWCHAR_MAX __WCHAR_MAX__/build/libopencm3/lib/stm32/l4__SIZEOF_SIZE_T__ 4__lock_close_recursive(lock) ((void) 0)__UINT64_TYPE__ long long unsigned intusbd_set_altsetting_callback__INT64_C(c) c ## LL_FVWRITE_IN_STREAMIO 1__lockable __lock_annotate(lockable)ep_reset__END_DECLS __generic(expr,t,yes,no) __builtin_choose_expr( __builtin_types_compatible_p(__typeof(expr), t), yes, no)__LONG_MAX__ 0x7fffffffL__ARM_FEATURE_CDEbInterfaceNumberMAX_USER_SET_CONFIG_CALLBACK 4unsignedstallINT_LEAST32_MIN (-INT_LEAST32_MAX - 1)_STRING_H_ short int_STDDEF_H __pt_guarded_by(x) __lock_annotate(pt_guarded_by(x))__guarded_by(x) __lock_annotate(guarded_by(x))__GNUCLIKE___OFFSETOF 1__UINT16_C(c) c__FLT64_MIN_EXP__ (-1021)_REENT_INIT_ATEXIT _NULL, _ATEXIT_INIT,__CC_SUPPORTS___INLINE__ 1__UDA_IBIT__ 32__printflike(fmtarg,firstvararg) __attribute__((__format__ (__printf__, fmtarg, firstvararg)))__USB_PRIVATE_H __fastcall __attribute__((__fastcall__))current_address__lock_annotate(x) BIT2 (1<<2)_REENT_SIGNAL_BUF(ptr) ((ptr)->_new._reent._signal_buf)__ATOMIC_RELAXED 0_ATTRIBUTE(attrs) __attribute__ (attrs)__ARM_FEATURE_COPROC__ATTRIBUTE_IMPURE_PTR__ __DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53BIT5 (1<<5)BIT1 (1<<1)__rangeof(type,start,end) (__offsetof(type, end) - __offsetof(type, start))INT8_CINT_LEAST32_MAX__USES_INITFINI__ 1USB_DEV_STATUS_SELF_POWERED 0x01__lock_init(lock) ((void) 0)__need_ptrdiff_tINTMAX_MAX __INTMAX_MAX____DBL_DECIMAL_DIG__ 17index__have_long32 1_GLOBAL_REENT _global_impure_ptr_NULL 0__flexarr [0]INT16_C(c) __INT16_C(c)__BSD_VISIBLE 0__INT16_MAX__ 0x7fff_WANT_REGISTER_FINI 1__DEVOLATILE(type,var) ((type)(__uintptr_t)(volatile void *)(var))DATA_OUT__sym_compat(sym,impl,verid) __asm__(".symver " #impl ", " #sym "@" #verid)__SSP_FORTIFY_LEVEL 0__ARM_FEATURE_SIMD32 1__XSI_VISIBLE 0INT_FAST32_MIN (-INT_FAST32_MAX - 1)__QQ_FBIT__ 7__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1otgfs_usb_driver stm32f107_usb_driver__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64USB_TRANSACTION_IN__GNUC_PREREQ__(ma,mi) __GNUC_PREREQ(ma, mi)__DEFINED_wchar_t __UTA_IBIT__ 64__ULLACCUM_IBIT__ 32__ARM_FEATURE_CRC32__strong_reference(sym,aliassym) extern __typeof (sym) aliassym __attribute__ ((__alias__ (#sym)))__LDBL_NORM_MAX__ 1.7976931348623157e+308L__ULLFRACT_EPSILON__ 0x1P-64ULLR__unreachable() __builtin_unreachable()__LOCK_INIT_RECURSIVE(class,lock) static int lock = 0;__SIZEOF_WINT_T__ 4__ARM_FEATURE_UNALIGNED 1__STDC__ 1__LDBL_DECIMAL_DIG__ 17USB_REQ_TYPE_RECIPIENT 0x1F__GNUCLIKE_ASM 3__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1__scanflike(fmtarg,firstvararg) __attribute__((__format__ (__scanf__, fmtarg, firstvararg)))_WIDE_ORIENT 1user_callback_reset__ULLACCUM_MIN__ 0.0ULLK_SYS__TYPES_H __INT_FAST32_WIDTH__ 32___int_wchar_t_h _RAND48_MULT_0 (0xe66d)__GNUCLIKE_BUILTIN_VAALIST 1__ARM_ASM_SYNTAX_UNIFIED__ 1_SIZE_T_DECLARED __locks_exclusive(...) __lock_annotate(exclusive_lock_function(__VA_ARGS__))USB_ENDPOINT_ATTR_BULK 0x02__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPROD__Long long_NEWLIB_VERSION "3.3.0"__pure __attribute__((__pure__))__ARM_PCS_VFP 1_GCC_SIZE_T __CC_SUPPORTS_WARNING 1PTRDIFF_MAX__ULLFRACT_MIN__ 0.0ULLRUINT_FAST8_MAX_REENT_MP_P5S(ptr) ((ptr)->_p5s)_REENT_CHECK_RAND48(ptr) INT_LEAST64_MIN__lock_release(lock) ((void) 0)__GCC_CONSTRUCTIVE_SIZE 64_BSD_WCHAR_T___LLFRACT_IBIT__ 0addr__INT16_TYPE__ short int__LLFRACT_MIN__ (-0.5LLR-0.5LLR)uint32_tBIT12 (1<<12)__weak_reference(sym,alias) __asm__(".weak " #alias); __asm__(".equ " #alias ", " #sym)__SACCUM_EPSILON__ 0x1P-7HK__GCC_ASM_FLAG_OUTPUTS__ 1_REENT_CHECK_VERIFY 1__ARM_FP 4__need_wchar_tuser_callback_resumeusbd_control_callback__UHA_IBIT__ 8__need_wint_t bMaxPower__ULACCUM_EPSILON__ 0x1P-32ULK__LDBL_DIG__ 15_Atomic(T) struct { T volatile __val; }__SIZE_WIDTH__ 32SIG_ATOMIC_MAXBIT16 (1<<16)otghs_usb_driver stm32f207_usb_driver__WINT_MIN__ 0U__locks_shared(...) __lock_annotate(shared_lock_function(__VA_ARGS__))__FLT64_DIG__ 15__WINT_MAX__ 0xffffffffUBIT22 (1<<22)__INT_LEAST8_WIDTH__ 8__long_double_t long double__INT_LEAST16_TYPE__ short intusbd_register_suspend_callbackLAST_DATA_IN__DBL_MAX__ ((double)1.7976931348623157e+308L)_REENT_WCRTOMB_STATE(ptr) ((ptr)->_new._reent._wcrtomb_state)short unsigned int__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1__thumb__ 1__LDBL_MAX_10_EXP__ 308INT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1__format_arg(fmtarg) __attribute__((__format_arg__ (fmtarg)))__compiler_membar() __asm __volatile(" " : : : "memory")__HQ_FBIT__ 15__bool_true_false_are_defined 1__datatype_type_tag(kind,type) __RCSID(s) struct __hack__lock_try_acquire_recursive(lock) ((void) 0)__SIZE_MAX__ 0xffffffffU__INT_LEAST16_MAX__ 0x7fffUSB_DT_STRING 3USB_ENDPOINT_ATTR_TYPE 0x03__ARM_ARCH__DEFINED_ptrdiff_t _SYS_CDEFS_H_ BIT25 (1<<25)type_mask__nonnull(x) __attribute__((__nonnull__ x))_RAND48_ADD (0x000b)SIG_ATOMIC_MIN __SIG_ATOMIC_MIN____ARM_FEATURE_LDREX 7INT32_MINUSB_ENDPOINT_ATTR_USAGETYPE 0x30bInterfaceCount__LLFRACT_EPSILON__ 0x1P-63LLR__SFRACT_MAX__ 0X7FP-7HR__FLT32X_MANT_DIG__ 53__WCHAR_WIDTH__ 32WINT_MAX__INT16_C(c) cINT_LEAST16_MINUSB_ENDPOINT_ADDR_IN(x) (0x80 | (x))INT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32_REENT_GETDATE_ERR_P(ptr) (&((ptr)->_new._reent._getdate_err))_ATEXIT_INIT {_NULL, 0, {_NULL}, {{_NULL}, {_NULL}, 0, 0}}USB_DT_ENDPOINT_SIZE 7__DEQUALIFY(type,var) ((type)(__uintptr_t)(const volatile void *)(var))__ATOMIC_ACQ_REL 4BIT4 (1<<4)__HQ_IBIT__ 0__packed __attribute__((__packed__))_WCHAR_T_DEFINED_ _usbd_driverUSB_REQ_SET_INTERFACE 11bEndpointAddress__asserts_shared(...) __lock_annotate(assert_shared_lock(__VA_ARGS__))__SYS_LOCK_H__ __FLT32_NORM_MAX__ 3.4028234663852886e+38F32_REENT_ASCTIME_SIZE 26SIG_ATOMIC_MAX __SIG_ATOMIC_MAX____UINTMAX_MAX__ 0xffffffffffffffffULL__INT_MAX__ 0x7fffffff__DBL_MANT_DIG__ 53__ULFRACT_IBIT__ 0UINT64_MAX __UINT64_MAX__INT_FAST16_MAXuser_callback_suspend__UTQ_FBIT__ 128__INT_LEAST64_TYPE__ long long int_usbd_transaction_REENT_INIT(var) { 0, _REENT_STDIO_STREAM(&(var), 0), _REENT_STDIO_STREAM(&(var), 1), _REENT_STDIO_STREAM(&(var), 2), 0, "", 0, _NULL, 0, _NULL, _NULL, 0, _NULL, _NULL, 0, _NULL, { { 0, _NULL, "", {0, 0, 0, 0, 0, 0, 0, 0, 0}, 0, 1, { {_RAND48_SEED_0, _RAND48_SEED_1, _RAND48_SEED_2}, {_RAND48_MULT_0, _RAND48_MULT_1, _RAND48_MULT_2}, _RAND48_ADD }, {0, {0}}, {0, {0}}, {0, {0}}, "", "", 0, {0, {0}}, {0, {0}}, {0, {0}}, {0, {0}}, {0, {0}} } }, _REENT_INIT_ATEXIT _NULL, {_NULL, 0, _NULL} }ctrl_buf__ARM_FEATURE_CDE_COPROCUSB_REQ_TYPE_CLASS 0x20__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xGCC: (15:12.2.rel1-1) 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0XFFFFP-16UR___int_least64_t_defined 1_Alignof(x) __alignof(x)iManufacturer__THROW UINTMAX_Cuser_control_callbackINT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0_REENT_L64A_BUF(ptr) ((ptr)->_new._reent._l64a_buf)__EXP(x) __ ##x ##__complete__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX___NOTHROW _REENT_CHECK_ASCTIME_BUF(ptr) _ANSIDECL_H_ USB_ENDPOINT_ATTR_SYNCTYPE 0x0C__USER_LABEL_PREFIX__ __UFRACT_FBIT__ 16__ACCUM_EPSILON__ 0x1P-15K__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)__GNUCLIKE_BUILTIN_MEMCPY 1_usbd_control_outUSB_REQ_TYPE_IN 0x80__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)USB_CLASS_VENDOR 0xFF__INT_FAST32_TYPE__ int__SIZEOF_LONG_LONG__ 8unsigned int_SIZE_T_DEFINED_ USB_DT_INTERFACE_ASSOCIATION_SIZE sizeof(struct usb_iface_assoc_descriptor)usb_control_state_SIZET_ __DEC_EVAL_METHOD__ 2__USACCUM_IBIT__ 8__ARM_ARCH_7EM__ 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0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__INT_WCHAR_T_H __FLT32X_MAX__ 1.7976931348623157e+308F32xwValue__ARM_EABI__ 1INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1__ARM_FEATURE_DSP 1WINT_MIN __WINT_MIN__USB_DT_DEVICE_SIZE sizeof(struct usb_device_descriptor)USB_ENDPOINT_ATTR_SYNC 0x0C__QQ_IBIT__ 0__LLACCUM_FBIT__ 31USB_FEAT_DEVICE_REMOTE_WAKEUP 1bInterfaceSubClass__GNUC_MINOR__ 2USB_REQ_TYPE_DIRECTION 0x80__lock_release_recursive(lock) ((void) 0)__UINT_LEAST32_TYPE__ long unsigned intinit__ARM_FEATURE_NUMERIC_MAXMIN_RAND48_MULT_1 (0xdeec)__INTMAX_TYPE__ long long intusbd_register_control_callback__GCC_ATOMIC_INT_LOCK_FREE 2_RAND48_SEED_0 (0x330e)INTMAX_MAXbFirstInterface__ARM_FEATURE_FP16_SCALAR_ARITHMETIC__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1UINT_LEAST32_MAX__FLT64_HAS_QUIET_NAN__ 1__ptrvalue _NOINLINE_STATIC _NOINLINE static__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CINT64_MIN__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intMMIO64(addr) (*(volatile uint64_t *)(addr))bDeviceClass__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRdriverWCHAR_MAX __WCHAR_MAX__/build/libopencm3/lib/stm32/l4__SIZEOF_SIZE_T__ 4__lock_close_recursive(lock) ((void) 0)__UINT64_TYPE__ long long unsigned intusbd_set_altsetting_callback__INT64_C(c) c ## LLINT8_MAX __INT8_MAX___FVWRITE_IN_STREAMIO 1__lockable __lock_annotate(lockable)ep_reset__END_DECLS __generic(expr,t,yes,no) __builtin_choose_expr( __builtin_types_compatible_p(__typeof(expr), t), yes, no)__LONG_MAX__ 0x7fffffffL__ARM_FEATURE_CDEbInterfaceNumberMAX_USER_SET_CONFIG_CALLBACK 4unsignedINT_LEAST32_MIN (-INT_LEAST32_MAX - 1)short int_STDDEF_H __pt_guarded_by(x) __lock_annotate(pt_guarded_by(x))__guarded_by(x) __lock_annotate(guarded_by(x))__GNUCLIKE___OFFSETOF 1__UINT16_C(c) c__FLT64_MIN_EXP__ (-1021)_REENT_INIT_ATEXIT _NULL, _ATEXIT_INIT,__CC_SUPPORTS___INLINE__ 1__UDA_IBIT__ 32__printflike(fmtarg,firstvararg) __attribute__((__format__ (__printf__, fmtarg, firstvararg)))__USB_PRIVATE_H __fastcall __attribute__((__fastcall__))current_address__lock_annotate(x) BIT2 (1<<2)_REENT_SIGNAL_BUF(ptr) ((ptr)->_new._reent._signal_buf)__ATOMIC_RELAXED 0_ATTRIBUTE(attrs) __attribute__ (attrs)__ARM_FEATURE_COPROC__ATTRIBUTE_IMPURE_PTR__ __DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53BIT5 (1<<5)BIT1 (1<<1)__rangeof(type,start,end) (__offsetof(type, end) - __offsetof(type, start))__dead2 __attribute__((__noreturn__))INT_LEAST32_MAX__USES_INITFINI__ 1USB_DEV_STATUS_SELF_POWERED 0x01__lock_init(lock) ((void) 0)__need_ptrdiff_tINTMAX_MAX __INTMAX_MAX____DBL_DECIMAL_DIG__ 17__have_long32 1_GLOBAL_REENT _global_impure_ptr_NULL 0__flexarr [0]INT16_C(c) __INT16_C(c)UINT32_MAX__INT16_MAX__ 0x7fff_WANT_REGISTER_FINI 1__DEVOLATILE(type,var) ((type)(__uintptr_t)(volatile void *)(var))DATA_OUT__sym_compat(sym,impl,verid) __asm__(".symver " #impl ", " #sym "@" #verid)__SSP_FORTIFY_LEVEL 0__ARM_FEATURE_SIMD32 1__XSI_VISIBLE 0_STDLIB_H_ INT_FAST32_MIN (-INT_FAST32_MAX - 1)__QQ_FBIT__ 7__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1otgfs_usb_driver stm32f107_usb_driver__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64__GNUC_PREREQ__(ma,mi) __GNUC_PREREQ(ma, mi)__DEFINED_wchar_t __UTA_IBIT__ 64__ULLACCUM_IBIT__ 32__ARM_FEATURE_CRC32__strong_reference(sym,aliassym) extern __typeof (sym) aliassym __attribute__ ((__alias__ (#sym)))__LDBL_NORM_MAX__ 1.7976931348623157e+308L__ULLFRACT_EPSILON__ 0x1P-64ULLR__unreachable() __builtin_unreachable()__LOCK_INIT_RECURSIVE(class,lock) static int lock = 0;__SIZEOF_WINT_T__ 4__ARM_FEATURE_UNALIGNED 1__STDC__ 1__LDBL_DECIMAL_DIG__ 17USB_REQ_TYPE_RECIPIENT 0x1Fusb_control_send_chunk__GNUCLIKE_ASM 3__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1__scanflike(fmtarg,firstvararg) __attribute__((__format__ (__scanf__, fmtarg, firstvararg)))_WIDE_ORIENT 1user_callback_reset__ULLACCUM_MIN__ 0.0ULLK_SYS__TYPES_H __INT_FAST32_WIDTH__ 32___int_wchar_t_h _RAND48_MULT_0 (0xe66d)__GNUCLIKE_BUILTIN_VAALIST 1__ARM_ASM_SYNTAX_UNIFIED__ 1__locks_exclusive(...) __lock_annotate(exclusive_lock_function(__VA_ARGS__))USB_ENDPOINT_ATTR_BULK 0x02__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPROD__Long long_NEWLIB_VERSION "3.3.0"__pure __attribute__((__pure__))__ARM_PCS_VFP 1_GCC_SIZE_T __CC_SUPPORTS_WARNING 1PTRDIFF_MAX__ULLFRACT_MIN__ 0.0ULLRUINT_FAST8_MAX_REENT_MP_P5S(ptr) ((ptr)->_p5s)_REENT_CHECK_RAND48(ptr) INT_LEAST64_MIN__lock_release(lock) ((void) 0)__GCC_CONSTRUCTIVE_SIZE 64_BSD_WCHAR_T___LLFRACT_IBIT__ 0__CC_SUPPORTS_VARADIC_XXX 1__INT16_TYPE__ short int__LLFRACT_MIN__ (-0.5LLR-0.5LLR)uint32_tBIT12 (1<<12)__weak_reference(sym,alias) __asm__(".weak " #alias); __asm__(".equ " #alias ", " #sym)__SACCUM_EPSILON__ 0x1P-7HK__GCC_ASM_FLAG_OUTPUTS__ 1_REENT_CHECK_VERIFY 1__ARM_FP 4__need_wchar_tuser_callback_resumeusbd_control_callback__UHA_IBIT__ 8__need_wint_t bMaxPower__ULACCUM_EPSILON__ 0x1P-32ULK__LDBL_DIG__ 15EXIT_SUCCESS 0_Atomic(T) struct { T volatile __val; }__SIZE_WIDTH__ 32SIG_ATOMIC_MAXBIT16 (1<<16)otghs_usb_driver stm32f207_usb_driver__WINT_MIN__ 0UINT_LEAST16_MIN__FLT64_DIG__ 15__WINT_MAX__ 0xffffffffUBIT22 (1<<22)__INT_LEAST8_WIDTH__ 8__long_double_t long double__INT_LEAST16_TYPE__ short intLAST_DATA_IN__DBL_MAX__ ((double)1.7976931348623157e+308L)_REENT_WCRTOMB_STATE(ptr) ((ptr)->_new._reent._wcrtomb_state)short unsigned int__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1__thumb__ 1__LDBL_MAX_10_EXP__ 308INT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1__format_arg(fmtarg) __attribute__((__format_arg__ (fmtarg)))__compiler_membar() __asm __volatile(" " : : : "memory")__HQ_FBIT__ 15__bool_true_false_are_defined 1__datatype_type_tag(kind,type) __RCSID(s) struct __hack__lock_try_acquire_recursive(lock) ((void) 0)__SIZE_MAX__ 0xffffffffU__INT_LEAST16_MAX__ 0x7fffUSB_DT_STRING 3USB_ENDPOINT_ATTR_TYPE 0x03__ARM_ARCH__DEFINED_ptrdiff_t _SYS_CDEFS_H_ BIT25 (1<<25)type_mask__DA_FBIT__ 31_RAND48_ADD (0x000b)EXIT_FAILURE 1SIG_ATOMIC_MIN __SIG_ATOMIC_MIN____ARM_FEATURE_LDREX 7INT32_MINUSB_ENDPOINT_ATTR_USAGETYPE 0x30bInterfaceCount__LLFRACT_EPSILON__ 0x1P-63LLR__SFRACT_MAX__ 0X7FP-7HR__FLT32X_MANT_DIG__ 53__WCHAR_WIDTH__ 32usb_control_setup_readWINT_MAX__INT16_C(c) cUSB_ENDPOINT_ADDR_IN(x) (0x80 | (x))INT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32_REENT_GETDATE_ERR_P(ptr) (&((ptr)->_new._reent._getdate_err))_ATEXIT_INIT {_NULL, 0, {_NULL}, {{_NULL}, {_NULL}, 0, 0}}USB_DT_ENDPOINT_SIZE 7__DEQUALIFY(type,var) ((type)(__uintptr_t)(const volatile void *)(var))__ATOMIC_ACQ_REL 4BIT4 (1<<4)__HQ_IBIT__ 0__packed __attribute__((__packed__))_WCHAR_T_DEFINED_ _usbd_driverUSB_REQ_SET_INTERFACE 11bEndpointAddress__asserts_shared(...) __lock_annotate(assert_shared_lock(__VA_ARGS__))__SYS_LOCK_H__ __FLT32_NORM_MAX__ 3.4028234663852886e+38F32_REENT_ASCTIME_SIZE 26SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__PTRDIFF_MIN (-PTRDIFF_MAX - 1)__UINTMAX_MAX__ 0xffffffffffffffffULL__DBL_MANT_DIG__ 53__ULFRACT_IBIT__ 0UINT64_MAX __UINT64_MAX__INT_FAST16_MAXuser_callback_suspend__INT_MAX__ 0x7fffffff__INT_LEAST64_TYPE__ long long int_REENT_INIT(var) { 0, _REENT_STDIO_STREAM(&(var), 0), _REENT_STDIO_STREAM(&(var), 1), _REENT_STDIO_STREAM(&(var), 2), 0, "", 0, _NULL, 0, _NULL, _NULL, 0, _NULL, _NULL, 0, _NULL, { { 0, _NULL, "", {0, 0, 0, 0, 0, 0, 0, 0, 0}, 0, 1, { {_RAND48_SEED_0, _RAND48_SEED_1, _RAND48_SEED_2}, {_RAND48_MULT_0, _RAND48_MULT_1, _RAND48_MULT_2}, _RAND48_ADD }, {0, {0}}, {0, {0}}, {0, {0}}, "", "", 0, {0, {0}}, {0, {0}}, {0, {0}}, {0, {0}}, {0, {0}} } }, _REENT_INIT_ATEXIT _NULL, {_NULL, 0, _NULL} }ctrl_buf__ARM_FEATURE_CDE_COPROCUSB_REQ_TYPE_CLASS 0x20__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xGCC: (15:12.2.rel1-1) 12.2.1 20221205˙˙˙˙| NA„Ž8`B0„ …†‡‰Š‹ŽR $BÎËĘÉČÇĆĹÄBV$A„Ž<A„…†Ž(fA„…Ž` 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1)INT32_C(c) __INT32_C(c)__ptr_t void *__GNUC_STDC_INLINE__ 1_REENT_RAND48_ADD(ptr) ((ptr)->_new._reent._r48._add)__FRACT_FBIT__ 15__LLACCUM_EPSILON__ 0x1P-31LLK__GNUC_PATCHLEVEL__ 1__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2__alloc_align(x) __attribute__((__alloc_align__(x)))__UINT_LEAST16_MAX__ 0xffffUINTPTR_MAX __UINTPTR_MAX___REENT_MP_RESULT_K(ptr) ((ptr)->_result_k)__predict_true(exp) __builtin_expect((exp), 1)_STDBOOL_H _REENT_WCSRTOMBS_STATE(ptr) ((ptr)->_new._reent._wcsrtombs_state)USB_CONFIG_ATTR_SELF_POWERED 0x40__FLT_DIG__ 6MMIO32(addr) (*(volatile uint32_t *)(addr))__SIZEOF_LONG__ 4bcdDeviceusbd_ep_stall_getusb_interface_descriptor_BSD_SIZE_T_DEFINED_ ___int32_t_defined 1__UINT_FAST32_TYPE__ unsigned int___int_size_t_h bmRequestType__SIZEOF_FLOAT__ 4__SACCUM_IBIT__ 8__GNUCLIKE_MATH_BUILTIN_RELOPS __FLT_MAX_10_EXP__ 38__PMT(args) argsUSB_REQ_GET_INTERFACE 10__FRACT_MAX__ 0X7FFFP-15R__GCC_IEC_559 0__DBL_MIN_10_EXP__ (-307)INT_LEAST32_MAX __INT_LEAST32_MAX___REENT_SMALL_CHECK_INIT(ptr) __INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5_READ_WRITE_RETURN_TYPE int__DEFINED_size_t USB_REQ_SET_CONFIGURATION 9BIT8 (1<<8)__need_wint_tBEGIN_DECLS __sym_default(sym,impl,verid) __asm__(".symver " #impl ", " #sym "@@" #verid)__alloc_size2(n,x) __attribute__((__alloc_size__(n, x)))__UINT16_MAX__ 0xffffusb_config_descriptor__TQ_FBIT__ 127__SHRT_MAX__ 0x7fff__POSIX_VISIBLE 0_HAVE_LONG_DOUBLE 1build_config_descriptor_Alignas(x) __aligned(x)__thumb2__ 1__ULLACCUM_FBIT__ 32_Bool_REENT_CHECK_ASCTIME_BUF(ptr) __STRICT_ANSI__ 1_SYS_FEATURES_H user_callback_set_configUINT_LEAST8_MAXUINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__LAST_DATA_OUTchar__USA_IBIT__ 16__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1PTRDIFF_MIN (-PTRDIFF_MAX - 1)__hidden __attribute__((__visibility__("hidden")))USB_CONFIG_ATTR_DEFAULT 0x80__DBL_IS_IEC_60559__ 2__UINT_FAST64_TYPE__ long long unsigned intUSB_ENDPOINT_ATTR_ASYNC 0x04_REENT_MBRTOWC_STATE(ptr) ((ptr)->_new._reent._mbrtowc_state)_WINT_T __lock_close(lock) ((void) 0)__FLT_MIN__ 1.1754943508222875e-38F__need_size_t __HA_FBIT__ 7BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)__FDPIC__USB_CONFIG_ATTR_REMOTE_WAKEUP 0x20USB_DT_INTERFACE_SIZE 9USB_DT_OTHER_SPEED_CONFIGURATION 7__FLT32_IS_IEC_60559__ 2__noinline __attribute__ ((__noinline__))UINT64_C(c) __UINT64_C(c)_REENT_EMERGENCY_SIZE 25iface_assocINT_FAST64_MIN__USFRACT_IBIT__ 0usb_standard_interface_get_status__weak_symbol __attribute__((__weak__))USB_REQ_SET_DESCRIPTOR 7__USFRACT_MIN__ 0.0UHR__used __attribute__((__used__))__ARM_NEON_REENT_EMERGENCY(ptr) ((ptr)->_emergency)__GNUCLIKE_CTOR_SECTION_HANDLING 1__UINT8_MAX__ 0xff___int16_t_defined 1UINTMAX_C(c) __UINTMAX_C(c)_REENT _impure_ptr__LDBL_MAX_EXP__ 1024USB_REQ_TYPE_VENDOR 0x40__SVID_VISIBLE 0__builtin_memcpy__exported __attribute__((__visibility__("default")))__SCCSID(s) struct __hackBIT7 (1<<7)__DBL_HAS_DENORM__ 1__OPTIMIZE_SIZE__ 1__CC_SUPPORTS___INLINE 1_MB_LEN_MAX 1extra_string_idx__DA_FBIT__ 31BIT17 (1<<17)USB_ENDPOINT_ATTR_NOSYNC 0x00__GXX_ABI_VERSION 1017__ULACCUM_IBIT__ 32__FLT_DENORM_MIN__ 1.4012984643248171e-45F__returns_twice __attribute__((__returns_twice__))__requires_shared(...) __lock_annotate(shared_locks_required(__VA_ARGS__))_END_STD_C _usbd_standard_request_device_T_SIZE __UINT32_C(c) c ## UL__UACCUM_MIN__ 0.0UKUINT32_C(c) __UINT32_C(c)__have_long32 1__FLT_EPSILON__ 1.1920928955078125e-7F__XSTRING(x) __STRING(x)__attribute_pure__ __ACCUM_IBIT__ 16USB_DT_ENDPOINT 5USB_ENDPOINT_ATTR_DATA 0x00__PTRDIFF_TYPE__ int__ARM_ARCH_ISA_THUMB__CC_SUPPORTS_INLINE 1USB_FEAT_TEST_MODE 2__GNUCLIKE_BUILTIN_VARARGS 1__UACCUM_EPSILON__ 0x1P-16UK__ARM_FEATURE_MATMUL_INT8__UINT8_TYPE__ unsigned char_REENT_SIGNGAM(ptr) ((ptr)->_new._reent._gamma_signgam)USB_ENDPOINT_ATTR_ADAPTIVE 0x08__GCC_ATOMIC_SHORT_LOCK_FREE 2__INT_WCHAR_T_H usb_standard_endpoint_get_status__USACCUM_FBIT__ 8_ELIDABLE_INLINE static __inline____NULLABILITY_PRAGMA_POP __MISC_VISIBLE 0__LACCUM_FBIT__ 31USB_ENDPOINT_ATTR_INTERRUPT 0x03__INT_LEAST16_WIDTH__ 16__FLT32_MIN__ 1.1754943508222875e-38F32__FLT32_HAS_QUIET_NAN__ 1__OBSOLETE_MATH __OBSOLETE_MATH_DEFAULTUSB_DT_INTERFACE 4__LDBL_HAS_INFINITY__ 1LIBOPENCM3_CM3_COMMON_H __TA_FBIT__ 63../../usb/usb_standard.cMMIO8(addr) (*(volatile uint8_t *)(addr))__USB_PRIVATE_H __FLT32X_MAX_10_EXP__ 308__ARM_ARCH_EXT_IDIV__ 1bool _Bool__offsetof(type,field) offsetof(type, field)UINTMAX_MAX __UINTMAX_MAX____SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 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(a) : (b))__ARM_FEATURE_CMSEINT16_MAXassoc__wchar_t__ __LDBL_HAS_QUIET_NAN__ 1bDescriptorType__LONG_LONG_WIDTH__ 64BIT6 (1<<6)_PTRDIFF_T force_nak__UINT_FAST64_MAX__ 0xffffffffffffffffULL__ARM_FP__HA_IBIT__ 8__INTPTR_WIDTH__ 32__STDC__ 1BIT9 (1<<9)__FLT32X_MIN__ 2.2250738585072014e-308F32xINT_FAST8_MIN (-INT_FAST8_MAX - 1)__strftimelike(fmtarg,firstvararg) __attribute__((__format__ (__strftime__, fmtarg, firstvararg)))__FLT64_MAX_EXP__ 1024__WCHAR_T __SYS_CONFIG_H__ __FLT64_MIN__ 2.2250738585072014e-308F64__GNUC_VA_LIST_COMPATIBILITY 1wMaxPacketSize__INT_WIDTH__ 32_HAVE_CC_INHIBIT_LOOP_TO_LIBCALL 1__FLT_MIN_EXP__ (-125)__ARM_ARCH_PROFILE__INT64_TYPE__ long long int__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4__BSD_VISIBLE 0__predict_false(exp) __builtin_expect((exp), 0)__unused __attribute__((__unused__))__nonnull_all __attribute__((__nonnull__))_REENT_MBSRTOWCS_STATE(ptr) ((ptr)->_new._reent._mbsrtowcs_state)MAX_USER_CONTROL_CALLBACK 4totallen__UFRACT_MAX__ 0XFFFFP-16UR___int_least64_t_defined 1_Alignof(x) __alignof(x)iManufacturer__THROW UINTMAX_Cuser_control_callbackINT_FAST64_MIN (-INT_FAST64_MAX - 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1)__FLT_HAS_QUIET_NAN__ 1__ATFILE_VISIBLE 0__GCC_ATOMIC_CHAR_LOCK_FREE 2control_state__LFRACT_EPSILON__ 0x1P-31LRSTM32L4 1__malloc_like __attribute__((__malloc__))bFunctionSubClassBIT20 (1<<20)__ARM_SIZEOF_MINIMAL_ENUM 1USB_REQ_TYPE_OTHER 0x03_POINTER_INT long__FLT32X_NORM_MAX__ 1.7976931348623157e+308F32x__arm__ 1INT_FAST64_MAXUSB_DT_INTERFACE_POWER 8__FRACT_EPSILON__ 0x1P-15R__FLT32_MIN_10_EXP__ (-37)__RAND_MAX 0x7fffffff__lock_try_acquire(lock) ((void) 0)__STRING(x) #x_WCHAR_T INT8_MAX __INT8_MAX____ARM_FP16_FORMAT_ALTERNATIVE__FBSDID(s) struct __hack_usbd_deviceINTPTR_MIN_MACHINE__DEFAULT_TYPES_H __BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)USB_REQ_TYPE_DEVICE 0x00_GCC_PTRDIFF_T __GNUCLIKE_BUILTIN_NEXT_ARG 1__TA_IBIT__ 64__LOCK_INIT(class,lock) static int lock = 0;_SIZE_T _WCHAR_T_H __ARM_FEATURE_QRDMX__ARM_ARCH_ISA_THUMB 2__LONG_LONG_MAX__ 0x7fffffffffffffffLL_FSEEK_OPTIMIZATION 1__WINT_WIDTH__ 32usb_standard_get_interface__arg_type_tag(arg_kind,arg_idx,type_tag_idx) _REENT_INIT_PTR(var) { memset((var), 0, sizeof(*(var))); _REENT_INIT_PTR_ZEROED(var); }BIT11 (1<<11)__COPYRIGHT(s) struct __hack__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1_REENT_MBRLEN_STATE(ptr) ((ptr)->_new._reent._mbrlen_state)_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0usbd_request_return_codes_STDDEF_H_ INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__DBL_MIN_EXP__ (-1021)__SIZE_T bFunctionClassUSB_DT_INTERFACE_ASSOCIATION 11INT8_MIN (-INT8_MAX - 1)__printf0like(fmtarg,firstvararg) __FLT32_DIG__ 6DATA_INbNumConfigurationsBIT15 (1<<15)UINT16_CdisconnectUSB_REQ_TYPE_ENDPOINT 0x02num_strings___int64_t_defined 1__LDBL_HAS_DENORM__ 1iface__SACCUM_FBIT__ 7__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1INT32_MAX__lock_close_recursive(lock) ((void) 0)__ACCUM_MIN__ (-0X1P15K-0X1P15K)__ARM_FEATURE_CRYPTOINT16_MIN (-INT16_MAX - 1)__INT_LEAST32_TYPE__ long intUSB_REQ_CLEAR_FEATURE 1USB_REQ_SET_ADDRESS 5UINT_LEAST16_MAXBIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__FRACT_IBIT__ 0__ATOMIC_ACQUIRE 2UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2__NEWLIB_PATCHLEVEL__ 0bLength__ORDER_LITTLE_ENDIAN__ 1234__size_t__FLT_NORM_MAX__ 3.4028234663852886e+38Fuser_callback_set_altsettinglong long unsigned int__FLT_MIN_10_EXP__ (-37)BIT31 (1<<31)wIndexcommand__LDBL_IS_IEC_60559__ 2__ULLACCUM_EPSILON__ 0x1P-32ULLK_SIZE_T_DEFINED __DQ_FBIT__ 63__GNU_VISIBLE 0INT_LEAST64_MAXuint16_t__PTRDIFF_T __UHQ_IBIT__ 0INT_LEAST8_MIN_REENT_WCTOMB_STATE(ptr) ((ptr)->_new._reent._wctomb_state)usbd_dev__INT_FAST16_TYPE__ intextra__USBD_H __SACCUM_MIN__ (-0X1P7HK-0X1P7HK)usb_standard_set_address__UINT_LEAST16_TYPE__ short unsigned intUINT16_MAX__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned intSTATUS_INusbd_control_complete_callback__signed signedSTATUS_OUT__UTQ_FBIT__ 128_REENT_ASCTIME_BUF(ptr) ((ptr)->_new._reent._asctime_buf)__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffff__have_longlong64 1INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)PTRDIFF_MAX __PTRDIFF_MAX____SIZEOF_SHORT__ 2bFunctionProtocolINT8_MIN__size_t _WCHAR_T_DEFINED idProduct__trylocks_exclusive(...) __lock_annotate(exclusive_trylock_function(__VA_ARGS__))USB_REQ_TYPE_TYPE 0x60ep_write_packetUINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRBIT26 (1<<26)__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long int__always_inline __inline__ __attribute__((__always_inline__))_ATEXIT_SIZE 32USBD_REQ_NOTSUPPidVendor_BSD_SIZE_T_ WCHAR_MIN__no_lock_analysis __lock_annotate(no_thread_safety_analysis)_WCHAR_T_ true 1_REENT_STDIO_STREAM(var,index) &(var)->__sf[index]descdescr_idx_T_WCHAR _BEGIN_STD_C __FLT64_MAX__ 1.7976931348623157e+308F64usb_iface_assoc_descriptor_TIME_T_ __int_least64_t_CLOCKID_T_ unsigned long_REENT_CHECK_TM(ptr) usb_device_descriptor__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15iInterface__FLT32X_MAX__ 1.7976931348623157e+308F32xwValueUSB_LANGID_ENGLISH_US__ARM_EABI__ 1INT16_MINusb_descriptor_type__FLT_IS_IEC_60559__ 2__THUMBEL__ 1_GCC_WCHAR_T __ARM_FEATURE_DSP 1WINT_MIN __WINT_MIN__USB_DT_DEVICE_SIZE sizeof(struct usb_device_descriptor)USB_ENDPOINT_ATTR_SYNC 0x0C__QQ_IBIT__ 0__LLACCUM_FBIT__ 31USB_FEAT_DEVICE_REMOTE_WAKEUP 1bInterfaceSubClass__USQ_IBIT__ 0USB_REQ_TYPE_DIRECTION 0x80__lock_release_recursive(lock) ((void) 0)__UINT_LEAST32_TYPE__ long unsigned intinit__ARM_FEATURE_NUMERIC_MAXMIN_RAND48_MULT_1 (0xdeec)__INTMAX_TYPE__ long long intUINTPTR_MAXUSB_REQ_TYPE_INTERFACE 0x01__GCC_ATOMIC_INT_LOCK_FREE 2UINT_FAST8_MAX_RAND48_SEED_0 (0x330e)INTMAX_MAXbFirstInterface__ARM_FEATURE_FP16_SCALAR_ARITHMETIC__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1UINT_LEAST32_MAX__FLT64_HAS_QUIET_NAN__ 1__ptrvalue _NOINLINE_STATIC _NOINLINE static_MACHINE__TYPES_H INT32_C__ARM_FEATURE_UNALIGNED 1USB_ENDPOINT_ATTR_BULK 0x02INT64_MIN__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intMMIO64(addr) (*(volatile uint64_t *)(addr))usb_standard_device_get_status__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRdriverWCHAR_MAX __WCHAR_MAX__/build/libopencm3/lib/stm32/l4__SIZEOF_SIZE_T__ 4usbd_register_set_config_callback__UINT64_TYPE__ long long unsigned intusbd_set_altsetting_callback__INT64_C(c) c ## LL_FVWRITE_IN_STREAMIO 1__lockable __lock_annotate(lockable)ep_reset__END_DECLS __generic(expr,t,yes,no) __builtin_choose_expr( __builtin_types_compatible_p(__typeof(expr), t), yes, no)__LONG_MAX__ 0x7fffffffL__ARM_FEATURE_CDEbInterfaceNumberMAX_USER_SET_CONFIG_CALLBACK 4unsignedINT_LEAST32_MIN (-INT_LEAST32_MAX - 1)_STRING_H_ short int_STDDEF_H __pt_guarded_by(x) __lock_annotate(pt_guarded_by(x))__guarded_by(x) __lock_annotate(guarded_by(x))__GNUCLIKE___OFFSETOF 1__UINT16_C(c) c__FLT64_MIN_EXP__ (-1021)_REENT_INIT_ATEXIT _NULL, _ATEXIT_INIT,__CC_SUPPORTS___INLINE__ 1__UDA_IBIT__ 32__printflike(fmtarg,firstvararg) __attribute__((__format__ (__printf__, fmtarg, firstvararg)))usb_descriptor_index__fastcall __attribute__((__fastcall__))current_address__lock_annotate(x) BIT2 (1<<2)_REENT_SIGNAL_BUF(ptr) ((ptr)->_new._reent._signal_buf)__ATOMIC_RELAXED 0_ATTRIBUTE(attrs) __attribute__ (attrs)__ARM_FEATURE_COPROC__ATTRIBUTE_IMPURE_PTR__ __DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53BIT5 (1<<5)BIT1 (1<<1)__rangeof(type,start,end) (__offsetof(type, end) - __offsetof(type, start))__dead2 __attribute__((__noreturn__))INT_LEAST32_MAX__USES_INITFINI__ 1USB_DEV_STATUS_SELF_POWERED 0x01__lock_init(lock) ((void) 0)__need_ptrdiff_t__ULFRACT_MAX__ 0XFFFFFFFFP-32ULR__DBL_DECIMAL_DIG__ 17index_PTRDIFF_T_ _GLOBAL_REENT _global_impure_ptr_NULL 0__flexarr [0]INT16_C(c) __INT16_C(c)__INT16_MAX__ 0x7fff_WANT_REGISTER_FINI 1__DEVOLATILE(type,var) ((type)(__uintptr_t)(volatile void *)(var))DATA_OUT__WCHAR_T__ __SSP_FORTIFY_LEVEL 0__ARM_FEATURE_SIMD32 1__XSI_VISIBLE 0INT_FAST32_MIN (-INT_FAST32_MAX - 1)__QQ_FBIT__ 7__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1otgfs_usb_driver stm32f107_usb_driver__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64__GNUC_PREREQ__(ma,mi) __GNUC_PREREQ(ma, mi)__DEFINED_wchar_t __UTA_IBIT__ 64__strong_reference(sym,aliassym) extern __typeof (sym) aliassym __attribute__ ((__alias__ (#sym)))__LDBL_NORM_MAX__ 1.7976931348623157e+308L__ULLFRACT_EPSILON__ 0x1P-64ULLR__unreachable() __builtin_unreachable()__ACCUM_EPSILON__ 0x1P-15K__LOCK_INIT_RECURSIVE(class,lock) static int lock = 0;__SIZEOF_WINT_T__ 4strlen__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17USB_REQ_TYPE_RECIPIENT 0x1F__GNUCLIKE_ASM 3__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1__scanflike(fmtarg,firstvararg) __attribute__((__format__ (__scanf__, fmtarg, firstvararg)))_WIDE_ORIENT 1user_callback_reset__ULLACCUM_MIN__ 0.0ULLK_SYS__TYPES_H __INT_FAST32_WIDTH__ 32___int_wchar_t_h memcpy__GNUCLIKE_BUILTIN_VAALIST 1__sym_compat(sym,impl,verid) __asm__(".symver " #impl ", " #sym "@" #verid)USB_ENDPOINT_ATTR_CONTROL 0x00__ARM_ASM_SYNTAX_UNIFIED__ 1__locks_exclusive(...) __lock_annotate(exclusive_lock_function(__VA_ARGS__))bDeviceClassusb_language_idINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPROD__Long long_NEWLIB_VERSION "3.3.0"__pure __attribute__((__pure__))__ARM_PCS_VFP 1_GCC_SIZE_T __CC_SUPPORTS_WARNING 1PTRDIFF_MAX__ULLFRACT_MIN__ 0.0ULLR_T_WCHAR_ _REENT_MP_P5S(ptr) ((ptr)->_p5s)_REENT_CHECK_RAND48(ptr) INT_LEAST64_MIN__lock_release(lock) ((void) 0)__GCC_CONSTRUCTIVE_SIZE 64_BSD_WCHAR_T___LLFRACT_IBIT__ 0__CC_SUPPORTS_VARADIC_XXX 1__LLFRACT_MIN__ (-0.5LLR-0.5LLR)uint32_tBIT12 (1<<12)__weak_reference(sym,alias) __asm__(".weak " #alias); __asm__(".equ " #alias ", " #sym)__SACCUM_EPSILON__ 0x1P-7HK__GCC_ASM_FLAG_OUTPUTS__ 1_REENT_CHECK_VERIFY 1__ARM_FP 4__need_wchar_tuser_callback_resumeusbd_control_callback__UHA_IBIT__ 8__need_wint_t bMaxPower__ULACCUM_EPSILON__ 0x1P-32ULK__LDBL_DIG__ 15_Atomic(T) struct { T volatile __val; }__SIZE_WIDTH__ 32SIG_ATOMIC_MAXBIT16 (1<<16)otghs_usb_driver stm32f207_usb_driver__WINT_MIN__ 0UINT_LEAST16_MIN__FLT64_DIG__ 15__WINT_MAX__ 0xffffffffUBIT22 (1<<22)__INT_LEAST8_WIDTH__ 8__long_double_t long double__INT_LEAST16_TYPE__ short int_RAND48_MULT_0 (0xe66d)LAST_DATA_IN__DBL_MAX__ ((double)1.7976931348623157e+308L)_REENT_WCRTOMB_STATE(ptr) ((ptr)->_new._reent._wcrtomb_state)short unsigned int__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1__thumb__ 1BIT30 (1<<30)INT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1__format_arg(fmtarg) __attribute__((__format_arg__ (fmtarg)))__compiler_membar() __asm __volatile(" " : : : "memory")__HQ_FBIT__ 15__bool_true_false_are_defined 1__datatype_type_tag(kind,type) __RCSID(s) struct __hack__lock_try_acquire_recursive(lock) ((void) 0)__SIZE_MAX__ 0xffffffffU__INT_LEAST16_MAX__ 0x7fffUSB_DT_STRING 3USB_ENDPOINT_ATTR_TYPE 0x03__DECONST(type,var) ((type)(__uintptr_t)(const void *)(var))__ARM_ARCH__DEFINED_ptrdiff_t _SYS_CDEFS_H_ BIT25 (1<<25)type_mask__nonnull(x) __attribute__((__nonnull__ x))_RAND48_ADD (0x000b)SIG_ATOMIC_MIN __SIG_ATOMIC_MIN____ARM_FEATURE_LDREX 7usb_standard_set_interfaceUSB_ENDPOINT_ATTR_USAGETYPE 0x30bInterfaceCount_REENT_ASCTIME_SIZE 26__LLFRACT_EPSILON__ 0x1P-63LLR__SFRACT_MAX__ 0X7FP-7HR__FLT32X_MANT_DIG__ 53__WCHAR_WIDTH__ 32WINT_MAX__INT16_C(c) cUSB_ENDPOINT_ADDR_IN(x) (0x80 | (x))INT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32_REENT_GETDATE_ERR_P(ptr) (&((ptr)->_new._reent._getdate_err))_ATEXIT_INIT {_NULL, 0, {_NULL}, {{_NULL}, {_NULL}, 0, 0}}USB_DT_ENDPOINT_SIZE 7__DEQUALIFY(type,var) ((type)(__uintptr_t)(const volatile void *)(var))usb_standard_get_descriptor__ATOMIC_ACQ_REL 4BIT4 (1<<4)__HQ_IBIT__ 0__packed __attribute__((__packed__))_WCHAR_T_DEFINED_ _usbd_driverUSB_REQ_SET_INTERFACE 11bEndpointAddress__asserts_shared(...) __lock_annotate(assert_shared_lock(__VA_ARGS__))__SYS_LOCK_H__ __FLT32_NORM_MAX__ 3.4028234663852886e+38F32found_indexSIG_ATOMIC_MAX __SIG_ATOMIC_MAX____UINTMAX_MAX__ 0xffffffffffffffffULL__DBL_MANT_DIG__ 53__ULFRACT_IBIT__ 0UINT64_MAX __UINT64_MAX__INT_FAST16_MAXuser_callback_suspend__INT_MAX__ 0x7fffffff__INT_LEAST64_TYPE__ long long int_REENT_INIT(var) { 0, _REENT_STDIO_STREAM(&(var), 0), _REENT_STDIO_STREAM(&(var), 1), _REENT_STDIO_STREAM(&(var), 2), 0, "", 0, _NULL, 0, _NULL, _NULL, 0, _NULL, _NULL, 0, _NULL, { { 0, _NULL, "", {0, 0, 0, 0, 0, 0, 0, 0, 0}, 0, 1, { {_RAND48_SEED_0, _RAND48_SEED_1, _RAND48_SEED_2}, {_RAND48_MULT_0, _RAND48_MULT_1, _RAND48_MULT_2}, _RAND48_ADD }, {0, {0}}, {0, {0}}, {0, {0}}, "", "", 0, {0, {0}}, {0, {0}}, {0, {0}}, {0, {0}}, {0, {0}} } }, _REENT_INIT_ATEXIT _NULL, {_NULL, 0, _NULL} }ctrl_buf__ARM_FEATURE_CDE_COPROCUSB_REQ_TYPE_CLASS 0x20__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xGCC: (15:12.2.rel1-1) 12.2.1 20221205˙˙˙˙| (AŽ~A„…†‡Ž"TA„…†Ž8A„…†Ž*A„ŽAŽAŽ,®B$„ …†‡‰Š‹ŽFHR $B(A„Ž HA„…M ĹÄAJĹÄ4A„J ÄAGÄ @A„M ÄAG ÄA,8A„M ÄBB ÄBB ÄBCÄA3aeabi)7E-M M "ń˙(,~K" jT !!…8!"" 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5_READ_WRITE_RETURN_TYPE int__DEFINED_size_t USB_REQ_SET_CONFIGURATION 9BIT8 (1<<8)wValueBEGIN_DECLS EVENT_CBW_VALID__alloc_size2(n,x) __attribute__((__alloc_size__(n, x)))__UINT16_MAX__ 0xffffusb_config_descriptor__TQ_FBIT__ 127SCSI_MODE_SENSE_6 0x1ASBC_ASC_LOGICAL_UNIT_NOT_READY__POSIX_VISIBLE 0_HAVE_LONG_DOUBLE 1scsi_request_sense_REENT_EMERGENCY_SIZE 25__USES_INITFINI__ 1msc_data_tx_cb__GNUCLIKE_BUILTIN_CONSTANT_P 1__thumb2__ 1__ULLACCUM_FBIT__ 32_Bool_WCHAR_T_DECLARED __predict_true(exp) __builtin_expect((exp), 1)INT_FAST32_MIN (-INT_FAST32_MAX - 1)trans_event__STRICT_ANSI__ 1_SYS_FEATURES_H NULLuser_callback_set_configUINT_LEAST8_MAXusb_msc_cbwUINT8_C(c) __UINT8_C(c)SCSI_MODE_SELECT_10 0x55__SIZEOF_LONG_DOUBLE__ 8__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__LAST_DATA_OUTchar__USA_IBIT__ 16__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1INT_FAST32_MAX__hidden __attribute__((__visibility__("hidden")))USB_CONFIG_ATTR_DEFAULT 0x80__UINT_FAST64_TYPE__ long long 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9__FLT32X_IS_IEC_60559__ 2__NEWLIB_PATCHLEVEL__ 0endpointWINT_MINLIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))UINT32_MAX_REENT_CHECK_EMERGENCY(ptr) USBD_REQ_HANDLEDusbd_ep_read_packetINT_FAST16_MAX __INT_FAST16_MAX____ARM_FEATURE_FP16_FML__containerof(x,s,m) ({ const volatile __typeof(((s *)0)->m) *__x = (x); __DEQUALIFY(s *, (const volatile char *)__x - __offsetof(s, m));})leftSCSI_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1E__restrict restrict_Atomic(T) struct { T volatile __val; }__USFRACT_EPSILON__ 0x1P-8UHRNULL ((void *)0)_Thread_local __thread__OPTIMIZE_SIZE__ 1__USFRACT_FBIT__ 8__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLKSCSI_REPORT_LUNS 0xA0__need_NULL__DOTS , ...interface__LLFRACT_MIN__ (-0.5LLR-0.5LLR)INT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX__USB_REQ_TYPE_STANDARD 0x00__UINT32_MAX__ 0xffffffffULiFunctionset_address_before_status_REENT_MBTOWC_STATE(ptr) ((ptr)->_new._reent._mbtowc_state)USB_REQ_CLEAR_FEATURE 1_REENT_MBLEN_STATE(ptr) ((ptr)->_new._reent._mblen_state)__trylocks_shared(...) __lock_annotate(shared_trylock_function(__VA_ARGS__))usbd_endpoint_callback__GCC_ATOMIC_POINTER_LOCK_FREE 2__ARM_FEATURE_QBIT 1__ARM_FEATURE_CLZ 1__ARM_FEATURE_FMA 1__ARM_FEATURE_COMPLEX__locks_shared(...) __lock_annotate(shared_lock_function(__VA_ARGS__))unsigned signedctrl_buf_len__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024__bounded BIT21 (1<<21)__UINT_LEAST32_MAX__ 0xffffffffUL__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)usb_setup_data__has_feature(x) 0__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1__ACCUM_MAX__ 0X7FFFFFFFP-15K__INT8_MAX__ 0x7fUSB_REQ_GET_STATUS 0BIT14 (1<<14)__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16__UINT_FAST16_TYPE__ unsigned int__GCC_DESTRUCTIVE_SIZE 64__GCC_IEC_559_COMPLEX 0__ARM_FEATURE_MVEbMaxPacketSize0__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intUSB_DT_DEVICE_QUALIFIER 6iSerialNumberUSB_MSC_PROTOCOL_CBI 0x00SBC_SENSE_KEY_RECOVERED_ERROR__attribute_format_strfmon__(a,b) __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST32_MIN_T_SIZE_ __FLT_EVAL_METHOD_TS_18661_3__ 0__attribute_malloc__ __SCHAR_WIDTH__ 8INT_LEAST16_MAXmax_lenUINT_FAST16_MAX__lock_acquire_recursive(lock) ((void) 0)__UINT_FAST8_TYPE__ unsigned int__LLACCUM_IBIT__ 32bNumEndpointsusbd_device__requires_unlocked(...) __lock_annotate(locks_excluded(__VA_ARGS__))USB_MSC_REQ_BULK_ONLY_RESET 0xFF_ATEXIT_SIZE 32__INT32_MAX__ 0x7fffffffL__min_size(x) static (x)_TIMER_T_ unsigned longUINTMAX_MAX__BEGIN_DECLS __INT_LEAST64_MAX__ 0x7fffffffffffffffLL__null_sentinel __attribute__((__sentinel__))dCBWDataTransferLength__need_NULL USB_DEV_STATUS_REMOTE_WAKEUP 0x02__FLT32_MANT_DIG__ 24INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32__section(x) __attribute__((__section__(x)))offsetof(TYPE,MEMBER) __builtin_offsetof (TYPE, MEMBER)__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned 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(x)usb_msc_cswSTALLEDcurrent_config__GNUC__ 12bmAttributesWCHAR_MAX_REENT_SIGNAL_BUF(ptr) ((ptr)->_new._reent._signal_buf)__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16__warn_references(sym,msg) __asm__(".section .gnu.warning." #sym); __asm__(".asciz \"" msg "\""); __asm__(".previous")__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0Uget_cbw_buf__UQQ_IBIT__ 0USB_MSC_SUBCLASS_ATAPI 0x02_NEWLIB_VERSION_H__ 1__GCC_ATOMIC_LONG_LOCK_FREE 2__ULACCUM_MIN__ 0.0ULKctrl_len__need_size_t__LDBL_MAX__ 1.7976931348623157e+308L__ARM_ARCH 7_SIZE_T_ USB_REQ_SET_FEATURE 3__FLT_RADIX__ 2BIT3 (1<<3)long long int_REENT_RAND48_MULT(ptr) ((ptr)->_new._reent._r48._mult)BIT29 (1<<29)MIN(a,b) ((a) < (b) ? (a) : (b))__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAXusb_msc_trans__wchar_t__ __PMT(args) args__LDBL_HAS_QUIET_NAN__ 1bDescriptorType__LONG_LONG_WIDTH__ 64BIT6 (1<<6)__DEFINED_wchar_t __need_wchar_t bCBWLUN__UINT_FAST64_MAX__ 0xffffffffffffffffULL__ARM_FP__HA_IBIT__ 8__INTPTR_WIDTH__ 32__INTMAX_C(c) c ## LLBIT9 (1<<9)__FLT32X_MIN__ 2.2250738585072014e-308F32xtrue 1INTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024UINT16_MAX__SYS_CONFIG_H__ MB_CUR_MAX __locale_mb_cur_max()__FLT64_MIN__ 2.2250738585072014e-308F64__GNUC_VA_LIST_COMPATIBILITY 1wMaxPacketSize_HAVE_CC_INHIBIT_LOOP_TO_LIBCALL 1__OBSOLETE_MATH_DEFAULT 1__NULLABILITY_PRAGMA_POP __ARM_ARCH_PROFILE__INT64_TYPE__ long long int__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4_PTRDIFF_T set_address__predict_false(exp) __builtin_expect((exp), 0)__unused __attribute__((__unused__))__nonnull_all __attribute__((__nonnull__))_REENT_MBSRTOWCS_STATE(ptr) ((ptr)->_new._reent._mbsrtowcs_state)__ASMNAME(cname) __XSTRING (__USER_LABEL_PREFIX__) cnameMAX_USER_CONTROL_CALLBACK 4__lock_try_acquire(lock) ((void) 0)__UFRACT_MAX__ 0XFFFFP-16URUSB_MSC_REQ_CODES_GET 0xFC___int_least64_t_defined 1INT64_MAXiManufacturer__THROW user_control_callbackINT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0_REENT_L64A_BUF(ptr) ((ptr)->_new._reent._l64a_buf)ascqcomplete__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX___NOTHROW _REENT_CHECK_ASCTIME_BUF(ptr) _ANSIDECL_H_ BBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)__USER_LABEL_PREFIX__ event__UFRACT_FBIT__ 16__UDQ_FBIT__ 64INT16_MIN (-INT16_MAX - 1)__GNUCLIKE_BUILTIN_MEMCPY 1SBC_ASC_MEDIUM_NOT_PRESENT__LDBL_MAX_10_EXP__ 308CSW_STATUS_FAILED 1USB_REQ_TYPE_IN 0x80__DEQUALIFY(type,var) ((type)(__uintptr_t)(const volatile void *)(var))USB_DT_DEVICE_SIZE sizeof(struct usb_device_descriptor)USB_CLASS_VENDOR 0xFF__INT_FAST32_TYPE__ int__SIZEOF_LONG_LONG__ 8unsigned int_SIZE_T_DEFINED_ USB_DT_INTERFACE_ASSOCIATION_SIZE sizeof(struct usb_iface_assoc_descriptor)usb_control_state__FLT_MIN_EXP__ (-125)__DEC_EVAL_METHOD__ 2usbd_ep_setupSCSI_VERIFY 0x2F__USACCUM_IBIT__ 8__ARM_ARCH_7EM__ 1__UDA_FBIT__ 32__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UINTMAX_TYPE__ long long unsigned int_FVWRITE_IN_STREAMIO 1bNumInterfaceslba_startep_stall_setSBC_ASC_INVALID_COMMAND_OPERATION_CODE_SYS_REENT_H_ __FLT_EVAL_METHOD__ 0bytes_to_readbInterfaceClass__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32bConfigurationValueCBW_STATUS_SUCCESS 0__ARM_FEATURE_LDREX_T_PTRDIFF __UQQ_FBIT__ 8INT16_C__ARM_FP16_ARGS__UACCUM_MAX__ 0XFFFFFFFFP-16UK__FLT32X_DIG__ 15evpdINT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX___WINT_T __LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4__STDC__ 1USB_REQ_TYPE_OUT 0x0___int_least8_t_defined 1__ARM_FEATURE_IDIV 1__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__SCSI_WRITE_12 0xAA__UINT8_TYPE__ unsigned charUSB_FEAT_ENDPOINT_HALT 0__unlocks(...) __lock_annotate(unlock_function(__VA_ARGS__))__EXPORT __ARM_FEATURE_COPROC 15SBC_ASC_UNRECOVERED_READ_ERROR_Noreturn __dead2extralenset_sbc_statusCSW_STATUS_SUCCESS 0INT8_MIN__strftimelike(fmtarg,firstvararg) __attribute__((__format__ (__strftime__, fmtarg, firstvararg)))bRequestiface_assoc__IMPORT _RAND48_SEED_2 (0x1234)poll__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)_MACHINE__TYPES_H bmCBWFlagsmsc_control_request_REENT_SIGNAL_SIZE 24__LDBL_MIN_10_EXP__ (-307)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1__ATFILE_VISIBLE 0__GCC_ATOMIC_CHAR_LOCK_FREE 2control_state___int_size_t_h __LFRACT_EPSILON__ 0x1P-31LR__GNUCLIKE_MATH_BUILTIN_RELOPS STM32L4 1__malloc_like __attribute__((__malloc__))bFunctionSubClasssbc_ascqBIT20 (1<<20)__ARM_SIZEOF_MINIMAL_ENUM 1__EXP(x) __ ##x ##___POINTER_INT long__FLT32X_NORM_MAX__ 1.7976931348623157e+308F32x__arm__ 1sbc_sense_keyCSW_SIGNATURE 0x53425355__FRACT_EPSILON__ 0x1P-15R__FLT32_MIN_10_EXP__ (-37)SBC_ASC_PERIPHERAL_DEVICE_WRITE_FAULT__RAND_MAX 0x7fffffff__lock_init_recursive(lock) ((void) 0)__STRING(x) #x_WCHAR_T __ARM_FEATURE_BF16_VECTOR_ARITHMETIC__ARM_FP16_FORMAT_ALTERNATIVE__FBSDID(s) struct __hack_usbd_deviceINTPTR_MIN_MACHINE__DEFAULT_TYPES_H __BIGGEST_ALIGNMENT__ 8DATA_INUSB_REQ_TYPE_DEVICE 0x00_GCC_PTRDIFF_T __GNUCLIKE_BUILTIN_NEXT_ARG 1__TA_IBIT__ 64usbd_ep_write_packet__LOCK_INIT(class,lock) static int lock = 0;SCSI_SYNCHRONIZE_CACHE 0x35_SIZE_T _WCHAR_T_H SBC_SENSE_KEY_HARDWARE_ERROR_RAND48_MULT_2 (0x0005)__ARM_FEATURE_QRDMXdCSWDataResidue__ARM_ARCH_ISA_THUMB 2__LONG_LONG_MAX__ 0x7fffffffffffffffLL_FSEEK_OPTIMIZATION 1__WINT_WIDTH__ 32SIG_ATOMIC_MAX __SIG_ATOMIC_MAX___MACHSTDLIB_H_ __USQ_IBIT__ 0_REENT_INIT_PTR(var) { memset((var), 0, sizeof(*(var))); _REENT_INIT_PTR_ZEROED(var); }BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1_REENT_MBRLEN_STATE(ptr) ((ptr)->_new._reent._mbrlen_state)_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0usbd_request_return_codes__SIZEOF_INT__ 4trans_WANT_IO_LONG_LONG 1__DBL_MIN_EXP__ (-1021)__SIZE_T bFunctionClassUSB_DT_INTERFACE_ASSOCIATION 11INT8_MIN (-INT8_MAX - 1)__printf0like(fmtarg,firstvararg) __FLT32_DIG__ 6_PTRDIFF_T_DECLARED SBC_ASCQ_INITIALIZING_COMMAND_REQUIREDbNumConfigurationsBIT15 (1<<15)UINT16_Cset_sbc_status_gooddisconnectSCSI_READ_10 0x28USB_REQ_TYPE_ENDPOINT 0x02num_strings___int64_t_defined 1__LDBL_HAS_DENORM__ 1__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)__lock_close_recursive(lock) ((void) 0)__ACCUM_MIN__ (-0X1P15K-0X1P15K)SCSI_READ_FORMAT_CAPACITIES 0x23_GCC_WCHAR_T __ARM_FEATURE_CRYPTO__INT_LEAST32_TYPE__ long intUSB_REQ_SET_ADDRESS 5_usbd_mass_storageBIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__FRACT_IBIT__ 0__ATOMIC_ACQUIRE 2UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2SBC_SENSE_KEY_MISCOMPAREbLength__ORDER_LITTLE_ENDIAN__ 1234__size_t__FLT_NORM_MAX__ 3.4028234663852886e+38Fuser_callback_set_altsettinglong long unsigned int__arg_type_tag(arg_kind,arg_idx,type_tag_idx) __alloc_size(x) __attribute__((__alloc_size__(x)))BIT31 (1<<31)_spc3_inquiry_responsewIndex_Null_unspecified __SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2_REENT_WCSRTOMBS_STATE(ptr) ((ptr)->_new._reent._wcsrtombs_state)__ULLACCUM_EPSILON__ 0x1P-32ULLK__APCS_32__ 1__DQ_FBIT__ 63dCBWSignatureINT_LEAST64_MAXuint16_t__PTRDIFF_T __UHQ_IBIT__ 0INT_LEAST8_MIN_REENT_WCTOMB_STATE(ptr) ((ptr)->_new._reent._wctomb_state)usbd_dev__INT_FAST16_TYPE__ intextra__USBD_H __SACCUM_MIN__ (-0X1P7HK-0X1P7HK)__ULFRACT_MAX__ 0XFFFFFFFFP-32ULR__const const__UINT_LEAST16_TYPE__ short unsigned int__need_wint_t__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned intSTATUS_INusbd_control_complete_callback__signed signedSCSI_READ_6 0x08STATUS_OUT__UTQ_FBIT__ 128_REENT_ASCTIME_BUF(ptr) ((ptr)->_new._reent._asctime_buf)__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffff__have_longlong64 1USB_MSC_REQ_CODES_GML 0xFESBC_ASCQ_OPERATION_IN_PROGRESSPTRDIFF_MAX __PTRDIFF_MAX____SIZEOF_SHORT__ 2USB_MSC_REQ_GET_MAX_LUN 0xFEbFunctionProtocolep_out_size_WCHAR_T_DEFINED idProduct__trylocks_exclusive(...) __lock_annotate(exclusive_trylock_function(__VA_ARGS__))USB_REQ_TYPE_TYPE 0x60UINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRproduct_id__DQ_IBIT__ 0_REENT_WCRTOMB_STATE(ptr) ((ptr)->_new._reent._wcrtomb_state)__always_inline __inline__ __attribute__((__always_inline__))iConfiguration_UNBUF_STREAM_OPT 1USBD_REQ_NOTSUPPidVendor_BSD_SIZE_T_ WCHAR_MINSCSI_TEST_UNIT_READY 0x00__no_lock_analysis __lock_annotate(no_thread_safety_analysis)force_nakmemsetUINT_LEAST16_MAX __UINT_LEAST16_MAX__descINT_LEAST64_MIN (-INT_LEAST64_MAX - 1)_T_WCHAR _BEGIN_STD_C ___int_ptrdiff_t_h _ATEXIT_DYNAMIC_ALLOC 1usb_iface_assoc_descriptor_TIME_T_ __int_least64_t_CLOCKID_T_ unsigned longINT16_C(c) __INT16_C(c)usb_device_descriptor__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15iInterface__FLT32X_MAX__ 1.7976931348623157e+308F32x___int16_t_defined 1__GNUCLIKE_BUILTIN_VAALIST 1__ARM_EABI__ 1INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1__ARM_FEATURE_DSP 1USB_ENDPOINT_ATTR_SYNC 0x0C__QQ_IBIT__ 0_WCHAR_T_ __LLACCUM_FBIT__ 31USB_FEAT_DEVICE_REMOTE_WAKEUP 1bInterfaceSubClass__GNUC_MINOR__ 2USB_REQ_TYPE_DIRECTION 0x80__lock_release_recursive(lock) ((void) 0)__UINT_LEAST32_TYPE__ long unsigned intinit__ARM_FEATURE_NUMERIC_MAXMIN_RAND48_MULT_1 (0xdeec)__INTMAX_TYPE__ long long intusbd_register_control_callback__GCC_ATOMIC_INT_LOCK_FREE 2_RAND48_SEED_0 (0x330e)INTMAX_MAXbFirstInterface__ARM_FEATURE_FP16_SCALAR_ARITHMETIC__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1__FLT64_HAS_INFINITY__ 1__ptrvalue _NOINLINE_STATIC _NOINLINE static__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_C__ARM_FEATURE_UNALIGNED 1__COPYRIGHT(s) struct __hackINT64_MIN__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intMMIO64(addr) (*(volatile uint64_t *)(addr))bDeviceClass__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRdriver/build/libopencm3/lib/stm32/l4__SIZEOF_SIZE_T__ 4usbd_register_set_config_callback__UINT64_TYPE__ long long unsigned intusbd_set_altsetting_callback__INT64_C(c) c ## LLINT8_MAX __INT8_MAX__HAVE_INITFINI_ARRAY 1__lockable __lock_annotate(lockable)ep_reset__END_DECLS __generic(expr,t,yes,no) __builtin_choose_expr( __builtin_types_compatible_p(__typeof(expr), t), yes, no)__LDBL_MIN__ 2.2250738585072014e-308LSBC_SENSE_KEY_UNIT_ATTENTION__ARM_FEATURE_CDEbInterfaceNumber__BSD_VISIBLE 0unsignedSCSI_START_STOP_UNIT 0x1B__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)_STRING_H_ short intscsi_read_10__pt_guarded_by(x) __lock_annotate(pt_guarded_by(x))UINT_FAST32_MAX_SYS_SIZE_T_H __UINT16_C(c) c__FLT64_MIN_EXP__ (-1021)_REENT_INIT_ATEXIT _NULL, _ATEXIT_INIT,__CC_SUPPORTS___INLINE__ 1__UDA_IBIT__ 32__printflike(fmtarg,firstvararg) __attribute__((__format__ (__printf__, fmtarg, firstvararg)))USB_MSC_SUBCLASS_IEEE1667 0x08UINT_LEAST32_MAXcurrent_address__lock_annotate(x) BIT2 (1<<2)INT64_C__ATOMIC_RELAXED 0_ATTRIBUTE(attrs) __attribute__ (attrs)__ARM_FEATURE_COPROC__ATTRIBUTE_IMPURE_PTR__ __DBL_HAS_INFINITY__ 1scsi_write_10__SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53BIT5 (1<<5)BIT1 (1<<1)__rangeof(type,start,end) (__offsetof(type, end) - __offsetof(type, start))INT8_C__GNUCLIKE___OFFSETOF 1INT_LEAST32_MAXSCSI_MODE_SENSE_10 0x5A__ARM_ARCH_EXT_IDIV__ 1USB_DEV_STATUS_SELF_POWERED 0x01__lock_init(lock) ((void) 0)__need_ptrdiff_tUSB_MSC_REQ_CODES_BOMSR 0xFF__DBL_DECIMAL_DIG__ 17_PTRDIFF_T_ SCSI_READ_12 0xA8_GLOBAL_REENT _global_impure_ptr__ULACCUM_FBIT__ 32__flexarr [0]ep_in_sizemsd_buf__INT16_MAX__ 0x7fff_WANT_REGISTER_FINI 1__DEVOLATILE(type,var) ((type)(__uintptr_t)(volatile void *)(var))DATA_OUT__WCHAR_T__ __INT_WIDTH__ 32__ARM_FEATURE_SIMD32 1scsi_inquiry__XSI_VISIBLE 0_STDLIB_H_ SBC_ASC_WRITE_PROTECTED__QQ_FBIT__ 7otgfs_usb_driver stm32f107_usb_driver__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64unlock__GNUC_PREREQ__(ma,mi) __GNUC_PREREQ(ma, mi)scsi_mode_sense_6__UTA_IBIT__ 64__ULLACCUM_IBIT__ 32__SHRT_WIDTH__ 16__strong_reference(sym,aliassym) extern __typeof (sym) aliassym __attribute__ ((__alias__ (#sym)))__LDBL_NORM_MAX__ 1.7976931348623157e+308L__ULLFRACT_EPSILON__ 0x1P-64ULLR__unreachable() __builtin_unreachable()__LOCK_INIT_RECURSIVE(class,lock) static int lock = 0;__SIZEOF_WINT_T__ 4strlen__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17USB_REQ_TYPE_RECIPIENT 0x1FSBC_SENSE_KEY_BLANK_CHECK__GNUCLIKE_ASM 3__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1__scanflike(fmtarg,firstvararg) __attribute__((__format__ (__scanf__, fmtarg, firstvararg)))__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)user_callback_reset__ULLACCUM_MIN__ 0.0ULLK_SYS__TYPES_H __INT_FAST32_WIDTH__ 32___int_wchar_t_h memcpy_NOINLINE __attribute__ ((__noinline__))_ELIDABLE_INLINE static __inline____sym_compat(sym,impl,verid) __asm__(".symver " #impl ", " #sym "@" #verid)__ARM_ASM_SYNTAX_UNIFIED__ 1__locks_exclusive(...) __lock_annotate(exclusive_lock_function(__VA_ARGS__))../../usb/usb_msc.cUSB_ENDPOINT_ATTR_BULK 0x02__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPROD__Long longSBC_ASC_NO_ADDITIONAL_SENSE_INFORMATIONCBW_STATUS_PHASE_ERROR 2__pure __attribute__((__pure__))__ARM_PCS_VFP 1_GCC_SIZE_T USB_MSC_SUBCLASS_LOCKABLE 0x07__CC_SUPPORTS_WARNING 1_REENT_CHECK_TM(ptr) __ULLFRACT_MIN__ 0.0ULLRUINT_FAST8_MAXBIT26 (1<<26)_REENT_MP_P5S(ptr) ((ptr)->_p5s)_REENT_CHECK_RAND48(ptr) INT_LEAST64_MIN__lock_release(lock) ((void) 0)__GCC_CONSTRUCTIVE_SIZE 64_BSD_WCHAR_T___LLFRACT_IBIT__ 0__CC_SUPPORTS_VARADIC_XXX 1uint32_tBIT12 (1<<12)__lock_acquire(lock) ((void) 0)__weak_reference(sym,alias) __asm__(".weak " #alias); __asm__(".equ " #alias ", " #sym)SCSI_INQUIRY 0x12__SACCUM_EPSILON__ 0x1P-7HKUSB_REQ_TYPE_OTHER 0x03__GCC_ASM_FLAG_OUTPUTS__ 1_REENT_CHECK_VERIFY 1__ARM_FP 4__need_wchar_tUSB_MSC_SUBCLASS_RBC 0x01user_callback_resumeusbd_control_callbackuser_callback_suspend__GNUC_STDC_INLINE__ 1ep_write_packetbMaxPower__ULACCUM_EPSILON__ 0x1P-32ULK__LDBL_DIG__ 15EXIT_SUCCESS 0BIT16 (1<<16)UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXmsc_data_rx_cbotghs_usb_driver stm32f207_usb_driver__WINT_MIN__ 0UINT_LEAST16_MINUINT_LEAST64_MAX __UINT_LEAST64_MAX____FLT64_DIG__ 15__WINT_MAX__ 0xffffffffUBIT22 (1<<22)__INT_LEAST8_WIDTH__ 8__long_double_t long double__INT_LEAST16_TYPE__ short int_RAND48_MULT_0 (0xe66d)LAST_DATA_IN__DBL_MAX__ ((double)1.7976931348623157e+308L)INT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1__thumb__ 1scsi_write_6usb_msc_initBIT30 (1<<30)SBC_ASC_FORMAT_ERROR__ARMEL__ 1__format_arg(fmtarg) __attribute__((__format_arg__ (fmtarg)))__compiler_membar() __asm __volatile(" " : : : "memory")__HQ_FBIT__ 15__bool_true_false_are_defined 1__MSC_H __datatype_type_tag(kind,type) __RCSID(s) struct __hack__lock_try_acquire_recursive(lock) ((void) 0)__SIZE_MAX__ 0xffffffffU__need_wint_t __INT_LEAST16_MAX__ 0x7fffUSB_DT_STRING 3USB_ENDPOINT_ATTR_TYPE 0x03__DECONST(type,var) ((type)(__uintptr_t)(const void *)(var))__ARM_ARCH__LONG_MAX__ 0x7fffffffL__volatile volatile_SYS_CDEFS_H_ BIT25 (1<<25)___int8_t_defined 1type_maskbyte_count__nonnull(x) __attribute__((__nonnull__ x))_RAND48_ADD (0x000b)sbc_sense_infoEXIT_FAILURE 1SIG_ATOMIC_MIN __SIG_ATOMIC_MIN____ARM_FEATURE_LDREX 7PTRDIFF_MAXUSB_ENDPOINT_ATTR_USAGETYPE 0x30bInterfaceCountscsi_format_unit__strfmonlike(fmtarg,firstvararg) __attribute__((__format__ (__strfmon__, fmtarg, firstvararg)))_STDDEF_H_ __LLFRACT_EPSILON__ 0x1P-63LLR__SFRACT_MAX__ 0X7FP-7HR__FLT32X_MANT_DIG__ 53__WCHAR_WIDTH__ 32SCSI_READ_TOC_PMA_ATIP 0x43WINT_MAX__INT16_C(c) cUSB_ENDPOINT_ADDR_IN(x) (0x80 | (x))INT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32_REENT_GETDATE_ERR_P(ptr) (&((ptr)->_new._reent._getdate_err))_ATEXIT_INIT {_NULL, 0, {_NULL}, {{_NULL}, {_NULL}, 0, 0}}USB_DT_ENDPOINT_SIZE 7__ISO_C_VISIBLE 1999__ATOMIC_ACQ_REL 4BIT4 (1<<4)__INT32_TYPE__ long int__IEEE_LITTLE_ENDIAN __DBL_MIN_10_EXP__ (-307)_usbd_driverUSB_REQ_SET_INTERFACE 11bEndpointAddress__asserts_shared(...) __lock_annotate(assert_shared_lock(__VA_ARGS__))__SYS_LOCK_H__ __SFRACT_FBIT__ 7__FLT32_NORM_MAX__ 3.4028234663852886e+38F32_REENT_ASCTIME_SIZE 26UINT64_C(c) __UINT64_C(c)_LDBL_EQ_DBL 1PTRDIFF_MIN (-PTRDIFF_MAX - 1)__UINTMAX_MAX__ 0xffffffffffffffffULL__DBL_MANT_DIG__ 53_REENT_SMALL_CHECK_INIT(ptr) __ULFRACT_IBIT__ 0USB_MSC_PROTOCOL_BBB 0x50dCSWTagUINT64_MAX __UINT64_MAX__INT_FAST16_MAXscsi_command__INT_MAX__ 0x7fffffff__INT_LEAST64_TYPE__ long long intusbd_mass_storage_REENT_INIT(var) { 0, _REENT_STDIO_STREAM(&(var), 0), _REENT_STDIO_STREAM(&(var), 1), _REENT_STDIO_STREAM(&(var), 2), 0, "", 0, _NULL, 0, _NULL, _NULL, 0, _NULL, _NULL, 0, _NULL, { { 0, _NULL, "", {0, 0, 0, 0, 0, 0, 0, 0, 0}, 0, 1, { {_RAND48_SEED_0, _RAND48_SEED_1, _RAND48_SEED_2}, {_RAND48_MULT_0, _RAND48_MULT_1, _RAND48_MULT_2}, _RAND48_ADD }, {0, {0}}, {0, {0}}, {0, {0}}, "", "", 0, {0, {0}}, {0, {0}}, {0, {0}}, {0, {0}}, {0, {0}} } }, _REENT_INIT_ATEXIT _NULL, {_NULL, 0, _NULL} }ctrl_buf__ARM_FEATURE_CDE_COPROCUSB_REQ_TYPE_CLASS 0x20__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xGCC: (15:12.2.rel1-1) 12.2.1 20221205˙˙˙˙| HA„…ŽVBÎĹÄ\A„…†ŽĐA„…†ŽhA„…†‡ŽdA„ŽA3aeabi)7E-M M "ń˙ !!!"""H"18"4Đ&Ct,Qh($$`\$1^$t$1@$&&1Ě&((1`(**1\*,1,-.01357su9;=?ACEGIKMOQSUWY[]_acegikmoqwy Ń;lźŃ 2 d•Ć ř0b’Ŕđ QłäGx§Ővy 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ď…5đsń¶ˇňß!ôŃ*őřTöî]÷îźŤr;<<'Ńi)Ďz*€,9§!W ű ../common/usr/lib/gcc/arm-none-eabi/12.2.1/include../../../include/libopencm3/usb../common/../../usb../../../include/libopencm3/cm3../../../include/libopencm3/stm32../../../include/libopencm3/stm32/l4../../../include/libopencm3/stm32/commonst_usbfs_core.cstdint.husbstd.husb_private.husbd.hst_usbfs_core.hcommon.hstdbool.hrcc.hmemorymap.hmemorymap.hmemorymap.hrcc.hrcc_common_all.htools.hst_usbfs.hst_usbfs.hst_usbfs_v2.hst_usbfs_common.h!</0 q " /L5fX/z !<Ó0 .w.".4Y<‚"" .‘/K@f..<."j É=5[f../# # y<6<ü %!!. < J2,. / ‰"/‚. .< M.…f Xi .< ff l/ X .. tp ..%¦/ .X! .%Bz J .·2." s!.X.É$.$.T$ .2¬ J //!s/I! x<Ú"V" .,0 $ J<JX!W= u„ /f..< t. ě!>#!K/6J.2// V0"/ e !f/</Y !$/Y !$ 0,!K!$/<N[ ~ ..LIBOPENCM3_CM3_MEMORYMAP_H __LACCUM_EPSILON__ 0x1P-31LK__thumb__ 1UINT16_C(c) __UINT16_C(c)__UACCUM_FBIT__ 16__APCS_32__ 1MAX_USER_SET_CONFIG_CALLBACK 4usbd_control_complete_callback__LFRACT_EPSILON__ 0x1P-31LR__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN____FLT_NORM_MAX__ 3.4028234663852886e+38FRCC_APB1ENR2 MMIO32(RCC_BASE + RCC_APB1ENR2_OFFSET)__USACCUM_MIN__ 0.0UHK__ARM_FEATURE_MATMUL_INT8RCC_APB1SMENR2_OFFSET 0x7cbmAttributes__FLT32_DIG__ 6__DBL_EPSILON__ ((double)2.2204460492503131e-16L)__FLT32X_MAX__ 1.7976931348623157e+308F32x__UACCUM_IBIT__ 16RCC_APB2ENR_TIM15EN (1 << 16)INTPTR_MIN (-INTPTR_MAX - 1)RCC_CFGR_SWS_MASK 0x3RCC_APB2SMENR_SPI1SMEN (1 << 12)RCC_CCIPR_UARTxSEL_LSE RCC_CCIPR_USARTxSEL_LSE__INT_FAST16_MAX__ 0x7fffffffRCC_AHB2ENR_OTGFSEN (1 << 12)TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)__FLT64_MANT_DIG__ 53UINT_LEAST16_MAXUINT_LEAST8_MAX __UINT_LEAST8_MAX__UINT_FAST16_MAX __UINT_FAST16_MAX____SIG_ATOMIC_MAX__ 0x7fffffffINT_LEAST16_MIN (-INT_LEAST16_MAX - 1)RCC_AHB1SMENR_OFFSET 0x68RCC_CICR MMIO32(RCC_BASE + 0x20)current_addressRCC_CCIPR_UARTxSEL_HSI16 RCC_CCIPR_USARTxSEL_HSI16USB_CNTR_REG (&MMIO32(USB_DEV_FS_BASE + 0x40))USB_CNTR_L1REQM (1 << 7)RCC_APB1SMENR1_PWRSMEN (1 << 28)RCC_AHB1SMENR MMIO32(RCC_BASE + RCC_AHB1SMENR_OFFSET)__USQ_IBIT__ 0__PTRDIFF_MAX__ 0x7fffffffRCC_APB2SMENR_OFFSET 0x80INT64_MIN (-INT64_MAX - 1)RCC_CFGR_PPRE2_DIV16 0x7USB_BCDR_SDET (1 << 6)__FLT64_MIN_10_EXP__ (-307)ep_read_packetneeds_zlpextra_string_idxBIT10 (1<<10)UINT_FAST64_MAXotghs_usb_driver stm32f207_usb_driver__STDC__ 1RCC_APB2SMENR_SDMMC1SMEN (1 << 10)doeptsiz__ULLFRACT_IBIT__ 0USB_REQ_TYPE_INTERFACE 0x01__FLT32_MAX_EXP__ 128__SA_FBIT__ 15RCC_CCIPR_LPTIMxSEL_HSI16 2__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__UDA_FBIT__ 32STATUS_INRCC_AHB1SMENR_DMA1SMEN (1 << 0)bDeviceClass__UINT64_TYPE__ long long unsigned int__DBL_MAX_10_EXP__ 308RCC_APB1ENR2_LPUART1EN (1 << 0)INT_LEAST32_MIN__USBD_H __UINT_FAST64_MAX__ 0xffffffffffffffffULLUART4_BASE (PERIPH_BASE_APB1 + 0x4c00)__ARM_FEATURE_IDIV 1LIBOPENCM3_RCC_COMMON_ALL_H RCC_AHB1SMENR_CRCSMEN (1 << 12)__WCHAR_TYPE__ unsigned int__SA_IBIT__ 16__UDA_IBIT__ 32__ELF__ 1UINT_FAST32_MAXRCC_CIER_HSI48RDYIE (1 << 10)__SIZEOF_LONG__ 4DWT_BASE (PPBI_BASE + 0x1000)__ARM_ARCH 7user_callback_resumeRCC_CFGR_SWS_SHIFT 2BIT11 (1<<11)_BoolRCC_AHB2RSTR MMIO32(RCC_BASE + RCC_AHB2RSTR_OFFSET)LIBOPENCM3_MEMORYMAP_H RCC_CSR_IWDGRSTF (1 << 29)BIT3 (1<<3)WCHAR_MAXRCC_PLLCFGR_PLLQ_MASK 0x3num_stringsUSB_CLR_EP_TX_DTOG(EP) SET_REG(USB_EP_REG(EP), GET_REG(USB_EP_REG(EP)) & (USB_EP_NTOGGLE_MSK | USB_EP_TX_DTOG))__UINT_LEAST64_TYPE__ long long unsigned intRCC_CFGR_SW_HSI16 0x1_STDBOOL_H SIG_ATOMIC_MINUSB_CLR_EP_NTOGGLE_BIT_AND_SET(EP,BIT,EXTRA_BITS) CLR_REG_BIT_MSK_AND_SET(USB_EP_REG(EP), USB_EP_NTOGGLE_MSK, BIT, EXTRA_BITS)__STRICT_ANSI__ 1WINT_MINRCC_APB2ENR_TIM17EN (1 << 18)__INTPTR_TYPE__ int__DQ_FBIT__ 63__UACCUM_EPSILON__ 0x1P-16UKbInterfaceClassRCC_APB1SMENR1_LPTIM1SMEN (1 << 31)__INT_FAST16_WIDTH__ 32RCC_CCIPR_LPTIMxSEL_APB 0__FLT_HAS_INFINITY__ 1usb_interface_descriptorUSB_CNTR_LP_MODE 0x0004RCC_APB1RSTR1_TIM4RST (1 << 2)USB_SET_EP_RX_ADDR(EP,ADDR) SET_REG(USB_EP_RX_ADDR(EP), ADDR)uint16_tRCC_CICR_PLLRDYC (1 << 5)RCC_APB1ENR1_USART2EN (1 << 17)USB_FNR_REG (&MMIO32(USB_DEV_FS_BASE + 0x48))INT_FAST64_MAX __INT_FAST64_MAX__BIT12 (1<<12)USB_CNTR_CTRM 0x8000USB_BCDR_DCDET (1 << 4)USB_EP_RX_ADDR(ep) ((uint16_t *)(USB_PMA_BASE + (USB_GET_BTABLE + (ep) * 8 + 4) * 1))RCC_APB1RSTR1_PWRRST (1 << 28)USB_EP6 6_usbd_driverUSB_TRANSACTION_OUTITM_BASE (PPBI_BASE + 0x0000)__FP_FAST_FMAF32 1TIM15_BASE (PERIPH_BASE_APB2 + 0x4000)RCC_CR_PLLSAI2RDY (1 << 29)RCC_CFGR_MCO_LSI 0x6RCC_APB1SMENR1_LCDSMEN (1 << 9)RCC_CFGR_MCOPRE_DIV4 2USB_BCDR_PDEN (1 << 2)RCC_CIFR_LSIRDYF (1 << 0)USB_DT_CONFIGURATION 2__USBSTD_H __SFRACT_MIN__ (-0.5HR-0.5HR)__INT_LEAST16_WIDTH__ 16__USFRACT_MIN__ 0.0UHRRCC_APB1SMENR1_USART2SMEN (1 << 17)__INT_LEAST32_TYPE__ long int__DBL_HAS_INFINITY__ 1GPIO_PORT_G_BASE (PERIPH_BASE_AHB2 + 0x1800)BIT13 (1<<13)RCC_CCIPR_USART1SEL_APB 0RCC_APB1RSTR1_I2C3RST (1 << 23)__SHRT_MAX__ 0x7fffRCC_CFGR_PPRE2_NODIV 0x0USB_EP_REG(EP) (&MMIO32(USB_DEV_FS_BASE) + (EP))INTMAX_MIN (-INTMAX_MAX - 1)POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)LIBOPENCM3_ST_USBFS_H RCC_CSR_RMVF (1 << 23)__FLT32_HAS_INFINITY__ 1USB_EP_RX_DTOG 0x4000RCC_CSR_MSIRANGE_SHIFT 8RCC_BDCR_LSECSSON (1 << 5)RCC_CFGR_MCO_PLL 0x5USB_DT_CONFIGURATION_SIZE 9RCC_PLLCFGR_PLLP (1 << 17)set_address__INT_FAST64_MAX__ 0x7fffffffffffffffLLmax_size__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)RCC_APB1RSTR1_CAN1RST (1 << 25)__GCC_ATOMIC_CHAR_LOCK_FREE 2__UINT_FAST16_TYPE__ unsigned intRCC_BDCR_LSERDY (1 << 1)GNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsUSB_CLR_ISTR_SUSP() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SUSP)RCC_BDCR MMIO32(RCC_BASE + 0x90)MMIO8(addr) (*(volatile uint8_t *)(addr))__UINT64_MAX__ 0xffffffffffffffffULLRCC_CCIPR_UART5SEL_SHIFT 8__SIZEOF_INT__ 4__ARMEL__ 1__FLT32X_MAX_10_EXP__ 308BIT14 (1<<14)__WCHAR_WIDTH__ 32__SIG_ATOMIC_TYPE__ int__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1st_usbfs_ep_setupRCC_APB1RSTR1_TIM6RST (1 << 4)__ULFRACT_EPSILON__ 0x1P-32ULRRCC_CICR_MSIRDYC (1 << 2)control_stateRCC_CCIPR_I2CxSEL_APB 0__UINT16_C(c) cUSB_ISTR_ESOF 0x0100__PRAGMA_REDEFINE_EXTNAME 1__INT_LEAST64_TYPE__ long long intUSB_CLR_ISTR_RESET() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_RESET)RCC_CCIPR_UARTxSEL_APB RCC_CCIPR_USARTxSEL_APBLPUART1_BASE (PERIPH_BASE_APB1 + 0x8000)RCC_PLLCFGR_PLLSRC_MASK 0x3USB_REQ_SET_INTERFACE 11UINTMAX_MAXUSB_DT_INTERFACE_ASSOCIATION 11RCC_AHB2SMENR_GPIODSMEN (1 << 3)__HAVE_SPECULATION_SAFE_VALUE 1I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)USB_CNTR_PMAOVRM 0x4000UINTMAX_C(c) __UINTMAX_C(c)__QQ_FBIT__ 7BIT15 (1<<15)RCC_CFGR_PPRE1_DIV4 0x5__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xINT8_CRCC_CR_MSIRANGE_1MHZ 4RCC_AHB1SMENR_TSCSMEN (1 << 16)RCC_APB2RSTR_USART1RST (1 << 14)BIT5 (1<<5)USB_OTG_FS_BASE (0x50000000U + 0x00000)__BIGGEST_ALIGNMENT__ 8__ARM_ARCHRCC_APB1RSTR1_DAC1RST (1 << 29)RCC_AHB2RSTR_GPIOARST (1 << 0)RCC_CFGR_STOPWUCK_HSI16 (1 << 15)__FLT32_MIN_10_EXP__ (-37)RCC_CSR_MSIRANGE_8MHZ 7RCC_APB1ENR1_UART4EN (1 << 19)USB_FNR_LSOF_SHIFT 11USB_EP_RX_COUNT(ep) ((uint16_t *)(USB_PMA_BASE + (USB_GET_BTABLE + (ep) * 8 + 6) * 1))__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLKtype_maskUSB_SET_EP_ADDR(EP,ADDR) SET_REG(USB_EP_REG(EP), ((GET_REG(USB_EP_REG(EP)) & (USB_EP_NTOGGLE_MSK & (~USB_EP_ADDR))) | ADDR))__INT_LEAST16_MAX__ 0x7fffidVendorbIntervalRCC_CICR_PLLSAI2RDYC (1 << 7)__TA_IBIT__ 64USB_CLR_EP_STAT_OUT(EP) USB_CLR_EP_KIND(EP)RCC_CR_PLLON (1 << 24)BIT16 (1<<16)__SACCUM_IBIT__ 8__UINT16_TYPE__ short unsigned intRCC_AHB2SMENR_GPIOFSMEN (1 << 5)RCC_APB2RSTR_SYSCFGRST (1 << 0)__ULLFRACT_FBIT__ 64RCC_CFGR_MCOPRE_DIV8 3extra_string__FLT32_NORM_MAX__ 3.4028234663852886e+38F32__FLT32X_HAS_INFINITY__ 1FMC_BASE (0xa0000000U)RCC_BDCR_LSEDRV_MASK 0x3USB_FNR_LSOF (3 << USB_FNR_LSOF_SHIFT)__INT8_C(c) cidProductRCC_CR_MSIRANGE_32MHZ 10RCC_APB2ENR_SDMMC1EN (1 << 10)INFO_BASE (0x1fff0000U)__ARM_EABI__ 1RCC_PLLCFGR_PLLR_DIV4 1RCC_AHB2SMENR_GPIOASMEN (1 << 0)UINT64_C(c) __UINT64_C(c)__FLT32_EPSILON__ 1.1920928955078125e-7F32INT_LEAST8_MAX __INT_LEAST8_MAX__false 0USB_EP_RX_CTR 0x8000__FLT_MAX_EXP__ 128RCC_AHB2ENR_GPIOBEN (1 << 1)__INT64_MAX__ 0x7fffffffffffffffLLforce_nakBIT17 (1<<17)__ATOMIC_SEQ_CST 5RCC_APB1SMENR1_TIM7SMEN (1 << 5)DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7590)USB_GET_EP_RX_BUFF(ep) (USB_PMA_BASE + (uint8_t *)(USB_GET_EP_RX_ADDR(ep) * 1))RCC_CR MMIO32(RCC_BASE + 0x00)bcdUSB__FLT32X_MAX_EXP__ 1024SDMMC1_BASE (PERIPH_BASE_APB2 + 0x2800)__FLT32_MANT_DIG__ 24RCC_ICSCR_MSICAL_MASK 0xff__UINT_FAST8_TYPE__ unsigned intRCC_BDCR_RTCSEL_SHIFT 8USBD_PM_TOP 0x40__UTA_FBIT__ 64DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)__DBL_DIG__ 15INTPTR_MAX __INTPTR_MAX__RCC_AHB1SMENR_DMA2SMEN (1 << 1)__DECIMAL_DIG__ 17usbd_deviceaddrINT_FAST16_MININT_FAST8_MAX __INT_FAST8_MAX__RCC_CFGR_HPRE_MASK 0xfst_usbfs_set_ep_rx_bufsize__ARM_PCS_VFP 1DESIG_PACKAGE MMIO16((INFO_BASE + 0x7500))USB_ISTR_DIR 0x0010PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)__GCC_IEC_559_COMPLEX 0UINT64_CUSB_ENDPOINT_ADDR_IN(x) (0x80 | (x))RCC_APB1ENR1_LPTIM1EN (1 << 31)USBD_REQ_NOTSUPPRCC_PLLCFGR_PLLP_DIV17 RCC_PLLCFGR_PLLPBIT18 (1<<18)__LFRACT_IBIT__ 0RCC_BDCR_BDRST (1 << 16)__USER_LABEL_PREFIX__ USB_ENDPOINT_ATTR_SYNCTYPE 0x0CRCC_PLLCFGR_PLLM_SHIFT 0x4USB_LPMCSR_REG (&MMIO32(USB_DEV_FS_BASE + 0x54))RCC_APB1RSTR1_SPI3RST (1 << 15)INT64_MAX __INT64_MAX____QQ_IBIT__ 0usb_config_descriptorRCC_AHB3ENR_FMCEN (1 << 0)UINT_LEAST64_MAXUSB_ISTR_SUSP 0x0800SPI2_BASE (PERIPH_BASE_APB1 + 0x3800)USB_REQ_TYPE_ENDPOINT 0x02__DBL_MIN__ ((double)2.2250738585072014e-308L)RCC_CFGR_STOPWUCK_MSI (0 << 15)USB_REQ_TYPE_CLASS 0x20current_config__INT_FAST8_MAX__ 0x7fffffffRCC_APB2SMENR_SYSCFGSMEN (1 << 0)RCC_APB1SMENR1_TIM3SMEN (1 << 1)RCC_CR_PLLSAI2ON (1 << 28)__INT_FAST8_WIDTH__ 32RCC_CCIPR_I2CxSEL_HSI16 2RCC_AHB3SMENR_OFFSET 0x70__LDBL_MAX__ 1.7976931348623157e+308LINT_FAST32_MAXRCC_AHB3RSTR_OFFSET 0x30RCC_AHB2RSTR_ADCRST (1 << 13)__FLT32_MIN_EXP__ (-125)ST_VREFINT_CAL MMIO16((INFO_BASE + 0x75aa))user_callback_set_altsettingtypeinterface__UINT32_C(c) c ## UL__LDBL_MIN_EXP__ (-1021)__DBL_MIN_10_EXP__ (-307)IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)BIT7 (1<<7)GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000)RCC_PLLCFGR_PLLSRC_NONE 0__FLT_MIN_10_EXP__ (-37)st_usbfs_ep_write_packetRCC_CCIPR_USART2SEL_SHIFT 2RCC_APB1ENR1_TIM7EN (1 << 5)RCC_CCIPR_USARTxSEL_MASK 0x3RCC_APB1SMENR1_OFFSET 0x78INT_LEAST64_MAX __INT_LEAST64_MAX____UDQ_IBIT__ 0AES_BASE (0x50000000U + 0x60000)RCC_CCIPR_USART1SEL_HSI16 2RCC_AHB3RSTR_QSPIRST (1 << 8)__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)__PTRDIFF_WIDTH__ 32bDeviceSubClass__ULLACCUM_MIN__ 0.0ULLKRCC_APB1RSTR1_OFFSET 0x38__ARM_FEATURE_DOTPRODINT_FAST64_MAXWWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)RCC_CICR_LSIRDYC (1 << 0)RCC_APB1SMENR1_TIM4SMEN (1 << 2)USB_DT_STRING 3DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)__ULFRACT_IBIT__ 0RCC_APB2ENR_SAI1EN (1 << 21)__WINT_MAX__ 0xffffffffUUSB_EP_RX_STAT 0x3000USB_EP_KIND 0x0100__ARM_FP16_FORMAT_ALTERNATIVERCC_CCIPR_I2C2SEL_SHIFT 14UINTPTR_MAXINT32_C(c) __INT32_C(c)USB_DT_ENDPOINT 5__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1__UINT32_TYPE__ long unsigned int__FLT_EPSILON__ 1.1920928955078125e-7FbInterfaceNumberRCC_PLLCFGR_PLLR_MASK 0x3__UINT8_C(c) cUSB_REQ_CLEAR_FEATURE 1RCC_CFGR_SWS_HSE 0x2__ARM_FEATURE_NUMERIC_MAXMINRCC_CFGR_MCOPRE_MASK 0x7RCC_AHB3SMENR MMIO32(RCC_BASE + RCC_AHB3SMENR_OFFSET)rx_fifo_sizeINT8_C(c) __INT8_C(c)UINT16_MAX __UINT16_MAX__USB_ENDPOINT_ATTR_DATA 0x00RCC_APB2RSTR_TIM15RST (1 << 16)__ULLFRACT_MIN__ 0.0ULLRRCC_CCIPR_ADCSEL_NONE 0unsigned char__ARM_FEATURE_QRDMXRCC_CCIPR_LPTIMxSEL_LSE 3BIT8 (1<<8)__SFRACT_IBIT__ 0__ORDER_LITTLE_ENDIAN__ 1234RCC_CIFR_HSIRDYF (1 << 3)usbd_request_return_codesFMC3_BANK_BASE (0x80000000U)RCC_CCIPR_USARTxSEL_APB 0RCC_APB1ENR1_CAN1EN (1 << 25)RCC_PLLCFGR_PLLQ_DIV4 1__FLT_DIG__ 6RCC_AHB1SMENR_SRAM1SMEN (1 << 9)RCC_CR_PLLSAI1RDY (1 << 27)__DBL_MAX_EXP__ 1024__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULK__LLFRACT_IBIT__ 0__UINT_LEAST16_MAX__ 0xffff__SIZE_WIDTH__ 32USB_EP_RX_STAT_NAK 0x2000__ARM_FEATURE_FP16_FML__ULFRACT_FBIT__ 32RCC_APB1RSTR1_TIM3RST (1 << 1)BIT2 (1<<2)__SIZEOF_SIZE_T__ 4RCC_CCIPR_CLK48SEL_PLL 2RCC_AHB2ENR_ADCEN (1 << 13)INT_LEAST16_MAX __INT_LEAST16_MAX____UINT_LEAST64_MAX__ 0xffffffffffffffffULLRCC_APB1SMENR1_WWDGSMEN (1 << 11)RCC_CCIPR_USART1SEL_LSE 3RCC_CCIPR_LPUART1SEL_SYS 1NVIC_BASE (SCS_BASE + 0x0100)__SFRACT_FBIT__ 7DMA2_BASE (PERIPH_BASE_AHB1 + 0x0400)__LLACCUM_EPSILON__ 0x1P-31LLKRCC_CSR_OBLRSTF (1 << 25)PTRDIFF_MIN (-PTRDIFF_MAX - 1)RCC_APB1SMENR1_I2C2SMEN (1 << 22)usb_device_descriptorinit__DBL_DECIMAL_DIG__ 17__SIZEOF_LONG_LONG__ 8FIREWALL_BASE (PERIPH_BASE_APB2 + 0x1C00)SIZE_MAXRCC_CR_MSIRANGE_200KHZ 1WCHAR_MAX __WCHAR_MAX__RCC_AHB1RSTR_FLASHRST (1 << 8)__FLT32_DECIMAL_DIG__ 9USB_CLR_ISTR_WKUP() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_WKUP)GPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000)RCC_PLLCFGR_PLLSRC_MSI 1BIT9 (1<<9)RCC_AHB1RSTR_CRCRST (1 << 12)realsizeRCC_CR_MSIRANGE_SHIFT 4ep_stall_setUINT8_CRCC_CR_HSIKERON (1 << 9)UINTMAX_CUSB_REQ_SET_CONFIGURATION 9__WINT_TYPE__ unsigned intst_usbfs_ep_stall_getUINT_LEAST32_MAX __UINT_LEAST32_MAX__RCC_CFGR_MCO_MSI 0x2SCB_BASE (SCS_BASE + 0x0D00)RCC_APB1ENR1_I2C3EN (1 << 23)RCC_APB2ENR_SPI1EN (1 << 12)RCC_CSR_MSIRANGE_MASK 0xfUSB_EP_TX_STAT_NAK 0x0020RCC_AHB3SMENR_FMCSMEN (1 << 0)__INT16_MAX__ 0x7fffLIBOPENCM3_ST_USBFS_V2_H USB_ISTR_L1REQ (1 << 7)__FLT_MANT_DIG__ 24INT_LEAST64_MINRCC_AHB2ENR_RNGEN (1 << 18)__ULACCUM_FBIT__ 32TIM1_BASE (PERIPH_BASE_APB2 + 0x2C00)st_usbfs_endpoints_reset__FLT64_HAS_QUIET_NAN__ 1bFunctionSubClassUSB_EP_NTOGGLE_MSK (USB_EP_RX_CTR | USB_EP_SETUP | USB_EP_TYPE | USB_EP_KIND | USB_EP_TX_CTR | USB_EP_ADDR)wMaxPacketSizeRCC_BDCR_RTCSEL_NONE 0IDLE__ULACCUM_IBIT__ 32RCC_CFGR_PPRE2_DIV4 0x5__ARM_FEATURE_COPROC 15BIT20 (1<<20)bEndpointAddress__ARM_ARCH_PROFILE 77USB_LPMCSR_BESL_SHIFT 4STM32L4 1__INT_LEAST8_MAX__ 0x7f__UQQ_FBIT__ 8__FLT_MIN_EXP__ (-125)RCC_ICSCR_HSITRIM_SHIFT 24__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__RCC_CFGR_PPRE2_SHIFT 11__UINT64_C(c) c ## ULL__FRACT_IBIT__ 0__FLT_RADIX__ 2__USA_FBIT__ 16USB_ENDPOINT_ATTR_ASYNC 0x04__LDBL_IS_IEC_60559__ 2__FLT32X_DIG__ 15UINT_FAST8_MAX __UINT_FAST8_MAX__RCC_PLLCFGR_PLLR_DIV8 3USB_ISTR_RESET 0x0400__FLT_EVAL_METHOD_TS_18661_3__ 0__SQ_FBIT__ 31__UINTMAX_MAX__ 0xffffffffffffffffULL__LDBL_HAS_DENORM__ 1__USA_IBIT__ 16__ACCUM_EPSILON__ 0x1P-15KRCC_CCIPR_USART1SEL_MASK 0x3__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LKRCC_CFGR_HPRE_DIV16 0xbRCC_CR_MSIRANGE_400KHZ 2RCC_PLLCFGR_PLLQEN (1 << 20)RCC_CCIPR_UART4SEL_SHIFT 6INT_FAST32_MIN__FRACT_EPSILON__ 0x1P-15R__FLT32X_MANT_DIG__ 53USB_ISTR_ERR 0x2000RCC_PLLCFGR_PLLQ_DIV6 2__GCC_ATOMIC_INT_LOCK_FREE 2BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)RCC_PLLCFGR_PLLSRC_HSE 3__LDBL_DECIMAL_DIG__ 17__INT_WIDTH__ 32I2C3_BASE (PERIPH_BASE_APB1 + 0x5c00)RCC_CFGR_SW_SHIFT 0PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)USB_ENDPOINT_ATTR_INTERRUPT 0x03sizeMIN(a,b) ((a) < (b) ? (a) : (b))RCC_CFGR_MCO_HSI16 0x3RCC_AHB2ENR_GPIOAEN (1 << 0)CORESIGHT_LAR_KEY 0xC5ACCE55__FLT32_IS_IEC_60559__ 2__UDQ_FBIT__ 64__FLT64_DIG__ 15__ARM_NEONRCC_CFGR_MCO_SHIFT 24RCC_AHB2SMENR_AESSMEN (1 << 16)__ARM_ARCH_7EM__ 1BIT4 (1<<4)__INT16_C(c) cBIT30 (1<<30)INT_FAST8_MAXRCC_CFGR_PPRE1_NODIV 0x0RCC_CIFR_PLLRDYF (1 << 5)BIT22 (1<<22)__FLT32X_DECIMAL_DIG__ 17RCC_CSR_MSIRANGE_2MHZ 5__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2__INT16_TYPE__ short intRCC_APB2RSTR_DFSDMRST (1 << 24)RCC_CICR_CSSC (1 << 8)__bool_true_false_are_defined 1RCC_CCIPR_ADCSEL_PLLSAI1R 1__FRACT_MIN__ (-0.5R-0.5R)SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)usb_endpoint_descriptorSWPMI1_BASE (PERIPH_BASE_APB1 + 0x8800)__SHRT_WIDTH__ 16RCC_CCIPR_LPUART1SEL_SHIFT 10otgfs_usb_driver stm32f107_usb_driverRCC_CIER_PLLSAI2RDYIE (1 << 7)RCC_BDCR_LSEDRV_MEDLOW 1RCC_PLLCFGR_PLLR_DIV6 2__GCC_ATOMIC_LONG_LOCK_FREE 2_GCC_STDINT_H PTRDIFF_MAX __PTRDIFF_MAX____GXX_TYPEINFO_EQUALITY_INLINE 0RCC_CCIPR_USARTxSEL_HSI16 2RCC_CIER_MSIRDYIE (1 << 2)__UHQ_FBIT__ 16uint8_tRCC_CFGR MMIO32(RCC_BASE + 0x08)RCC_PLLSAI2_CFGR MMIO32(RCC_BASE + 0x14)num_altsettingRCC_CFGR_MCO_HSI48 0x8RCC_CFGR_SWS_PLL 0x3RCC_CSR_MSIRANGE_1MHZ 4bInterfaceCountRCC_CFGR_MCOPRE_DIV16 4RCC_BDCR_LSEDRV_LOW 0BIT23 (1<<23)QUADSPI_BANK_BASE (0x90000000U)RCC_BDCR_LSCOSEL (1 << 25)__FP_FAST_FMAF 1RCC_AHB1ENR_FLASHEN (1 << 8)__WCHAR_MIN__ 0URCC_APB2SMENR_TIM16SMEN (1 << 17)RCC_CIFR MMIO32(RCC_BASE + 0x1c)USB_FEAT_ENDPOINT_HALT 0RCC_APB2ENR_FWEN (1 << 7)RCC_APB2ENR_OFFSET 0x60USB_REQ_TYPE_DIRECTION 0x80RCC_CFGR_HPRE_NODIV 0x0__LLFRACT_EPSILON__ 0x1P-63LLR__INT_FAST64_WIDTH__ 64__FRACT_FBIT__ 15st_usbfs_ep_nak_setRCC_CFGR_PPRE1_DIV8 0x6__INT32_MAX__ 0x7fffffffL__CHAR_UNSIGNED__ 1ctrl_bufUSB_CNTR_FSUSP 0x0008BIT24 (1<<24)RCC_CFGR_SW_MSI 0x0__SCHAR_MAX__ 0x7f__GCC_HAVE_DWARF2_CFI_ASM 1USB_REQ_SET_SYNCH_FRAME 12INT16_MAX __INT16_MAX__TPIU_BASE (PPBI_BASE + 0x40000)__SACCUM_EPSILON__ 0x1P-7HKUSB_FNR_FN (0x7FF << 0)RCC_CCIPR_ADCSEL_SHIFT 28RCC_PLLCFGR_PLLSRC_HSI16 2USB_EP_TX_STAT_DISABLED 0x0000__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRRCC_CR_MSIRANGE_48MHZ 11st_usbfs_set_addressUSB_REQ_TYPE_IN 0x80cur_altsetting__HA_FBIT__ 7__UACCUM_MIN__ 0.0UKRCC_ICSCR_MSICAL_SHIFT 0INT_LEAST32_MAX __INT_LEAST32_MAX__RCC_APB1RSTR2 MMIO32(RCC_BASE + RCC_APB1RSTR2_OFFSET)__UFRACT_EPSILON__ 0x1P-16UR__FLT_HAS_QUIET_NAN__ 1UINT_FAST64_MAX __UINT_FAST64_MAX__USB_ENDPOINT_ADDR_OUT(x) (x)BIT25 (1<<25)ep_nak_set__FLT32X_NORM_MAX__ 1.7976931348623157e+308F32xRCC_PLLCFGR_PLLP_DIV7 0SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__USART1_BASE (PERIPH_BASE_APB2 + 0x3800)STIR_BASE (SCS_BASE + 0x0F00)RCC_PLLCFGR_PLLQ_SHIFT 21RCC_AHB2SMENR_SRAM2SMEN (1 << 9)RCC_AHB2ENR_AESEN (1 << 16)RCC_CR_MSIRANGE_24MHZ 9__SCHAR_WIDTH__ 8__ORDER_PDP_ENDIAN__ 3412__ATOMIC_ACQUIRE 2__INT_FAST32_WIDTH__ 32USB_BCDR_DPPU (1 << 15)__INT_FAST64_TYPE__ long long int__ACCUM_FBIT__ 15__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_QBIT 1CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)TIM16_BASE (PERIPH_BASE_APB2 + 0x4400)UINT32_C(c) __UINT32_C(c)__ARM_FEATURE_UNALIGNED 1RCC_CR_MSION (1 << 0)__SACCUM_MAX__ 0X7FFFP-7HKBIT26 (1<<26)INTMAX_MAXRCC_AHB2RSTR_GPIOFRST (1 << 5)st_usbfs_copy_to_pmRCC_CR_HSIRDY (1 << 10)__ACCUM_IBIT__ 16UINT64_MAX __UINT64_MAX__USB_CNTR_L1RESUME (1 << 5)__INTMAX_WIDTH__ 64USB_ENDPOINT_ATTR_BULK 0x02EXTI_BASE (PERIPH_BASE_APB2 + 0x0400)__ARM_FEATURE_LDREX 7__INT_LEAST64_WIDTH__ 64RCC_AHB2SMENR_GPIOCSMEN (1 << 2)RCC_CIFR_HSI48RDYF (1 << 10)RCC_ICSCR_HSICAL_SHIFT 16__LDBL_EPSILON__ 2.2204460492503131e-16LRCC_CCIPR_USARTxSEL_LSE 3RCC_CFGR_HPRE_DIV512 0xfUSB_SET_EP_STAT_OUT(EP) USB_SET_EP_KIND(EP)__ATOMIC_RELAXED 0RCC_AHB2SMENR_GPIOESMEN (1 << 4)__LFRACT_MAX__ 0X7FFFFFFFP-31LR__LDBL_MIN__ 2.2250738585072014e-308LRCC_CCIPR_USART1SEL_SHIFT 0RCC_APB1RSTR2_LPTIM2RST (1 << 5)SET_REG(REG,VAL) (*(REG) = (uint16_t)(VAL))USB_SET_EP_RX_STAT(EP,STAT) TOG_SET_REG_BIT_MSK_AND_SET(USB_EP_REG(EP), USB_EP_RX_STAT_TOG_MSK, STAT, USB_EP_RX_CTR | USB_EP_TX_CTR)__THUMB_INTERWORK__ 1RCC_AHB2ENR_GPIOHEN (1 << 7)PPBI_BASE (0xE0000000U)__UINT8_TYPE__ unsigned charBIT27 (1<<27)__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)wLengthRCC_CFGR_HPRE_DIV64 0xcstall__GCC_IEC_559 0__FLT_IS_IEC_60559__ 2__FLT32X_EPSILON__ 2.2204460492503131e-16F32xGPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800)RCC_CCIPR_SAI2SEL_SHIFT 24USB_BCDR_REG (&MMIO32(USB_DEV_FS_BASE + 0x58))USB_REQ_GET_DESCRIPTOR 6st_usbfs_ep_stall_setMMIO32(addr) (*(volatile uint32_t *)(addr))RCC_CCIPR_I2C3SEL_SHIFT 16RCC_APB1RSTR2_OFFSET 0x3c__ULLACCUM_FBIT__ 32RCC_AHB1ENR_CRCEN (1 << 12)GET_REG(REG) ((uint16_t) *(REG))usbd_endpoint_callbackBIT28 (1<<28)usb_iface_assoc_descriptor__SIZE_MAX__ 0xffffffffU__ATOMIC_RELEASE 3__ARM_BF16_FORMAT_ALTERNATIVERCC_APB1RSTR1_I2C1RST (1 << 21)__INT_LEAST8_WIDTH__ 8altsettingUSB_EP_TX_ADDR(ep) ((uint16_t *)(USB_PMA_BASE + (USB_GET_BTABLE + (ep) * 8 + 0) * 1))__GNUC__ 12RCC_CCIPR_SAIxSEL_PLLSAI1P 0st_usbfs_ep_read_packet__ARM_FEATURE_COPROCUINTMAX_MAX __UINTMAX_MAX__RCC_ICSCR MMIO32(RCC_BASE + 0x04)__INT_FAST16_TYPE__ intiManufacturer__INT_LEAST32_WIDTH__ 32RCC_AHB1RSTR_TSCRST (1 << 16)__UTQ_IBIT__ 0USB_EP_TYPE 0x0600__DBL_IS_IEC_60559__ 2USB_EP_SETUP 0x0800__UTA_IBIT__ 64__SIZEOF_WINT_T__ 4USB_CNTR_RESETM 0x0400RCC_AHB1RSTR_DMA2RST (1 << 1)RCC_CFGR_MCOPRE_DIV1 0st_usbfs_force_nakUSB_REQ_GET_INTERFACE 10RCC_CCIPR_LPUART1SEL_HSI16 2RCC_APB1ENR1_DAC1EN (1 << 29)RCC_APB1RSTR1_USART2RST (1 << 17)RCC_CCIPR MMIO32(RCC_BASE + 0x88)__ARM_FEATURE_SAT 1RCC_APB1ENR1_PWREN (1 << 28)USB_DT_OTG 9__INT_MAX__ 0x7fffffffep_setupRCC_CR_MSIPLLEN (1 << 2)__FLT_MAX__ 3.4028234663852886e+38F__INT_LEAST8_TYPE__ signed char__GXX_ABI_VERSION 1017BIT29 (1<<29)INT32_Cuser_callback_ctr__ARM_ARCH_ISA_THUMBUSB_CLR_ISTR_SOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SOF)__FLT64_IS_IEC_60559__ 2__SIZEOF_WCHAR_T__ 4INTMAX_C__USACCUM_MAX__ 0XFFFFP-8UHKUSB_REQ_GET_STATUS 0extra__INT8_MAX__ 0x7fRCC_AHB2ENR_OFFSET 0x4cRCC_APB2ENR_TIM8EN (1 << 13)__INT_LEAST32_MAX__ 0x7fffffffLUSB_EP0 0RCC_APB1SMENR1_OPAMPSMEN (1 << 30)RCC_APB2ENR MMIO32(RCC_BASE + RCC_APB2ENR_OFFSET)__USACCUM_EPSILON__ 0x1P-8UHKRCC_AHB2SMENR_GPIOBSMEN (1 << 1)__USFRACT_EPSILON__ 0x1P-8UHRRCC_CFGR_MCOPRE_SHIFT 28__INTMAX_C(c) c ## LL__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)SAI1_BASE (PERIPH_BASE_APB2 + 0x5400)__UINT_FAST16_MAX__ 0xffffffffU__ARM_ARCH_EXT_IDIV__ 1__UINT_FAST64_TYPE__ long long unsigned intCOMP_BASE (PERIPH_BASE_APB2 + 0x0200)RCC_AHB2RSTR_OTGFSRST (1 << 12)USB_BTABLE_BTABLE 0xFFF8BIT0 (1<<0)RCC_CR_HSION (1 << 8)RCC_BDCR_RTCEN (1 << 15)RCC_CFGR_PPRE1_DIV2 0x4USB_EP_TX_DTOG 0x0040RTC_BASE (PERIPH_BASE_APB1 + 0x2800)RCC_CIER_PLLSAI1RDYIE (1 << 6)USB_CONFIG_ATTR_DEFAULT 0x80RCC_AHB2ENR_GPIOEEN (1 << 4)RCC_CSR_SFTRSTF (1 << 28)RCC_CCIPR_CLK48SEL_MSI 3RCC_APB2RSTR_SAI1RST (1 << 21)LIBOPENCM3_MEMORYMAP_COMMON_H ADC1_BASE (0x50000000U + 0x40000)__UINT_FAST8_MAX__ 0xffffffffURCC_CIFR_PLLSAI2RDYF (1 << 7)ctrl_lenUSB_ENDPOINT_ATTR_FEEDBACK 0x10RCC_CIFR_HSERDYF (1 << 4)__SQ_IBIT__ 0LCD_BASE (PERIPH_BASE_APB1 + 0x2400)RCC_CCIPR_UARTxSEL_SYS RCC_CCIPR_USARTxSEL_SYSINT_FAST16_MIN (-INT_FAST16_MAX - 1)RCC_APB1RSTR1_TIM2RST (1 << 0)__ARM_FEATURE_SIMD32 1RCC_PLLCFGR_PLLSRC_SHIFT 0__UHQ_IBIT__ 0ST_TSENSE_CAL2_110C MMIO16((INFO_BASE + 0x75ca))RCC_APB2SMENR_TIM15SMEN (1 << 16)CLR_REG_BIT_MSK(REG,MSK,BIT) CLR_REG_BIT_MSK_AND_SET((REG), (MSK), (BIT), 0)disconnectRCC_APB1ENR1_TIM6EN (1 << 4)__thumb2__ 1__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1RCC_AHB2ENR MMIO32(RCC_BASE + RCC_AHB2ENR_OFFSET)__LACCUM_FBIT__ 31__ULACCUM_MIN__ 0.0ULKRCC_CFGR_HPRE_SHIFT 4RCC_CR_MSIRANGE_4MHZ 6RCC_CFGR_SW_HSE 0x2RCC_PLLCFGR_PLLQ_DIV8 3RCC_CCIPR_CLK48SEL_MASK 0x3RCC_CCIPR_ADCSEL_PLLSAI2R 2RCC_PLLCFGR_PLLN_SHIFT 0x8USB_DEV_STATUS_SELF_POWERED 0x01__LONG_MAX__ 0x7fffffffLUSB_REQ_SET_DESCRIPTOR 7__INT32_C(c) c ## LVREFBUF_BASE (PERIPH_BASE_APB2 + 0x0030)__FLT64_NORM_MAX__ 1.7976931348623157e+308F64USB_GET_EP_RX_ADDR(EP) GET_REG(USB_EP_RX_ADDR(EP))INTPTR_MAXUSB_CLR_EP_KIND(EP) SET_REG(USB_EP_REG(EP), (GET_REG(USB_EP_REG(EP)) & (USB_EP_NTOGGLE_MSK & (~USB_EP_KIND))))RCC_CICR_HSIRDYC (1 << 3)bLengthUSB_CNTR_ERRM 0x2000INT_FAST16_MAX __INT_FAST16_MAX__RCC_APB1SMENR1_I2C3SMEN (1 << 23)USB_REQ_TYPE_OUT 0x0RCC_ICSCR_HSICAL_MASK 0xffRCC_CICR_LSECSSC (1 << 9)RCC_PLLPEN (1 << 16)__FLT32X_IS_IEC_60559__ 2RCC_APB1RSTR1_LPTIM1RST (1 << 31)RCC_APB1SMENR1_TIM5SMEN (1 << 3)RCC_CFGR_MCO_HSE 0x4UINT_FAST32_MAX __UINT_FAST32_MAX__RCC_CIER_LSE_CSSIE (1 << 9)bRequestUINT32_CTIM2_BASE (PERIPH_BASE_APB1 + 0x0000)_usbd_deviceshort unsigned intRCC_AHB2RSTR_AESRST (1 << 16)signed charRCC_CCIPR_LPTIMxSEL_MASK 0x3st_usbfs_copy_from_pmrxbcntUSB_GET_EP_TX_COUNT(EP) GET_REG(USB_EP_TX_COUNT(EP))USB_EP_RX_STAT_TOG_MSK (USB_EP_RX_STAT | USB_EP_NTOGGLE_MSK)bFunctionClassLIBOPENCM3_RCC_H USB_CNTR_FRES 0x0001RCC_APB2SMENR_SAI2SMEN (1 << 22)BIT6 (1<<6)INTMAX_C(c) __INTMAX_C(c)WINT_MAX __WINT_MAX____ULLACCUM_EPSILON__ 0x1P-32ULLKDESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 0x14)__CHAR_BIT__ 8INTMAX_MINRCC_APB1RSTR1_UART4RST (1 << 19)RCC_CR_MSIRANGE_2MHZ 5RCC_CFGR_SWS_MSI 0x0RCC_CFGR_PPRE1_SHIFT 8toggle_maskRCC_APB2RSTR_TIM16RST (1 << 17)bDeviceProtocolEND_DECLS USB_ENDPOINT_ATTR_IMPLICIT_FEEDBACK_DATA 0x20BEGIN_DECLS endpointUSB_CNTR_SOFM 0x0200usb_control_stateRCC_BDCR_LSESYSDIS (1 << 7)RCC_CFGR_PPRE2_DIV8 0x6__CHAR16_TYPE__ short unsigned int_usbd_transaction__FLT64_MIN__ 2.2250738585072014e-308F64__INTPTR_MAX__ 0x7fffffff__ARM_FP16_ARGSRCC_APB2RSTR_TIM8RST (1 << 13)FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000)USB_BCDR_PS2DET (1 << 7)__GCC_ATOMIC_POINTER_LOCK_FREE 2USB_LPMCSR_BESL (15 << USB_LPMCSR_BESL_SHIFT)__ARM_FEATURE_LDREX__DBL_MAX__ ((double)1.7976931348623157e+308L)RCC_CFGR_MCOPRE_DIV2 1USB_CLR_EP_TX_CTR(EP) USB_CLR_EP_NTOGGLE_BIT_AND_SET(EP, USB_EP_TX_CTR, USB_EP_RX_CTR)__FLT32_MAX_10_EXP__ 38USB_EP_TYPE_INTERRUPT 0x0600iface_assocRCC_CIER_HSIRDYIE (1 << 3)USB_DT_DEVICE_SIZE sizeof(struct usb_device_descriptor)stateITR_BASE (SCS_BASE + 0x0000)INT_LEAST8_MAXiFunction__WINT_WIDTH__ 32bInterfaceSubClassRCC_APB1RSTR2_SWPMI1RST (1 << 2)PERIPH_BASE (0x40000000U)fifo_mem_topiConfigurationUINT_FAST8_MAX__ARM_FP16_FORMAT_IEEERCC_CIFR_CSSF (1 << 8)RCC_APB1ENR1_TIM3EN (1 << 1)__USES_INITFINI__ 1USBD_REQ_NEXT_CALLBACK__FLT64_MAX_EXP__ 1024RCC_APB1ENR1_LCDEN (1 << 9)USB_BCDR_BCDEN (1 << 0)RCC_CFGR_PPRE1_DIV16 0x7USB_EP1 1callback__REGISTER_PREFIX__ RCC_CFGR_PPRE2_MASK 0x7RCC_BDCR_RTCSEL_LSE 1__USFRACT_MAX__ 0XFFP-8UHRPERIPH_BASE_AHB2 (0x48000000U)CRS_BASE (PERIPH_BASE_APB1 + 0x6000)RCC_CRRCR MMIO32(RCC_BASE + 0x98)__FLT32_MAX__ 3.4028234663852886e+38F32STALLEDBIT1 (1<<1)USB_DT_OTHER_SPEED_CONFIGURATION 7RCC_AHB2SMENR_OTGFSSMEN (1 << 12)RCC_AHB2SMENR_RNGSMEN (1 << 18)__FRACT_MAX__ 0X7FFFP-15RRCC_APB1ENR2_SWPMI1EN (1 << 2)__USQ_FBIT__ 32__INT_FAST8_TYPE__ intLAST_DATA_OUTUINT8_C(c) __UINT8_C(c)UINT32_MAXRCC_APB1SMENR1_SPI3SMEN (1 << 15)__ARM_FEATURE_BF16_SCALAR_ARITHMETICRCC_CR_MSIRANGE_16MHZ 8USB_DT_DEVICE_QUALIFIER 6RCC_CSR MMIO32(RCC_BASE + 0x94)__STDC_HOSTED__ 1__UINTMAX_C(c) c ## ULLUSB_CONFIG_ATTR_SELF_POWERED 0x40GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400)user_callback_reset__UACCUM_MAX__ 0XFFFFFFFFP-16UKRCC_CSR_LPWRRSTF (1 << 31)FMC1_BANK_BASE (0x60000000U)RCC_CFGR_HPRE_DIV4 0x9long intRCC_CFGR_MCO_SYSCLK 0x1__WINT_MIN__ 0U__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)USB_SET_EP_TX_STAT(EP,STAT) TOG_SET_REG_BIT_MSK_AND_SET(USB_EP_REG(EP), USB_EP_TX_STAT_TOG_MSK, STAT, USB_EP_RX_CTR | USB_EP_TX_CTR)INT16_MAX__DBL_HAS_DENORM__ 1TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1__FLT64_MAX_10_EXP__ 308USB_SET_EP_TX_ADDR(EP,ADDR) SET_REG(USB_EP_TX_ADDR(EP), ADDR)__PTRDIFF_TYPE__ intctrl_buf_lenUSB_BTABLE_REG (&MMIO32(USB_DEV_FS_BASE + 0x50))__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2__USACCUM_FBIT__ 8__GNUC_STDC_INLINE__ 1UINT64_MAXUSB_CNTR_PWDN 0x0002__ARM_FPset_address_before_statusRCC_APB2ENR_TIM1EN (1 << 11)RCC_AHB2SMENR_GPIOGSMEN (1 << 6)RCC_CICR_LSERDYC (1 << 1)RCC_CSR_BORRSTF (1 << 27)RCC_CIER_LSERDYIE (1 << 1)RCC_CCIPR_I2CxSEL_MASK 0x3RCC_APB2SMENR MMIO32(RCC_BASE + RCC_APB2SMENR_OFFSET)__UTQ_FBIT__ 128__USB_PRIVATE_H LIBOPENCM3_CM3_COMMON_H RCC_AHB2SMENR MMIO32(RCC_BASE + RCC_AHB2SMENR_OFFSET)RCC_APB1ENR1_I2C2EN (1 << 22)RCC_CCIPR_CLK48SEL_HSI48 0RCC_CCIPR_LPTIMxSEL_LSI 1RCC_CIFR_PLLSAI1RDYF (1 << 6)__ARM_FEATURE_DSP 1__ARM_FEATURE_CRYPTORCC_CFGR_HPRE_DIV256 0xeFPB_BASE (PPBI_BASE + 0x2000)RCC_CCIPR_LPTIM2SEL_SHIFT 20__FLT32_HAS_DENORM__ 1RCC_CFGR_MCO_MASK 0xfRCC_AHB2RSTR_GPIOHRST (1 << 7)typelookupINT32_MIN (-INT32_MAX - 1)__ARM_FEATURE_FP16_SCALAR_ARITHMETIC__SACCUM_FBIT__ 7__HQ_FBIT__ 15__LLACCUM_IBIT__ 32USB_REQ_GET_CONFIGURATION 8uint32_tUSB_EP_TYPE_CONTROL 0x0200USB_DADDR_EF (1 << 7)__LLFRACT_FBIT__ 63__LDBL_DIG__ 15__CHAR32_TYPE__ long unsigned intRCC_APB1SMENR2 MMIO32(RCC_BASE + RCC_APB1SMENR2_OFFSET)SIG_ATOMIC_MIN __SIG_ATOMIC_MIN__RCC_CFGR_SW_PLL 0x3__GCC_ATOMIC_SHORT_LOCK_FREE 2RCC_AHB2ENR_GPIOGEN (1 << 6)RCC_AHB1ENR_DMA2EN (1 << 1)__ULFRACT_MAX__ 0XFFFFFFFFP-32ULRRCC_CRRCR_HSI48ON (1 << 0)__SIZEOF_POINTER__ 4RCC_CCIPR_LPUART1SEL_APB 0__GCC_ASM_FLAG_OUTPUTS__ 1USB_LPMCSR_LPMEN (1 << 0)RCC_APB1SMENR1_CAN1SMEN (1 << 25)CLR_REG_BIT_MSK_AND_SET(REG,MSK,BIT,EXTRA_BITS) SET_REG((REG), (GET_REG((REG)) & (MSK) & (~(BIT))) | (EXTRA_BITS))RCC_CCIPR_LPUART1SEL_MASK 0x3RCC_CFGR_HPRE_DIV128 0xdUINT_LEAST64_MAX __UINT_LEAST64_MAX____UINTMAX_TYPE__ long long unsigned intRCC_APB2SMENR_TIM17SMEN (1 << 18)__INTPTR_WIDTH__ 32INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)INT_FAST16_MAXGPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0c00)USART3_BASE (PERIPH_BASE_APB1 + 0x4800)INTPTR_MINextralenRCC_CCIPR_SAI1SEL_SHIFT 22RCC_CR_MSIRANGE_MASK 0xfCLR_REG_BIT(REG,BIT) SET_REG((REG), (~(BIT)))RCC_AHB1RSTR MMIO32(RCC_BASE + RCC_AHB1RSTR_OFFSET)USB_ENDPOINT_ATTR_TYPE 0x03__FLT64_HAS_INFINITY__ 1__GCC_DESTRUCTIVE_SIZE 64RCC_PLLCFGR_PLLREN (1<<24)RCC_BDCR_LSECSSD (1 << 6)USB_DT_INTERFACE_POWER 8__FINITE_MATH_ONLY__ 0RCC_CCIPR_CLK48SEL_SHIFT 26__LONG_LONG_MAX__ 0x7fffffffffffffffLLRCC_CR_PLLRDY (1 << 25)USB_ENDPOINT_ATTR_CONTROL 0x00__ATOMIC_ACQ_REL 4RCC_AHB1RSTR_DMA1RST (1 << 0)__GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"USB_DT_INTERFACE_ASSOCIATION_SIZE sizeof(struct usb_iface_assoc_descriptor)MMIO64(addr) (*(volatile uint64_t *)(addr))__STDC_VERSION__ 199901L__LFRACT_MIN__ (-0.5LR-0.5LR)PTRDIFF_MAXRCC_CFGR_MCO_NOCLK 0x0__LLFRACT_MIN__ (-0.5LLR-0.5LLR)RCC_CCIPR_ADCSEL_MASK 0x3USB_ENDPOINT_ATTR_ADAPTIVE 0x08INT64_C(c) __INT64_C(c)__GCC_ATOMIC_LLONG_LOCK_FREE 1__ULACCUM_EPSILON__ 0x1P-32ULKUSB_GET_EP_TX_BUFF(ep) (USB_PMA_BASE + (uint8_t *)(USB_GET_EP_TX_ADDR(ep) * 1))usbd_set_config_callbackINT_LEAST32_MIN (-INT_LEAST32_MAX - 1)__LONG_LONG_WIDTH__ 64iInterfaceRCC_AHB3ENR_OFFSET 0x50RCC_CFGR_PPRE2_DIV2 0x4bAlternateSetting__VERSION__ "12.2.1 20221205"__FLT64_EPSILON__ 2.2204460492503131e-16F64USB_EP2 2USB_DEV_STATUS_REMOTE_WAKEUP 0x02GPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400)__UINT_LEAST16_TYPE__ short unsigned int__LDBL_HAS_QUIET_NAN__ 1RCC_CR_CSSON (1 << 19)__WCHAR_MAX__ 0xffffffffUUART5_BASE (PERIPH_BASE_APB1 + 0x5000)USB_REQ_TYPE_VENDOR 0x40RCC_BDCR_LSEON (1 << 0)USB_FEAT_DEVICE_REMOTE_WAKEUP 1RCC_APB2ENR_DFSDMEN (1 << 24)__ULLACCUM_IBIT__ 32RCC_APB2SMENR_SAI1SMEN (1 << 21)__LDBL_MANT_DIG__ 53RCC_APB2ENR_USART1EN (1 << 14)RCC_BDCR_LSEDRV_SHIFT 3RCC_AHB2RSTR_OFFSET 0x2c__DQ_IBIT__ 0__FLT64_MAX__ 1.7976931348623157e+308F64INT_LEAST8_MINUSB_EP_TYPE_BULK 0x0000RCC_CRRCR_HSI48RDY (1 << 1)CORESIGHT_LSR_SLI (1<<0)__UQQ_IBIT__ 0LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))USB_DT_DEVICE 1DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x75e0)USB_EP_ADDR 0x000F__ARM_FEATURE_CDEbFirstInterfaceRCC_AHB2ENR_GPIODEN (1 << 3)RCC_CCIPR_USART1SEL_SYS 1SYS_TICK_BASE (SCS_BASE + 0x0010)RCC_APB1ENR2_LPTIM2EN (1 << 5)USB_ISTR_REG (&MMIO32(USB_DEV_FS_BASE + 0x44))__UINT_LEAST32_MAX__ 0xffffffffULLIBOPENCM3_TOOLS_H STATUS_OUT__ACCUM_MIN__ (-0X1P15K-0X1P15K)__ORDER_BIG_ENDIAN__ 4321__ARM_FEATURE_CMSEbFunctionProtocolRCC_AHB2ENR_GPIOFEN (1 << 5)PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)__UFRACT_MAX__ 0XFFFFP-16URRCC_CR_PLLSAI1ON (1 << 26)I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)__UINT_FAST32_TYPE__ unsigned intRCC_AHB1ENR_OFFSET 0x48__SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)RCC_APB1ENR1_SPI3EN (1 << 15)USB_FNR_LCK (1 << 13)true 1USB_REQ_TYPE_RECIPIENT 0x1FRCC_APB1ENR1_TIM5EN (1 << 3)MAX_USER_CONTROL_CALLBACK 4iProductusb_interfaceUSB_REQ_TYPE_DEVICE 0x00USB_CONFIG_ATTR_REMOTE_WAKEUP 0x20USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6c00)complete__FLT_DECIMAL_DIG__ 9BIT31 (1<<31)__INT32_TYPE__ long int__USACCUM_IBIT__ 8GPIO_PORT_H_BASE (PERIPH_BASE_AHB2 + 0x1c00)USB_EP_TX_STAT_VALID 0x0030RCC_AHB3ENR MMIO32(RCC_BASE + RCC_AHB3ENR_OFFSET)RCC_CCIPR_I2CxSEL_SYS 1__ULFRACT_MIN__ 0.0ULRusb_setup_dataRCC_AHB1ENR MMIO32(RCC_BASE + RCC_AHB1ENR_OFFSET)__TQ_FBIT__ 127USB_REQ_TYPE_TYPE 0x60__UINTPTR_TYPE__ unsigned intBIT21 (1<<21)RCC_AHB2RSTR_GPIOCRST (1 << 2)bcdDeviceuser_control_callbackUINT8_MAX __UINT8_MAX__RCC_APB1RSTR1 MMIO32(RCC_BASE + RCC_APB1RSTR1_OFFSET)USB_GET_EP_TX_ADDR(EP) GET_REG(USB_EP_TX_ADDR(EP))__LFRACT_FBIT__ 31bMaxPacketSize0driver__ARM_FEATURE_BF16_VECTOR_ARITHMETICUSB_DT_DEBUG 10configUSB_GET_BTABLE GET_REG(USB_BTABLE_REG)USB_ISTR_WKUP 0x1000RCC_BDCR_LSEBYP (1 << 2)UINT8_MAXUSB_CLR_ISTR_PMAOVR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_PMAOVR)RCC_AHB3ENR_QSPIEN (1 << 8)RCC_APB1SMENR1_SPI2SMEN (1 << 14)USBD_REQ_HANDLED__ARM_SIZEOF_MINIMAL_ENUM 1RCC_APB2RSTR_OFFSET 0x40RCC_AHB1RSTR_OFFSET 0x28USB_REQ_TYPE_STANDARD 0x00RCC_CSR_MSIRANGE_4MHZ 6USB_FNR_RXDP (1 << 15)INT_LEAST16_MAXbmRequestTypeRCC_APB1ENR1 MMIO32(RCC_BASE + RCC_APB1ENR1_OFFSET)DATA_IN__DA_FBIT__ 31__FLT32_MIN__ 1.1754943508222875e-38F32wValueSIZE_MAX __SIZE_MAX__INT8_MINUSB_CLR_ISTR_ESOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ESOF)usbd_set_altsetting_callback__GCC_ATOMIC_BOOL_LOCK_FREE 2INT_FAST64_MIN__INT_FAST32_MAX__ 0x7fffffffRCC_AHB2SMENR_ADCSMEN (1 << 13)__FLT_MAX_10_EXP__ 38RCC_APB2RSTR_SPI1RST (1 << 12)WINT_MIN __WINT_MIN____DA_IBIT__ 32fifo_mem_top_ep0__VFP_FP__ 1RCC_CCIPR_ADCSEL_SYS 3__ARM_ASM_SYNTAX_UNIFIED__ 1/build/libopencm3/lib/stm32/l4RCC_CSR_FWRSTF (1 << 24)INT32_MAX__ARM_FP 4RCC_CSR_WWDGRSTF (1 << 30)RCC_PLLCFGR_PLLM_MASK 0x7__UFRACT_MIN__ 0.0URUSB_BCDR_PDET (1 << 5)RCC_APB1SMENR1_UART5SMEN (1 << 20)RCC_APB1ENR2_OFFSET 0x5cRCC_APB2SMENR_DFSDMSMEN (1 << 24)RCC_BDCR_RTCSEL_HSEDIV32 3__GCC_CONSTRUCTIVE_SIZE 64__ARM_SIZEOF_WCHAR_T 4RCC_AHB1ENR_TSCEN (1 << 16)TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)__SIZEOF_DOUBLE__ 8__UINT_FAST32_MAX__ 0xffffffffU__LDBL_MAX_EXP__ 1024USB_EP3 3USB_DADDR_ADDR 0x007FRCC_BDCR_RTCSEL_MASK 0x3QUADSPI_BASE (0xa0001000U)USB_EP_TX_STAT_TOG_MSK (USB_EP_TX_STAT | USB_EP_NTOGGLE_MSK)bNumConfigurationsRCC_CR_HSERDY (1 << 17)__ARM_FEATURE_FP16_VECTOR_ARITHMETIC__ARM_32BIT_STATE 1ep_stall_getRCC_APB1RSTR1_USART3RST (1 << 18)RCC_AHB2RSTR_GPIOERST (1 << 4)LAST_DATA_IN__INTMAX_MAX__ 0x7fffffffffffffffLLUSB_DT_ENDPOINT_SIZE 7INT64_MAXbInterfaceProtocolRCC_APB1ENR1_TIM2EN (1 << 0)UINT_LEAST16_MAX __UINT_LEAST16_MAX__RCC_CR_HSIASFS (1 << 11)__LONG_WIDTH__ 32RCC_CICR_HSERDYC (1 << 4)__OPTIMIZE__ 1usbd_control_callbackUSB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x6800)__arm__ 1PTRDIFF_MINRCC_APB1RSTR1_UART5RST (1 << 20)USB_CNTR_SUSPM 0x0800USB_REQ_TYPE_OTHER 0x03RCC_CR_HSEBYP (1 << 18)UINT32_MAX __UINT32_MAX____OPTIMIZE_SIZE__ 1USB_CNTR_WKUPM 0x1000RCC_APB2SMENR_TIM8SMEN (1 << 13)RCC_CFGR_PPRE1_MASK 0x7ep_resetpollUSB_ISTR_PMAOVR 0x4000INT_FAST32_MIN (-INT_FAST32_MAX - 1)USB_GET_EP_RX_COUNT(EP) GET_REG(USB_EP_RX_COUNT(EP))__INT8_TYPE__ signed char__LDBL_DENORM_MIN__ 4.9406564584124654e-324LSYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000)RCC_CR_MSIRANGE_100KHZ 0RCC_APB1RSTR1_OPAMPRST (1 << 30)RCC_APB1SMENR2_SWPMI1SMEN (1 << 2)RCC_CIER_HSERDYIE (1 << 4)USB_SET_EP_TX_COUNT(EP,COUNT) SET_REG(USB_EP_TX_COUNT(EP), COUNT)LPTIM2_BASE (PERIPH_BASE_APB1 + 0x9400)UINT_LEAST32_MAX__ACCUM_MAX__ 0X7FFFFFFFP-15KRCC_CIFR_LSECSSF (1 << 9)../common/st_usbfs_core.cRCC_APB1SMENR1_TIM2SMEN (1 << 0)__FLT64_MIN_EXP__ (-1021)__INT_FAST32_TYPE__ intuser_callback_sofRCC_APB1RSTR1_LCDRST (1 << 9)DAC_BASE (PERIPH_BASE_APB1 + 0x7400)RCC_APB2ENR_TIM16EN (1 << 17)__FLT32_HAS_QUIET_NAN__ 1RCC_APB2RSTR_SAI2RST (1 << 22)__ARM_NEON__TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)USART2_BASE (PERIPH_BASE_APB1 + 0x4400)RCC_BDCR_LSCOEN (1 << 24)USB_REQ_SET_FEATURE 3stringsTOG_SET_REG_BIT_MSK(REG,MSK,BIT) TOG_SET_REG_BIT_MSK_AND_SET((REG), (MSK), (BIT), 0)CORESIGHT_LSR_SLK (1<<1)INT8_MAXRCC_CIER_LSIRDYIE (1 << 0)RCC_CSR_LSIRDY (1 << 1)CORESIGHT_LAR_OFFSET 0xfb0RCC_CFGR_MCO_LSE 0x7RCC_APB1ENR1_I2C1EN (1 << 21)WCHAR_MIN__FLT32X_MIN_EXP__ (-1021)LIBOPENCM3_ST_USBFS_COMMON_H USB_ISTR_CTR 0x8000RNG_BASE (0x50000000U + 0x60800)__ARM_ARCH_PROFILERCC_CCIPR_SAIxSEL_MASK 0x3__LACCUM_IBIT__ 32RCC_CCIPR_LPTIM1SEL_SHIFT 18RCC_CCIPR_LPUART1SEL_LSE 3RCC_AHB2RSTR_GPIOGRST (1 << 6)MMIO16(addr) (*(volatile uint16_t *)(addr))st_usbfs_devSCS_BASE (PPBI_BASE + 0xE000)INT16_MINWCHAR_MIN __WCHAR_MIN__RCC_CCIPR_UARTxSEL_MASK RCC_CCIPR_USARTxSEL_MASKlong long unsigned int__SIZEOF_SHORT__ 2UINTPTR_MAX __UINTPTR_MAX__INT8_MAX __INT8_MAX__RCC_PLLCFGR_PLLM(x) ((x)-1)USB_REQ_SET_ADDRESS 5__UINT8_MAX__ 0xffUSB_SET_EP_RX_COUNT(EP,COUNT) SET_REG(USB_EP_RX_COUNT(EP), COUNT)USB_ISTR_EP_ID 0x000FINT64_CTOG_SET_REG_BIT_MSK_AND_SET(REG,MSK,BIT,EXTRA_BITS) do { register uint16_t toggle_mask = GET_REG(REG) & (MSK); toggle_mask ^= BIT; SET_REG((REG), toggle_mask | (EXTRA_BITS)); } while (0)RCC_APB1SMENR1_TIM6SMEN (1 << 4)RCC_CFGR_SW_MASK 0x3chardescRCC_CR_MSIRANGE_800KHZ 3BIT19 (1<<19)UINT_FAST16_MAXRCC_APB1RSTR1_I2C2RST (1 << 22)__FLT64_DECIMAL_DIG__ 17__UINTPTR_MAX__ 0xffffffffU__ARM_FEATURE_COMPLEXRCC_AHB1ENR_DMA1EN (1 << 0)bDescriptorTypeUSB_SET_EP_TYPE(EP,TYPE) SET_REG(USB_EP_REG(EP), (GET_REG(USB_EP_REG(EP)) & (USB_EP_NTOGGLE_MSK & (~USB_EP_TYPE))) | TYPE)USB_EP_RX_STAT_STALL 0x1000__SFRACT_EPSILON__ 0x1P-7HR__ATOMIC_CONSUME 1__FLT_MIN__ 1.1754943508222875e-38F__INT_LEAST16_TYPE__ short intRCC_PLLCFGR_PLLQ_DIV2 0RCC_APB1SMENR2_LPTIM2SMEN (1 << 5)INT32_MAX __INT32_MAX__USB_TRANSACTION_SETUP__USFRACT_FBIT__ 8USB_TRANSACTION_INUSB_FEAT_TEST_MODE 2RCC_CIFR_MSIRDYF (1 << 2)RCC_CR_MSIRDY (1 << 1)__GCC_ATOMIC_WCHAR_T_LOCK_FREE 2RCC_CCIPR_SAIxSEL_PLLSAI2P 1RCC_APB2RSTR_TIM17RST (1 << 18)RCC_APB1RSTR1_TIM5RST (1 << 3)__SIZEOF_PTRDIFF_T__ 4USB_DADDR_REG (&MMIO32(USB_DEV_FS_BASE + 0x4C))RCC_APB1ENR1_USART3EN (1 << 18)RCC_CIER_PLLRDYIE (1 << 5)user_callback_suspendFMC_QUADSPI_BASE (0xA0000000U)RCC_APB1ENR1_UART5EN (1 << 20)bConfigurationValueRCC_CCIPR_USARTxSEL_SYS 1DMA1_BASE (PERIPH_BASE_AHB1 + 0x0000)RCC_APB1RSTR1_SPI2RST (1 << 14)RCC_CFGR_HPRE_DIV8 0xa__FLT32X_HAS_QUIET_NAN__ 1USB_LPMCSR_REMWAKE (1 << 3)__GNUC_EXECUTION_CHARSET_NAME "UTF-8"USB_EP_TX_CTR 0x0080RCC_AHB3RSTR MMIO32(RCC_BASE + RCC_AHB3RSTR_OFFSET)USB_EP4 4RCC_CCIPR_SAIxSEL_PLL 2RCC_CSR_RESET_FLAGS (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF | RCC_CSR_IWDGRSTF | RCC_CSR_SFTRSTF | RCC_CSR_BORRSTF | RCC_CSR_PINRSTF | RCC_CSR_OBLRSTF | RCC_CSR_FWRSTF)__SIG_ATOMIC_WIDTH__ 32__DBL_MIN_EXP__ (-1021)USB_EP_RX_STAT_DISABLED 0x0000bNumEndpointsRCC_BASE (PERIPH_BASE_AHB1 + 0x1000)MPU_BASE (SCS_BASE + 0x0D90)USB_EP_TYPE_ISO 0x0400RCC_APB2RSTR_TIM1RST (1 << 11)UINT16_MAXINT_LEAST16_MINRCC_PLLCFGR_PLLR_SHIFT 25__LDBL_MAX_10_EXP__ 308SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)GET_REG_BIT(REG,BIT) (GET_REG(REG) & (BIT))USB_DT_INTERFACE_SIZE 9RCC_AHB3RSTR_FMCRST (1 << 0)RCC_ICSCR_MSITRIM_SHIFT 8USB_DT_INTERFACE 4__INT64_TYPE__ long long intRCC_CFGR_SWS_HSI16 0x1INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)__ARM_FEATURE_CRC32__TA_FBIT__ 63__LDBL_NORM_MAX__ 1.7976931348623157e+308Lbool _Bool__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64RCC_ICSCR_HSITRIM_MASK 0x1fuser_callback_set_config__UINT_LEAST32_TYPE__ long unsigned intRCC_CCIPR_I2C1SEL_SHIFT 12_usbd_resetSAI2_BASE (PERIPH_BASE_APB2 + 0x5800)RCC_AHB2RSTR_RNGRST (1 << 18)USB_BCDR_SDEN (1 << 3)RCC_APB1ENR1_OPAMPEN (1 << 30)INT32_MIN__HA_IBIT__ 8INT16_C(c) __INT16_C(c)RCC_CR_MSIRGSEL (1 << 3)INT8_MIN (-INT8_MAX - 1)__FLT32X_HAS_DENORM__ 1TSC_BASE (PERIPH_BASE_AHB1 + 0x4000)INT16_CRCC_CR_MSIRANGE_8MHZ 7pm_topRCC_APB2SMENR_USART1SMEN (1 << 14)RCC_PLLCFGR MMIO32(RCC_BASE + 0x0c)__HQ_IBIT__ 0long long int__FLT_EVAL_METHOD__ 0RCC_CIFR_LSERDYF (1 << 1)RCC_CR_HSEON (1 << 16)USB_CNTR_RESUME 0x0010RCC_APB2ENR_SAI2EN (1 << 22)__UHA_FBIT__ 8RCC_CSR_PINRSTF (1 << 26)__ARM_FEATURE_CLZ 1INT_LEAST32_MAXUSB_EP_TX_STAT_STALL 0x0010RCC_APB2SMENR_TIM1SMEN (1 << 11)__ARM_FEATURE_FMA 1RCC_APB1RSTR1_TIM7RST (1 << 5)__ARM_NEON_FP__FDPIC__CORESIGHT_LSR_OFFSET 0xfb4INT64_MIN__UINT16_MAX__ 0xffffOPAMP_BASE (PERIPH_BASE_APB1 + 0x7800)RCC_AHB2ENR_GPIOCEN (1 << 2)bNumInterfacesRCC_APB1ENR1_SPI2EN (1 << 14)__UFRACT_IBIT__ 0RCC_APB1SMENR2_LPUART1SMEN (1 << 0)USB_CLASS_VENDOR 0xFFBX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)wIndex__DBL_HAS_QUIET_NAN__ 1__LDBL_MIN_10_EXP__ (-307)RCC_BDCR_LSEDRV_HIGH 3base_addressRCC_CCIPR_SWPMI1SEL (1 << 30)USB_ISTR_SOF 0x0200SIG_ATOMIC_MAX__USFRACT_IBIT__ 0RCC_AHB2SMENR_OFFSET 0x6c__FLT32X_MIN_10_EXP__ (-307)WINT_MAXTIM17_BASE (PERIPH_BASE_APB2 + 0x4800)__DEC_EVAL_METHOD__ 2INT_LEAST64_MAX__LDBL_HAS_INFINITY__ 1USB_EP_TX_COUNT(ep) ((uint16_t *)(USB_PMA_BASE + (USB_GET_BTABLE + (ep) * 8 + 2) * 1))USB_SET_EP_KIND(EP) SET_REG(USB_EP_REG(EP), (GET_REG(USB_EP_REG(EP)) & (USB_EP_NTOGGLE_MSK & (~USB_EP_KIND))) | USB_EP_KIND)long unsigned intDFSDM_BASE (PERIPH_BASE_APB2 + 0x6000)RCC_APB1SMENR1_USART3SMEN (1 << 18)__SFRACT_MAX__ 0X7FP-7HRRCC_APB1ENR1_TIM4EN (1 << 2)RCC_AHB2RSTR_GPIOBRST (1 << 1)DBGMCU_BASE (PPBI_BASE + 0x00042000)USB_ENDPOINT_ATTR_USAGETYPE 0x30USB_BCDR_DCDEN (1 << 1)RCC_AHB2SMENR_GPIOHSMEN (1 << 7)USB_ENDPOINT_ATTR_NOSYNC 0x00USB_LPMCSR_LPMACK (1 << 1)__SIZEOF_LONG_DOUBLE__ 8LPTIM1_BASE (PERIPH_BASE_APB1 + 0x7c00)__FLT64_HAS_DENORM__ 1RCC_CCIPR_CLK48SEL_PLLSAI1Q 1__FLT_HAS_DENORM__ 1__LLACCUM_FBIT__ 31UINT_LEAST8_MAX__THUMBEL__ 1__DBL_MANT_DIG__ 53iSerialNumberistrRCC_APB2RSTR MMIO32(RCC_BASE + RCC_APB2RSTR_OFFSET)RCC_CICR_HSI48RDYC (1 << 10)USB_ENDPOINT_ATTR_SYNC 0x0CDATA_OUTINT_FAST8_MIN (-INT_FAST8_MAX - 1)__TQ_IBIT__ 0RCC_APB1SMENR1_I2C1SMEN (1 << 21)__FLT32X_MIN__ 2.2250738585072014e-308F32xRCC_ICSCR_MSITRIM_MASK 0xff__SIZEOF_FLOAT__ 4USB_CNTR_ESOFM 0x0100__SIZE_TYPE__ unsigned intUSB_CLR_EP_RX_DTOG(EP) SET_REG(USB_EP_REG(EP), GET_REG(USB_EP_REG(EP)) & (USB_EP_NTOGGLE_MSK | USB_EP_RX_DTOG))__UINT_LEAST8_TYPE__ unsigned charUINT16_CUSB_EP7 7RCC_AHB3SMENR_QSPISMEN (1 << 8)RCC_APB1SMENR1_DAC1SMEN (1 << 29)USB_CLR_EP_RX_CTR(EP) USB_CLR_EP_NTOGGLE_BIT_AND_SET(EP, USB_EP_RX_CTR, USB_EP_TX_CTR)st_usbfs_pollINT_FAST8_MININT16_MIN (-INT16_MAX - 1)RCC_PLLCFGR_PLLR_DIV2 0__UFRACT_FBIT__ 16unsigned intep_write_packetID_BASE (SCS_BASE + 0x0FD0)_REG_BIT(base,bit) (((base) << 5) + (bit))RCC_CICR_PLLSAI1RDYC (1 << 6)__ARM_FEATURE_MVE__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0x75a8))USB_EP5 5RCC_BDCR_RTCSEL_LSI 2RCC_APB1ENR1_OFFSET 0x58USB_FNR_RXDM (1 << 14)__ARM_FEATURE_CDE_COPROC__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRbMaxPowerRCC_APB1SMENR1 MMIO32(RCC_BASE + RCC_APB1SMENR1_OFFSET)short intwTotalLengthRCC_APB2RSTR_SDMMC1RST (1 << 10)__GNUC_MINOR__ 2RCC_CIER MMIO32(RCC_BASE + 0x18)BBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)RCC_AHB1SMENR_FLASHSMEN (1 << 8)ST_USBFS_CORE INTMAX_MAX __INTMAX_MAX__RCC_AHB2RSTR_GPIODRST (1 << 3)__INTMAX_TYPE__ long long intRCC_APB1RSTR2_LPUART1RST (1 << 0)RCC_CFGR_HPRE_DIV2 0x8__ULLFRACT_EPSILON__ 0x1P-64ULLRRCC_CCIPR_USART3SEL_SHIFT 4USB_EP_TX_STAT 0x0030RCC_PLLSAI1_CFGR MMIO32(RCC_BASE + 0x10)RCC_CSR_LSION (1 << 0)RCC_APB1SMENR1_UART4SMEN (1 << 19)RCC_APB2ENR_SYSCFGEN (1 << 0)TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)RCC_BDCR_LSEDRV_MEDHIGH 2__FLT_DENORM_MIN__ 1.4012984643248171e-45FINT_FAST32_MAX __INT_FAST32_MAX__RCC_CCIPR_SAIxSEL_EXT 3TIM8_BASE (PERIPH_BASE_APB2 + 0x3400)RCC_CCIPR_DFSDMSEL (1 << 31)INT_FAST64_MIN (-INT_FAST64_MAX - 1)__UINT_LEAST8_MAX__ 0xff__ARM_ARCH_ISA_THUMB 2USB_EP_RX_STAT_VALID 0x3000__UINT32_MAX__ 0xffffffffUL__UHA_IBIT__ 8RCC_PLLCFGR_PLLN_MASK 0x7f__INT64_C(c) c ## LLUSB_ENDPOINT_ATTR_ISOCHRONOUS 0x01USB_CLR_ISTR_ERR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ERR)__GNUC_PATCHLEVEL__ 1GCC: (15:12.2.rel1-1) 12.2.1 20221205˙˙˙˙| DB„Ž$(B „…†‡Ž… BDA„…†ŽŘA„Ž8<„C„…†‡Ž¬A„…†‡Ž(đA„…†‡ŽN ÎÇĆĹÄĂBA3aeabi)7E-M M "ń˙@ 4Ô4|ś ě ""##$&')+-MO/13579;=?ACEGIKQ>o Ň7k™ É 9j ™ĎPS D7(IDbŘx8Ž<˘#µ„Îâ¬úđ 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" LIBOPENCM3_CM3_MEMORYMAP_H __LACCUM_EPSILON__ 0x1P-31LK__thumb__ 1UINT16_C(c) __UINT16_C(c)USB_FNR_RXDM (1 << 14)__UACCUM_FBIT__ 16__APCS_32__ 1MAX_USER_SET_CONFIG_CALLBACK 4usbd_control_complete_callback__LFRACT_EPSILON__ 0x1P-31LR__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__RCC_SDMMC1__FLT_NORM_MAX__ 3.4028234663852886e+38FRCC_APB1ENR2 MMIO32(RCC_BASE + RCC_APB1ENR2_OFFSET)__USACCUM_MIN__ 0.0UHK__ARM_FEATURE_MATMUL_INT8RCC_APB1SMENR2_OFFSET 0x7cbmAttributes__FLT32_DIG__ 6__DBL_EPSILON__ ((double)2.2204460492503131e-16L)__FLT32X_MAX__ 1.7976931348623157e+308F32x__UACCUM_IBIT__ 16RCC_APB2ENR_TIM15EN (1 << 16)INTPTR_MIN (-INTPTR_MAX - 1)RCC_CFGR_SWS_MASK 0x3RCC_APB2SMENR_SPI1SMEN (1 << 12)RCC_CCIPR_UARTxSEL_LSE RCC_CCIPR_USARTxSEL_LSERCC_AHB2ENR_OTGFSEN (1 << 12)TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)__FLT64_MANT_DIG__ 53UINT_LEAST16_MAXUINT_LEAST8_MAX __UINT_LEAST8_MAX__UINT_FAST16_MAX __UINT_FAST16_MAX____SIG_ATOMIC_MAX__ 0x7fffffffINT_LEAST16_MIN (-INT_LEAST16_MAX - 1)MAX_USER_CONTROL_CALLBACK 4RCC_CICR MMIO32(RCC_BASE + 0x20)RCC_APB1ENR1_DAC1EN (1 << 29)current_addressRCC_CCIPR_UARTxSEL_HSI16 RCC_CCIPR_USARTxSEL_HSI16USB_CNTR_REG (&MMIO32(USB_DEV_FS_BASE + 0x40))USB_CNTR_L1REQM (1 << 7)RCC_APB1SMENR1_PWRSMEN (1 << 28)RCC_AHB1SMENR MMIO32(RCC_BASE + RCC_AHB1SMENR_OFFSET)__USQ_IBIT__ 0__PTRDIFF_MAX__ 0x7fffffffRCC_APB2SMENR_OFFSET 0x80INT64_MIN (-INT64_MAX - 1)RCC_CFGR_PPRE2_DIV16 0x7VREFBUF_BASE (PERIPH_BASE_APB2 + 0x0030)__FLT64_MIN_10_EXP__ (-307)RCC_TIM6RCC_QSPIUSB_BCDR_SDET (1 << 6)needs_zlpextra_string_idxRCC_AHB2RSTR_GPIOFRST (1 << 5)BIT10 (1<<10)UINT_FAST64_MAXotghs_usb_driver stm32f207_usb_driver__STDC__ 1RCC_APB2SMENR_SDMMC1SMEN (1 << 10)doeptsizRCC_FW__ULLFRACT_IBIT__ 0USB_REQ_TYPE_INTERFACE 0x01__FLT32_MAX_EXP__ 128__SA_FBIT__ 15RCC_CCIPR_LPTIMxSEL_HSI16 2__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__UDA_FBIT__ 32STATUS_INRCC_AHB1SMENR_DMA1SMEN (1 << 0)bDeviceClass__UINT64_TYPE__ long long unsigned int__DBL_MAX_10_EXP__ 308RCC_APB1ENR2_LPUART1EN (1 << 0)INT_LEAST32_MIN__USBD_H __UINT_FAST64_MAX__ 0xffffffffffffffffULLUART4_BASE (PERIPH_BASE_APB1 + 0x4c00)SCC_SPI1SCC_SPI2SCC_SPI3__WCHAR_TYPE__ unsigned int__SA_IBIT__ 16__UDA_IBIT__ 32__ELF__ 1UINT_FAST32_MAXRCC_CIER_HSI48RDYIE (1 << 10)__SIZEOF_LONG__ 4USB_BCDR_BCDEN (1 << 0)DWT_BASE (PPBI_BASE + 0x1000)__ARM_ARCH 7user_callback_resumeRCC_CFGR_SWS_SHIFT 2BIT11 (1<<11)RCC_APB1SMENR1_TIM3SMEN (1 << 1)_BoolRCC_AHB2RSTR MMIO32(RCC_BASE + RCC_AHB2RSTR_OFFSET)LIBOPENCM3_MEMORYMAP_H RCC_CSR_IWDGRSTF (1 << 29)BIT3 (1<<3)WCHAR_MAXRCC_PLLCFGR_PLLQ_MASK 0x3__DBL_DECIMAL_DIG__ 17num_stringsUSB_CLR_EP_TX_DTOG(EP) SET_REG(USB_EP_REG(EP), GET_REG(USB_EP_REG(EP)) & (USB_EP_NTOGGLE_MSK | USB_EP_TX_DTOG))__UINT_LEAST64_TYPE__ long long unsigned intRCC_CFGR_SW_HSI16 0x1_STDBOOL_H SIG_ATOMIC_MIN__SHRT_WIDTH__ 16__STRICT_ANSI__ 1WINT_MINRCC_APB2ENR_TIM17EN (1 << 18)__INTPTR_TYPE__ int__DQ_FBIT__ 63__UACCUM_EPSILON__ 0x1P-16UKbInterfaceClassRCC_APB1SMENR1_LPTIM1SMEN (1 << 31)__INT_FAST16_WIDTH__ 32RCC_CCIPR_LPTIMxSEL_APB 0__FLT_HAS_INFINITY__ 1usb_interface_descriptorUSB_CNTR_LP_MODE 0x0004RCC_APB1RSTR1_TIM4RST (1 << 2)USB_SET_EP_RX_ADDR(EP,ADDR) SET_REG(USB_EP_RX_ADDR(EP), ADDR)uint16_tRCC_CICR_PLLRDYC (1 << 5)RCC_APB1ENR1_USART2EN (1 << 17)USB_FNR_REG (&MMIO32(USB_DEV_FS_BASE + 0x48))INT_FAST64_MAX __INT_FAST64_MAX__BIT12 (1<<12)USB_CNTR_CTRM 0x8000__FLT32X_MANT_DIG__ 53USB_EP_RX_ADDR(ep) ((uint16_t *)(USB_PMA_BASE + (USB_GET_BTABLE + (ep) * 8 + 4) * 1))RCC_APB1RSTR1_PWRRST (1 << 28)USB_EP6 6_usbd_driverITM_BASE (PPBI_BASE + 0x0000)__FP_FAST_FMAF32 1RCC_APB2ENR_SPI1EN (1 << 12)RCC_CFGR_MCO_LSI 0x6RCC_APB1SMENR1_LCDSMEN (1 << 9)RCC_CFGR_MCOPRE_DIV4 2USB_BCDR_PDEN (1 << 2)RCC_CIFR_LSIRDYF (1 << 0)USB_DT_CONFIGURATION 2__USBSTD_H __SFRACT_MIN__ (-0.5HR-0.5HR)__INT_LEAST16_WIDTH__ 16__USFRACT_MIN__ 0.0UHRRCC_APB1SMENR1_USART2SMEN (1 << 17)__INT_LEAST32_TYPE__ long int__DBL_HAS_INFINITY__ 1GPIO_PORT_G_BASE (PERIPH_BASE_AHB2 + 0x1800)BIT13 (1<<13)RCC_CCIPR_USART1SEL_APB 0RCC_APB1RSTR1_I2C3RST (1 << 23)__SHRT_MAX__ 0x7fffRCC_CFGR_PPRE2_NODIV 0x0USB_GET_EP_TX_BUFF(ep) (USB_PMA_BASE + (uint8_t *)(USB_GET_EP_TX_ADDR(ep) * 1))USB_EP_REG(EP) (&MMIO32(USB_DEV_FS_BASE) + (EP))INTMAX_MIN (-INTMAX_MAX - 1)__FLT_IS_IEC_60559__ 2POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)USB_ISTR_SOF 0x0200LIBOPENCM3_ST_USBFS_H RCC_CSR_RMVF (1 << 23)__FLT32_HAS_INFINITY__ 1USB_EP_RX_DTOG 0x4000RCC_CSR_MSIRANGE_SHIFT 8RCC_BDCR_LSECSSON (1 << 5)RCC_CFGR_MCO_PLL 0x5RCC_APB1ENR2_OFFSET 0x5cUSB_DT_CONFIGURATION_SIZE 9RCC_PLLCFGR_PLLP (1 << 17)set_address__INT_FAST64_MAX__ 0x7fffffffffffffffLL__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)RCC_APB1RSTR1_CAN1RST (1 << 25)__GCC_ATOMIC_CHAR_LOCK_FREE 2__UINT_FAST16_TYPE__ unsigned intSCC_ADC1GNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsUSB_CLR_ISTR_SUSP() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SUSP)RCC_BDCR MMIO32(RCC_BASE + 0x90)MMIO8(addr) (*(volatile uint8_t *)(addr))__UINT64_MAX__ 0xffffffffffffffffULLRCC_CCIPR_UART5SEL_SHIFT 8__SIZEOF_INT__ 4__ARMEL__ 1__FLT32X_MAX_10_EXP__ 308BIT14 (1<<14)RCC_AHB1ENR MMIO32(RCC_BASE + RCC_AHB1ENR_OFFSET)__WCHAR_WIDTH__ 32__SIG_ATOMIC_TYPE__ int__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1RCC_AHB2ENR_AESEN (1 << 16)st_usbfs_ep_setupRCC_APB1RSTR1_TIM6RST (1 << 4)__ULFRACT_EPSILON__ 0x1P-32ULRcontrol_stateRCC_CR_MSIRGSEL (1 << 3)RCC_CCIPR_I2CxSEL_APB 0RCC_USART1RCC_USART2RCC_USART3__UINT16_C(c) cRCC_CR_PLLON (1 << 24)__PRAGMA_REDEFINE_EXTNAME 1__INT_LEAST64_TYPE__ long long intUSB_CLR_ISTR_RESET() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_RESET)RCC_CCIPR_UARTxSEL_APB RCC_CCIPR_USARTxSEL_APBLPUART1_BASE (PERIPH_BASE_APB1 + 0x8000)RCC_PLLCFGR_PLLSRC_MASK 0x3USB_REQ_SET_INTERFACE 11UINTMAX_MAXUSB_DT_INTERFACE_ASSOCIATION 11RCC_AHB2SMENR_GPIODSMEN (1 << 3)__HAVE_SPECULATION_SAFE_VALUE 1I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)USB_CNTR_PMAOVRM 0x4000UINTMAX_C(c) __UINTMAX_C(c)__QQ_FBIT__ 7BIT15 (1<<15)RCC_CFGR_PPRE1_DIV4 0x5__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xINT8_CSCC_PWRRCC_AHB1SMENR_TSCSMEN (1 << 16)RCC_APB2RSTR_USART1RST (1 << 14)BIT5 (1<<5)USB_OTG_FS_BASE (0x50000000U + 0x00000)__BIGGEST_ALIGNMENT__ 8__ARM_ARCHRCC_APB1RSTR1_DAC1RST (1 << 29)RCC_SAI1RCC_SAI2RCC_AHB2RSTR_GPIOARST (1 << 0)RCC_CFGR_STOPWUCK_HSI16 (1 << 15)__FLT32_MIN_10_EXP__ (-37)RCC_CSR_MSIRANGE_8MHZ 7RCC_APB1ENR1_UART4EN (1 << 19)USB_FNR_LSOF_SHIFT 11USB_EP_RX_COUNT(ep) ((uint16_t *)(USB_PMA_BASE + (USB_GET_BTABLE + (ep) * 8 + 6) * 1))__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLKRCC_PLLCFGR_PLLQ_DIV4 1USB_SET_EP_ADDR(EP,ADDR) SET_REG(USB_EP_REG(EP), ((GET_REG(USB_EP_REG(EP)) & (USB_EP_NTOGGLE_MSK & (~USB_EP_ADDR))) | ADDR))__INT_LEAST16_MAX__ 0x7fffidVendorbIntervalRCC_CICR_PLLSAI2RDYC (1 << 7)USB_CLR_EP_STAT_OUT(EP) USB_CLR_EP_KIND(EP)IDLEBIT16 (1<<16)__SACCUM_IBIT__ 8__UINT16_TYPE__ short unsigned intRCC_AHB2SMENR_GPIOFSMEN (1 << 5)RCC_APB2RSTR_SYSCFGRST (1 << 0)RCC_ADC__ULLFRACT_FBIT__ 64RCC_CFGR_MCOPRE_DIV8 3extra_string__FLT32_NORM_MAX__ 3.4028234663852886e+38F32__FLT32X_HAS_INFINITY__ 1FMC_BASE (0xa0000000U)RCC_BDCR_LSEDRV_MASK 0x3USB_FNR_LSOF (3 << USB_FNR_LSOF_SHIFT)__INT8_C(c) cidProductRCC_CR_MSIRANGE_32MHZ 10INFO_BASE (0x1fff0000U)__ARM_EABI__ 1RCC_PLLCFGR_PLLR_DIV4 1RCC_AHB2SMENR_GPIOASMEN (1 << 0)__FLT32_MANT_DIG__ 24__FLT32_EPSILON__ 1.1920928955078125e-7F32INT_LEAST8_MAX __INT_LEAST8_MAX__false 0USB_EP_RX_CTR 0x8000__FLT_MAX_EXP__ 128RCC_AHB2ENR_GPIOBEN (1 << 1)__INT64_MAX__ 0x7fffffffffffffffLLSCC_LCDBIT17 (1<<17)__ATOMIC_SEQ_CST 5RCC_APB1SMENR1_TIM7SMEN (1 << 5)DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7590)RCC_APB2RSTR_TIM15RST (1 << 16)USB_GET_EP_RX_BUFF(ep) (USB_PMA_BASE + (uint8_t *)(USB_GET_EP_RX_ADDR(ep) * 1))RCC_CR MMIO32(RCC_BASE + 0x00)bcdUSB__FLT32X_MAX_EXP__ 1024SDMMC1_BASE (PERIPH_BASE_APB2 + 0x2800)BIT6 (1<<6)RCC_ICSCR_MSICAL_MASK 0xff__UINT_FAST8_TYPE__ unsigned intRCC_BDCR_RTCSEL_SHIFT 8RCC_AESRCC_AHB3SMENR_FMCSMEN (1 << 0)RCC_LPTIM1__UTA_FBIT__ 64DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)__DBL_DIG__ 15SCC_RNGINTPTR_MAX __INTPTR_MAX__RCC_AHB1SMENR_DMA2SMEN (1 << 1)__DECIMAL_DIG__ 17usbd_deviceINT_FAST16_MININT_FAST8_MAX __INT_FAST8_MAX____ARM_PCS_VFP 1DESIG_PACKAGE MMIO16((INFO_BASE + 0x7500))USB_ISTR_DIR 0x0010PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)__GCC_IEC_559_COMPLEX 0UINT64_CUSB_ENDPOINT_ADDR_IN(x) (0x80 | (x))RCC_APB1ENR1_LPTIM1EN (1 << 31)USBD_REQ_NOTSUPPRCC_PLLCFGR_PLLP_DIV17 RCC_PLLCFGR_PLLPBIT18 (1<<18)__LFRACT_IBIT__ 0RCC_BDCR_BDRST (1 << 16)__USER_LABEL_PREFIX__ USB_ENDPOINT_ATTR_SYNCTYPE 0x0CRCC_PLLCFGR_PLLM_SHIFT 0x4USB_LPMCSR_REG (&MMIO32(USB_DEV_FS_BASE + 0x54))RCC_APB1RSTR1_SPI3RST (1 << 15)SCC_TIM4INT64_MAX __INT64_MAX____QQ_IBIT__ 0usb_config_descriptorRCC_AHB3ENR_FMCEN (1 << 0)TIM17_BASE (PERIPH_BASE_APB2 + 0x4800)UINT_LEAST64_MAXSCC_SRAM1SCC_SRAM2SPI2_BASE (PERIPH_BASE_APB1 + 0x3800)USB_REQ_TYPE_ENDPOINT 0x02__DBL_MIN__ ((double)2.2250738585072014e-308L)RCC_CFGR_STOPWUCK_MSI (0 << 15)USB_REQ_TYPE_CLASS 0x20current_config__INT_FAST8_MAX__ 0x7fffffffRCC_APB2SMENR_SYSCFGSMEN (1 << 0)RCC_LCDRCC_CR_PLLSAI2ON (1 << 28)__INT_FAST8_WIDTH__ 32RCC_CCIPR_I2CxSEL_HSI16 2RCC_AHB3SMENR_OFFSET 0x70__LDBL_MAX__ 1.7976931348623157e+308LINT_FAST32_MAXRCC_AHB3RSTR_OFFSET 0x30RCC_AHB2RSTR_ADCRST (1 << 13)__FLT32_MIN_EXP__ (-125)ST_VREFINT_CAL MMIO16((INFO_BASE + 0x75aa))user_callback_set_altsettingtypeuser_control_callbackinterface__UINT32_C(c) c ## UL__LDBL_MIN_EXP__ (-1021)__DBL_MIN_10_EXP__ (-307)IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)BIT7 (1<<7)GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000)RCC_PLLCFGR_PLLSRC_NONE 0__FLT_MIN_10_EXP__ (-37)RCC_CCIPR_USART2SEL_SHIFT 2RCC_APB1ENR1_TIM7EN (1 << 5)RCC_CCIPR_USARTxSEL_MASK 0x3RCC_APB1SMENR1_OFFSET 0x78INT_LEAST64_MAX __INT_LEAST64_MAX____UDQ_IBIT__ 0AES_BASE (0x50000000U + 0x60000)RCC_CCIPR_USART1SEL_HSI16 2RCC_AHB3RSTR_QSPIRST (1 << 8)__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)__PTRDIFF_WIDTH__ 32bDeviceSubClass__ULLACCUM_MIN__ 0.0ULLKRCC_APB1RSTR1_OFFSET 0x38SCC_I2C2SCC_I2C3__ARM_FEATURE_DOTPRODINT_FAST64_MAXWWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)RCC_CICR_LSIRDYC (1 << 0)RCC_APB1SMENR1_TIM4SMEN (1 << 2)USB_DT_STRING 3DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)RCC_APB2ENR_SAI1EN (1 << 21)__WINT_MAX__ 0xffffffffUUSB_EP_RX_STAT 0x3000USB_EP_KIND 0x0100__ARM_FP16_FORMAT_ALTERNATIVERCC_CCIPR_I2C2SEL_SHIFT 14UINTPTR_MAXINT32_C(c) __INT32_C(c)rcc_periph_clkenUSB_DT_ENDPOINT 5__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1__UINT32_TYPE__ long unsigned int__FLT_EPSILON__ 1.1920928955078125e-7FRCC_TSCbInterfaceNumberRCC_PLLCFGR_PLLR_MASK 0x3__UINT8_C(c) cLIBOPENCM3_RCC_COMMON_ALL_H USB_REQ_CLEAR_FEATURE 1RCC_CFGR_SWS_HSE 0x2__ARM_FEATURE_NUMERIC_MAXMINRCC_CFGR_MCOPRE_MASK 0x7RCC_AHB3SMENR MMIO32(RCC_BASE + RCC_AHB3SMENR_OFFSET)rx_fifo_sizeINT8_C(c) __INT8_C(c)USB_EP_TYPE_ISO 0x0400UINT16_MAX __UINT16_MAX__SCC_TSCUSB_ENDPOINT_ATTR_DATA 0x00RCC_CCIPR_CLK48SEL_SHIFT 26__ULLFRACT_MIN__ 0.0ULLRRCC_CCIPR_ADCSEL_NONE 0unsigned char__ARM_FEATURE_QRDMXRCC_CCIPR_LPTIMxSEL_LSE 3BIT8 (1<<8)__SFRACT_IBIT__ 0__ORDER_LITTLE_ENDIAN__ 1234RCC_CIFR_HSIRDYF (1 << 3)usbd_request_return_codesFMC3_BANK_BASE (0x80000000U)RCC_CCIPR_USARTxSEL_APB 0RCC_APB1ENR1_CAN1EN (1 << 25)__FLT_DIG__ 6RCC_AHB1SMENR_SRAM1SMEN (1 << 9)RCC_CR_PLLSAI1RDY (1 << 27)__DBL_MAX_EXP__ 1024__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULK__LLFRACT_IBIT__ 0__UINT_LEAST16_MAX__ 0xffff__SIZE_WIDTH__ 32USB_EP_RX_STAT_NAK 0x2000SCC_DAC1__ULFRACT_FBIT__ 32RCC_APB1RSTR1_TIM3RST (1 << 1)BIT2 (1<<2)__SIZEOF_SIZE_T__ 4USB_FNR_RXDP (1 << 15)RCC_CCIPR_CLK48SEL_PLL 2RCC_AHB2ENR_ADCEN (1 << 13)INT_LEAST16_MAX __INT_LEAST16_MAX____UINT_LEAST64_MAX__ 0xffffffffffffffffULLRCC_APB1SMENR1_WWDGSMEN (1 << 11)usbd_driverRCC_CCIPR_USART1SEL_LSE 3initRCC_CCIPR_LPUART1SEL_SYS 1NVIC_BASE (SCS_BASE + 0x0100)__SFRACT_FBIT__ 7DMA2_BASE (PERIPH_BASE_AHB1 + 0x0400)ep_read_packet__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32USB_CNTR_FRES 0x0001RCC_CSR_OBLRSTF (1 << 25)PTRDIFF_MIN (-PTRDIFF_MAX - 1)RCC_APB1SMENR1_I2C2SMEN (1 << 22)usb_device_descriptorRCC_GPIOARCC_GPIOBRCC_GPIOCRCC_GPIODRCC_GPIOERCC_GPIOFRCC_GPIOGSIZE_MAXRCC_CR_MSIRANGE_200KHZ 1SCC_GPIOASCC_GPIOBWCHAR_MAX __WCHAR_MAX__SCC_GPIODRCC_AHB1RSTR_FLASHRST (1 << 8)__FLT32_DECIMAL_DIG__ 9SCC_GPIOGSCC_GPIOHUSB_CLR_ISTR_WKUP() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_WKUP)GPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000)RCC_PLLCFGR_PLLSRC_MSI 1BIT9 (1<<9)RCC_AHB1RSTR_CRCRST (1 << 12)RCC_CR_MSIRANGE_SHIFT 4ep_stall_setUINT8_CRCC_CR_HSIKERON (1 << 9)SCC_GPIOC__WINT_TYPE__ unsigned intst_usbfs_ep_stall_getUINT_LEAST32_MAX __UINT_LEAST32_MAX__RCC_CFGR_MCO_MSI 0x2SCB_BASE (SCS_BASE + 0x0D00)RCC_APB1ENR1_I2C3EN (1 << 23)__SIG_ATOMIC_WIDTH__ 32RCC_CSR_MSIRANGE_MASK 0xfSCC_USART1SCC_USART2SCC_USART3RCC_AHB1SMENR_CRCSMEN (1 << 12)__INT16_MAX__ 0x7fffLIBOPENCM3_ST_USBFS_V2_H __ULACCUM_EPSILON__ 0x1P-32ULK__FLT_MANT_DIG__ 24INT_LEAST64_MINRCC_AHB2ENR_RNGEN (1 << 18)__ULACCUM_FBIT__ 32TIM1_BASE (PERIPH_BASE_APB2 + 0x2C00)st_usbfs_endpoints_reset__FLT64_HAS_QUIET_NAN__ 1bFunctionSubClassUSB_EP_NTOGGLE_MSK (USB_EP_RX_CTR | USB_EP_SETUP | USB_EP_TYPE | USB_EP_KIND | USB_EP_TX_CTR | USB_EP_ADDR)wMaxPacketSizeRCC_BDCR_RTCSEL_NONE 0__ARM_ARCH_PROFILE 77__ULACCUM_IBIT__ 32RCC_CFGR_PPRE2_DIV4 0x5RCC_DFSDMRCC_CR_MSIRANGE_1MHZ 4BIT20 (1<<20)bEndpointAddressUSB_LPMCSR_BESL_SHIFT 4CRS_BASE (PERIPH_BASE_APB1 + 0x6000)__INT_LEAST8_MAX__ 0x7f__UQQ_FBIT__ 8__FLT_MIN_EXP__ (-125)RCC_ICSCR_HSITRIM_SHIFT 24__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__RCC_CFGR_PPRE2_SHIFT 11__UINT64_C(c) c ## ULL__FRACT_IBIT__ 0__FLT_RADIX__ 2__USA_FBIT__ 16USB_ENDPOINT_ATTR_ASYNC 0x04__LDBL_IS_IEC_60559__ 2__FLT32X_DIG__ 15UINT_FAST8_MAX __UINT_FAST8_MAX____LDBL_EPSILON__ 2.2204460492503131e-16LUSB_ISTR_RESET 0x0400__FLT_EVAL_METHOD_TS_18661_3__ 0__SQ_FBIT__ 31__UINTMAX_MAX__ 0xffffffffffffffffULL__LDBL_HAS_DENORM__ 1__USA_IBIT__ 16__ACCUM_EPSILON__ 0x1P-15KRCC_CCIPR_USART1SEL_MASK 0x3__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LKRCC_CFGR_HPRE_DIV16 0xbRCC_CR_MSIRANGE_400KHZ 2RCC_PLLCFGR_PLLQEN (1 << 20)RCC_CCIPR_UART4SEL_SHIFT 6INT_FAST32_MINRCC_USBRCC_FLASHUSB_ISTR_ERR 0x2000RCC_PLLCFGR_PLLQ_DIV6 2__GCC_ATOMIC_INT_LOCK_FREE 2BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)RCC_PLLCFGR_PLLSRC_HSE 3SCC_FLASH__LDBL_DECIMAL_DIG__ 17__INT_WIDTH__ 32USB_SET_EP_TX_STAT(EP,STAT) TOG_SET_REG_BIT_MSK_AND_SET(USB_EP_REG(EP), USB_EP_TX_STAT_TOG_MSK, STAT, USB_EP_RX_CTR | USB_EP_TX_CTR)I2C3_BASE (PERIPH_BASE_APB1 + 0x5c00)force_nakRCC_CFGR_SW_SHIFT 0PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)USB_ENDPOINT_ATTR_INTERRUPT 0x03RCC_BDCR_LSERDY (1 << 1)MIN(a,b) ((a) < (b) ? (a) : (b))RCC_CFGR_MCO_HSI16 0x3RCC_AHB2ENR_GPIOAEN (1 << 0)CORESIGHT_LAR_KEY 0xC5ACCE55__FLT32_IS_IEC_60559__ 2__UDQ_FBIT__ 64RCC_CCIPR_I2C3SEL_SHIFT 16__FLT64_DIG__ 15__ARM_NEONRCC_CFGR_MCO_SHIFT 24RCC_AHB2SMENR_AESSMEN (1 << 16)__ARM_ARCH_7EM__ 1STM32L4 1usbd_dev__INT16_C(c) cBIT30 (1<<30)INT_FAST8_MAXRCC_CFGR_PPRE1_NODIV 0x0RCC_CIFR_PLLRDYF (1 << 5)BIT22 (1<<22)__FLT32X_DECIMAL_DIG__ 17RCC_CSR_MSIRANGE_2MHZ 5__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2__INT16_TYPE__ short intRCC_APB2RSTR_DFSDMRST (1 << 24)RCC_CICR_CSSC (1 << 8)__bool_true_false_are_defined 1RCC_CCIPR_ADCSEL_PLLSAI1R 1__FRACT_MIN__ (-0.5R-0.5R)SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)SCC_LPTIM2usb_endpoint_descriptorSWPMI1_BASE (PERIPH_BASE_APB1 + 0x8800)RCC_CCIPR_LPUART1SEL_SHIFT 10otgfs_usb_driver stm32f107_usb_driverRCC_CIER_PLLSAI2RDYIE (1 << 7)RCC_BDCR_LSEDRV_MEDLOW 1RCC_PLLCFGR_PLLR_DIV6 2__GCC_ATOMIC_LONG_LOCK_FREE 2_GCC_STDINT_H PTRDIFF_MAX __PTRDIFF_MAX__RCC_CFGR_SW_MSI 0x0RCC_CCIPR_USARTxSEL_HSI16 2RCC_CIER_MSIRDYIE (1 << 2)__UHQ_FBIT__ 16uint8_tRCC_CFGR MMIO32(RCC_BASE + 0x08)RCC_PLLSAI2_CFGR MMIO32(RCC_BASE + 0x14)num_altsettingRCC_CFGR_MCO_HSI48 0x8RCC_CFGR_SWS_PLL 0x3RCC_CSR_MSIRANGE_1MHZ 4bInterfaceCountSCC_ADCUSB_EP_TX_STAT_STALL 0x0010RCC_BDCR_LSEDRV_LOW 0BIT23 (1<<23)QUADSPI_BANK_BASE (0x90000000U)RCC_BDCR_LSCOSEL (1 << 25)__FP_FAST_FMAF 1RCC_AHB1ENR_FLASHEN (1 << 8)__WCHAR_MIN__ 0URCC_APB2SMENR_TIM16SMEN (1 << 17)RCC_CIFR MMIO32(RCC_BASE + 0x1c)USB_FEAT_ENDPOINT_HALT 0USB_DADDR_ADDR 0x007FRCC_APB2ENR_FWEN (1 << 7)USB_ISTR_PMAOVR 0x4000RCC_APB2ENR_OFFSET 0x60USB_REQ_TYPE_DIRECTION 0x80RCC_CFGR_HPRE_NODIV 0x0__LLFRACT_EPSILON__ 0x1P-63LLR__INT_FAST64_WIDTH__ 64__FRACT_FBIT__ 15RCC_OTGFSst_usbfs_ep_nak_setUSB_EP4 4RCC_UART4SCC_LPTIM1SCC_OTGFS__INT32_MAX__ 0x7fffffffL__CHAR_UNSIGNED__ 1SCC_UART4SCC_UART5SCC_AESctrl_bufUSB_CNTR_FSUSP 0x0008BIT24 (1<<24)__SCHAR_MAX__ 0x7f__GCC_HAVE_DWARF2_CFI_ASM 1USB_REQ_SET_SYNCH_FRAME 12SCC_DMA1SCC_DMA2TPIU_BASE (PPBI_BASE + 0x40000)../st_usbfs_v2.c__SACCUM_EPSILON__ 0x1P-7HKUSB_FNR_FN (0x7FF << 0)RCC_CCIPR_ADCSEL_SHIFT 28DAC_BASE (PERIPH_BASE_APB1 + 0x7400)USB_EP_TX_STAT_DISABLED 0x0000__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRRCC_CR_MSIRANGE_48MHZ 11st_usbfs_set_addressRCC_CIER_HSERDYIE (1 << 4)cur_altsetting__HA_FBIT__ 7__UACCUM_MIN__ 0.0UKRCC_ICSCR_MSICAL_SHIFT 0INT_LEAST32_MAX __INT_LEAST32_MAX__RCC_APB1RSTR2 MMIO32(RCC_BASE + RCC_APB1RSTR2_OFFSET)__UFRACT_EPSILON__ 0x1P-16UR__FLT_HAS_QUIET_NAN__ 1RCC_DMA1UINT_FAST64_MAX __UINT_FAST64_MAX__USB_ENDPOINT_ADDR_OUT(x) (x)BIT25 (1<<25)ep_nak_set__FLT32X_NORM_MAX__ 1.7976931348623157e+308F32xRCC_PLLCFGR_PLLP_DIV7 0SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__USART1_BASE (PERIPH_BASE_APB2 + 0x3800)RCC_AHB2RSTR_GPIOBRST (1 << 1)RCC_PLLCFGR_PLLQ_SHIFT 21RCC_AHB2SMENR_SRAM2SMEN (1 << 9)UINTMAX_CRCC_CCIPR_CLK48SEL_MSI 3__SCHAR_WIDTH__ 8USB_REQ_TYPE_IN 0x80__ARM_FEATURE_FP16_FML__ORDER_PDP_ENDIAN__ 3412__ATOMIC_ACQUIRE 2__INT_FAST32_WIDTH__ 32USB_BCDR_DPPU (1 << 15)__INT_FAST64_TYPE__ long long int__ACCUM_FBIT__ 15__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__INTMAX_TYPE__ long long int__ARM_FEATURE_QBIT 1CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)TIM16_BASE (PERIPH_BASE_APB2 + 0x4400)UINT32_C(c) __UINT32_C(c)__ARM_FEATURE_UNALIGNED 1RCC_CR_MSION (1 << 0)__SACCUM_MAX__ 0X7FFFP-7HKBIT26 (1<<26)INTMAX_MAXst_usbfs_copy_to_pmRCC_CR_HSIRDY (1 << 10)__ACCUM_IBIT__ 16UINT64_MAX __UINT64_MAX__USB_CNTR_L1RESUME (1 << 5)__INTMAX_WIDTH__ 64USB_ENDPOINT_ATTR_BULK 0x02__FRACT_EPSILON__ 0x1P-15RUSB_EP_TX_DTOG 0x0040__ARM_FEATURE_LDREX 7__INT_LEAST64_WIDTH__ 64valueRCC_CIFR_HSI48RDYF (1 << 10)SCC_DFSDMRCC_ICSCR_HSICAL_SHIFT 16RCC_CCIPR_USARTxSEL_LSE 3RCC_CFGR_HPRE_DIV512 0xf__ARM_32BIT_STATE 1__ATOMIC_RELAXED 0RCC_AHB2SMENR_GPIOESMEN (1 << 4)__LFRACT_MAX__ 0X7FFFFFFFP-31LR__LDBL_MIN__ 2.2250738585072014e-308LRCC_CCIPR_USART1SEL_SHIFT 0RCC_APB1RSTR2_LPTIM2RST (1 << 5)SET_REG(REG,VAL) (*(REG) = (uint16_t)(VAL))USB_SET_EP_RX_STAT(EP,STAT) TOG_SET_REG_BIT_MSK_AND_SET(USB_EP_REG(EP), USB_EP_RX_STAT_TOG_MSK, STAT, USB_EP_RX_CTR | USB_EP_TX_CTR)USB_ISTR_ESOF 0x0100RCC_PLLCFGR_PLLSRC_HSI16 2__THUMB_INTERWORK__ 1RCC_AHB2ENR_GPIOHEN (1 << 7)PPBI_BASE (0xE0000000U)__UINT8_TYPE__ unsigned charBIT27 (1<<27)__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)wLengthRCC_CFGR_HPRE_DIV64 0xc__SIZEOF_LONG_LONG__ 8__GCC_IEC_559 0st_usbfs_v2_usb_driver__FLT32X_EPSILON__ 2.2204460492503131e-16F32xGPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800)RCC_CCIPR_SAI2SEL_SHIFT 24USB_EP_TX_CTR 0x0080USB_REQ_GET_DESCRIPTOR 6FIREWALL_BASE (PERIPH_BASE_APB2 + 0x1C00)st_usbfs_ep_stall_setMMIO32(addr) (*(volatile uint32_t *)(addr))RCC_TIM1RCC_TIM2RCC_TIM3RCC_TIM4RCC_TIM5RCC_APB1RSTR2_OFFSET 0x3cRCC_TIM7RCC_TIM8GET_REG(REG) ((uint16_t) *(REG))usbd_endpoint_callbackBIT28 (1<<28)usb_iface_assoc_descriptor__SIZE_MAX__ 0xffffffffU__ATOMIC_RELEASE 3__ARM_BF16_FORMAT_ALTERNATIVERCC_APB1RSTR1_I2C1RST (1 << 21)__INT_LEAST8_WIDTH__ 8altsettingUSB_EP_TX_ADDR(ep) ((uint16_t *)(USB_PMA_BASE + (USB_GET_BTABLE + (ep) * 8 + 0) * 1))__GNUC__ 12RCC_CCIPR_SAIxSEL_PLLSAI1P 0st_usbfs_ep_read_packet__ARM_FEATURE_COPROCRCC_CCIPR_SAIxSEL_PLLSAI2P 1RCC_ICSCR MMIO32(RCC_BASE + 0x04)__INT_FAST16_TYPE__ intiManufacturer__INT_LEAST32_WIDTH__ 32RCC_AHB1RSTR_TSCRST (1 << 16)__UTQ_IBIT__ 0USB_EP_TYPE 0x0600__DBL_IS_IEC_60559__ 2USB_EP_SETUP 0x0800__UTA_IBIT__ 64__SIZEOF_WINT_T__ 4USB_CNTR_RESETM 0x0400RCC_AHB1RSTR_DMA2RST (1 << 1)RCC_CFGR_MCOPRE_DIV1 0USB_REQ_GET_INTERFACE 10RCC_CCIPR_LPUART1SEL_HSI16 2__ARM_FEATURE_IDIV 1RCC_APB1RSTR1_USART2RST (1 << 17)RCC_CCIPR MMIO32(RCC_BASE + 0x88)USB_CLR_EP_NTOGGLE_BIT_AND_SET(EP,BIT,EXTRA_BITS) CLR_REG_BIT_MSK_AND_SET(USB_EP_REG(EP), USB_EP_NTOGGLE_MSK, BIT, EXTRA_BITS)__ARM_FEATURE_SAT 1RCC_APB1ENR1_PWREN (1 << 28)USB_DT_OTG 9__INT_MAX__ 0x7fffffffep_setupRCC_CR_MSIPLLEN (1 << 2)__FLT_MAX__ 3.4028234663852886e+38F__INT_LEAST8_TYPE__ signed charTIM8_BASE (PERIPH_BASE_APB2 + 0x3400)__GXX_ABI_VERSION 1017BIT29 (1<<29)INT32_Cuser_callback_ctr__ARM_ARCH_ISA_THUMBUSB_CLR_ISTR_SOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SOF)__FLT64_IS_IEC_60559__ 2__SIZEOF_WCHAR_T__ 4INTMAX_C__USACCUM_MAX__ 0XFFFFP-8UHKUSB_REQ_GET_STATUS 0extra__INT8_MAX__ 0x7fRCC_AHB2ENR_OFFSET 0x4cRCC_APB2ENR_TIM8EN (1 << 13)__INT_LEAST32_MAX__ 0x7fffffffLSCC_QSPIUSB_EP0 0RCC_APB2ENR MMIO32(RCC_BASE + RCC_APB2ENR_OFFSET)__USACCUM_EPSILON__ 0x1P-8UHKRCC_AHB2SMENR_GPIOBSMEN (1 << 1)__LLACCUM_EPSILON__ 0x1P-31LLK__USFRACT_EPSILON__ 0x1P-8UHRRCC_CFGR_MCOPRE_SHIFT 28__INTMAX_C(c) c ## LL__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)SAI1_BASE (PERIPH_BASE_APB2 + 0x5400)__UINT_FAST16_MAX__ 0xffffffffU__ARM_ARCH_EXT_IDIV__ 1__UINT_FAST64_TYPE__ long long unsigned intRCC_CAN1COMP_BASE (PERIPH_BASE_APB2 + 0x0200)__ULFRACT_IBIT__ 0BIT0 (1<<0)RCC_CR_HSION (1 << 8)RCC_BDCR_RTCEN (1 << 15)RCC_CFGR_PPRE1_DIV2 0x4STIR_BASE (SCS_BASE + 0x0F00)RTC_BASE (PERIPH_BASE_APB1 + 0x2800)RCC_CIER_PLLSAI1RDYIE (1 << 6)USB_CONFIG_ATTR_DEFAULT 0x80RCC_LPUART1RCC_AHB2ENR_GPIOEEN (1 << 4)RCC_CSR_SFTRSTF (1 << 28)RCC_APB2RSTR_SAI1RST (1 << 21)LIBOPENCM3_MEMORYMAP_COMMON_H ADC1_BASE (0x50000000U + 0x40000)__UINT_FAST8_MAX__ 0xffffffffURCC_CIFR_PLLSAI2RDYF (1 << 7)ctrl_lenUSB_ENDPOINT_ATTR_FEEDBACK 0x10RCC_CIFR_HSERDYF (1 << 4)__SQ_IBIT__ 0LCD_BASE (PERIPH_BASE_APB1 + 0x2400)RCC_CCIPR_UARTxSEL_SYS RCC_CCIPR_USARTxSEL_SYSINT_FAST16_MIN (-INT_FAST16_MAX - 1)RCC_APB1RSTR1_TIM2RST (1 << 0)__ARM_FEATURE_SIMD32 1RCC_PLLCFGR_PLLSRC_SHIFT 0__UHQ_IBIT__ 0ST_TSENSE_CAL2_110C MMIO16((INFO_BASE + 0x75ca))RCC_APB2SMENR_TIM15SMEN (1 << 16)CLR_REG_BIT_MSK(REG,MSK,BIT) CLR_REG_BIT_MSK_AND_SET((REG), (MSK), (BIT), 0)disconnectRCC_APB1ENR1_TIM6EN (1 << 4)__thumb2__ 1__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1RCC_AHB2ENR MMIO32(RCC_BASE + RCC_AHB2ENR_OFFSET)__LACCUM_FBIT__ 31__ULACCUM_MIN__ 0.0ULKRCC_CFGR_HPRE_SHIFT 4RCC_CR_MSIRANGE_4MHZ 6RCC_CFGR_SW_HSE 0x2RCC_PLLCFGR_PLLQ_DIV8 3RCC_CCIPR_CLK48SEL_MASK 0x3RCC_CCIPR_ADCSEL_PLLSAI2R 2RCC_PLLCFGR_PLLN_SHIFT 0x8USB_DEV_STATUS_SELF_POWERED 0x01__LONG_MAX__ 0x7fffffffLUSB_REQ_SET_DESCRIPTOR 7__INT32_C(c) c ## LRCC_SWPMI1__FLT64_NORM_MAX__ 1.7976931348623157e+308F64BIT4 (1<<4)INTPTR_MAXUSB_CLR_EP_KIND(EP) SET_REG(USB_EP_REG(EP), (GET_REG(USB_EP_REG(EP)) & (USB_EP_NTOGGLE_MSK & (~USB_EP_KIND))))RCC_CICR_HSIRDYC (1 << 3)bLengthUSB_CNTR_ERRM 0x2000INT_FAST16_MAX __INT_FAST16_MAX__RCC_APB1SMENR1_I2C3SMEN (1 << 23)USB_REQ_TYPE_OUT 0x0RCC_ICSCR_HSICAL_MASK 0xffRCC_CICR_LSECSSC (1 << 9)RCC_PLLPEN (1 << 16)__FLT32X_IS_IEC_60559__ 2RCC_APB1RSTR1_LPTIM1RST (1 << 31)RCC_APB1SMENR1_TIM5SMEN (1 << 3)RCC_CFGR_MCO_HSE 0x4UINT_FAST32_MAX __UINT_FAST32_MAX__RCC_CIER_LSE_CSSIE (1 << 9)bRequestUINT32_CTIM2_BASE (PERIPH_BASE_APB1 + 0x0000)_usbd_deviceshort unsigned intRCC_AHB2RSTR_AESRST (1 << 16)signed charRCC_CCIPR_LPTIMxSEL_MASK 0x3st_usbfs_copy_from_pmrxbcntUSB_GET_EP_TX_COUNT(EP) GET_REG(USB_EP_TX_COUNT(EP))USB_EP_RX_STAT_TOG_MSK (USB_EP_RX_STAT | USB_EP_NTOGGLE_MSK)bFunctionClassLIBOPENCM3_RCC_H USB_ENDPOINT_ATTR_ADAPTIVE 0x08RCC_PLLCFGR_PLLR_DIV8 3RCC_APB2SMENR_SAI2SMEN (1 << 22)INTMAX_C(c) __INTMAX_C(c)WINT_MAX __WINT_MAX____ULLACCUM_EPSILON__ 0x1P-32ULLKDESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 0x14)__CHAR_BIT__ 8INTMAX_MINRCC_APB1RSTR1_UART4RST (1 << 19)RCC_CR_MSIRANGE_2MHZ 5RCC_CFGR_SWS_MSI 0x0RCC_CFGR_PPRE1_SHIFT 8RCC_APB2RSTR_TIM16RST (1 << 17)USB_GET_EP_RX_ADDR(EP) GET_REG(USB_EP_RX_ADDR(EP))bDeviceProtocolEND_DECLS USB_ENDPOINT_ATTR_IMPLICIT_FEEDBACK_DATA 0x20BEGIN_DECLS endpointUSB_CNTR_SOFM 0x0200usb_control_stateRCC_BDCR_LSESYSDIS (1 << 7)RCC_CFGR_PPRE2_DIV8 0x6__GXX_TYPEINFO_EQUALITY_INLINE 0__CHAR16_TYPE__ short unsigned int__FLT64_MIN__ 2.2250738585072014e-308F64__INTPTR_MAX__ 0x7fffffff__ARM_FP16_ARGSRCC_APB2RSTR_TIM8RST (1 << 13)FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000)USB_BCDR_PS2DET (1 << 7)__GCC_ATOMIC_POINTER_LOCK_FREE 2SCC_I2C1USB_LPMCSR_BESL (15 << USB_LPMCSR_BESL_SHIFT)__ARM_FEATURE_LDREX__DBL_MAX__ ((double)1.7976931348623157e+308L)RCC_CFGR_MCOPRE_DIV2 1USB_CLR_EP_TX_CTR(EP) USB_CLR_EP_NTOGGLE_BIT_AND_SET(EP, USB_EP_TX_CTR, USB_EP_RX_CTR)__FLT32_MAX_10_EXP__ 38USB_EP_TYPE_INTERRUPT 0x0600RCC_CRCSCC_WWDGiface_assocINT_LEAST32_MIN (-INT_LEAST32_MAX - 1)USB_DT_DEVICE_SIZE sizeof(struct usb_device_descriptor)stateITR_BASE (SCS_BASE + 0x0000)INT_LEAST8_MAXiFunction__WINT_WIDTH__ 32bInterfaceSubClassRCC_APB1RSTR2_SWPMI1RST (1 << 2)RCC_CRSPERIPH_BASE (0x40000000U)fifo_mem_topiConfigurationUINT_FAST8_MAX__ARM_FP16_FORMAT_IEEERCC_CIFR_CSSF (1 << 8)RCC_APB1ENR1_TIM3EN (1 << 1)RCC_SPI2RCC_SPI3RCC_LPTIM2__USES_INITFINI__ 1USBD_REQ_NEXT_CALLBACK__FLT64_MAX_EXP__ 1024RCC_APB1ENR1_LCDEN (1 << 9)RCC_CR_PLLSAI2RDY (1 << 29)RCC_CFGR_PPRE1_DIV16 0x7USB_EP1 1RCC_CICR_MSIRDYC (1 << 2)__REGISTER_PREFIX__ RCC_CFGR_PPRE2_MASK 0x7RCC_BDCR_RTCSEL_LSE 1__USFRACT_MAX__ 0XFFP-8UHRPERIPH_BASE_AHB2 (0x48000000U)RCC_SYSCFGSCC_SAI1SCC_SAI2WCHAR_MIN __WCHAR_MIN____FLT32_MAX__ 3.4028234663852886e+38F32STALLEDBIT1 (1<<1)USB_DT_OTHER_SPEED_CONFIGURATION 7RCC_AHB2SMENR_OTGFSSMEN (1 << 12)RCC_AHB2SMENR_RNGSMEN (1 << 18)__FRACT_MAX__ 0X7FFFP-15RUSB_BCDR_REG (&MMIO32(USB_DEV_FS_BASE + 0x58))RCC_GPIOHRCC_APB1ENR2_SWPMI1EN (1 << 2)__USQ_FBIT__ 32__INT_FAST8_TYPE__ intLAST_DATA_OUTUINT8_C(c) __UINT8_C(c)UINT32_MAXRCC_APB1SMENR1_SPI3SMEN (1 << 15)__ARM_FEATURE_BF16_SCALAR_ARITHMETICRCC_CR_MSIRANGE_16MHZ 8USB_DT_DEVICE_QUALIFIER 6RCC_CSR MMIO32(RCC_BASE + 0x94)__STDC_HOSTED__ 1__UINTMAX_C(c) c ## ULLUSB_CONFIG_ATTR_SELF_POWERED 0x40GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400)user_callback_reset__UACCUM_MAX__ 0XFFFFFFFFP-16UKRCC_CSR_LPWRRSTF (1 << 31)FMC1_BANK_BASE (0x60000000U)RCC_CFGR_HPRE_DIV4 0x9long intRCC_CFGR_MCO_SYSCLK 0x1__WINT_MIN__ 0U__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)USB_EP_RX_STAT_VALID 0x3000INT16_MAX__DBL_HAS_DENORM__ 1TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1__FLT64_MAX_10_EXP__ 308USB_SET_EP_TX_ADDR(EP,ADDR) SET_REG(USB_EP_TX_ADDR(EP), ADDR)__PTRDIFF_TYPE__ intctrl_buf_lenUSB_BTABLE_REG (&MMIO32(USB_DEV_FS_BASE + 0x50))__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2__USACCUM_FBIT__ 8__GNUC_STDC_INLINE__ 1USB_REQ_SET_CONFIGURATION 9UINT64_MAXUSB_CNTR_PWDN 0x0002__ARM_FPset_address_before_statusRCC_APB2ENR_TIM1EN (1 << 11)RCC_AHB2SMENR_GPIOGSMEN (1 << 6)RCC_CICR_LSERDYC (1 << 1)RCC_CSR_BORRSTF (1 << 27)RCC_CIER_LSERDYIE (1 << 1)RCC_CCIPR_I2CxSEL_MASK 0x3RCC_APB2SMENR MMIO32(RCC_BASE + RCC_APB2SMENR_OFFSET)__UTQ_FBIT__ 128__USB_PRIVATE_H LIBOPENCM3_CM3_COMMON_H RCC_AHB2SMENR MMIO32(RCC_BASE + RCC_AHB2SMENR_OFFSET)RCC_APB1ENR1_I2C2EN (1 << 22)RCC_CCIPR_CLK48SEL_HSI48 0RCC_CCIPR_LPTIMxSEL_LSI 1RCC_CIFR_PLLSAI1RDYF (1 << 6)__ARM_FEATURE_DSP 1__ARM_FEATURE_CRYPTORCC_CFGR_HPRE_DIV256 0xeFPB_BASE (PPBI_BASE + 0x2000)RCC_CCIPR_LPTIM2SEL_SHIFT 20__FLT32_HAS_DENORM__ 1RCC_CFGR_MCO_MASK 0xfRCC_AHB2RSTR_GPIOHRST (1 << 7)INT32_MIN (-INT32_MAX - 1)__ARM_FEATURE_FP16_SCALAR_ARITHMETIC__SACCUM_FBIT__ 7__HQ_FBIT__ 15__LLACCUM_IBIT__ 32USB_REQ_GET_CONFIGURATION 8RCC_ADC1uint32_tUSB_EP_TYPE_CONTROL 0x0200USB_DADDR_EF (1 << 7)__LLFRACT_FBIT__ 63__LDBL_DIG__ 15__CHAR32_TYPE__ long unsigned intRCC_APB1SMENR2 MMIO32(RCC_BASE + RCC_APB1SMENR2_OFFSET)SIG_ATOMIC_MIN __SIG_ATOMIC_MIN__RCC_CFGR_SW_PLL 0x3__GCC_ATOMIC_SHORT_LOCK_FREE 2RCC_AHB2ENR_GPIOGEN (1 << 6)RCC_AHB1ENR_DMA2EN (1 << 1)__ULFRACT_MAX__ 0XFFFFFFFFP-32ULRRCC_CRRCR_HSI48ON (1 << 0)uintptr_t__SIZEOF_POINTER__ 4RCC_CCIPR_LPUART1SEL_APB 0__GCC_ASM_FLAG_OUTPUTS__ 1USB_LPMCSR_LPMEN (1 << 0)RCC_APB1SMENR1_CAN1SMEN (1 << 25)CLR_REG_BIT_MSK_AND_SET(REG,MSK,BIT,EXTRA_BITS) SET_REG((REG), (GET_REG((REG)) & (MSK) & (~(BIT))) | (EXTRA_BITS))RCC_CCIPR_LPUART1SEL_MASK 0x3RCC_CFGR_HPRE_DIV128 0xdUINT_LEAST64_MAX __UINT_LEAST64_MAX____UINTMAX_TYPE__ long long unsigned intRCC_APB2SMENR_TIM17SMEN (1 << 18)RCC_APB2RSTR_TIM1RST (1 << 11)__INTPTR_WIDTH__ 32INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)INT_FAST16_MAXGPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0c00)USART3_BASE (PERIPH_BASE_APB1 + 0x4800)INTPTR_MINextralenRCC_CCIPR_SAI1SEL_SHIFT 22SCC_FMCRCC_CR_MSIRANGE_MASK 0xfCLR_REG_BIT(REG,BIT) SET_REG((REG), (~(BIT)))RCC_AHB1RSTR MMIO32(RCC_BASE + RCC_AHB1RSTR_OFFSET)USB_ENDPOINT_ATTR_TYPE 0x03__FLT64_HAS_INFINITY__ 1__GCC_DESTRUCTIVE_SIZE 64RCC_PLLCFGR_PLLREN (1<<24)RCC_BDCR_LSECSSD (1 << 6)USB_DT_INTERFACE_POWER 8__FINITE_MATH_ONLY__ 0__LONG_LONG_MAX__ 0x7fffffffffffffffLLRCC_CR_PLLRDY (1 << 25)USB_ENDPOINT_ATTR_CONTROL 0x00__ATOMIC_ACQ_REL 4RCC_AHB1RSTR_DMA1RST (1 << 0)__GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"USB_DT_INTERFACE_ASSOCIATION_SIZE sizeof(struct usb_iface_assoc_descriptor)MMIO64(addr) (*(volatile uint64_t *)(addr))__STDC_VERSION__ 199901L__LFRACT_MIN__ (-0.5LR-0.5LR)PTRDIFF_MAXRCC_CFGR_MCO_NOCLK 0x0__LLFRACT_MIN__ (-0.5LLR-0.5LLR)RCC_CCIPR_ADCSEL_MASK 0x3__INT_FAST16_MAX__ 0x7fffffffINT64_C(c) __INT64_C(c)__GCC_ATOMIC_LLONG_LOCK_FREE 1RCC_APB2ENR_SDMMC1EN (1 << 10)USB_ISTR_L1REQ (1 << 7)usbd_set_config_callbackRCC_AHB1ENR_CRCEN (1 << 12)__LONG_LONG_WIDTH__ 64iInterfaceRCC_AHB3ENR_OFFSET 0x50RCC_CFGR_PPRE2_DIV2 0x4bAlternateSetting__VERSION__ "12.2.1 20221205"__FLT64_EPSILON__ 2.2204460492503131e-16F64USB_EP2 2USB_DEV_STATUS_REMOTE_WAKEUP 0x02GPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400)UINT64_C(c) __UINT64_C(c)__ULLACCUM_FBIT__ 32__LDBL_HAS_QUIET_NAN__ 1RCC_CR_CSSON (1 << 19)__WCHAR_MAX__ 0xffffffffUUSBD_PM_TOP 0x40UART5_BASE (PERIPH_BASE_APB1 + 0x5000)USB_REQ_TYPE_VENDOR 0x40RCC_BDCR_LSEON (1 << 0)USB_FEAT_DEVICE_REMOTE_WAKEUP 1RCC_APB2ENR_DFSDMEN (1 << 24)__ULLACCUM_IBIT__ 32RCC_APB2SMENR_SAI1SMEN (1 << 21)__LDBL_MANT_DIG__ 53RCC_APB2ENR_USART1EN (1 << 14)RCC_BDCR_LSEDRV_SHIFT 3RCC_AHB2RSTR_OFFSET 0x2c__DQ_IBIT__ 0__FLT64_MAX__ 1.7976931348623157e+308F64INT_LEAST8_MINUSB_EP_TYPE_BULK 0x0000RCC_CRRCR_HSI48RDY (1 << 1)CORESIGHT_LSR_SLI (1<<0)__UQQ_IBIT__ 0LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))USB_DT_DEVICE 1DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x75e0)USB_BTABLE_BTABLE 0xFFF8SCC_SWPMI1__ARM_FEATURE_CDEbFirstInterfaceUSB_SET_EP_STAT_OUT(EP) USB_SET_EP_KIND(EP)RCC_AHB2ENR_GPIODEN (1 << 3)RCC_CCIPR_USART1SEL_SYS 1SYS_TICK_BASE (SCS_BASE + 0x0010)RCC_APB1ENR2_LPTIM2EN (1 << 5)USB_ISTR_REG (&MMIO32(USB_DEV_FS_BASE + 0x44))__UINT_LEAST32_MAX__ 0xffffffffULLIBOPENCM3_TOOLS_H STATUS_OUT__ACCUM_MIN__ (-0X1P15K-0X1P15K)__ORDER_BIG_ENDIAN__ 4321__ARM_FEATURE_CMSEbFunctionProtocolPERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)__UFRACT_MAX__ 0XFFFFP-16URI2C1_BASE (PERIPH_BASE_APB1 + 0x5400)__UINT_FAST32_TYPE__ unsigned intRCC_AHB1ENR_OFFSET 0x48__SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__ARM_FEATURE_COPROC 15RCC_APB1ENR1_SPI3EN (1 << 15)USB_FNR_LCK (1 << 13)true 1INT16_MAX __INT16_MAX__USB_REQ_TYPE_RECIPIENT 0x1FRCC_APB1ENR1_TIM5EN (1 << 3)iProductusb_interfaceUSB_REQ_TYPE_DEVICE 0x00USB_CONFIG_ATTR_REMOTE_WAKEUP 0x20USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6c00)complete__FLT_DECIMAL_DIG__ 9BIT31 (1<<31)__INT32_TYPE__ long int__USACCUM_IBIT__ 8GPIO_PORT_H_BASE (PERIPH_BASE_AHB2 + 0x1c00)USB_EP_TX_STAT_VALID 0x0030RCC_AHB3ENR MMIO32(RCC_BASE + RCC_AHB3ENR_OFFSET)RCC_CCIPR_I2CxSEL_SYS 1__ULFRACT_MIN__ 0.0ULRusb_setup_dataRCC_AHB3SMENR_QSPISMEN (1 << 8)__TQ_FBIT__ 127USB_REQ_TYPE_TYPE 0x60__UINTPTR_TYPE__ unsigned intBIT21 (1<<21)RCC_AHB2RSTR_GPIOCRST (1 << 2)bcdDeviceUINT8_MAX __UINT8_MAX__RCC_APB1RSTR1 MMIO32(RCC_BASE + RCC_APB1RSTR1_OFFSET)USB_GET_EP_TX_ADDR(EP) GET_REG(USB_EP_TX_ADDR(EP))__LFRACT_FBIT__ 31bMaxPacketSize0driver__ARM_FEATURE_BF16_VECTOR_ARITHMETICUSB_DT_DEBUG 10configUSB_GET_BTABLE GET_REG(USB_BTABLE_REG)USB_ISTR_WKUP 0x1000RCC_BDCR_LSEBYP (1 << 2)UINT8_MAXUSB_CLR_ISTR_PMAOVR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_PMAOVR)RCC_AHB3ENR_QSPIEN (1 << 8)RCC_APB1SMENR1_SPI2SMEN (1 << 14)USBD_REQ_HANDLED__ARM_SIZEOF_MINIMAL_ENUM 1RCC_APB2RSTR_OFFSET 0x40RCC_AHB1RSTR_OFFSET 0x28USB_REQ_TYPE_STANDARD 0x00RCC_CSR_MSIRANGE_4MHZ 6type_maskINT_LEAST16_MAXbmRequestTypeRCC_APB1ENR1 MMIO32(RCC_BASE + RCC_APB1ENR1_OFFSET)DATA_IN__DA_FBIT__ 31__FLT32_MIN__ 1.1754943508222875e-38F32wValueSIZE_MAX __SIZE_MAX__INT8_MINRCC_I2C1RCC_I2C2RCC_I2C3USB_CLR_ISTR_ESOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ESOF)RCC_CRRCR MMIO32(RCC_BASE + 0x98)__GCC_ATOMIC_BOOL_LOCK_FREE 2INT_FAST64_MIN__INT_FAST32_MAX__ 0x7fffffffRCC_AHB2SMENR_ADCSMEN (1 << 13)__FLT_MAX_10_EXP__ 38RCC_APB2RSTR_SPI1RST (1 << 12)SCC_TIM16WINT_MIN __WINT_MIN__lbuf__DA_IBIT__ 32fifo_mem_top_ep0__VFP_FP__ 1RCC_CCIPR_ADCSEL_SYS 3__ARM_ASM_SYNTAX_UNIFIED__ 1/build/libopencm3/lib/stm32/l4RCC_CSR_FWRSTF (1 << 24)INT32_MAXSCC_SYSCFG__ARM_FP 4RCC_CSR_WWDGRSTF (1 << 30)RCC_PLLCFGR_PLLM_MASK 0x7__UFRACT_MIN__ 0.0URUSB_BCDR_PDET (1 << 5)RCC_APB1SMENR1_UART5SMEN (1 << 20)RCC_APB1RSTR1_I2C2RST (1 << 22)RCC_APB2SMENR_DFSDMSMEN (1 << 24)RCC_BDCR_RTCSEL_HSEDIV32 3__GCC_CONSTRUCTIVE_SIZE 64__ARM_SIZEOF_WCHAR_T 4RCC_APB1RSTR1_TIM7RST (1 << 5)RCC_AHB1ENR_TSCEN (1 << 16)TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)__SIZEOF_DOUBLE__ 8__UINT_FAST32_MAX__ 0xffffffffU__LDBL_MAX_EXP__ 1024USB_EP3 3RCC_FMCRCC_BDCR_RTCSEL_MASK 0x3QUADSPI_BASE (0xa0001000U)USB_EP_TX_STAT_TOG_MSK (USB_EP_TX_STAT | USB_EP_NTOGGLE_MSK)bNumConfigurationsRCC_CR_HSERDY (1 << 17)__ARM_FEATURE_FP16_VECTOR_ARITHMETICdisconnectedSCC_CRCep_stall_getrcc_periph_clock_enableRCC_APB1RSTR1_USART3RST (1 << 18)RCC_AHB2RSTR_GPIOERST (1 << 4)LAST_DATA_INUSB_EP_ADDR 0x000F__INTMAX_MAX__ 0x7fffffffffffffffLLUSB_DT_ENDPOINT_SIZE 7INT64_MAXbInterfaceProtocolRCC_APB1ENR1_TIM2EN (1 << 0)UINT_LEAST16_MAX __UINT_LEAST16_MAX__RCC_CR_HSIASFS (1 << 11)__LONG_WIDTH__ 32RCC_CICR_HSERDYC (1 << 4)__OPTIMIZE__ 1usbd_control_callbackUSB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x6800)__arm__ 1PTRDIFF_MINRCC_APB1RSTR1_UART5RST (1 << 20)RCC_DAC1USB_CNTR_SUSPM 0x0800USB_REQ_TYPE_OTHER 0x03RCC_CR_HSEBYP (1 << 18)UINT32_MAX __UINT32_MAX____OPTIMIZE_SIZE__ 1USB_CNTR_WKUPM 0x1000RCC_APB2SMENR_TIM8SMEN (1 << 13)SCC_SDMMC1RCC_CFGR_PPRE1_MASK 0x7ep_resetpollRCC_AHB2SMENR_GPIOCSMEN (1 << 2)INT_FAST32_MIN (-INT_FAST32_MAX - 1)USB_GET_EP_RX_COUNT(EP) GET_REG(USB_EP_RX_COUNT(EP))__INT8_TYPE__ signed char__LDBL_DENORM_MIN__ 4.9406564584124654e-324LSYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000)RCC_CR_MSIRANGE_100KHZ 0RCC_APB1RSTR1_OPAMPRST (1 << 30)RCC_APB1SMENR2_SWPMI1SMEN (1 << 2)st_usbfs_ep_write_packetUSB_SET_EP_TX_COUNT(EP,COUNT) SET_REG(USB_EP_TX_COUNT(EP), COUNT)RCC_TIM15LPTIM2_BASE (PERIPH_BASE_APB1 + 0x9400)UINT_LEAST32_MAX__ACCUM_MAX__ 0X7FFFFFFFP-15KRCC_CIFR_LSECSSF (1 << 9)RCC_APB1SMENR1_TIM2SMEN (1 << 0)__FLT64_MIN_EXP__ (-1021)__INT_FAST32_TYPE__ intuser_callback_sofRCC_APB1RSTR1_LCDRST (1 << 9)RCC_APB2ENR_TIM16EN (1 << 17)RCC_AHB1SMENR_OFFSET 0x68RCC_APB2RSTR_SAI2RST (1 << 22)__ARM_NEON__TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)USART2_BASE (PERIPH_BASE_APB1 + 0x4400)RCC_BDCR_LSCOEN (1 << 24)USB_REQ_SET_FEATURE 3USB_BCDR_DCDEN (1 << 1)stringsTOG_SET_REG_BIT_MSK(REG,MSK,BIT) TOG_SET_REG_BIT_MSK_AND_SET((REG), (MSK), (BIT), 0)CORESIGHT_LSR_SLK (1<<1)INT8_MAXRCC_CIER_LSIRDYIE (1 << 0)RCC_CSR_LSIRDY (1 << 1)CORESIGHT_LAR_OFFSET 0xfb0RCC_CFGR_MCO_LSE 0x7RCC_APB1ENR1_I2C1EN (1 << 21)WCHAR_MIN__FLT32X_MIN_EXP__ (-1021)LIBOPENCM3_ST_USBFS_COMMON_H USB_ISTR_CTR 0x8000RNG_BASE (0x50000000U + 0x60800)__ARM_ARCH_PROFILERCC_CCIPR_SAIxSEL_MASK 0x3__LACCUM_IBIT__ 32RCC_CCIPR_LPTIM1SEL_SHIFT 18RCC_CCIPR_LPUART1SEL_LSE 3RCC_AHB2RSTR_GPIOGRST (1 << 6)MMIO16(addr) (*(volatile uint16_t *)(addr))st_usbfs_devSCS_BASE (PPBI_BASE + 0xE000)INT16_MINRCC_CIER_HSIRDYIE (1 << 3)RCC_CCIPR_UARTxSEL_MASK RCC_CCIPR_USARTxSEL_MASKlong long unsigned int__SIZEOF_SHORT__ 2UINTPTR_MAX __UINTPTR_MAX__INT8_MAX __INT8_MAX__RCC_PLLCFGR_PLLM(x) ((x)-1)USB_REQ_SET_ADDRESS 5__UINT8_MAX__ 0xffUSB_SET_EP_RX_COUNT(EP,COUNT) SET_REG(USB_EP_RX_COUNT(EP), COUNT)USB_ISTR_EP_ID 0x000FINT64_CTOG_SET_REG_BIT_MSK_AND_SET(REG,MSK,BIT,EXTRA_BITS) do { register uint16_t toggle_mask = GET_REG(REG) & (MSK); toggle_mask ^= BIT; SET_REG((REG), toggle_mask | (EXTRA_BITS)); } while (0)RCC_APB1SMENR1_TIM6SMEN (1 << 4)RCC_CCIPR_SWPMI1SEL (1 << 30)RCC_CFGR_SW_MASK 0x3chardescRCC_CR_MSIRANGE_800KHZ 3BIT19 (1<<19)UINT_FAST16_MAX__FLT64_DECIMAL_DIG__ 17__UINTPTR_MAX__ 0xffffffffURCC_AHB2ENR_GPIOFEN (1 << 5)RCC_AHB1ENR_DMA1EN (1 << 0)bDescriptorTypeUSB_SET_EP_TYPE(EP,TYPE) SET_REG(USB_EP_REG(EP), (GET_REG(USB_EP_REG(EP)) & (USB_EP_NTOGGLE_MSK & (~USB_EP_TYPE))) | TYPE)USB_EP_RX_STAT_STALL 0x1000__SFRACT_EPSILON__ 0x1P-7HR__ATOMIC_CONSUME 1__FLT_MIN__ 1.1754943508222875e-38F__INT_LEAST16_TYPE__ short intRCC_PLLCFGR_PLLQ_DIV2 0RCC_APB1SMENR2_LPTIM2SMEN (1 << 5)INT32_MAX __INT32_MAX____USFRACT_FBIT__ 8USB_FEAT_TEST_MODE 2RCC_CIFR_MSIRDYF (1 << 2)RCC_CR_MSIRDY (1 << 1)USB_EP_TX_STAT_NAK 0x0020__GCC_ATOMIC_WCHAR_T_LOCK_FREE 2RCC_TIM16RCC_TIM17RCC_APB2RSTR_TIM17RST (1 << 18)RCC_APB1RSTR1_TIM5RST (1 << 3)__SIZEOF_PTRDIFF_T__ 4USB_DADDR_REG (&MMIO32(USB_DEV_FS_BASE + 0x4C))RCC_APB1ENR1_USART3EN (1 << 18)SCC_TIM15RCC_CIER_PLLRDYIE (1 << 5)SCC_TIM17user_callback_suspendFMC_QUADSPI_BASE (0xA0000000U)RCC_APB1ENR1_UART5EN (1 << 20)bConfigurationValueRCC_CCIPR_USARTxSEL_SYS 1DMA1_BASE (PERIPH_BASE_AHB1 + 0x0000)RCC_APB1RSTR1_SPI2RST (1 << 14)RCC_CFGR_HPRE_DIV8 0xa__FLT32X_HAS_QUIET_NAN__ 1USB_LPMCSR_REMWAKE (1 << 3)__GNUC_EXECUTION_CHARSET_NAME "UTF-8"RCC_AHB3RSTR MMIO32(RCC_BASE + RCC_AHB3RSTR_OFFSET)__INT64_C(c) c ## LLRCC_CCIPR_SAIxSEL_PLL 2RCC_CSR_RESET_FLAGS (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF | RCC_CSR_IWDGRSTF | RCC_CSR_SFTRSTF | RCC_CSR_BORRSTF | RCC_CSR_PINRSTF | RCC_CSR_OBLRSTF | RCC_CSR_FWRSTF)RCC_CFGR_PPRE1_DIV8 0x6__DBL_MIN_EXP__ (-1021)USB_EP_RX_STAT_DISABLED 0x0000bNumEndpointsRCC_BASE (PERIPH_BASE_AHB1 + 0x1000)MPU_BASE (SCS_BASE + 0x0D90)TIM15_BASE (PERIPH_BASE_APB2 + 0x4000)UINT16_MAXINT_LEAST16_MINRCC_AHB2RSTR_OTGFSRST (1 << 12)__LDBL_MAX_10_EXP__ 308SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)GET_REG_BIT(REG,BIT) (GET_REG(REG) & (BIT))USB_DT_INTERFACE_SIZE 9RCC_AHB3RSTR_FMCRST (1 << 0)RCC_ICSCR_MSITRIM_SHIFT 8EXTI_BASE (PERIPH_BASE_APB2 + 0x0400)USB_DT_INTERFACE 4__INT64_TYPE__ long long intRCC_CFGR_SWS_HSI16 0x1INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)__ARM_FEATURE_CRC32__TA_FBIT__ 63__LDBL_NORM_MAX__ 1.7976931348623157e+308Lbool _Bool__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64USB_ISTR_SUSP 0x0800RCC_ICSCR_HSITRIM_MASK 0x1fuser_callback_set_config__UINT_LEAST32_TYPE__ long unsigned intRCC_CCIPR_I2C1SEL_SHIFT 12SAI2_BASE (PERIPH_BASE_APB2 + 0x5800)RCC_AHB2RSTR_RNGRST (1 << 18)USB_BCDR_SDEN (1 << 3)RCC_APB1ENR1_OPAMPEN (1 << 30)INT32_MIN__HA_IBIT__ 8INT16_C(c) __INT16_C(c)__TA_IBIT__ 64INT8_MIN (-INT8_MAX - 1)__FLT32X_HAS_DENORM__ 1TSC_BASE (PERIPH_BASE_AHB1 + 0x4000)INT16_CRCC_CR_MSIRANGE_8MHZ 7pm_top__FLT32_HAS_QUIET_NAN__ 1RCC_PLLCFGR MMIO32(RCC_BASE + 0x0c)__HQ_IBIT__ 0long long int__FLT_EVAL_METHOD__ 0RCC_CIFR_LSERDYF (1 << 1)RCC_CR_HSEON (1 << 16)USB_CNTR_RESUME 0x0010RCC_APB2ENR_SAI2EN (1 << 22)__UHA_FBIT__ 8__ARM_FEATURE_COMPLEXRCC_CSR_PINRSTF (1 << 26)__ARM_FEATURE_CLZ 1INT_LEAST32_MAXSCC_TIM1SCC_TIM2SCC_TIM3RCC_APB2SMENR_TIM1SMEN (1 << 11)SCC_TIM5SCC_TIM6SCC_TIM7SCC_TIM8__ARM_FEATURE_FMA 1RCC_PWR__ARM_NEON_FP__FDPIC__CORESIGHT_LSR_OFFSET 0xfb4INT64_MIN__UINT16_MAX__ 0xffffOPAMP_BASE (PERIPH_BASE_APB1 + 0x7800)RCC_AHB2ENR_GPIOCEN (1 << 2)bNumInterfacesRCC_APB1ENR1_SPI2EN (1 << 14)__UFRACT_IBIT__ 0RCC_APB1SMENR2_LPUART1SMEN (1 << 0)USB_CLASS_VENDOR 0xFFRCC_SPI1BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)wIndex__DBL_HAS_QUIET_NAN__ 1__LDBL_MIN_10_EXP__ (-307)RCC_BDCR_LSEDRV_HIGH 3base_addressRCC_DMA2RCC_CFGR_MCOPRE_DIV16 4SIG_ATOMIC_MAX__USFRACT_IBIT__ 0RCC_AHB2SMENR_OFFSET 0x6c__FLT32X_MIN_10_EXP__ (-307)WINT_MAXRCC_CFGR_HPRE_MASK 0xf__DEC_EVAL_METHOD__ 2INT_LEAST64_MAX__LDBL_HAS_INFINITY__ 1USB_EP_TX_COUNT(ep) ((uint16_t *)(USB_PMA_BASE + (USB_GET_BTABLE + (ep) * 8 + 2) * 1))USB_SET_EP_KIND(EP) SET_REG(USB_EP_REG(EP), (GET_REG(USB_EP_REG(EP)) & (USB_EP_NTOGGLE_MSK & (~USB_EP_KIND))) | USB_EP_KIND)long unsigned intDFSDM_BASE (PERIPH_BASE_APB2 + 0x6000)RCC_APB1SMENR1_USART3SMEN (1 << 18)__SFRACT_MAX__ 0X7FP-7HRRCC_APB1ENR1_TIM4EN (1 << 2)RCC_APB1SMENR1_OPAMPSMEN (1 << 30)DBGMCU_BASE (PPBI_BASE + 0x00042000)USB_ENDPOINT_ATTR_USAGETYPE 0x30RCC_CR_PLLSAI1ON (1 << 26)RCC_AHB2SMENR_GPIOHSMEN (1 << 7)USB_ENDPOINT_ATTR_NOSYNC 0x00USB_LPMCSR_LPMACK (1 << 1)__SIZEOF_LONG_DOUBLE__ 8SCC_LPUART1LPTIM1_BASE (PERIPH_BASE_APB1 + 0x7c00)__FLT64_HAS_DENORM__ 1RCC_CCIPR_CLK48SEL_PLLSAI1Q 1__FLT_HAS_DENORM__ 1__LLACCUM_FBIT__ 31UINT_LEAST8_MAX__THUMBEL__ 1__DBL_MANT_DIG__ 53RCC_CR_MSIRANGE_24MHZ 9iSerialNumberRCC_PLLCFGR_PLLR_SHIFT 25RCC_APB2RSTR MMIO32(RCC_BASE + RCC_APB2RSTR_OFFSET)RCC_CICR_HSI48RDYC (1 << 10)USB_ENDPOINT_ATTR_SYNC 0x0Cst_usbfs_v2_usbd_initDATA_OUTSCC_GPIOESCC_GPIOFINT_FAST8_MIN (-INT_FAST8_MAX - 1)__TQ_IBIT__ 0RCC_APB1SMENR1_I2C1SMEN (1 << 21)__FLT32X_MIN__ 2.2250738585072014e-308F32xRCC_ICSCR_MSITRIM_MASK 0xff__SIZEOF_FLOAT__ 4SCC_CAN1usbd_set_altsetting_callbackUSB_CNTR_ESOFM 0x0100__SIZE_TYPE__ unsigned intRCC_UART5RCC_RNGUSB_CLR_EP_RX_DTOG(EP) SET_REG(USB_EP_REG(EP), GET_REG(USB_EP_REG(EP)) & (USB_EP_NTOGGLE_MSK | USB_EP_RX_DTOG))__UINT_LEAST8_TYPE__ unsigned charUSB_BCDR_DCDET (1 << 4)UINT16_CUSB_EP7 7RCC_APB1SMENR1_DAC1SMEN (1 << 29)USB_CLR_EP_RX_CTR(EP) USB_CLR_EP_NTOGGLE_BIT_AND_SET(EP, USB_EP_RX_CTR, USB_EP_TX_CTR)st_usbfs_pollINT_FAST8_MININT16_MIN (-INT16_MAX - 1)RCC_PLLCFGR_PLLR_DIV2 0__UFRACT_FBIT__ 16unsigned intep_write_packetID_BASE (SCS_BASE + 0x0FD0)_REG_BIT(base,bit) (((base) << 5) + (bit))RCC_CICR_PLLSAI1RDYC (1 << 6)__ARM_FEATURE_MVEST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0x75a8))RCC_APB2SMENR_USART1SMEN (1 << 14)USB_EP5 5RCC_BDCR_RTCSEL_LSI 2st_usbfs_v2_disconnectRCC_APB1ENR1_OFFSET 0x58__UHA_IBIT__ 8__ARM_FEATURE_CDE_COPROC__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRbMaxPowerRCC_APB1SMENR1 MMIO32(RCC_BASE + RCC_APB1SMENR1_OFFSET)short intwTotalLengthRCC_APB2RSTR_SDMMC1RST (1 << 10)__GNUC_MINOR__ 2RCC_OPAMPRCC_CIER MMIO32(RCC_BASE + 0x18)BBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)RCC_AHB1SMENR_FLASHSMEN (1 << 8)ST_USBFS_CORE INTMAX_MAX __INTMAX_MAX__RCC_AHB2RSTR_GPIODRST (1 << 3)SCC_OPAMPRCC_APB1RSTR2_LPUART1RST (1 << 0)__UINT_LEAST16_TYPE__ short unsigned intRCC_CFGR_HPRE_DIV2 0x8__ULLFRACT_EPSILON__ 0x1P-64ULLRRCC_CCIPR_USART3SEL_SHIFT 4USB_EP_TX_STAT 0x0030RCC_PLLSAI1_CFGR MMIO32(RCC_BASE + 0x10)RCC_CSR_LSION (1 << 0)RCC_APB1SMENR1_UART4SMEN (1 << 19)RCC_APB2ENR_SYSCFGEN (1 << 0)TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)RCC_BDCR_LSEDRV_MEDHIGH 2__FLT_DENORM_MIN__ 1.4012984643248171e-45FINT_FAST32_MAX __INT_FAST32_MAX__RCC_CCIPR_SAIxSEL_EXT 3UINTMAX_MAX __UINTMAX_MAX__RCC_CCIPR_DFSDMSEL (1 << 31)INT_FAST64_MIN (-INT_FAST64_MAX - 1)__UINT_LEAST8_MAX__ 0xff__ARM_ARCH_ISA_THUMB 2__UINT32_MAX__ 0xffffffffULRCC_PLLCFGR_PLLN_MASK 0x7fUSB_ENDPOINT_ATTR_ISOCHRONOUS 0x01USB_CLR_ISTR_ERR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ERR)__GNUC_PATCHLEVEL__ 1GCC: (15:12.2.rel1-1) 12.2.1 20221205˙˙˙˙| $8AŽA„…†ŽHA„…†ŽA3aeabi)7E-M M "ń˙$) ,8)0)!#CE%')+-/13579;=?AGBišËý.b–Ä ô .d• ÄúFI 2JWkH4żŘî1Ist_usbfs_v2.c$tst_usbfs_v2_disconnect$dst_usbfs_v2_usbd_initwm4.0.c5e6bdb01417bb5a599260a3f8c9cb62wm4.common.h.21.c9066c2f6b12c71b40226ea6107829a4wm4.stdint.h.29.6d480f4ba0f60596e88234283d42444fwm4.stdbool.h.29.4a1c88fe569adb8d03217dd16982ca34wm4.common.h.67.5c568a1f62c8e726909b04e29f9e1fc0wm4.memorymap.h.21.8c90486dae5eea2d8efddd23fe5d09d9wm4.memorymap.h.26.bb1efb6ce36cc052fd0489ef5a3533f5wm4.rcc.h.40.e8c13f444ba606cb63a83dcc96231a47wm4.tools.h.21.75e74419488d11c9cf865f0f24faab06wm4.st_usbfs_common.h.45.f60d64c4129b0b0e3e198ec0990d50afwm4.st_usbfs_v2.h.44.2ff915b11dfbd53c9d02162ed9241078wm4.usbstd.h.44.4afe4d1bc74038b0efb850274c9ca72fwm4.usbd.h.59.36297d267a452a295a2169d9133104f5wm4.usb_private.h.39.0319c55b21f25116dad040a5212d0c5dwm4.st_usbfs_core.h.28.065eabeab16a03ca11e811d6f3ae3701rcc_periph_clock_enablest_usbfs_devst_usbfs_copy_to_pmst_usbfs_copy_from_pmst_usbfs_v2_usb_driverst_usbfs_set_addressst_usbfs_ep_setupst_usbfs_endpoints_resetst_usbfs_ep_stall_setst_usbfs_ep_nak_setst_usbfs_ep_stall_getst_usbfs_ep_write_packetst_usbfs_ep_read_packetst_usbfs_poll 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(0x0000ffff)OTG_GINTMSK_GINAKEFFM 0x00000040__FLT_NORM_MAX__ 3.4028234663852886e+38FSIZE_MAX__USACCUM_MIN__ 0.0UHK__ARM_FEATURE_MATMUL_INT8_REENT_L64A_BUF(ptr) ((ptr)->_new._reent._l64a_buf)bmAttributes__FLT32_DIG__ 6__DBL_EPSILON__ ((double)2.2204460492503131e-16L)__FLT32X_MAX__ 1.7976931348623157e+308F32x__UACCUM_IBIT__ 16USB_CONFIG_ATTR_DEFAULT 0x80INTPTR_MIN (-INTPTR_MAX - 1)__MISC_VISIBLE 0bInterfaceSubClass__INT_FAST16_MAX__ 0x7fffffffOTG_HPRT_PTCTL_SE0_NAK (0x3 << 13)__SIZEOF_SHORT__ 2_REENT_CHECK_RAND48(ptr) __FLT64_MANT_DIG__ 53UINT_LEAST16_MAXUINT_LEAST8_MAX __UINT_LEAST8_MAX__UINT_FAST16_MAX __UINT_FAST16_MAX____SIG_ATOMIC_MAX__ 0x7fffffff_WINT_T INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)MAX_USER_CONTROL_CALLBACK 4current_address__ARM_PCS_VFP 1INT_LEAST16_MIN__FLT32_HAS_INFINITY__ 1_CLOCK_T_ unsigned long__have_longlong64 1__PTRDIFF_MAX__ 0x7fffffffINT64_MIN (-INT64_MAX - 1)__FLT64_MIN_10_EXP__ (-307)__GNUCLIKE_BUILTIN_CONSTANT_P 1OTG_GRXSTSP_DPID_MDATA (0x3 << 15)needs_zlpextra_string_idxBIT10 (1<<10)UINT_FAST64_MAX__printflike(fmtarg,firstvararg) __attribute__((__format__ (__printf__, fmtarg, firstvararg)))USB_ENDPOINT_ATTR_FEEDBACK 0x10_Booldoeptsiz_Null_unspecified __ULLFRACT_IBIT__ 0_READ_WRITE_BUFSIZE_TYPE int__FLT32_MAX_EXP__ 128__SA_FBIT__ 15OTG_HPTXSTS_PTXQTOP_TYPE_ZEROLENGTH (0x01<<25)__UDA_FBIT__ 32__ACCUM_MIN__ (-0X1P15K-0X1P15K)STATUS_INOTG_HCFG_FSLSS (1 << 2)bDeviceClassOTG_GINTMSK_ESUSPM 0x00000400__DBL_MAX_10_EXP__ 308__const const__USBD_H USB_ENDPOINT_ATTR_CONTROL 0x00OTG_DOEPCTL0_EPENA (1 << 31)__ARM_FEATURE_IDIV 1__WCHAR_TYPE__ unsigned int__GNUCLIKE___TYPEOF 1OTG_DOEPTSIZ0 0xB10OTG_DOEPCTL0_STALL (1 << 21)__UDA_IBIT__ 32__ELF__ 1UINT_FAST32_MAX__SIZEOF_LONG__ 4__need_wint_t USB_FEAT_DEVICE_REMOTE_WAKEUP 1short unsigned intBIT11 (1<<11)__flexarr [0]BIT3 (1<<3)num_strings__UINT_LEAST64_TYPE__ long long unsigned int_STDBOOL_H OTG_DOEPCTL0_MPSIZ_16 (0x2 << 0)SIG_ATOMIC_MIN__SHRT_WIDTH__ 16__STRICT_ANSI__ 1__P(protos) protos__INTPTR_TYPE__ int__DQ_FBIT__ 63__UACCUM_EPSILON__ 0x1P-16UKbInterfaceClass__INT_FAST16_WIDTH__ 32OTG_GINTSTS_CMOD (1 << 0)__FLT_HAS_INFINITY__ 1OTG_DCTL_POPRGDNE (1 << 11)usb_interface_descriptoruint16_tBIT1 (1<<1)OTG_DOEPMSK_B2BSTUP (1 << 6)OTG_GINTSTS_SRQINT (1 << 30)INT_FAST64_MAX __INT_FAST64_MAX__BIT12 (1<<12)__predict_true(exp) __builtin_expect((exp), 1)_usbd_driverOTG_HPRT_PTCTL_PACKET (0x4 << 13)USB_TRANSACTION_OUT__aligned(x) __attribute__((__aligned__(x)))__FLT32X_HAS_INFINITY__ 1USB_DT_ENDPOINT 5__FP_FAST_FMAF32 1OTG_DVBUSDIS 0x828_T_PTRDIFF_ BIT17 (1<<17)OTG_DCTL_SGONAK (1 << 9)__DEQUALIFY(type,var) ((type)(__uintptr_t)(const volatile void *)(var))__USBSTD_H __unbounded __INT_LEAST16_WIDTH__ 16__USFRACT_MIN__ 0.0UHR_FVWRITE_IN_STREAMIO 1_WANT_REGISTER_FINI 1__INT_LEAST32_TYPE__ long int__DBL_HAS_INFINITY__ 1_MB_LEN_MAX 1__no_lock_analysis __lock_annotate(no_thread_safety_analysis)OTG_DCFG_NZLSOHSK 0x0004BIT13 (1<<13)OTG_DOEPCTL0_USBAEP (1 << 15)__SHRT_MAX__ 0x7fffPTRDIFF_MAX __PTRDIFF_MAX__INTMAX_MIN (-INTMAX_MAX - 1)OTG_HAINT 0x414__ATOMIC_ACQ_REL 4_REENT_WCSRTOMBS_STATE(ptr) ((ptr)->_new._reent._wcsrtombs_state)__fastcall __attribute__((__fastcall__))USB_DT_CONFIGURATION_SIZE 9_NOINLINE __attribute__ ((__noinline__))UINTMAX_MAXOTG_HCINTMSK_CHHM (1 << 1)__INT_FAST64_MAX__ 0x7fffffffffffffffLLmax_sizeOTG_DIEPCTL0_MPSIZ_8 (0x3 << 0)__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GCC_ATOMIC_CHAR_LOCK_FREE 2__UINT_FAST16_TYPE__ unsigned intINT_LEAST8_MAX __INT_LEAST8_MAX__GNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsMMIO8(addr) (*(volatile uint8_t *)(addr))__UINT64_MAX__ 0xffffffffffffffffULLOTG_GRXSTSR 0x01COTG_DOEPINTX_EPDISD (1 << 1)OTG_GINTSTS_GINAKEFF (1 << 6)__SIZEOF_INT__ 4__ARMEL__ 1__pure __attribute__((__pure__))__FLT32X_MAX_10_EXP__ 308BIT14 (1<<14)OTG_HCTSIZ_DPID_MASK (0x3 << 29)dwc_ep_setup__SIG_ATOMIC_TYPE__ int_BSD_SIZE_T_DEFINED_ __GNUCLIKE_CTOR_SECTION_HANDLING 1__ULFRACT_EPSILON__ 0x1P-32ULRcontrol_stateOTG_GUSBCFG_FDMOD 0x40000000__UINT16_C(c) c__PRAGMA_REDEFINE_EXTNAME 1__INT_LEAST64_TYPE__ long long intOTG_GOTGINT 0x004_Alignas(x) __aligned(x)OTG_HPTXSTS_PTXQSAV_MASK (0x00ff0000)__lock_acquire(lock) ((void) 0)USB_REQ_SET_INTERFACE 11OTG_HCINT_BBERR (1 << 8)INT64_C__requires_unlocked(...) __lock_annotate(locks_excluded(__VA_ARGS__))__need_size_t___int_wchar_t_h __SYS_LOCK_H__ USB_REQ_SET_CONFIGURATION 9OTG_GRXSTSP_PKTSTS_MASK (0xf << 17)_REENT_CHECK_ASCTIME_BUF(ptr) UINTMAX_C(c) __UINTMAX_C(c)__QQ_FBIT__ 7OTG_DOEPINTX_XFRC (1 << 0)BIT15 (1<<15)OTG_DIEPMSK_BIM (1 << 9)INT8_CmemcpyBIT5 (1<<5)__BIGGEST_ALIGNMENT__ 8__ARM_ARCH__UINT8_TYPE__ unsigned char_REENT_MBLEN_STATE(ptr) ((ptr)->_new._reent._mblen_state)__FLT32_MIN_10_EXP__ (-37)OTG_HPRT_PSPD_LOW (0x2 << 17)__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLK__ULLACCUM_IBIT__ 32user_callback_set_config__INT_LEAST16_MAX__ 0x7fffidVendorOTG_GCCFG_VBUSBSEN (1 << 19)bIntervalOTG_DOEPCTL0_NAKSTS (1 << 17)IDLEBIT16 (1<<16)__SACCUM_IBIT__ 8_ANSIDECL_H_ __UINT16_TYPE__ short unsigned int__EXPOTG_DIEPCTL0_MPSIZ_16 (0x2 << 0)OTG_GUSBCFG 0x00Cextra_string__FLT32_NORM_MAX__ 3.4028234663852886e+38F32OTG_DIEPINT(x) (0x908 + 0x20*(x))__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2OTG_GOTGCTL_HNGSCS (1 << 8)OTG_GINTMSK_USBSUSPM 0x00000800_ATEXIT_SIZE 32__ARM_ARCH_ISA_THUMB 2PTRDIFF_MAXOTG_DIEPCTLX_SD0PID (1 << 28)OTG_HPRT_PSUSP (1 << 7)__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__INT8_C(c) cOTG_GOTGINT_DBCDNE (1 << 19)idProduct__ARM_EABI__ 1__printf0like(fmtarg,firstvararg) UINT64_C(c) __UINT64_C(c)__FLT32_EPSILON__ 1.1920928955078125e-7F32OTG_GRXSTSP_DPID_DATA0 (0x0 << 15)USB_ENDPOINT_ATTR_INTERRUPT 0x03false 0__FLT_MAX_EXP__ 128__INT64_MAX__ 0x7fffffffffffffffLLforce_nak__CC_SUPPORTS___INLINE 1__ATOMIC_SEQ_CST 5_GCC_SIZE_T __lock_close_recursive(lock) ((void) 0)_REENT_CHECK_SIGNAL_BUF(ptr) bcdUSBOTG_DOEPCTL0_SNAK (1 << 27)__FLT32X_MAX_EXP__ 1024__CC_SUPPORTS_WARNING 1__FLT32_MANT_DIG__ 24OTG_DOEPCTL(x) (0xB00 + 0x20*(x))__UINT_FAST8_TYPE__ unsigned intOTG_GOTGCTL_DBCT (1 << 17)__UTA_FBIT__ 64dwc_poll__DBL_DIG__ 15INTPTR_MAX __INTPTR_MAX____EXP(x) __ ##x ##____DECIMAL_DIG__ 17usbd_deviceaddrINT_FAST16_MININT_FAST8_MAX __INT_FAST8_MAX___STDDEF_H __long_double_t long double__has_feature(x) 0OTG_GINTMSK_IISOIXFRM 0x00100000__FLT_DECIMAL_DIG__ 9_REENT_EMERGENCY_SIZE 25__UTA_IBIT__ 64__GCC_IEC_559_COMPLEX 0UINT64_COTG_GINTSTS_ISOODRP (1 << 14)USB_ENDPOINT_ADDR_IN(x) (0x80 | (x))OTG_GOTGCTL_BSVLD (1 << 19)OTG_DOEPMSK_OPEM (1 << 8)USBD_REQ_NOTSUPPBIT18 (1<<18)__LFRACT_IBIT__ 0__USER_LABEL_PREFIX__ USB_ENDPOINT_ATTR_SYNCTYPE 0x0C__attribute_malloc__ _SIZE_T_DECLARED ___int16_t_defined 1OTG_GCCFG_PWRDWN (1 << 16)_REENT_TM(ptr) (&(ptr)->_new._reent._localtime_buf)OTG_HCTSIZ_DPID_DATA1 (0x2 << 29)INT64_MAX __INT64_MAX__OTG_GRXSTSP_DPID_MASK (0x3 << 15)__QQ_IBIT__ 0OTG_HPTXSTS_PTXQTOP_EVENFRM (0<<31)OTG_GINTMSK_PTXFEM 0x04000000OTG_DIEPINTX_INEPNE (1 << 6)__pt_guarded_by(x) __lock_annotate(pt_guarded_by(x))UINT_LEAST64_MAXOTG_DOEPCTL0 0xB00USB_REQ_TYPE_ENDPOINT 0x02__DBL_MIN__ ((double)2.2250738585072014e-308L)USB_REQ_TYPE_CLASS 0x20current_config__INT_FAST8_MAX__ 0x7fffffff_WCHAR_T OTG_HPTXSTS_PTXQTOP_TYPE_INOUT (0x00<<25)__INT_FAST8_WIDTH__ 32__DEC_EVAL_METHOD__ 2USB_REQ_GET_STATUS 0INT_FAST32_MAX__ARM_FP16_ARGSOTG_DCFG_DAD 0x07F0__FLT32_MIN_EXP__ (-125)user_callback_set_altsetting__LLFRACT_MIN__ (-0.5LLR-0.5LLR)typeinterface__LDBL_MIN_EXP__ (-1021)__DBL_MIN_10_EXP__ (-307)OTG_HCINTMSK_STALLM (1 << 3)BIT7 (1<<7)__UFRACT_MIN__ 0.0UR_GCC_PTRDIFF_T _T_SIZE_ __FLT_MIN_10_EXP__ (-37)__FLT32X_DIG__ 15INT_LEAST64_MAX __INT_LEAST64_MAX____UDQ_IBIT__ 0dwc_ep_stall_get__DBL_MANT_DIG__ 53__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)__PTRDIFF_WIDTH__ 32__FBSDID(s) struct __hackOTG_HPRT_PTCTL_FORCE_ENABLE (0x5 << 13)bDeviceSubClassINT8_MAX __INT8_MAX____ULLACCUM_MIN__ 0.0ULLK__INT_WCHAR_T_H __lock_annotate(x) INT_FAST64_MAXdwc_set_addressUSB_DT_STRING 3OTG_HCTSIZ_DPID_MDATA (0x3 << 29)__size_t __WINT_MAX__ 0xffffffffU__ARM_FP16_FORMAT_ALTERNATIVEUINTPTR_MAXOTG_HPRT_POCA (1 << 4)INT32_C(c) __INT32_C(c)INT_LEAST32_MINdwc_flush_txfifoOTG_HCINT_DTERR (1 << 10)__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1__UINT32_TYPE__ long unsigned int__FLT_EPSILON__ 1.1920928955078125e-7F__GNUCLIKE___OFFSETOF 1bInterfaceNumber__UINT8_C(c) cUSB_REQ_CLEAR_FEATURE 1__CC_SUPPORTS_INLINE 1__ARM_FEATURE_NUMERIC_MAXMINOTG_HPRT_PSPD_FULL (0x1 << 17)rx_fifo_sizeINT8_C(c) __INT8_C(c)UINT16_MAX __UINT16_MAX____weak_symbol __attribute__((__weak__))OTG_GCCFG_VBDEN (1 << 21)OTG_HPRT_PCSTS (1 << 0)_REENT_RAND48_ADD(ptr) ((ptr)->_new._reent._r48._add)__ULLFRACT_MIN__ 0.0ULLROTG_DOEPMSK_XFRCM (1 << 0)unsigned char__ARM_FEATURE_QRDMXBIT8 (1<<8)__SFRACT_IBIT__ 0__lock_release(lock) ((void) 0)__ORDER_LITTLE_ENDIAN__ 1234OTG_HCCHAR_EPTYP_MASK (3 << 18)_REENT_SIGNGAM(ptr) ((ptr)->_new._reent._gamma_signgam)usbd_request_return_codesOTG_GINTSTS 0x014OTG_GUSBCFG_CTXPKT 0x80000000__FLT_DIG__ 6OTG_GRXSTSP 0x020OTG_GRXFSIZ 0x024__alloc_size2(n,x) __attribute__((__alloc_size__(n, x)))_REENT_ASCTIME_BUF(ptr) ((ptr)->_new._reent._asctime_buf)OTG_GRXSTSP_PKTSTS_SETUP_COMP (0x4 << 17)__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULK__LLFRACT_IBIT__ 0__UINT_LEAST16_MAX__ 0xffff__SIZE_WIDTH__ 32OTG_HPTXSTS_PTXQTOP_TERMINATE (1<<24)__null_sentinel __attribute__((__sentinel__))__ARM_FEATURE_FP16_FML__GNUCLIKE___SECTION 1BIT2 (1<<2)OTG_GOTGINT_HNSSCHG (1 << 9)__SIZEOF_SIZE_T__ 4_PTRDIFF_T_DECLARED _PTRDIFF_T __Long longINT_LEAST16_MAX __INT_LEAST16_MAX__HAVE_INITFINI_ARRAY 1OTG_DVBUSPULSE 0x82C__lock_release_recursive(lock) ((void) 0)__format_arg(fmtarg) __attribute__((__format_arg__ (fmtarg)))OTG_GRSTCTL_AHBIDL (1 << 31)INT_FAST16_MAXWCHAR_MINOTG_DCTL_SDIS (1 << 1)BEGIN_DECLS UINT_FAST8_MAX __UINT_FAST8_MAX__OTG_DOEPMSK_STUPM (1 << 3)ep_read_packet__LLACCUM_EPSILON__ 0x1P-31LLKOTG_DAINT 0x818MIN(a,b) ((a) < (b) ? (a) : (b))PTRDIFF_MIN (-PTRDIFF_MAX - 1)usb_device_descriptor__DBL_DECIMAL_DIG__ 17__SIZEOF_LONG_LONG__ 8OTG_DCTL_RWUSIG (1 << 0)WCHAR_MAX __WCHAR_MAX__OTG_GOTGINT_SEDET (1 << 2)__FLT32_DECIMAL_DIG__ 9__NEWLIB_MINOR__ 3OTG_DIEPINTX_ITTXFE (1 << 4)_REENT_MBSRTOWCS_STATE(ptr) ((ptr)->_new._reent._mbsrtowcs_state)OTG_HCINTMSK_FRMORM (1 << 9)__datatype_type_tag(kind,type) initOTG_DIEPCTL0_MPSIZ_32 (0x1 << 0)ep_stall_setUINT8_C__OBSOLETE_MATH_DEFAULT 1__bounded __WINT_TYPE__ unsigned int___int_least8_t_defined 1/build/libopencm3/lib/stm32/l4__arg_type_tag(arg_kind,arg_idx,type_tag_idx) OTG_GOTGCTL_SRQ (1 << 1)USB_REQ_TYPE_STANDARD 0x00_ATEXIT_DYNAMIC_ALLOC 1OTG_DIEPCTL0_SNAK (1 << 27)__INT16_MAX__ 0x7fff__ULACCUM_EPSILON__ 0x1P-32ULK__FLT_MANT_DIG__ 24INT_LEAST64_MIN__asserts_exclusive(...) __lock_annotate(assert_exclusive_lock(__VA_ARGS__))OTG_PCGCCTL 0xE00__ULACCUM_FBIT__ 32__USB_DWC_COMMON_H_ __GNUC_VA_LIST_COMPATIBILITY 1bFunctionSubClassOTG_HCCHAR_EPDIR_IN (1 << 15)OTG_DOEPMSK_EPDM (1 << 1)__asserts_shared(...) __lock_annotate(assert_shared_lock(__VA_ARGS__))wMaxPacketSizeOTG_DCTL_GINSTS (1 << 2)__ARM_ARCH_PROFILE 77__GNUCLIKE_MATH_BUILTIN_RELOPS fifo__ULACCUM_IBIT__ 32__ARM_FEATURE_COPROC 15BIT20 (1<<20)bEndpointAddressOTG_HPTXSTS_PTXQTOP_TYPE_DISABLECMD (0x11<<25)OTG_GCCFG_NOVBUSSENS (1 << 21)_WCHAR_T_H __INT_LEAST8_MAX__ 0x7fUSB_ENDPOINT_ATTR_ADAPTIVE 0x08__FLT_MIN_EXP__ (-125)__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__OTG_HCINT_ACK (1 << 5)__UINT64_C(c) c ## ULL__FRACT_IBIT__ 0__FLT_RADIX__ 2__USA_FBIT__ 16__HQ_FBIT__ 15USB_ENDPOINT_ATTR_ASYNC 0x04USBD_REQ_HANDLEDOTG_DOEPINT(x) (0xB08 + 0x20*(x))usb_config_descriptor__RAND_MAX 0x7fffffffUSB_REQ_GET_DESCRIPTOR 6__ARM_BF16_FORMAT_ALTERNATIVEOTG_DOEPCTL0_MPSIZ_8 (0x3 << 0)__FLT_EVAL_METHOD_TS_18661_3__ 0OTG_HFNUM_FRNUM_MASK (0x0000ffff)__SQ_FBIT__ 31__UINTMAX_MAX__ 0xffffffffffffffffULLOTG_HPRT_PPWR (1 << 12)__LDBL_HAS_DENORM__ 1__USA_IBIT__ 16__ACCUM_EPSILON__ 0x1P-15K__LLFRACT_EPSILON__ 0x1P-63LLR__UINT64_TYPE__ long long unsigned int__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK_REENT_CHECK_TM(ptr) BIT21 (1<<21)OTG_DIEPCTL0_USBAEP (1 << 15)_REENT_INIT_PTR(var) { memset((var), 0, sizeof(*(var))); _REENT_INIT_PTR_ZEROED(var); }INT_FAST32_MIN__FRACT_EPSILON__ 0x1P-15R__FLT32X_MANT_DIG__ 53__NEWLIB_PATCHLEVEL__ 0__lock_init_recursive(lock) ((void) 0)__GCC_ATOMIC_INT_LOCK_FREE 2__GCC_ASM_FLAG_OUTPUTS__ 1BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)OTG_HCTSIZ_PKTCNT_MASK (0x3ff << 19)__LDBL_DECIMAL_DIG__ 17__INT_WIDTH__ 32OTG_GOTGCTL_HSHNPEN (1 << 10)dwc_ep_nak_setOTG_GINTSTS_MMIS (1 << 1)__FLT32_IS_IEC_60559__ 2__UDQ_FBIT__ 64OTG_GOTGCTL_SRQSCS (1 << 0)_GLOBAL_REENT _global_impure_ptr__FLT64_DIG__ 15__ARM_NEON__weak_reference(sym,alias) __asm__(".weak " #alias); __asm__(".equ " #alias ", " #sym)__ARM_ARCH_7EM__ 1___int64_t_defined 1OTG_HCINTMSK_NAKM (1 << 4)__GNUCLIKE_BUILTIN_NEXT_ARG 1OTG_HPRT_POCCHNG (1 << 5)BIT30 (1<<30)INT_FAST8_MAXBIT22 (1<<22)OTG_HCFG_FSLSPCS_6MHz (0x2 << 0)__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2__INT16_TYPE__ short int_REENT_RAND48_SEED(ptr) ((ptr)->_new._reent._r48._seed)OTG_GUSBCFG_NPTXRWEN 0x00004000__FRACT_MIN__ (-0.5R-0.5R)__ULFRACT_FBIT__ 32__GNUCLIKE_BUILTIN_MEMCPY 1usb_endpoint_descriptor__sym_default(sym,impl,verid) __asm__(".symver " #impl ", " #sym "@@" #verid)otgfs_usb_driver stm32f107_usb_driver_SIZE_T_DEFINED_ size_t__GCC_ATOMIC_LONG_LOCK_FREE 2_GCC_STDINT_H __ARM_FEATURE_CRYPTOOTG_GINTMSK_HCIM 0x02000000__GXX_TYPEINFO_EQUALITY_INLINE 0_REENT_STDIO_STREAM(var,index) &(var)->__sf[index]___int_least32_t_defined 1OTG_HCTSIZ_DPID_DATA0 (0x0 << 29)__UHQ_FBIT__ 16uint8_tnum_altsetting__USACCUM_IBIT__ 8NULL__locks_exclusive(...) __lock_annotate(exclusive_lock_function(__VA_ARGS__))OTG_DIEPCTL0_NAKSTS (1 << 17)OTG_GINTMSK_NPTXFEM 0x00000020OTG_HFNUM_FTREM_MASK (0xffff0000)BIT23 (1<<23)__FP_FAST_FMAF 1__WCHAR_MIN__ 0UOTG_HAINTMSK_HAINT_MASK (0x0000ffff)OTG_DCTL_CGONAK (1 << 10)OTG_GUSBCFG_PHYSEL (1 << 6)USB_FEAT_ENDPOINT_HALT 0_REENT_CHECK_MP(ptr) __HAVE_SPECULATION_SAFE_VALUE 1_GCC_WCHAR_T _WCHAR_T_DEFINED_ __LOCK_INIT(class,lock) static int lock = 0;___int_size_t_h OTG_HPTXSTS_PTXQTOP_ODDFRM (1<<31)OTG_GRSTCTL_TXFNUM_MASK (0x1f << 6)OTG_GINTSTS_HCINT (1 << 25)OTG_GAHBCFG_PTXFELVL 0x0100STM32L4 1__INT_FAST64_WIDTH__ 64__FRACT_FBIT__ 15UINT_LEAST64_MAX __UINT_LEAST64_MAX____dead2 __attribute__((__noreturn__))__need_size_t __INT32_MAX__ 0x7fffffffL__volatile volatile__CHAR_UNSIGNED__ 1__SFRACT_FBIT__ 7BIT24 (1<<24)_BSD_WCHAR_T___SCHAR_MAX__ 0x7f__GCC_HAVE_DWARF2_CFI_ASM 1../../usb/usb_dwc_common.cINT16_MAX __INT16_MAX___SIZE_T_ __SACCUM_EPSILON__ 0x1P-7HKpktsts__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRUINT64_MAX __UINT64_MAX__OTG_DIEPMSK_ITTXFEMSK (1 << 4)OTG_HCTSIZ_DPID_DATA2 (0x1 << 29)USB_ENDPOINT_ATTR_DATA 0x00USB_REQ_TYPE_IN 0x80cur_altsettingLIBOPENCM3_USB_DWC_OTG_COMMON_H __UACCUM_MIN__ 0.0UK__containerof(x,s,m) ({ const volatile __typeof(((s *)0)->m) *__x = (x); __DEQUALIFY(s *, (const volatile char *)__x - __offsetof(s, m));})INT_LEAST32_MAX __INT_LEAST32_MAX__OTG_HCCHAR(x) (0x500 + 0x20*(x))__GNUCLIKE_ASM 3OTG_HCCHAR_CHDIS (1 << 30)__FLT_HAS_QUIET_NAN__ 1UINT_FAST64_MAX __UINT_FAST64_MAX__USB_ENDPOINT_ADDR_OUT(x) (x)BIT25 (1<<25)ep_nak_set__FLT32X_NORM_MAX__ 1.7976931348623157e+308F32xSIG_ATOMIC_MAX __SIG_ATOMIC_MAX___REENT_INIT_PTR_ZEROED(var) { (var)->_stdin = _REENT_STDIO_STREAM(var, 0); (var)->_stdout = _REENT_STDIO_STREAM(var, 1); (var)->_stderr = _REENT_STDIO_STREAM(var, 2); (var)->_new._reent._rand_next = 1; (var)->_new._reent._r48._seed[0] = _RAND48_SEED_0; (var)->_new._reent._r48._seed[1] = _RAND48_SEED_1; (var)->_new._reent._r48._seed[2] = _RAND48_SEED_2; (var)->_new._reent._r48._mult[0] = _RAND48_MULT_0; (var)->_new._reent._r48._mult[1] = _RAND48_MULT_1; (var)->_new._reent._r48._mult[2] = _RAND48_MULT_2; (var)->_new._reent._r48._add = _RAND48_ADD; }USB_DT_INTERFACE_SIZE 9OTG_DIEPCTL0_EPDIS (1 << 30)UINTMAX_C_REENT_MP_RESULT_K(ptr) ((ptr)->_result_k)_T_WCHAR_ __SCHAR_WIDTH__ 8__ORDER_PDP_ENDIAN__ 3412__ATOMIC_ACQUIRE 2__INT_FAST32_WIDTH__ 32dev_base_address (usbd_dev->driver->base_address)__SIZEOF_PTRDIFF_T__ 4__INT_FAST64_TYPE__ long long int__noinline __attribute__ ((__noinline__))__ACCUM_FBIT__ 15__LLACCUM_FBIT__ 31__attribute_pure__ _HAVE_LONG_DOUBLE 1__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_QBIT 1__UINT32_C(c) c ## UL__WINT_WIDTH__ 32UINT32_C(c) __UINT32_C(c)__ARM_FEATURE_UNALIGNED 1__nonnull(x) __attribute__((__nonnull__ x))__SACCUM_MAX__ 0X7FFFP-7HK__section(x) __attribute__((__section__(x)))BIT26 (1<<26)INTMAX_MAXOTG_DIEPMSK_TXFURM (1 << 8)__LDBL_NORM_MAX__ 1.7976931348623157e+308L__ptrvalue __ACCUM_IBIT__ 16OTG_GRSTCTL_FCRST (1 << 2)OTG_HPTXSTS_PTXQTOP_CHANNEL_NUMBER_MASK (0xf<<27)OTG_GINTMSK_OEPINT 0x00080000__INTMAX_WIDTH__ 64USB_ENDPOINT_ATTR_BULK 0x02OTG_DCFG 0x800OTG_GINTSTS_IPXFR (1 << 21)__ARM_FEATURE_LDREX 7__INT_LEAST64_WIDTH__ 64__NULLABILITY_PRAGMA_POP OTG_GRXSTSP_DPID_DATA1 (0x2 << 15)_NEWLIB_VERSION_H__ 1__LDBL_EPSILON__ 2.2204460492503131e-16L__need_wint_t__ARM_32BIT_STATE 1__ATOMIC_RELAXED 0OTG_GUSBCFG_HNPCAP 0x00000200__LFRACT_MAX__ 0X7FFFFFFFP-31LR__LDBL_MIN__ 2.2250738585072014e-308LOTG_DIEPMSK_EPDM (1 << 1)OTG_GINTMSK_IEPINT 0x00040000BIT27 (1<<27)__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)__NEWLIB__ 3wLength__returns_twice __attribute__((__returns_twice__))stallOTG_HCINTMSK_TXERRM (1 << 7)_REENT_MP_RESULT(ptr) ((ptr)->_result)__GCC_IEC_559 0__FLT_IS_IEC_60559__ 2__FLT32X_EPSILON__ 2.2204460492503131e-16F32x__UFRACT_IBIT__ 0_REENT_GETDATE_ERR_P(ptr) (&((ptr)->_new._reent._getdate_err))OTG_HCINTMSK_DTERRM (1 << 10)dwc_disconnect_END_STD_C OTG_GOTGCTL_CIDSTS (1 << 16)MMIO32(addr) (*(volatile uint32_t *)(addr))_NULL 0__wchar_t__ OTG_CID_HAS_VBDEN 0x00002000usbd_endpoint_callbackusb_iface_assoc_descriptor_TIME_T_ __int_least64_t_WCHAR_T_DECLARED __alloc_size(x) __attribute__((__alloc_size__(x)))_REENT_CHECK_EMERGENCY(ptr) _UNBUF_STREAM_OPT 1BIT28 (1<<28)__sym_compat(sym,impl,verid) __asm__(".symver " #impl ", " #sym "@" #verid)_NEWLIB_VERSION "3.3.0"__INT_LEAST8_WIDTH__ 8altsetting__GNUC__ 12usbd_devOTG_DCTL_SGINAK (1 << 8)__ARM_FEATURE_COPROC__INT_FAST16_TYPE__ intiManufacturerOTG_DOEPTSIZ(x) (0xB10 + 0x20*(x))__INT_LEAST32_WIDTH__ 32__UTQ_IBIT__ 0rxstsp__DBL_IS_IEC_60559__ 2OTG_HPRT_PTCTL_K (0x2 << 13)OTG_DIEPMSK 0x810__SIZEOF_WINT_T__ 4OTG_GINTSTS_SOF (1 << 3)__FLT64_MAX_10_EXP__ 308OTG_DIEPINTX_EPDISD (1 << 1)USB_REQ_GET_INTERFACE 10INT_FAST8_MIN__ARM_FEATURE_SAT 1__INT_MAX__ 0x7fffffffOTG_GINTMSK_CIDSCHGM 0x10000000ep_setupOTG_HCINTMSK_ACKM (1 << 5)__FLT_MAX__ 3.4028234663852886e+38F__INT_LEAST8_TYPE__ signed char__GXX_ABI_VERSION 1017BIT29 (1<<29)INT32_C__DBL_MAX_EXP__ 1024user_callback_ctrotghs_usb_driver stm32f207_usb_driver__ARM_ARCH_ISA_THUMB__FLT64_IS_IEC_60559__ 2OTG_DIEPINTX_TOC (1 << 3)__SIZEOF_WCHAR_T__ 4OTG_DIEPMSK_XFRCM (1 << 0)INTMAX_C__USACCUM_MAX__ 0XFFFFP-8UHK__strong_reference(sym,aliassym) extern __typeof (sym) aliassym __attribute__ ((__alias__ (#sym)))extra__INT8_MAX__ 0x7f_WCHAR_T_ __INT_LEAST32_MAX__ 0x7fffffffLOTG_HCCHAR_DAD_MASK (0x7f << 22)__GNUCLIKE_BUILTIN_VARARGS 1_Kmax (sizeof (size_t) << 3)OTG_DIEPCTL0_MPSIZ_MASK (0x3 << 0)__ASMNAME(cname) __XSTRING (__USER_LABEL_PREFIX__) cname_Thread_local __thread__USACCUM_EPSILON__ 0x1P-8UHK___int_least16_t_defined 1OTG_HPRT_PENA (1 << 2)INT_FAST32_MIN (-INT_FAST32_MAX - 1)OTG_HCCHAR_EPDIR_OUT (0 << 15)_SYS_SIZE_T_H __INTMAX_C(c) c ## LLOTG_DIEPSIZ0_STUPCNT_3 (0x3 << 29)__UINT_FAST16_MAX__ 0xffffffffU__ARM_ARCH_EXT_IDIV__ 1__UINT_FAST64_TYPE__ long long unsigned int_REENT_RAND_NEXT(ptr) ((ptr)->_new._reent._rand_next)BIT0 (1<<0)OTG_GRSTCTL_TXFNUM_ALL (0x10 << 6)__locks_shared(...) __lock_annotate(shared_lock_function(__VA_ARGS__))__GNUCLIKE_BUILTIN_VAALIST 1__UFRACT_EPSILON__ 0x1P-16URINT8_MAX__SIZE_MAX__ 0xffffffffUOTG_GCCFG_VBUSASEN (1 << 18)_RAND48_MULT_0 (0xe66d)WINT_MIN_REENT_EMERGENCY(ptr) ((ptr)->_emergency)OTG_GINTMSK 0x018__UINT_FAST8_MAX__ 0xffffffffUOTG_FIFO(x) (((x) + 1) << 12)OTG_GINTMSK_SRQIM 0x40000000ctrl_len_REENT _impure_ptr_REENT_WCTOMB_STATE(ptr) ((ptr)->_new._reent._wctomb_state)OTG_DOEPINTX_B2BSTUP (1 << 6)OTG_DIEPCTL0_EPENA (1 << 31)__SQ_IBIT__ 0USB_ENDPOINT_ATTR_IMPLICIT_FEEDBACK_DATA 0x20INT_FAST16_MIN (-INT_FAST16_MAX - 1)__ARM_FEATURE_SIMD32 1OTG_DIEPCTL0_STALL (1 << 21)__need_NULLoffsetof(TYPE,MEMBER) __builtin_offsetof (TYPE, MEMBER)__UHQ_IBIT__ 0_TIMER_T_ unsigned long__packed __attribute__((__packed__))disconnect__SFRACT_MIN__ (-0.5HR-0.5HR)__thumb2__ 1__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1OTG_HCINTMSK_NYET (1 << 6)__LACCUM_FBIT__ 31__ULACCUM_MIN__ 0.0ULK__min_size(x) static (x)_SYS__TYPES_H OTG_GUSBCFG_TRDT_MASK (0xf << 10)USB_DEV_STATUS_SELF_POWERED 0x01__LONG_MAX__ 0x7fffffffLUSB_REQ_SET_DESCRIPTOR 7__RCSID(s) struct __hack__lock_try_acquire(lock) ((void) 0)__INT32_C(c) c ## LOTG_HCFG 0x400OTG_HCCHAR_MCNT_1 (0x1 << 20)OTG_GOTGCTL 0x000__FLT64_NORM_MAX__ 1.7976931348623157e+308F64OTG_GRXSTSP_FRMNUM_MASK (0xf << 21)INTPTR_MAXdwc_endpoints_resetbLength__GNUCLIKE_BUILTIN_STDARG 1OTG_GRXSTSP_PKTSTS_OUT_COMP (0x3 << 17)USB_REQ_TYPE_OUT 0x0OTG_DOEPMSK_BOIM (1 << 9)__FLT32X_IS_IEC_60559__ 2OTG_GRXSTSP_PKTSTS_CHH (0x7 << 17)__IEEE_LITTLE_ENDIAN OTG_HCINT_STALL (1 << 3)UINT_FAST32_MAX __UINT_FAST32_MAX__OTG_GRXSTSP_BCNT_MASK (0x7ff << 4)_BEGIN_STD_C bRequestUINT32_C_usbd_device__need_wchar_tOTG_DIEPCTL0_EPTYP_MASK (0x3 << 18)signed chariFunctionrxbcnt___int_least64_t_defined 1OTG_GUSBCFG_TOCAL 0x00000003__size_t__ bFunctionClass__SYS_CONFIG_H__ __predict_false(exp) __builtin_expect((exp), 0)OTG_GAHBCFG_TXFELVL 0x0080BIT6 (1<<6)INTMAX_C(c) __INTMAX_C(c)WINT_MAX __WINT_MAX____ULLACCUM_EPSILON__ 0x1P-32ULLKOTG_DIEPEMPMSK 0x834__CHAR_BIT__ 8INTMAX_MIN__INTMAX_TYPE__ long long int_POINTER_INT longOTG_DCTL_TCTL_MASK (7 << 4)__HQ_IBIT__ 0__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xOTG_HPTXSTS_PTXQTOP_MASK (0xff000000)_REENT_INIT(var) { 0, _REENT_STDIO_STREAM(&(var), 0), _REENT_STDIO_STREAM(&(var), 1), _REENT_STDIO_STREAM(&(var), 2), 0, "", 0, _NULL, 0, _NULL, _NULL, 0, _NULL, _NULL, 0, _NULL, { { 0, _NULL, "", {0, 0, 0, 0, 0, 0, 0, 0, 0}, 0, 1, { {_RAND48_SEED_0, _RAND48_SEED_1, _RAND48_SEED_2}, {_RAND48_MULT_0, _RAND48_MULT_1, _RAND48_MULT_2}, _RAND48_ADD }, {0, {0}}, {0, {0}}, {0, {0}}, "", "", 0, {0, {0}}, {0, {0}}, {0, {0}}, {0, {0}}, {0, {0}} } }, _REENT_INIT_ATEXIT _NULL, {_NULL, 0, _NULL} }bDeviceProtocolOTG_GINTSTS_EOPF (1 << 15)__ARM_FEATURE_DOTPROD_GLOBAL_ATEXIT (_GLOBAL_REENT->_atexit)intstsendpoint_BSD_SIZE_T_ usb_control_stateOTG_HAINTMSK 0x418UINT16_C(c) __UINT16_C(c)_usbd_transaction__FLT64_MIN__ 2.2250738585072014e-308F64__INTPTR_MAX__ 0x7fffffffINT8_MINOTG_HCINT_NYET (1 << 6)__GCC_ATOMIC_POINTER_LOCK_FREE 2_Nonnull __DBL_MAX__ ((double)1.7976931348623157e+308L)OTG_GINTMSK_ISOODRPM 0x00004000_RAND48_MULT_1 (0xdeec)__FLT32_MAX_10_EXP__ 38_REENT_RAND48_MULT(ptr) ((ptr)->_new._reent._r48._mult)iface_assocINT_LEAST32_MIN (-INT_LEAST32_MAX - 1)stateINT_LEAST8_MAX_REENT_MBRTOWC_STATE(ptr) ((ptr)->_new._reent._mbrtowc_state)__WCHAR_T__ OTG_GRXSTSP_PKTSTS_DTERR (0x5 << 17)fifo_mem_top_REENT_CHECK_VERIFY 1_ANSI_STDDEF_H dwc_ep_read_packetiConfigurationUSB_REQ_SET_SYNCH_FRAME 12__ARM_FP16_FORMAT_IEEEOTG_GINTMSK_PRTIM 0x01000000_RAND48_MULT_2 (0x0005)_CLOCKID_T_ unsigned long__CC_SUPPORTS_VARADIC_XXX 1__USES_INITFINI__ 1__DEVOLATILE(type,var) ((type)(__uintptr_t)(volatile void *)(var))USBD_REQ_NEXT_CALLBACK__FLT64_MAX_EXP__ 1024__lockable __lock_annotate(lockable)OTG_HCCHAR_EPDIR_MASK (1 << 15)callback__REGISTER_PREFIX__ __FINITE_MATH_ONLY__ 0OTG_GOTGINT_ADTOCHG (1 << 18)OTG_HCCHAR_MCNT_3 (0x3 << 20)__unlocks(...) __lock_annotate(unlock_function(__VA_ARGS__))OTG_HCCHAR_EPTYP_INTERRUPT (3 << 18)__USFRACT_MAX__ 0XFFP-8UHROTG_HCCHAR_EPTYP_ISOCHRONOUS (1 << 18)_STRING_H_ __FLT32_MAX__ 3.4028234663852886e+38F32STALLEDOTG_HCCHAR_MCNT_MASK (0x3 << 20)__lock_close(lock) ((void) 0)OTG_GINTMSK_USBRST 0x00001000__FRACT_MAX__ 0X7FFFP-15R__warn_references(sym,msg) __asm__(".section .gnu.warning." #sym); __asm__(".asciz \"" msg "\""); __asm__(".previous")OTG_DIEPINTX_TXFE (1 << 7)__generic(expr,t,yes,no) __builtin_choose_expr( __builtin_types_compatible_p(__typeof(expr), t), yes, no)OTG_HCINT(x) (0x508 + 0x20*(x))__USQ_FBIT__ 32__INT_FAST8_TYPE__ intLAST_DATA_OUTUINT8_C(c) __UINT8_C(c)UINT32_MAX__ARM_FEATURE_BF16_SCALAR_ARITHMETIC__ptr_t void *OTG_HCINT_AHBERR (1 << 2)unsigneddwc_ep_write_packet__STDC_HOSTED__ 1__UINTMAX_C(c) c ## ULL__need_ptrdiff_tUSB_CONFIG_ATTR_SELF_POWERED 0x40user_callback_reset__requires_exclusive(...) __lock_annotate(exclusive_locks_required(__VA_ARGS__))INT_LEAST64_MAXlong intUSB_DT_ENDPOINT_SIZE 7OTG_HPRT_PENCHNG (1 << 3)_REENT_MP_P5S(ptr) ((ptr)->_p5s)__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)INT16_MAX__DBL_HAS_DENORM__ 1__ATFILE_VISIBLE 0__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1OTG_HCTSIZ(x) (0x510 + 0x20*(x))_WCHAR_T_DEFINED _N_LISTS 30OTG_HFIR 0x404__PTRDIFF_TYPE__ intctrl_buf_lenOTG_GRXSTSP_PKTSTS_OUT (0x2 << 17)__USACCUM_FBIT__ 8__GNUC_STDC_INLINE__ 1OTG_DOEPCTL0_EPTYP_MASK (0x3 << 18)UINT64_MAX__ARM_FPset_address_before_statusOTG_HPTXSTS_PTXQTOP_ENDPOINT_NUMBER_MASK (0xf<<27)__EXPORT __PMT(args) argsOTG_HCINTMSK_AHBERR (1 << 2)_PTRDIFF_T_ UINT_FAST8_MAXOTG_GINTMSK_IPXFRM 0x00200000__WCHAR_WIDTH__ 32__UTQ_FBIT__ 128__USB_PRIVATE_H __strftimelike(fmtarg,firstvararg) __attribute__((__format__ (__strftime__, fmtarg, firstvararg)))LIBOPENCM3_CM3_COMMON_H __PTRDIFF_T OTG_GINTSTS_ESUSP (1 << 10)__ARM_FEATURE_DSP 1OTG_HNPTXFSIZ_PTXFD_MASK (0xffff0000)OTG_GOTGCTL_DHNPEN (1 << 11)OTG_GRXSTSP_PKTSTS_GOUTNAK (0x1 << 17)__FLT32_HAS_DENORM__ 1__strfmonlike(fmtarg,firstvararg) __attribute__((__format__ (__strfmon__, fmtarg, firstvararg)))user_callback_resumebFunctionProtocolINT32_MIN (-INT32_MAX - 1)__ARM_FEATURE_FP16_SCALAR_ARITHMETIC__always_inline __inline__ __attribute__((__always_inline__))__SACCUM_FBIT__ 7USB_CONFIG_ATTR_REMOTE_WAKEUP 0x20__LLACCUM_IBIT__ 32uint32_t__SIZE_T OTG_DIEPCTL0_TXFNUM_MASK (0xf << 22)__LDBL_DIG__ 15__CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN __SIG_ATOMIC_MIN__OTG_GRSTCTL_TXFFLSH (1 << 5)__XSI_VISIBLE 0__pure2 __attribute__((__const__))__GCC_ATOMIC_SHORT_LOCK_FREE 2OTG_GINTMSK_EOPFM 0x00008000__ULFRACT_MAX__ 0XFFFFFFFFP-32ULROTG_HCCHAR_LSDEV (1 << 17)__SIZEOF_POINTER__ 4__DOTS , ...WINT_MIN __WINT_MIN__OTG_HCFG_FSLSPCS_48MHz (0x1 << 0)OTG_HCCHAR_ODDFRM (1 << 29)OTG_HPTXSTS 0x410__UINTMAX_TYPE__ long long unsigned int_T_SIZE OTG_DSTS 0x808OTG_HCCHAR_MPSIZ_MASK (0x7ff << 0)OTG_HFNUM 0x408__INTPTR_WIDTH__ 32OTG_DIEPSIZ0_PKTCNT (1 << 19)__trylocks_shared(...) __lock_annotate(shared_trylock_function(__VA_ARGS__))_REENT_STRTOK_LAST(ptr) ((ptr)->_new._reent._strtok_last)__DEFINED_wchar_t INTPTR_MINOTG_GINTSTS_INCOMPISOOUT (1 << 21)__result_use_check __attribute__((__warn_unused_result__))OTG_HCCHAR_EPTYP_BULK (2 << 18)OTG_GINTSTS_RXFLVL (1 << 4)__GNUC_PREREQ(maj,min) ((__GNUC__ << 16) + __GNUC_MINOR__ >= ((maj) << 16) + (min))USB_ENDPOINT_ATTR_TYPE 0x03__FLT64_HAS_INFINITY__ 1__GCC_DESTRUCTIVE_SIZE 64USB_DT_INTERFACE_POWER 8USB_DT_DEVICE_QUALIFIER 6__LONG_LONG_MAX__ 0x7fffffffffffffffLLOTG_DOEPCTL0_SNPM (1 << 20)USB_REQ_SET_FEATURE 3__GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"USB_DT_INTERFACE_ASSOCIATION_SIZE sizeof(struct usb_iface_assoc_descriptor)MMIO64(addr) (*(volatile uint64_t *)(addr))__STDC_VERSION__ 199901L__LFRACT_MIN__ (-0.5LR-0.5LR)_HAVE_CC_INHIBIT_LOOP_TO_LIBCALL 1__CONCAT1(x,y) x ## y__RCSID_SOURCE(s) struct __hackOTG_GINTSTS_USBSUSP (1 << 11)__ISO_C_VISIBLE 1999OTG_HPTXFSIZ_PTXSA_MASK (0x0000ffff)INT64_C(c) __INT64_C(c)__GCC_ATOMIC_LLONG_LOCK_FREE 1_SYS_CDEFS_H_ USB_DT_INTERFACE_ASSOCIATION 11usbd_set_config_callbackUSB_REQ_TYPE_INTERFACE 0x01__LONG_LONG_WIDTH__ 64iInterfacebFirstInterfaceOTG_GOTGINT_HNGDET (1 << 17)bAlternateSetting__VERSION__ "12.2.1 20221205"__FLT64_EPSILON__ 2.2204460492503131e-16F64OTG_DOEPMSK 0x814OTG_DCTL 0x804__NEWLIB_H__ 1OTG_GINTSTS_ENUMDNE (1 << 13)USB_DEV_STATUS_REMOTE_WAKEUP 0x02OTG_HCINT_FRMOR (1 << 9)OTG_GRXSTSP_PKTSTS_SETUP (0x6 << 17)__ULLACCUM_FBIT__ 32_REENT_SIGNAL_BUF(ptr) ((ptr)->_new._reent._signal_buf)OTG_GRSTCTL_RXFFLSH (1 << 4)__LDBL_HAS_QUIET_NAN__ 1OTG_GAHBCFG_GINT 0x0001__WCHAR_MAX__ 0xffffffffU_SIZE_T USB_DT_DEVICE 1OTG_HCTSIZ_DOPING (1 << 31)OTG_DOEPCTL0_CNAK (1 << 26)__LDBL_MANT_DIG__ 53__ULLFRACT_FBIT__ 64WCHAR_MAX__DQ_IBIT__ 0buf32__FLT64_MAX__ 1.7976931348623157e+308F64_SIZE_T_DEFINED INT_LEAST8_MINUSB_DT_DEVICE_SIZE sizeof(struct usb_device_descriptor)__UQQ_IBIT__ 0LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))___int8_t_defined 1__SIG_ATOMIC_WIDTH__ 32_Noreturn __dead2__bool_true_false_are_defined 1__ARM_FEATURE_CDE__BSD_VISIBLE 0__need_NULL OTG_DOEPCTL0_MPSIZ_MASK (0x3 << 0)__ARM_FEATURE_LDREX__UINT_LEAST32_MAX__ 0xffffffffULSTATUS_OUTNULL ((void *)0)__USFRACT_EPSILON__ 0x1P-8UHR__ORDER_BIG_ENDIAN__ 4321__ARM_FEATURE_CMSEOTG_HPRT_PLSTS_DP (1 << 10)OTG_DIEPCTL0 0x900__UFRACT_MAX__ 0XFFFFP-16UR_MACHINE__DEFAULT_TYPES_H __UINT_FAST32_TYPE__ unsigned int__SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)OTG_GINTSTS_DISCINT (1 << 29)INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)USB_REQ_TYPE_RECIPIENT 0x1FiProductusb_interfaceUSB_REQ_TYPE_DEVICE 0x00completeOTG_GRSTCTL_CSRST (1 << 0)BIT31 (1<<31)__INT32_TYPE__ long int_T_PTRDIFF OTG_HPTXSTS_PTXFSAVL_MASK (0x0000ffff)OTG_GINTSTS_NPTXFE (1 << 5)__UFRACT_FBIT__ 16OTG_HCINT_NAK (1 << 4)_READ_WRITE_RETURN_TYPE int__ULFRACT_MIN__ 0.0ULR__HA_IBIT__ 8usb_setup_data__TQ_FBIT__ 127__UINTPTR_TYPE__ unsigned int__WINT_MIN__ 0UBIT9 (1<<9)bcdDeviceuser_control_callbackUINT8_MAX __UINT8_MAX__OTG_GINTMSK_WUIM 0x80000000OTG_GRSTCTL 0x010__guarded_by(x) __lock_annotate(guarded_by(x))OTG_HCINTMSK_BBERRM (1 << 8)__LFRACT_FBIT__ 31bMaxPacketSize0driver__ARM_FEATURE_BF16_VECTOR_ARITHMETICUSB_DT_DEBUG 10config_RAND48_SEED_2 (0x1234)__STDC__ 1UINT8_MAXOTG_DIEPMSK_TOM (1 << 3)OTG_HPRT_PCDET (1 << 1)OTG_HCINTMSK(x) (0x50C + 0x20*(x))__ARM_SIZEOF_MINIMAL_ENUM 1OTG_GRXSTSP_DPID_DATA2 (0x1 << 15)__INT64_C(c) c ## LLtype_maskOTG_HCFG_FSLSPCS_MASK (0x3 << 0)INT_LEAST16_MAXbmRequestTypeDATA_IN__DA_FBIT__ 31__FLT32_MIN__ 1.1754943508222875e-38F32OTG_DAINTMSK 0x81CwValueSIZE_MAX __SIZE_MAX__OTG_DOEPCTL0_MPSIZ_32 (0x1 << 0)__XSTRING(x) __STRING(x)__SCCSID(s) struct __hackusbd_set_altsetting_callback__GCC_ATOMIC_BOOL_LOCK_FREE 2INT_FAST64_MINREBASE(x) MMIO32((x) + (dev_base_address))__INT_FAST32_MAX__ 0x7fffffff__FLT_MAX_10_EXP__ 38OTG_GINTMSK_SOFM 0x00000008dwc_ep_stall_setOTG_GRXSTSP_PKTSTS_IN_COMP (0x3 << 17)__ATTRIBUTE_IMPURE_PTR__ __DA_IBIT__ 32fifo_mem_top_ep0__VFP_FP__ 1set_address__ARM_ASM_SYNTAX_UNIFIED__ 1_REENT_CHECK_MISC(ptr) _WANT_IO_LONG_LONG 1INT32_MAX__ARM_FP 4__ULFRACT_IBIT__ 0OTG_GINTSTS_CIDSCHG (1 << 28)__builtin_memcpyOTG_HPRT 0x440__scanflike(fmtarg,firstvararg) __attribute__((__format__ (__scanf__, fmtarg, firstvararg)))OTG_HCCHAR_MCNT_2 (0x2 << 20)__GCC_CONSTRUCTIVE_SIZE 64__ARM_SIZEOF_WCHAR_T 4OTG_GINTMSK_OTGINT 0x00000004UINT_LEAST32_MAX __UINT_LEAST32_MAX____SIZEOF_DOUBLE__ 8__UINT_FAST32_MAX__ 0xffffffffU__LDBL_MAX_EXP__ 1024true 1__UACCUM_MAX__ 0XFFFFFFFFP-16UK__USQ_IBIT__ 0bNumConfigurations_BSD_WCHAR_T_ __GNU_VISIBLE 0__ARM_FEATURE_FP16_VECTOR_ARITHMETICdisconnected_RAND48_ADD (0x000b)ep_stall_getOTG_GOTGCTL_ASVLD (1 << 18)_RAND48_SEED_0 (0x330e)_ATTRIBUTE(attrs) __attribute__ (attrs)LAST_DATA_INOTG_GINTMSK_ENUMDNEM 0x00002000__INTMAX_MAX__ 0x7fffffffffffffffLL__requires_shared(...) __lock_annotate(shared_locks_required(__VA_ARGS__))INT64_MAXbInterfaceProtocolOTG_GINTMSK_MMISM 0x00000002UINT_LEAST16_MAX __UINT_LEAST16_MAX__OTG_GAHBCFG 0x008__LONG_WIDTH__ 32_REENT_MP_FREELIST(ptr) ((ptr)->_freelist)__OPTIMIZE__ 1__signed signed__SSP_FORTIFY_LEVEL 0usbd_control_callback_SYS_FEATURES_H __arm__ 1PTRDIFF_MINOTG_GINTSTS_OEPINT (1 << 19)__restrict restrictOTG_GRSTCTL_HSRST (1 << 1)OTG_HCINTMSK_XFRCM (1 << 0)OTG_DIEPSIZ0_STUPCNT_MASK (0x3 << 29)USB_REQ_TYPE_OTHER 0x03UINT32_MAX __UINT32_MAX____OPTIMIZE_SIZE__ 1ctrl_buf__size_tOTG_GINTSTS_USBRST (1 << 12)__nonnull_all __attribute__((__nonnull__))_ELIDABLE_INLINE static __inline__ep_resetpoll__alloc_align(x) __attribute__((__alloc_align__(x)))_T_WCHAR bDescriptorTypeOTG_DCFG_PFIVL 0x1800_SIZET_ __THUMB_INTERWORK__ 1__INT8_TYPE__ signed char__LDBL_DENORM_MIN__ 4.9406564584124654e-324LOTG_DIEPSIZ0_XFRSIZ_MASK (0x7f << 0)__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1__hidden __attribute__((__visibility__("hidden")))_STDDEF_H_ OTG_GNPTXFSIZ 0x028__RAND_MAX__DEFINED_ptrdiff_t UINT_LEAST32_MAX__GNUC_PREREQ__(ma,mi) __GNUC_PREREQ(ma, mi)__ACCUM_MAX__ 0X7FFFFFFFP-15K__FLT64_MIN_EXP__ (-1021)__INT_FAST32_TYPE__ int__lock_init(lock) ((void) 0)OTG_GCCFG 0x038_Nullable USB_REQ_TYPE_TYPE 0x60__FLT64_HAS_QUIET_NAN__ 1__ARM_NEON___NOTHROW __CC_SUPPORTS___INLINE__ 1OTG_DIEPTSIZ0 0x910stringsOTG_DIEPCTL0_CNAK (1 << 26)OTG_DIEPMSK_INEPNEM (1 << 6)__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)_REENT_INIT_ATEXIT _NULL, _ATEXIT_INIT,_REENT_SIGNAL_SIZE 24_SYS_REENT_H_ __FLT32X_MIN_EXP__ (-1021)_BSD_PTRDIFF_T_ __WCHAR_T __lock_try_acquire_recursive(lock) ((void) 0)__CC_SUPPORTS___FUNC__ 1OTG_DOEPMSK_OTEPDM (1 << 4)__lock_acquire_recursive(lock) ((void) 0)__ARM_ARCH_PROFILEOTG_DOEPINTX_STUP (1 << 3)__LACCUM_IBIT__ 32MMIO16(addr) (*(volatile uint16_t *)(addr))__INT16_C(c) cOTG_HPRT_PRES (1 << 6)___int_ptrdiff_t_h INT16_MININT16_CWCHAR_MIN __WCHAR_MIN____attribute_format_strfmon__(a,b) long long unsigned intOTG_HCCHAR_EPNUM_MASK (0xf << 11)OTG_DIEPTXF(x) (0x104 + 4*((x)-1))UINTPTR_MAX __UINTPTR_MAX__OTG_GUSBCFG_SRPCAP 0x00000100__have_long32 1USB_REQ_SET_ADDRESS 5__UINT8_MAX__ 0xffOTG_GUSBCFG_FHMOD 0x20000000USB_REQ_TYPE_DIRECTION 0x80OTG_DIEPSIZ0_STUPCNT_2 (0x2 << 29)_REENT_WCRTOMB_STATE(ptr) ((ptr)->_new._reent._wcrtomb_state)__BEGIN_DECLS USB_REQ_GET_CONFIGURATION 8chardescBIT19 (1<<19)_REENT_SMALL_CHECK_INIT(ptr) UINT_FAST16_MAX__FLT64_DECIMAL_DIG__ 17__UINTPTR_MAX__ 0xffffffffU__ARM_FEATURE_COMPLEX__SFRACT_EPSILON__ 0x1P-7HR__ATOMIC_CONSUME 1__unused __attribute__((__unused__))__FLT_MIN__ 1.1754943508222875e-38F__INT_LEAST16_TYPE__ short intOTG_DIEPMSK_INEPNMM (1 << 5)END_DECLS INT32_MAX __INT32_MAX__USB_TRANSACTION_SETUP__USFRACT_FBIT__ 8USB_TRANSACTION_INUSB_FEAT_TEST_MODE 2bInterfaceCount__GCC_ATOMIC_WCHAR_T_LOCK_FREE 2OTG_HPTXFSIZ 0x100__LLFRACT_FBIT__ 63__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLKOTG_HPRT_PSPD_HIGH (0x0 << 17)___int32_t_defined 1USB_DT_OTHER_SPEED_CONFIGURATION 7bConfigurationValue__FLT32X_HAS_QUIET_NAN__ 1__GNUC_EXECUTION_CHARSET_NAME "UTF-8"OTG_GNPTXSTS 0x02C__compiler_membar() __asm __volatile(" " : : : "memory")__DBL_MIN_EXP__ (-1021)__exported __attribute__((__visibility__("default")))__NULLABILITY_PRAGMA_PUSH _REENT_MBRLEN_STATE(ptr) ((ptr)->_new._reent._mbrlen_state)bNumEndpointsUINT16_MAX__CC_SUPPORTS_DYNAMIC_ARRAY_INIT 1__FLT32X_DECIMAL_DIG__ 17__LDBL_MAX_10_EXP__ 308OTG_DOEPINTX_OTEPDIS (1 << 4)__IMPORT OTG_HCCHAR_CHENA (1 << 31)USB_DT_INTERFACE 4__INT64_TYPE__ long long intINT_LEAST8_MIN (-INT_LEAST8_MAX - 1)__ARM_FEATURE_CRC32__TA_FBIT__ 63__rangeof(type,start,end) (__offsetof(type, end) - __offsetof(type, start))bool _Bool__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64USB_DT_OTG 9__UINT_LEAST32_TYPE__ long unsigned int_NOINLINE_STATIC _NOINLINE static_usbd_resetOTG_DOEPCTL0_MPSIZ_64 (0x0 << 0)_LONG_DOUBLE long double__used __attribute__((__used__))OTG_HPRT_PTCTL_DISABLED (0x0 << 13)INT32_MIN__OBSOLETE_MATH __OBSOLETE_MATH_DEFAULTINT16_C(c) __INT16_C(c)__TA_IBIT__ 64_ATEXIT_INIT {_NULL, 0, {_NULL}, {{_NULL}, {_NULL}, 0, 0}}OTG_DTXFSTS(x) (0x918 + 0x20*(x))INT8_MIN (-INT8_MAX - 1)__FLT32X_HAS_DENORM__ 1OTG_HCINT_CHH (1 << 1)OTG_HCCHAR_EPTYP_CONTROL (0 << 18)pm_top__FLT32_HAS_QUIET_NAN__ 1__DECONST(type,var) ((type)(__uintptr_t)(const void *)(var))__ATOMIC_RELEASE 3BIT4 (1<<4)OTG_DCFG_DSPD 0x0003long long int__FLT_EVAL_METHOD__ 0__SA_IBIT__ 16__COPYRIGHT(s) struct __hack_WIDE_ORIENT 1OTG_HAINTMSK_HAINTM_MASK (0x0000ffff)unsigned signed__UHA_FBIT__ 8__ULLFRACT_EPSILON__ 0x1P-64ULLR__END_DECLS OTG_CID 0x03C__ARM_FEATURE_CLZ 1INT_LEAST32_MAX__POSIX_VISIBLE 0__ARM_FEATURE_FMA 1__DEFINED_size_t OTG_GOTGINT_SRSSCHG (1 << 8)__ARM_NEON_FP__FDPIC__INT64_MIN__UINT16_MAX__ 0xffffbNumInterfacesOTG_DIEPSIZ0_STUPCNT_1 (0x1 << 29)__ARM_ARCH 7OTG_HPTXFSIZ_PTXFD_MASK (0xffff0000)user_callback_suspendextralenUSB_CLASS_VENDOR 0xFF__SVID_VISIBLE 0wIndex__CONCAT(x,y) __CONCAT1(x,y)__DBL_HAS_QUIET_NAN__ 1__LDBL_MIN_10_EXP__ (-307)__has_extension __has_featurebase_addressSIG_ATOMIC_MAX__USFRACT_IBIT__ 0__UINT_FAST64_MAX__ 0xffffffffffffffffULL__FLT32X_MIN_10_EXP__ (-307)WINT_MAXOTG_HPRT_PSPD_MASK (0x3 << 17)OTG_GINTSTS_PTXFE (1 << 26)_REENT_ASCTIME_SIZE 26USB_REQ_TYPE_VENDOR 0x40OTG_GINTMSK_DISCINT 0x20000000__LDBL_HAS_INFINITY__ 1_FSEEK_OPTIMIZATION 1long unsigned intUSB_DT_CONFIGURATION 2OTG_DOEPCTLX_SD0PID (1 << 28)OTG_HPRT_PTCTL_J (0x1 << 13)__SFRACT_MAX__ 0X7FP-7HROTG_GINTMSK_RXFLVLM 0x00000010OTG_DOEPCTL0_EPDIS (1 << 30)OTG_DSTS_SUSPSTS (1 << 0)USB_ENDPOINT_ATTR_USAGETYPE 0x30_MACHINE__TYPES_H USB_ENDPOINT_ATTR_NOSYNC 0x00__LDBL_MAX__ 1.7976931348623157e+308L__SIZEOF_LONG_DOUBLE__ 8OTG_GINTSTS_GONAKEFF (1 << 7)user_callback_sof__FLT64_HAS_DENORM__ 1OTG_GRXSTSP_EPNUM_MASK (0xf << 0)__FLT_HAS_DENORM__ 1__GNUCLIKE_MATH_BUILTIN_CONSTANTS UINT_LEAST8_MAX__THUMBEL__ 1OTG_GINTSTS_IISOIXFR (1 << 20)OTG_HNPTXFSIZ_PTXSA_MASK (0x0000ffff)iSerialNumberUSB_ENDPOINT_ATTR_SYNC 0x0CDATA_OUTOTG_DCTL_GONSTS (1 << 3)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__TQ_IBIT__ 0__FLT32X_MIN__ 2.2250738585072014e-308F32x__SIZEOF_FLOAT__ 4__SIZE_T__ __SIZE_TYPE__ unsigned int_Alignof(x) __alignof(x)__offsetof(type,field) offsetof(type, field)OTG_GINTSTS_IEPINT (1 << 18)__UINT_LEAST8_TYPE__ unsigned char_RAND48_SEED_1 (0xabcd)__LARGEFILE_VISIBLE 0__unreachable() __builtin_unreachable()UINT16_C__STRING(x) #xOTG_GOTGCTL_HNPRQ (1 << 9)__CHAR16_TYPE__ short unsigned intINT16_MIN (-INT16_MAX - 1)__LDBL_IS_IEC_60559__ 2_REENT_MBTOWC_STATE(ptr) ((ptr)->_new._reent._mbtowc_state)OTG_GCCFG_SOFOUTEN (1 << 20)unsigned intep_write_packet__malloc_like __attribute__((__malloc__))__THROW __ARM_FEATURE_MVE__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32OTG_GINTMSK_EPMISM 0x00020000OTG_HPRT_PLSTS_DM (1 << 11)INT_FAST16_MAX __INT_FAST16_MAX____UHA_IBIT__ 8__ARM_FEATURE_CDE_COPROC__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRbMaxPower__trylocks_exclusive(...) __lock_annotate(exclusive_trylock_function(__VA_ARGS__))short int__UQQ_FBIT__ 8OTG_DIEPTSIZ(x) (0x910 + 0x20*(x))wTotalLength__GNUC_MINOR__ 2OTG_HPRT_PRST (1 << 8)_Atomic(T) struct { T volatile __val; }BBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)INTMAX_MAX __INTMAX_MAX____UINT_LEAST16_TYPE__ short unsigned int_LDBL_EQ_DBL 1OTG_GINTMSK_IISOOXFRM 0x00200000OTG_GRXSTSP_PKTSTS_IN (0x2 << 17)OTG_DIEPCTL0_MPSIZ_64 (0x0 << 0)OTG_HCTSIZ_XFRSIZ_MASK (0x7ffff << 0)OTG_HCINT_TXERR (1 << 7)OTG_GINTMSK_GONAKEFFM 0x00000080OTG_GINTSTS_OTGINT (1 << 2)__FLT_DENORM_MIN__ 1.4012984643248171e-45FOTG_HCINT_XFRC (1 << 0)INT_FAST32_MAX __INT_FAST32_MAX__UINTMAX_MAX __UINTMAX_MAX__INT_FAST64_MIN (-INT_FAST64_MAX - 1)__UINT_LEAST8_MAX__ 0xff__HA_FBIT__ 7__UINT32_MAX__ 0xffffffffUL__LOCK_INIT_RECURSIVE(class,lock) static int lock = 0;USB_ENDPOINT_ATTR_ISOCHRONOUS 0x01OTG_GINTSTS_HPRTINT (1 << 24)OTG_GINTSTS_WKUPINT (1 << 31)__GNUC_PATCHLEVEL__ 1GCC: (15:12.2.rel1-1) 12.2.1 20221205˙˙˙˙| 6B „…†‡‰ŠŽLE„Ž‚C„…Ž$(JA„…†‡ŽpA„…Žg A0ěE „…†‡‰ŠŽK ÎĘÉČÇĆĹÄDA3aeabi)7E-M M "ń˙ !!""##$$%%''))*,-/13ik579;=?ACEGIKMOQSUWY[]_acegm<u¦× <lť Î 8j šČř(Y‹ĽíP°ĺlo +68L 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protosRCC_APB2ENR_TIM17EN (1 << 18)__INTPTR_TYPE__ int__DQ_FBIT__ 63__UACCUM_EPSILON__ 0x1P-16UKbInterfaceClassRCC_CCIPR MMIO32(RCC_BASE + 0x88)__INT_FAST16_WIDTH__ 32RCC_CCIPR_LPTIMxSEL_MASK 0x3RCC_CCIPR_LPTIMxSEL_APB 0__FLT_HAS_INFINITY__ 1OTG_DCTL_POPRGDNE (1 << 11)usb_interface_descriptorRCC_APB1RSTR1_TIM4RST (1 << 2)uint16_tRCC_CICR_PLLRDYC (1 << 5)BIT1 (1<<1)OTG_DOEPMSK_B2BSTUP (1 << 6)OTG_GINTSTS_SRQINT (1 << 30)__bool_true_false_are_defined 1INT_FAST64_MAX __INT_FAST64_MAX__BIT12 (1<<12)__FLT32X_MANT_DIG__ 53OTG_DIEPCTL0_EPTYP_MASK (0x3 << 18)OTG_GUSBCFG_SRPCAP 0x00000100RCC_APB1RSTR1_PWRRST (1 << 28)__predict_true(exp) __builtin_expect((exp), 1)RCC_APB1SMENR1_LPTIM1SMEN (1 << 31)LIBOPENCM3_USB_DWC_OTG_COMMON_H _usbd_driverOTG_HPRT_PTCTL_PACKET (0x4 << 13)__aligned(x) __attribute__((__aligned__(x)))OTG_GOTGCTL_BSVLD (1 << 19)OTG_GCCFG_VBUSBSEN (1 << 19)__FP_FAST_FMAF32 1OTG_DVBUSDIS 0x828GPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800)OTG_GINTMSK_IEPINT 0x00040000OTG_HCCHAR_EPTYP_ISOCHRONOUS (1 << 18)OTG_HCINTMSK_NYET (1 << 6)_T_PTRDIFF_ BIT17 (1<<17)RCC_CFGR_MCO_LSI 0x6RCC_APB1SMENR1_LCDSMEN (1 << 9)RCC_CIFR_LSIRDYF (1 << 0)USB_DT_CONFIGURATION 2__USBSTD_H __unbounded __INT_LEAST16_WIDTH__ 16__USFRACT_MIN__ 0.0UHRRCC_APB1ENR2_SWPMI1EN (1 << 2)_WANT_REGISTER_FINI 1OTG_GAHBCFG 0x008__INT_LEAST32_TYPE__ long int__DBL_HAS_INFINITY__ 1_MB_LEN_MAX 1__no_lock_analysis __lock_annotate(no_thread_safety_analysis)GPIO_PORT_G_BASE (PERIPH_BASE_AHB2 + 0x1800)BIT13 (1<<13)RCC_CCIPR_USART1SEL_APB 0__min_size(x) static (x)RCC_APB1RSTR1_I2C3RST (1 << 23)__SHRT_MAX__ 0x7fffRCC_CFGR_PPRE2_NODIV 0x0OTG_HCINTMSK_ACKM (1 << 5)INT_FAST16_MAX __INT_FAST16_MAX__OTG_FS_CID MMIO32(USB_OTG_FS_BASE + OTG_CID)INTMAX_MIN (-INTMAX_MAX - 1)RCC_CSR_RMVF (1 << 23)__FLT32_HAS_INFINITY__ 1_REENT_WCSRTOMBS_STATE(ptr) ((ptr)->_new._reent._wcsrtombs_state)__fastcall __attribute__((__fastcall__))RCC_CSR_MSIRANGE_SHIFT 8RCC_BDCR_LSECSSON (1 << 5)RCC_CFGR_MCO_PLL 0x5USB_DT_CONFIGURATION_SIZE 9RCC_PLLCFGR_PLLP (1 << 17)_NOINLINE __attribute__ ((__noinline__))UINTMAX_MAXOTG_HCINTMSK_CHHM (1 << 1)__INT_FAST64_MAX__ 0x7fffffffffffffffLLOTG_DIEPCTL0_MPSIZ_8 (0x3 << 0)__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)RCC_APB1RSTR1_CAN1RST (1 << 25)__GCC_ATOMIC_CHAR_LOCK_FREE 2__UINT_FAST16_TYPE__ unsigned intSCC_ADC1GNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsRCC_BDCR MMIO32(RCC_BASE + 0x90)MMIO8(addr) (*(volatile uint8_t *)(addr))__UINT64_MAX__ 0xffffffffffffffffULLRCC_CIER_HSIRDYIE (1 << 3)RCC_APB1ENR1_TIM6EN (1 << 4)OTG_GINTSTS_GINAKEFF (1 << 6)__SIZEOF_INT__ 4__ARMEL__ 1__FLT32X_MAX_10_EXP__ 308BIT14 (1<<14)OTG_GCCFG_VBDEN (1 << 21)OTG_HPTXSTS_PTXQTOP_CHANNEL_NUMBER_MASK (0xf<<27)ITM_BASE (PPBI_BASE + 0x0000)dwc_ep_setup__SIG_ATOMIC_TYPE__ int_BSD_SIZE_T_DEFINED_ __GNUCLIKE_CTOR_SECTION_HANDLING 1RCC_APB1RSTR1_TIM6RST (1 << 4)__ULFRACT_EPSILON__ 0x1P-32ULRRCC_CICR_MSIRDYC (1 << 2)control_stateOTG_GUSBCFG_TRDT_MASK (0xf << 10)RCC_CR_MSIRGSEL (1 << 3)RCC_CCIPR_I2CxSEL_APB 0RCC_USART1RCC_USART2RCC_USART3__UINT16_C(c) cRCC_CR_PLLON (1 << 24)__PRAGMA_REDEFINE_EXTNAME 1__INT_LEAST64_TYPE__ long long intRCC_CCIPR_LPUART1SEL_SYS 1RCC_CCIPR_UARTxSEL_APB RCC_CCIPR_USARTxSEL_APBLPUART1_BASE (PERIPH_BASE_APB1 + 0x8000)OTG_HPTXSTS_PTXQSAV_MASK (0x00ff0000)__lock_acquire(lock) ((void) 0)RCC_APB2SMENR_SDMMC1SMEN (1 << 10)USB_REQ_SET_INTERFACE 11__sym_compat(sym,impl,verid) __asm__(".symver " #impl ", " #sym "@" #verid)INT64_C__requires_unlocked(...) __lock_annotate(locks_excluded(__VA_ARGS__))OTG_GAHBCFG_TXFELVL 0x0080___int_wchar_t_h __SYS_LOCK_H__ __HAVE_SPECULATION_SAFE_VALUE 1OTG_GRXSTSP_PKTSTS_MASK (0xf << 17)I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)OTG_FS_DIEPCTL(x) MMIO32(USB_OTG_FS_BASE + OTG_DIEPCTL(x))_REENT_CHECK_ASCTIME_BUF(ptr) UINTMAX_C(c) __UINTMAX_C(c)__QQ_FBIT__ 7__LDBL_DECIMAL_DIG__ 17BIT15 (1<<15)RCC_CFGR_PPRE1_DIV4 0x5__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xINT8_CSCC_PWRRCC_AHB1SMENR_TSCSMEN (1 << 16)RCC_APB2RSTR_USART1RST (1 << 14)BIT5 (1<<5)USB_OTG_FS_BASE (0x50000000U + 0x00000)__BIGGEST_ALIGNMENT__ 8OTG_GRSTCTL_CSRST (1 << 0)__ARM_ARCH__UINT8_TYPE__ unsigned charRCC_SAI1RCC_SAI2OTG_DIEPINTX_ITTXFE (1 << 4)INT_FAST64_MIN (-INT_FAST64_MAX - 1)OTG_GOTGINT 0x004RCC_AHB2RSTR_GPIOARST (1 << 0)RCC_CFGR_STOPWUCK_HSI16 (1 << 15)_REENT_MBLEN_STATE(ptr) ((ptr)->_new._reent._mblen_state)__FLT32_MIN_10_EXP__ (-37)RCC_CSR_MSIRANGE_8MHZ 7OTG_HCFG_FSLSPCS_MASK (0x3 << 0)RCC_APB1ENR1_UART4EN (1 << 19)OTG_HPRT_PSPD_LOW (0x2 << 17)__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLKRCC_PLLCFGR_PLLQ_DIV4 1__INT_LEAST16_MAX__ 0x7fffidVendor__LOCK_INIT_RECURSIVE(class,lock) static int lock = 0;bIntervalOTG_FS_HFNUM MMIO32(USB_OTG_FS_BASE + OTG_HFNUM)RCC_CICR_PLLSAI2RDYC (1 << 7)OTG_HCTSIZ_DPID_MDATA (0x3 << 29)OTG_DOEPCTL0_NAKSTS (1 << 17)OTG_FS_DIEPINT(x) MMIO32(USB_OTG_FS_BASE + OTG_DIEPINT(x))OTG_HPRT_PSPD_HIGH (0x0 << 17)IDLEBIT16 (1<<16)__SACCUM_IBIT__ 8_ANSIDECL_H_ __UINT16_TYPE__ short unsigned int__FLT64_NORM_MAX__ 1.7976931348623157e+308F64__EXPOTG_DIEPCTL0_MPSIZ_16 (0x2 << 0)RCC_ADCRCC_CFGR_MCOPRE_DIV8 3OTG_DCFG_DSPD 0x0003extra_string__FLT32_NORM_MAX__ 3.4028234663852886e+38F32OTG_DIEPINT(x) (0x908 + 0x20*(x))OTG_FS_GOTGINT MMIO32(USB_OTG_FS_BASE + OTG_GOTGINT)OTG_GOTGCTL_HNGSCS (1 << 8)__FLT32X_HAS_INFINITY__ 1_ATEXIT_SIZE 32OTG_FS_GRXFSIZ MMIO32(USB_OTG_FS_BASE + OTG_GRXFSIZ)FMC_BASE (0xa0000000U)PTRDIFF_MAXOTG_DIEPCTLX_SD0PID (1 << 28)OTG_HPRT_PSUSP (1 << 7)RCC_BDCR_LSEDRV_MASK 0x3__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__INT8_C(c) cOTG_GOTGINT_DBCDNE (1 << 19)idProductOTG_GINTSTS_INCOMPISOOUT (1 << 21)INFO_BASE (0x1fff0000U)__ARM_EABI__ 1RCC_PLLCFGR_PLLR_DIV4 1__printf0like(fmtarg,firstvararg) OTG_FS_DOEPINT(x) MMIO32(USB_OTG_FS_BASE + OTG_DOEPINT(x))__FLT32_MANT_DIG__ 24__FLT32_EPSILON__ 1.1920928955078125e-7F32OTG_GRXSTSP_DPID_DATA0 (0x0 << 15)INT_LEAST8_MAX __INT_LEAST8_MAX__false 0__FLT_MAX_EXP__ 128RCC_AHB2ENR_GPIOBEN (1 << 1)__INT64_MAX__ 0x7fffffffffffffffLLSCC_LCD__CC_SUPPORTS___INLINE 1__ATOMIC_SEQ_CST 5OTG_HCTSIZ_DPID_MASK (0x3 << 29)_GCC_SIZE_T DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7590)__lock_close_recursive(lock) ((void) 0)RCC_APB2RSTR_TIM15RST (1 << 16)stm32f107_usbd_init_REENT_CHECK_SIGNAL_BUF(ptr) RCC_CR MMIO32(RCC_BASE + 0x00)bcdUSBLPTIM2_BASE (PERIPH_BASE_APB1 + 0x9400)OTG_DOEPCTL0_SNAK (1 << 27)__FLT32X_MAX_EXP__ 1024SDMMC1_BASE (PERIPH_BASE_APB2 + 0x2800)BIT6 (1<<6)RCC_ICSCR_MSICAL_MASK 0xff__UINT_FAST8_TYPE__ unsigned intRCC_BDCR_RTCSEL_SHIFT 8RCC_AESRCC_AHB3SMENR_FMCSMEN (1 << 0)RCC_LPTIM1__UTA_FBIT__ 64dwc_pollDESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)__DBL_DIG__ 15SCC_RNGOTG_HNPTXFSIZ_PTXFD_MASK (0xffff0000)INTPTR_MAX __INTPTR_MAX__OTG_DIEPCTL(x) (0x900 + 0x20*(x))__EXP(x) __ ##x ##____DECIMAL_DIG__ 17usbd_deviceINT_FAST16_MININT_FAST8_MAX __INT_FAST8_MAX___STDDEF_H __long_double_t long double__DEQUALIFY(type,var) ((type)(__uintptr_t)(const volatile void *)(var))DESIG_PACKAGE MMIO16((INFO_BASE + 0x7500))__has_feature(x) 0_Alignas(x) __aligned(x)_REENT_EMERGENCY_SIZE 25PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)__GCC_IEC_559_COMPLEX 0UINT64_COTG_GINTSTS_ISOODRP (1 << 14)USB_ENDPOINT_ADDR_IN(x) (0x80 | (x))OTG_FS_HPRT MMIO32(USB_OTG_FS_BASE + OTG_HPRT)RCC_APB1ENR1_LPTIM1EN (1 << 31)RCC_APB1RSTR1_UART4RST (1 << 19)USBD_REQ_NOTSUPPRCC_PLLCFGR_PLLP_DIV17 RCC_PLLCFGR_PLLPOTG_GRXSTSP_PKTSTS_SETUP_COMP (0x4 << 17)BIT18 (1<<18)__LFRACT_IBIT__ 0OTG_FS_DTXFSTS(x) MMIO32(USB_OTG_FS_BASE + OTG_DTXFSTS(x))RCC_AHB3SMENR_QSPISMEN (1 << 8)__USER_LABEL_PREFIX__ OTG_GCCFG_NOVBUSSENS (1 << 21)USB_ENDPOINT_ATTR_SYNCTYPE 0x0C__attribute_malloc__ _SIZE_T_DECLARED ___int16_t_defined 1RCC_APB1RSTR1_SPI3RST (1 << 15)OTG_GCCFG_PWRDWN (1 << 16)RCC_APB1SMENR1_PWRSMEN (1 << 28)_REENT_TM(ptr) (&(ptr)->_new._reent._localtime_buf)OTG_HCTSIZ_DPID_DATA1 (0x2 << 29)SCC_TIM5INT64_MAX __INT64_MAX___BEGIN_STD_C __QQ_IBIT__ 0OTG_HPTXSTS_PTXQTOP_EVENFRM (0<<31)OTG_GINTMSK_PTXFEM 0x04000000__DEFINED_size_t OTG_HCINT_NYET (1 << 6)OTG_GRXSTSP_FRMNUM_MASK (0xf << 21)usb_config_descriptorRCC_AHB3ENR_FMCEN (1 << 0)TIM17_BASE (PERIPH_BASE_APB2 + 0x4800)UINT_LEAST64_MAX__DECONST(type,var) ((type)(__uintptr_t)(const void *)(var))SCC_SRAM1SCC_SRAM2SPI2_BASE (PERIPH_BASE_APB1 + 0x3800)USB_REQ_TYPE_ENDPOINT 0x02__DBL_MIN__ ((double)2.2250738585072014e-308L)RCC_CFGR_STOPWUCK_MSI (0 << 15)USB_REQ_TYPE_CLASS 0x20current_config__INT_FAST8_MAX__ 0x7fffffff_WCHAR_T RCC_LCDRCC_CR_PLLSAI2ON (1 << 28)__INT_FAST8_WIDTH__ 32RCC_CCIPR_I2CxSEL_HSI16 2RCC_AHB3SMENR_OFFSET 0x70__LDBL_MAX__ 1.7976931348623157e+308LINT_FAST32_MAXRCC_AHB3RSTR_OFFSET 0x30__ARM_FP16_ARGSOTG_DCFG_DAD 0x07F0__FLT32_MIN_EXP__ (-125)ST_VREFINT_CAL MMIO16((INFO_BASE + 0x75aa))CORESIGHT_LSR_SLK (1<<1)__LLFRACT_MIN__ (-0.5LLR-0.5LLR)typeuser_control_callbackOTG_GINTSTS_CMOD (1 << 0)interface__UINT32_C(c) c ## UL__LDBL_MIN_EXP__ (-1021)OTG_HPRT_PTCTL_SE0_NAK (0x3 << 13)__DBL_MIN_10_EXP__ (-307)IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)BIT7 (1<<7)GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000)_GCC_PTRDIFF_T RCC_PLLCFGR_PLLSRC_NONE 0_T_SIZE_ __FLT_MIN_10_EXP__ (-37)RCC_CCIPR_USART2SEL_SHIFT 2RCC_APB1ENR1_TIM7EN (1 << 5)RCC_CCIPR_USARTxSEL_MASK 0x3SCC_SDMMC1RCC_CCIPR_LPUART1SEL_APB 0RX_FIFO_SIZE 128INT_LEAST64_MAX __INT_LEAST64_MAX__OTG_DOEPCTL0_MPSIZ_32 (0x1 << 0)__UDQ_IBIT__ 0AES_BASE (0x50000000U + 0x60000)dwc_ep_stall_get__DBL_MANT_DIG__ 53__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)OTG_FS_DIEPTSIZ0 MMIO32(USB_OTG_FS_BASE + OTG_DIEPTSIZ0)__PTRDIFF_WIDTH__ 32__FBSDID(s) struct __hackOTG_HPRT_PTCTL_FORCE_ENABLE (0x5 << 13)bDeviceSubClass__ULLACCUM_MIN__ 0.0ULLKRCC_APB1RSTR1_OFFSET 0x38SCC_I2C2SCC_I2C3__lock_annotate(x) RCC_APB1SMENR1_TIM2SMEN (1 << 0)RCC_APB1SMENR1_USART2SMEN (1 << 17)INT_FAST64_MAXdwc_set_addressRCC_CICR_LSIRDYC (1 << 0)RCC_APB1SMENR1_TIM4SMEN (1 << 2)USB_DT_STRING 3DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)RCC_AHB2RSTR_GPIOCRST (1 << 2)RCC_APB2ENR_SAI1EN (1 << 21)__size_t __WINT_MAX__ 0xffffffffURCC_CFGR_HPRE_DIV512 0xf__sym_default(sym,impl,verid) __asm__(".symver " #impl ", " #sym "@@" #verid)__ARM_FP16_FORMAT_ALTERNATIVERCC_CCIPR_I2C2SEL_SHIFT 14UINTPTR_MAXOTG_FS_HPTXFSIZ MMIO32(USB_OTG_FS_BASE + OTG_HPTXFSIZ)OTG_HPRT_POCA (1 << 4)INT32_C(c) __INT32_C(c)rcc_periph_clkenUSB_DT_ENDPOINT 5__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1__UINT32_TYPE__ long unsigned int__FLT_EPSILON__ 1.1920928955078125e-7F__GNUCLIKE___OFFSETOF 1RCC_TSCbInterfaceNumberRCC_PLLCFGR_PLLR_MASK 0x3__UINT8_C(c) cLIBOPENCM3_RCC_COMMON_ALL_H USB_REQ_CLEAR_FEATURE 1__CC_SUPPORTS_INLINE 1TIM8_BASE (PERIPH_BASE_APB2 + 0x3400)OTG_FS_PCGCCTL MMIO32(USB_OTG_FS_BASE + OTG_PCGCCTL)RCC_CFGR_MCOPRE_MASK 0x7RCC_AHB3SMENR MMIO32(RCC_BASE + RCC_AHB3SMENR_OFFSET)OTG_HPRT_PSPD_FULL (0x1 << 17)rx_fifo_sizeINT8_C(c) __INT8_C(c)UINT16_MAX __UINT16_MAX__SCC_TSC__weak_symbol __attribute__((__weak__))RCC_AHB2RSTR_GPIOGRST (1 << 6)__flexarr [0]OTG_HPRT_PCSTS (1 << 0)_REENT_RAND48_ADD(ptr) ((ptr)->_new._reent._r48._add)__ULLFRACT_MIN__ 0.0ULLRRCC_BDCR_BDRST (1 << 16)RCC_CCIPR_ADCSEL_NONE 0OTG_DOEPMSK_XFRCM (1 << 0)unsigned charRCC_CICR_HSERDYC (1 << 4)__ARM_FEATURE_QRDMXRCC_CCIPR_LPTIMxSEL_LSE 3BIT8 (1<<8)__SFRACT_IBIT__ 0OTG_FS_HCINTMSK(x) MMIO32(USB_OTG_FS_BASE + OTG_HCINTMSK(x))__lock_release(lock) ((void) 0)__ORDER_LITTLE_ENDIAN__ 1234_PTRDIFF_T_DECLARED _REENT_SIGNGAM(ptr) ((ptr)->_new._reent._gamma_signgam)usbd_request_return_codesFMC3_BANK_BASE (0x80000000U)OTG_GINTSTS 0x014RCC_CCIPR_USARTxSEL_APB 0RCC_APB1ENR1_CAN1EN (1 << 25)OTG_GUSBCFG_CTXPKT 0x80000000__FLT_DIG__ 6RCC_APB2SMENR_OFFSET 0x80OTG_GRXFSIZ 0x024RCC_AHB1SMENR_SRAM1SMEN (1 << 9)__alloc_size2(n,x) __attribute__((__alloc_size__(n, x)))OTG_DIEPSIZ0_STUPCNT_3 (0x3 << 29)OTG_FS_DOEPTSIZ0 MMIO32(USB_OTG_FS_BASE + OTG_DOEPTSIZ0)RCC_CR_PLLSAI1RDY (1 << 27)__DBL_MAX_EXP__ 1024__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULK__LLFRACT_IBIT__ 0__UINT_LEAST16_MAX__ 0xffff__SIZE_WIDTH__ 32OTG_HPTXSTS_PTXQTOP_TERMINATE (1<<24)__null_sentinel __attribute__((__sentinel__))SCC_DAC1__GNUCLIKE___SECTION 1RCC_APB1RSTR1_TIM3RST (1 << 1)BIT2 (1<<2)OTG_FS_DAINT MMIO32(USB_OTG_FS_BASE + OTG_DAINT)OTG_GOTGINT_HNSSCHG (1 << 9)OTG_HAINT 0x414__SIZEOF_SIZE_T__ 4RCC_CCIPR_CLK48SEL_PLL 2_PTRDIFF_T RCC_AHB2ENR_ADCEN (1 << 13)__Long longOTG_FS_DIEPCTL0 MMIO32(USB_OTG_FS_BASE + OTG_DIEPCTL0)INT_LEAST16_MAX __INT_LEAST16_MAX__HAVE_INITFINI_ARRAY 1RCC_APB1SMENR1_WWDGSMEN (1 << 11)OTG_DVBUSPULSE 0x82C__lock_release_recursive(lock) ((void) 0)usbd_driver__format_arg(fmtarg) __attribute__((__format_arg__ (fmtarg)))OTG_GRSTCTL_AHBIDL (1 << 31)user_callback_set_altsettingRCC_CCIPR_USART1SEL_LSE 3initWCHAR_MINRCC_AHB1RSTR_FLASHRST (1 << 8)RCC_CIFR_HSERDYF (1 << 4)OTG_DCTL_SDIS (1 << 1)BEGIN_DECLS NVIC_BASE (SCS_BASE + 0x0100)__SFRACT_FBIT__ 7DMA2_BASE (PERIPH_BASE_AHB1 + 0x0400)ep_read_packet__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32OTG_DAINT 0x818RCC_CSR_OBLRSTF (1 << 25)PTRDIFF_MIN (-PTRDIFF_MAX - 1)RCC_APB1SMENR1_I2C2SMEN (1 << 22)usb_device_descriptorRCC_GPIOARCC_GPIOBRCC_GPIOCRCC_GPIODRCC_GPIOERCC_GPIOFRCC_GPIOGRCC_GPIOHRCC_CR_MSIRANGE_200KHZ 1SCC_GPIOASCC_GPIOBSCC_GPIOCSCC_GPIODSCC_GPIOE__FLT32_DECIMAL_DIG__ 9SCC_GPIOGSCC_GPIOHGPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000)RCC_PLLCFGR_PLLSRC_MSI 1__NEWLIB_MINOR__ 3RCC_AHB1RSTR_CRCRST (1 << 12)_REENT_MBSRTOWCS_STATE(ptr) ((ptr)->_new._reent._mbsrtowcs_state)OTG_HCINTMSK_FRMORM (1 << 9)__datatype_type_tag(kind,type) RCC_CR_MSIRANGE_SHIFT 4OTG_FS_DOEPCTL0 MMIO32(USB_OTG_FS_BASE + OTG_DOEPCTL0)OTG_DIEPCTL0_MPSIZ_32 (0x1 << 0)ep_stall_set_WCHAR_T_DEFINED_ RCC_CR_HSIKERON (1 << 9)__bounded USB_REQ_SET_CONFIGURATION 9__WINT_TYPE__ unsigned intOTG_HPRT_PENCHNG (1 << 3)___int_least8_t_defined 1RCC_CFGR_MCO_MSI 0x2SCB_BASE (SCS_BASE + 0x0D00)/build/libopencm3/lib/stm32/l4__arg_type_tag(arg_kind,arg_idx,type_tag_idx) RCC_APB2ENR_SPI1EN (1 << 12)RCC_PLLCFGR_PLLSRC_HSI16 2SCC_USART1SCC_USART2SCC_USART3_ATEXIT_DYNAMIC_ALLOC 1RCC_AHB1SMENR_CRCSMEN (1 << 12)OTG_DIEPCTL0_SNAK (1 << 27)__INT16_MAX__ 0x7fffRCC_APB2ENR_TIM1EN (1 << 11)__ULACCUM_EPSILON__ 0x1P-32ULK__FLT_MANT_DIG__ 24INT_LEAST64_MIN__asserts_exclusive(...) __lock_annotate(assert_exclusive_lock(__VA_ARGS__))OTG_PCGCCTL 0xE00__ULACCUM_FBIT__ 32TIM1_BASE (PERIPH_BASE_APB2 + 0x2C00)__USB_DWC_COMMON_H_ __GNUC_VA_LIST_COMPATIBILITY 1bFunctionSubClassOTG_HCCHAR_EPDIR_IN (1 << 15)OTG_DOEPMSK_EPDM (1 << 1)USB_ENDPOINT_ATTR_FEEDBACK 0x10__asserts_shared(...) __lock_annotate(assert_shared_lock(__VA_ARGS__))wMaxPacketSizeRCC_BDCR_RTCSEL_NONE 0OTG_DCTL_GINSTS (1 << 2)__ARM_ARCH_PROFILE 77__GNUCLIKE_MATH_BUILTIN_RELOPS OTG_DOEPINTX_EPDISD (1 << 1)__ULACCUM_IBIT__ 32RCC_CFGR_PPRE2_DIV4 0x5RCC_DFSDMRCC_CR_MSIRANGE_1MHZ 4BIT20 (1<<20)bEndpointAddressRCC_AHB2ENR_RNGEN (1 << 18)OTG_GRXSTSP_PKTSTS_IN_COMP (0x3 << 17)STM32L4 1_WCHAR_T_H __INT_LEAST8_MAX__ 0x7f__UQQ_FBIT__ 8__FLT_MIN_EXP__ (-125)RCC_ICSCR_HSITRIM_SHIFT 24OTG_GRXSTSP_DPID_DATA2 (0x1 << 15)__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__RCC_CFGR_PPRE2_SHIFT 11__UINT64_C(c) c ## ULL__FRACT_IBIT__ 0__FLT_RADIX__ 2__USA_FBIT__ 16USB_ENDPOINT_ATTR_ASYNC 0x04__LDBL_IS_IEC_60559__ 2__FLT32X_DIG__ 15UINT_FAST8_MAX __UINT_FAST8_MAX____RAND_MAX 0x7fffffff__LDBL_EPSILON__ 2.2204460492503131e-16L__ARM_BF16_FORMAT_ALTERNATIVEOTG_DOEPCTL0_MPSIZ_8 (0x3 << 0)__FLT_EVAL_METHOD_TS_18661_3__ 0OTG_DIEPCTL0 0x900__SQ_FBIT__ 31__UINTMAX_MAX__ 0xffffffffffffffffULLOTG_HPRT_PPWR (1 << 12)__LDBL_HAS_DENORM__ 1__USA_IBIT__ 16__ACCUM_EPSILON__ 0x1P-15KcompleteOTG_HCCHAR_EPTYP_BULK (2 << 18)RCC_CCIPR_USART1SEL_MASK 0x3__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LKRCC_CFGR_HPRE_DIV16 0xb_REENT_CHECK_TM(ptr) FMC_QUADSPI_BASE (0xA0000000U)OTG_GRXSTSP_PKTSTS_DTERR (0x5 << 17)BIT21 (1<<21)RCC_PLLCFGR_PLLQEN (1 << 20)OTG_DIEPCTL0_USBAEP (1 << 15)_REENT_INIT_PTR(var) { memset((var), 0, sizeof(*(var))); _REENT_INIT_PTR_ZEROED(var); }INT_FAST32_MINRCC_USBRCC_FLASH__NEWLIB_PATCHLEVEL__ 0RCC_PLLCFGR_PLLQ_DIV6 2__GCC_ATOMIC_INT_LOCK_FREE 2BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)RCC_PLLCFGR_PLLSRC_HSE 3SCC_FLASH__INT_WIDTH__ 32I2C3_BASE (PERIPH_BASE_APB1 + 0x5c00)force_nakOTG_GINTMSK_EPMISM 0x00020000RCC_CFGR_SW_SHIFT 0PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)USB_ENDPOINT_ATTR_INTERRUPT 0x03RCC_BDCR_LSERDY (1 << 1)dwc_ep_nak_setRCC_CFGR_MCO_HSI16 0x3RCC_AHB2ENR_GPIOAEN (1 << 0)CORESIGHT_LAR_KEY 0xC5ACCE55__FLT32_IS_IEC_60559__ 2__UDQ_FBIT__ 64OTG_GOTGCTL_SRQSCS (1 << 0)_GLOBAL_REENT _global_impure_ptr__FLT64_DIG__ 15__ARM_NEON__weak_reference(sym,alias) __asm__(".weak " #alias); __asm__(".equ " #alias ", " #sym)RCC_CFGR_MCO_SHIFT 24RCC_AHB2SMENR_AESSMEN (1 << 16)__ARM_ARCH_7EM__ 1___int64_t_defined 1_REENT_CHECK_VERIFY 1__GNUCLIKE_BUILTIN_NEXT_ARG 1__INT16_C(c) cBIT30 (1<<30)INT_FAST8_MAXRCC_CIFR_PLLRDYF (1 << 5)BIT22 (1<<22)__FLT32X_DECIMAL_DIG__ 17RCC_CSR_MSIRANGE_2MHZ 5__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2__INT16_TYPE__ short intRCC_APB2RSTR_DFSDMRST (1 << 24)UINTMAX_C_REENT_RAND48_SEED(ptr) ((ptr)->_new._reent._r48._seed)RCC_CCIPR_ADCSEL_PLLSAI1R 1__FRACT_MIN__ (-0.5R-0.5R)__ULFRACT_FBIT__ 32__GNUCLIKE_BUILTIN_MEMCPY 1SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)SCC_LPTIM2usb_endpoint_descriptorSWPMI1_BASE (PERIPH_BASE_APB1 + 0x8800)RCC_CCIPR_LPUART1SEL_SHIFT 10otgfs_usb_driver stm32f107_usb_driverRCC_CIER_PLLSAI2RDYIE (1 << 7)_SIZE_T_DEFINED_ RCC_BDCR_LSCOSEL (1 << 25)RCC_PLLCFGR_PLLR_DIV6 2OTG_DOEPCTL(x) (0xB00 + 0x20*(x))__GCC_ATOMIC_LONG_LOCK_FREE 2_GCC_STDINT_H PTRDIFF_MAX __PTRDIFF_MAX____GXX_TYPEINFO_EQUALITY_INLINE 0_REENT_STDIO_STREAM(var,index) &(var)->__sf[index]___int_least32_t_defined 1OTG_DCFG_PFIVL 0x1800__UHQ_FBIT__ 16uint8_tOTG_GUSBCFG_NPTXRWEN 0x00004000OTG_FS_DOEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + OTG_DOEPTSIZ(x))RCC_CFGR MMIO32(RCC_BASE + 0x08)RCC_PLLSAI2_CFGR MMIO32(RCC_BASE + 0x14)num_altsettingRCC_CFGR_MCO_HSI48 0x8RCC_CFGR_SWS_PLL 0x3RCC_CSR_MSIRANGE_1MHZ 4bInterfaceCountNULL__locks_exclusive(...) __lock_annotate(exclusive_lock_function(__VA_ARGS__))SCC_ADCOTG_HCINT_DTERR (1 << 10)__compiler_membar() __asm __volatile(" " : : : "memory")RCC_BDCR_LSEDRV_LOW 0RCC_CSR_FWRSTF (1 << 24)OTG_DIEPINTX_TXFE (1 << 7)BIT23 (1<<23)QUADSPI_BANK_BASE (0x90000000U)__FP_FAST_FMAF 1RCC_AHB1ENR_FLASHEN (1 << 8)__WCHAR_MIN__ 0UOTG_HAINTMSK_HAINT_MASK (0x0000ffff)OTG_DCTL_CGONAK (1 << 10)RCC_APB2SMENR_TIM16SMEN (1 << 17)RCC_CIFR MMIO32(RCC_BASE + 0x1c)OTG_GUSBCFG_PHYSEL (1 << 6)USB_FEAT_ENDPOINT_HALT 0RCC_AHB2SMENR_GPIOHSMEN (1 << 7)_REENT_CHECK_MP(ptr) RCC_CSR_MSIRANGE_MASK 0xfOTG_DCTL_SGINAK (1 << 8)_GCC_WCHAR_T RCC_APB2ENR_FWEN (1 << 7)OTG_FS_DAINTMSK MMIO32(USB_OTG_FS_BASE + OTG_DAINTMSK)__LOCK_INIT(class,lock) static int lock = 0;___int_size_t_h RCC_APB1SMENR1_USART3SMEN (1 << 18)OTG_GRSTCTL_TXFNUM_MASK (0x1f << 6)RCC_APB2ENR_OFFSET 0x60RCC_CFGR_HPRE_NODIV 0x0__LLFRACT_EPSILON__ 0x1P-63LLR__INT_FAST64_WIDTH__ 64__FRACT_FBIT__ 15RCC_OTGFS__dead2 __attribute__((__noreturn__))__need_size_t RCC_CFGR_PPRE1_DIV8 0x6RCC_CIER_PLLSAI1RDYIE (1 << 6)SCC_OTGFS__INT32_MAX__ 0x7fffffffL__volatile volatileOTG_GRXSTSP_PKTSTS_CHH (0x7 << 17)__CHAR_UNSIGNED__ 1SCC_UART4SCC_UART5SCC_AESBIT24 (1<<24)_BSD_WCHAR_T_OTG_GINTSTS_NPTXFE (1 << 5)__SCHAR_MAX__ 0x7f__GCC_HAVE_DWARF2_CFI_ASM 1RCC_CCIPR_LPUART1SEL_HSI16 2INT16_MAX __INT16_MAX___SIZE_T_ OTG_FS_GINTMSK MMIO32(USB_OTG_FS_BASE + OTG_GINTMSK)TPIU_BASE (PPBI_BASE + 0x40000)OTG_HCCHAR_EPNUM_MASK (0xf << 11)__SACCUM_EPSILON__ 0x1P-7HKRCC_CCIPR_ADCSEL_SHIFT 28DAC_BASE (PERIPH_BASE_APB1 + 0x7400)__need_size_t__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRRCC_CR_MSIRANGE_48MHZ 11OTG_HPTXSTS_PTXQTOP_TYPE_INOUT (0x00<<25)RCC_PLLCFGR_PLLM_SHIFT 0x4USB_ENDPOINT_ATTR_DATA 0x00USB_REQ_TYPE_IN 0x80cur_altsetting__HA_FBIT__ 7__UACCUM_MIN__ 0.0UK__containerof(x,s,m) ({ const volatile __typeof(((s *)0)->m) *__x = (x); __DEQUALIFY(s *, (const volatile char *)__x - __offsetof(s, m));})RCC_ICSCR_MSICAL_SHIFT 0INT_LEAST32_MAX __INT_LEAST32_MAX__OTG_HCCHAR(x) (0x500 + 0x20*(x))MIN(a,b) ((a) < (b) ? (a) : (b))__GNUCLIKE_ASM 3__UFRACT_EPSILON__ 0x1P-16UROTG_HCCHAR_CHDIS (1 << 30)__FLT_HAS_QUIET_NAN__ 1RCC_DMA1UINT_FAST64_MAX __UINT_FAST64_MAX__usbd_devBIT25 (1<<25)OTG_FS_DOEPMSK MMIO32(USB_OTG_FS_BASE + OTG_DOEPMSK)ep_nak_set__THROW __FLT32X_NORM_MAX__ 1.7976931348623157e+308F32xRCC_PLLCFGR_PLLP_DIV7 0SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__USART1_BASE (PERIPH_BASE_APB2 + 0x3800)_REENT_INIT_PTR_ZEROED(var) { (var)->_stdin = _REENT_STDIO_STREAM(var, 0); (var)->_stdout = _REENT_STDIO_STREAM(var, 1); (var)->_stderr = _REENT_STDIO_STREAM(var, 2); (var)->_new._reent._rand_next = 1; (var)->_new._reent._r48._seed[0] = _RAND48_SEED_0; (var)->_new._reent._r48._seed[1] = _RAND48_SEED_1; (var)->_new._reent._r48._seed[2] = _RAND48_SEED_2; (var)->_new._reent._r48._mult[0] = _RAND48_MULT_0; (var)->_new._reent._r48._mult[1] = _RAND48_MULT_1; (var)->_new._reent._r48._mult[2] = _RAND48_MULT_2; (var)->_new._reent._r48._add = _RAND48_ADD; }USB_DT_INTERFACE_SIZE 9OTG_DIEPCTL0_EPDIS (1 << 30)OTG_HCFG_FSLSS (1 << 2)RCC_AHB2SMENR_SRAM2SMEN (1 << 9)SCC_LPTIM1_REENT_MP_RESULT_K(ptr) ((ptr)->_result_k)RCC_CR_MSIRANGE_24MHZ 9__SCHAR_WIDTH__ 8__ARM_FEATURE_FP16_FML__ORDER_PDP_ENDIAN__ 3412__ATOMIC_ACQUIRE 2__INT_FAST32_WIDTH__ 32__INT_FAST64_TYPE__ long long int__noinline __attribute__ ((__noinline__))__ACCUM_FBIT__ 15__LLACCUM_FBIT__ 31__attribute_pure__ _HAVE_LONG_DOUBLE 1__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_QBIT 1CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)__WINT_WIDTH__ 32UINT32_C(c) __UINT32_C(c)OTG_HPTXSTS_PTXQTOP_ODDFRM (1<<31)__ARM_FEATURE_UNALIGNED 1RCC_CR_MSION (1 << 0)OTG_DIEPSIZ0_STUPCNT_MASK (0x3 << 29)_CLOCKID_T_ unsigned long__SACCUM_MAX__ 0X7FFFP-7HK__section(x) __attribute__((__section__(x)))BIT26 (1<<26)INTMAX_MAXOTG_DIEPMSK_TXFURM (1 << 8)__LDBL_NORM_MAX__ 1.7976931348623157e+308LRCC_CR_HSIRDY (1 << 10)__ptrvalue __ACCUM_IBIT__ 16OTG_GRSTCTL_FCRST (1 << 2)UINT64_MAX __UINT64_MAX__OTG_GINTMSK_OEPINT 0x00080000OTG_HPTXSTS_PTXQTOP_MASK (0xff000000)__INTMAX_WIDTH__ 64OTG_HCINT_TXERR (1 << 7)USB_ENDPOINT_ATTR_BULK 0x02__FRACT_EPSILON__ 0x1P-15ROTG_DCFG 0x800OTG_GINTSTS_IPXFR (1 << 21)__ARM_FEATURE_LDREX 7OTG_FS_DIEPTXF(x) MMIO32(USB_OTG_FS_BASE + OTG_DIEPTXF(x))__INT_LEAST64_WIDTH__ 64RCC_AHB2SMENR_GPIOCSMEN (1 << 2)RCC_CIFR_HSI48RDYF (1 << 10)__NULLABILITY_PRAGMA_POP RCC_ICSCR_HSICAL_SHIFT 16_NEWLIB_VERSION_H__ 1RCC_APB1ENR1_USART2EN (1 << 17)RCC_CCIPR_USARTxSEL_LSE 3__need_wint_t__ARM_32BIT_STATE 1__ATOMIC_RELAXED 0RCC_CFGR_PPRE1_MASK 0x7__LFRACT_MAX__ 0X7FFFFFFFP-31LR__LDBL_MIN__ 2.2250738585072014e-308LRCC_CCIPR_USART1SEL_SHIFT 0RCC_APB1RSTR2_LPTIM2RST (1 << 5)SET_REG(REG,VAL) (*(REG) = (uint16_t)(VAL))OTG_HPRT_PTCTL_DISABLED (0x0 << 13)OTG_DOEPMSK_BOIM (1 << 9)OTG_DIEPMSK_EPDM (1 << 1)__THUMB_INTERWORK__ 1RCC_AHB2ENR_GPIOHEN (1 << 7)PPBI_BASE (0xE0000000U)OTG_GINTMSK_IISOIXFRM 0x00100000BIT27 (1<<27)__OBSOLETE_MATH_DEFAULT 1__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)__NEWLIB__ 3wLengthOTG_DCTL_GONSTS (1 << 3)__returns_twice __attribute__((__returns_twice__))__SIZEOF_LONG_LONG__ 8RCC_CCIPR_USART1SEL_HSI16 2OTG_HCINTMSK_TXERRM (1 << 7)_REENT_MP_RESULT(ptr) ((ptr)->_result)__GCC_IEC_559 0OTG_GRXSTSP_PKTSTS_OUT_COMP (0x3 << 17)__FLT_IS_IEC_60559__ 2__FLT32X_EPSILON__ 2.2204460492503131e-16F32x__UFRACT_IBIT__ 0RCC_CCIPR_SAI2SEL_SHIFT 24USB_REQ_GET_DESCRIPTOR 6_REENT_GETDATE_ERR_P(ptr) (&((ptr)->_new._reent._getdate_err))FIREWALL_BASE (PERIPH_BASE_APB2 + 0x1C00)USB_REQ_TYPE_VENDOR 0x40dwc_disconnect_END_STD_C OTG_GOTGCTL_CIDSTS (1 << 16)MMIO32(addr) (*(volatile uint32_t *)(addr))OTG_GINTSTS_HCINT (1 << 25)RCC_TIM1_NULL 0RCC_TIM3RCC_TIM4RCC_TIM5RCC_APB1RSTR2_OFFSET 0x3cRCC_TIM7RCC_TIM8__wchar_t__ GET_REG(REG) ((uint16_t) *(REG))usbd_endpoint_callbackusb_iface_assoc_descriptor__pt_guarded_by(x) __lock_annotate(pt_guarded_by(x))_WCHAR_T_DECLARED __alloc_size(x) __attribute__((__alloc_size__(x)))_REENT_CHECK_EMERGENCY(ptr) _UNBUF_STREAM_OPT 1BIT28 (1<<28)RCC_APB1RSTR1_I2C1RST (1 << 21)_NEWLIB_VERSION "3.3.0"__INT_LEAST8_WIDTH__ 8altsetting__GNUC__ 12CRS_BASE (PERIPH_BASE_APB1 + 0x6000)__ARM_FEATURE_COPROCRCC_CCIPR_SAIxSEL_PLLSAI2P 1RCC_ICSCR MMIO32(RCC_BASE + 0x04)__INT_FAST16_TYPE__ intiManufacturerOTG_DOEPTSIZ(x) (0xB10 + 0x20*(x))RCC_CFGR_SWS_MASK 0x3__INT_LEAST32_WIDTH__ 32RCC_AHB1RSTR_TSCRST (1 << 16)__UTQ_IBIT__ 0__DBL_IS_IEC_60559__ 2OTG_HPRT_PTCTL_K (0x2 << 13)__UTA_IBIT__ 64OTG_DIEPMSK 0x810__SIZEOF_WINT_T__ 4OTG_GINTSTS_SOF (1 << 3)RCC_AHB1RSTR_DMA2RST (1 << 1)RCC_CFGR_MCOPRE_DIV1 0RCC_CCIPR_CLK48SEL_MSI 3USB_REQ_GET_INTERFACE 10INT_FAST8_MIN__ARM_FEATURE_IDIV 1RCC_APB1RSTR1_USART2RST (1 << 17)__ARM_FEATURE_SAT 1RCC_APB1ENR1_PWREN (1 << 28)OTG_GOTGINT_ADTOCHG (1 << 18)USB_DT_OTG 9__INT_MAX__ 0x7fffffffOTG_GINTMSK_CIDSCHGM 0x10000000ep_setupRCC_CR_MSIPLLEN (1 << 2)__FLT_MAX__ 3.4028234663852886e+38F__INT_LEAST8_TYPE__ signed char__GXX_ABI_VERSION 1017BIT29 (1<<29)INT32_Cuser_callback_ctrotghs_usb_driver stm32f207_usb_driver__ARM_ARCH_ISA_THUMB__FLT64_IS_IEC_60559__ 2OTG_DIEPINTX_TOC (1 << 3)__SIZEOF_WCHAR_T__ 4OTG_DIEPMSK_XFRCM (1 << 0)INTMAX_C__USACCUM_MAX__ 0XFFFFP-8UHK__strong_reference(sym,aliassym) extern __typeof (sym) aliassym __attribute__ ((__alias__ (#sym)))RCC_AHB2ENR_GPIOEEN (1 << 4)extra__INT8_MAX__ 0x7fRCC_AHB2ENR_OFFSET 0x4cRCC_APB2RSTR_SAI1RST (1 << 21)RCC_APB2ENR_TIM8EN (1 << 13)_WCHAR_T_ __INT_LEAST32_MAX__ 0x7fffffffLOTG_HCCHAR_DAD_MASK (0x7f << 22)SCC_QSPI__GNUCLIKE_BUILTIN_VARARGS 1_Kmax (sizeof (size_t) << 3)OTG_DIEPCTL0_MPSIZ_MASK (0x3 << 0)RCC_APB1SMENR1_OPAMPSMEN (1 << 30)__ASMNAME(cname) __XSTRING (__USER_LABEL_PREFIX__) cnameRCC_AHB1RSTR MMIO32(RCC_BASE + RCC_AHB1RSTR_OFFSET)__USACCUM_EPSILON__ 0x1P-8UHK___int_least16_t_defined 1RCC_AHB2SMENR_GPIOBSMEN (1 << 1)OTG_HPRT_PENA (1 << 2)INT_FAST32_MIN (-INT_FAST32_MAX - 1)OTG_HCCHAR_EPDIR_OUT (0 << 15)__LLACCUM_EPSILON__ 0x1P-31LLKOTG_HAINTMSK 0x418_SYS_SIZE_T_H RCC_CFGR_MCOPRE_SHIFT 28__INTMAX_C(c) c ## LL__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)SAI1_BASE (PERIPH_BASE_APB2 + 0x5400)__UINT_FAST16_MAX__ 0xffffffffU__ARM_ARCH_EXT_IDIV__ 1__UINT_FAST64_TYPE__ long long unsigned intINT_FAST16_MAXRCC_CAN1COMP_BASE (PERIPH_BASE_APB2 + 0x0200)_REENT_RAND_NEXT(ptr) ((ptr)->_new._reent._rand_next)BIT0 (1<<0)OTG_GRSTCTL_TXFNUM_ALL (0x10 << 6)OTG_HPTXSTS_PTXQTOP_TYPE_DISABLECMD (0x11<<25)RCC_CR_HSION (1 << 8)RCC_BDCR_RTCEN (1 << 15)RCC_CFGR_PPRE1_DIV2 0x4__GNUCLIKE_BUILTIN_VAALIST 1STIR_BASE (SCS_BASE + 0x0F00)RTC_BASE (PERIPH_BASE_APB1 + 0x2800)RCC_CFGR_HPRE_DIV64 0xcUSB_CONFIG_ATTR_DEFAULT 0x80RCC_APB2SMENR_TIM8SMEN (1 << 13)RCC_LPUART1UART4_BASE (PERIPH_BASE_APB1 + 0x4c00)__SIZE_MAX__ 0xffffffffUOTG_GCCFG_VBUSASEN (1 << 18)_RAND48_MULT_0 (0xe66d)WINT_MINRCC_APB1ENR1_I2C1EN (1 << 21)LIBOPENCM3_MEMORYMAP_COMMON_H _REENT_EMERGENCY(ptr) ((ptr)->_emergency)OTG_GINTMSK 0x018OTG_DIEPMSK_INEPNMM (1 << 5)__UINT_FAST8_MAX__ 0xffffffffUOTG_GRXSTSP_DPID_MASK (0x3 << 15)OTG_DCFG_NZLSOHSK 0x0004OTG_FIFO(x) (((x) + 1) << 12)RCC_CIFR_PLLSAI2RDYF (1 << 7)ctrl_len_REENT _impure_ptr_REENT_WCTOMB_STATE(ptr) ((ptr)->_new._reent._wctomb_state)OTG_DOEPINTX_B2BSTUP (1 << 6)OTG_DIEPCTL0_EPENA (1 << 31)__SQ_IBIT__ 0LCD_BASE (PERIPH_BASE_APB1 + 0x2400)RCC_CCIPR_UARTxSEL_SYS RCC_CCIPR_USARTxSEL_SYSINT_FAST16_MIN (-INT_FAST16_MAX - 1)RCC_APB1RSTR1_TIM2RST (1 << 0)__ARM_FEATURE_SIMD32 1OTG_DIEPCTL0_STALL (1 << 21)__need_NULLoffsetof(TYPE,MEMBER) __builtin_offsetof (TYPE, MEMBER)RCC_PLLCFGR_PLLSRC_SHIFT 0__UHQ_IBIT__ 0ST_TSENSE_CAL2_110C MMIO16((INFO_BASE + 0x75ca))RCC_APB2SMENR_TIM15SMEN (1 << 16)_TIMER_T_ unsigned longCLR_REG_BIT_MSK(REG,MSK,BIT) CLR_REG_BIT_MSK_AND_SET((REG), (MSK), (BIT), 0)__packed __attribute__((__packed__))disconnect__SFRACT_MIN__ (-0.5HR-0.5HR)__thumb2__ 1__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1RCC_AHB2ENR MMIO32(RCC_BASE + RCC_AHB2ENR_OFFSET)__LACCUM_FBIT__ 31__ULACCUM_MIN__ 0.0ULKOTG_DOEPCTL0 0xB00RCC_CR_MSIRANGE_4MHZ 6RCC_BDCR_LSEDRV_SHIFT 3RCC_CFGR_SW_HSE 0x2OTG_FS_HAINT MMIO32(USB_OTG_FS_BASE + OTG_HAINT)RCC_PLLCFGR_PLLQ_DIV8 3RCC_CCIPR_CLK48SEL_MASK 0x3_SYS__TYPES_H RCC_CCIPR_ADCSEL_PLLSAI2R 2RCC_PLLCFGR_PLLN_SHIFT 0x8_RAND48_SEED_2 (0x1234)USB_DEV_STATUS_SELF_POWERED 0x01__LONG_MAX__ 0x7fffffffLOTG_HPTXFSIZ 0x100USB_REQ_SET_DESCRIPTOR 7__RCSID(s) struct __hack__lock_try_acquire(lock) ((void) 0)__INT32_C(c) c ## LRCC_SWPMI1OTG_GINTSTS_USBSUSP (1 << 11)OTG_HCFG 0x400__END_DECLS __USQ_IBIT__ 0TIM16_BASE (PERIPH_BASE_APB2 + 0x4400)BIT4 (1<<4)INTPTR_MAXOTG_FS_HFIR MMIO32(USB_OTG_FS_BASE + OTG_HFIR)dwc_endpoints_resetRCC_CICR_HSIRDYC (1 << 3)bLength__GNUCLIKE_BUILTIN_STDARG 1RCC_APB1SMENR1_I2C3SMEN (1 << 23)USB_REQ_TYPE_OUT 0x0RCC_ICSCR_HSICAL_MASK 0xffOTG_DIEPCTL0_CNAK (1 << 26)RCC_CICR_LSECSSC (1 << 9)OTG_DOEPCTL0_USBAEP (1 << 15)RCC_PLLPEN (1 << 16)__FLT32X_IS_IEC_60559__ 2RCC_APB1RSTR1_LPTIM1RST (1 << 31)__IEEE_LITTLE_ENDIAN RCC_APB1SMENR1_TIM5SMEN (1 << 3)__lock_init_recursive(lock) ((void) 0)RCC_CFGR_MCO_HSE 0x4UINT_FAST32_MAX __UINT_FAST32_MAX__OTG_GRXSTSP_BCNT_MASK (0x7ff << 4)RCC_CIER_LSE_CSSIE (1 << 9)BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)bRequestUINT32_CTIM2_BASE (PERIPH_BASE_APB1 + 0x0000)_usbd_deviceshort unsigned intRCC_AHB2RSTR_AESRST (1 << 16)signed chariFunctionrxbcnt___int_least64_t_defined 1OTG_GUSBCFG_TOCAL 0x00000003__size_t__ bFunctionClassLIBOPENCM3_RCC_H RCC_PLLCFGR_PLLR_DIV8 3__predict_false(exp) __builtin_expect((exp), 0)RCC_APB2SMENR_SAI2SMEN (1 << 22)RCC_APB2SMENR_SYSCFGSMEN (1 << 0)RCC_CCIPR_UART4SEL_SHIFT 6INTMAX_C(c) __INTMAX_C(c)WINT_MAX __WINT_MAX____ULLACCUM_EPSILON__ 0x1P-32ULLKDESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 0x14)__CHAR_BIT__ 8INTMAX_MINOTG_GOTGCTL_DHNPEN (1 << 11)__INTMAX_TYPE__ long long intRCC_CR_MSIRANGE_2MHZ 5_POINTER_INT longOTG_DCTL_TCTL_MASK (7 << 4)SCC_DFSDMRCC_CFGR_PPRE1_SHIFT 8RCC_AHB2RSTR_ADCRST (1 << 13)RCC_APB2RSTR_TIM16RST (1 << 17)_REENT_INIT(var) { 0, _REENT_STDIO_STREAM(&(var), 0), _REENT_STDIO_STREAM(&(var), 1), _REENT_STDIO_STREAM(&(var), 2), 0, "", 0, _NULL, 0, _NULL, _NULL, 0, _NULL, _NULL, 0, _NULL, { { 0, _NULL, "", {0, 0, 0, 0, 0, 0, 0, 0, 0}, 0, 1, { {_RAND48_SEED_0, _RAND48_SEED_1, _RAND48_SEED_2}, {_RAND48_MULT_0, _RAND48_MULT_1, _RAND48_MULT_2}, _RAND48_ADD }, {0, {0}}, {0, {0}}, {0, {0}}, "", "", 0, {0, {0}}, {0, {0}}, {0, {0}}, {0, {0}}, {0, {0}} } }, _REENT_INIT_ATEXIT _NULL, {_NULL, 0, _NULL} }bDeviceProtocolOTG_GINTSTS_EOPF (1 << 15)__ARM_FEATURE_DOTPROD_GLOBAL_ATEXIT (_GLOBAL_REENT->_atexit)RCC_APB1ENR2 MMIO32(RCC_BASE + RCC_APB1ENR2_OFFSET)USB_ENDPOINT_ATTR_IMPLICIT_FEEDBACK_DATA 0x20RCC_CCIPR_I2CxSEL_MASK 0x3endpoint_BSD_SIZE_T_ usb_control_stateRCC_BDCR_LSESYSDIS (1 << 7)RCC_CFGR_PPRE2_DIV8 0x6unsigned signedOTG_GUSBCFG 0x00C__FLT64_MIN__ 2.2250738585072014e-308F64__INTPTR_MAX__ 0x7fffffff__CC_SUPPORTS_VARADIC_XXX 1OTG_DOEPMSK_STUPM (1 << 3)SCC_DMA1SCC_DMA2RCC_APB2RSTR_TIM8RST (1 << 13)FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000)OTG_DIEPINTX_XFRC (1 << 0)__GCC_ATOMIC_POINTER_LOCK_FREE 2_Nonnull SCC_I2C1__DBL_MAX__ ((double)1.7976931348623157e+308L)OTG_GINTMSK_ISOODRPM 0x00004000RCC_FWOTG_HPRT_PLSTS_DP (1 << 10)__FLT32_MAX_10_EXP__ 38__GNU_VISIBLE 0_REENT_RAND48_MULT(ptr) ((ptr)->_new._reent._r48._mult)RCC_CRCSCC_WWDGiface_assocINT_LEAST32_MIN (-INT_LEAST32_MAX - 1)iInterfacestateRCC_AHB2SMENR_GPIOESMEN (1 << 4)ITR_BASE (SCS_BASE + 0x0000)INT_LEAST8_MAX_REENT_MBRTOWC_STATE(ptr) ((ptr)->_new._reent._mbrtowc_state)__WCHAR_T__ RCC_CRSPERIPH_BASE (0x40000000U)fifo_mem_top_ANSI_STDDEF_H RCC_BDCR_LSEBYP (1 << 2)dwc_ep_read_packetRCC_BDCR_LSEON (1 << 0)iConfigurationUSB_REQ_SET_SYNCH_FRAME 12__ARM_FP16_FORMAT_IEEEOTG_GINTMSK_PRTIM 0x01000000RCC_CCIPR_ADCSEL_SYS 3RCC_CIFR_CSSF (1 << 8)_RAND48_MULT_2 (0x0005)RCC_SPI1RCC_SPI2RCC_SPI3RCC_LPTIM2__USES_INITFINI__ 1__DEVOLATILE(type,var) ((type)(__uintptr_t)(volatile void *)(var))USBD_REQ_NEXT_CALLBACK__FLT64_MAX_EXP__ 1024RCC_APB1ENR1_LCDEN (1 << 9)RCC_CR_PLLSAI2RDY (1 << 29)__lockable __lock_annotate(lockable)OTG_HCCHAR_EPDIR_MASK (1 << 15)__has_extension __has_feature__REGISTER_PREFIX__ RCC_CFGR_PPRE2_MASK 0x7RCC_BDCR_RTCSEL_LSE 1__unlocks(...) __lock_annotate(unlock_function(__VA_ARGS__))OTG_HCCHAR_EPTYP_INTERRUPT (3 << 18)__USFRACT_MAX__ 0XFFP-8UHR_RAND48_MULT_1 (0xdeec)PERIPH_BASE_AHB2 (0x48000000U)RCC_SYSCFGSCC_SAI1SCC_SAI2_STRING_H_ __FLT32_MAX__ 3.4028234663852886e+38F32__ARM_FEATURE_CLZ 1STALLEDOTG_HCCHAR_MCNT_MASK (0x3 << 20)__lock_close(lock) ((void) 0)USB_DT_OTHER_SPEED_CONFIGURATION 7OTG_GINTMSK_USBRST 0x00001000RCC_AHB2SMENR_OTGFSSMEN (1 << 12)RCC_AHB2SMENR_RNGSMEN (1 << 18)__FRACT_MAX__ 0X7FFFP-15R__ARM_FEATURE_NUMERIC_MAXMIN__warn_references(sym,msg) __asm__(".section .gnu.warning." #sym); __asm__(".asciz \"" msg "\""); __asm__(".previous")_REENT_ASCTIME_BUF(ptr) ((ptr)->_new._reent._asctime_buf)__generic(expr,t,yes,no) __builtin_choose_expr( __builtin_types_compatible_p(__typeof(expr), t), yes, no)OTG_HCINT(x) (0x508 + 0x20*(x))__USQ_FBIT__ 32RCC_TIM2OTG_HCTSIZ(x) (0x510 + 0x20*(x))__INT_FAST8_TYPE__ intOTG_GRXSTSP_PKTSTS_OUT (0x2 << 17)LAST_DATA_OUTRCC_CIER_PLLRDYIE (1 << 5)UINT8_C(c) __UINT8_C(c)UINT32_MAXRCC_APB1SMENR1_SPI3SMEN (1 << 15)__ARM_FEATURE_BF16_SCALAR_ARITHMETIC__ptr_t void *OTG_HCINT_STALL (1 << 3)RCC_CR_MSIRANGE_16MHZ 8unsignedOTG_DCTL_RWUSIG (1 << 0)RCC_CSR MMIO32(RCC_BASE + 0x94)__STDC_HOSTED__ 1__UINTMAX_C(c) c ## ULL__need_ptrdiff_tUSB_CONFIG_ATTR_SELF_POWERED 0x40RCC_APB2RSTR_SYSCFGRST (1 << 0)GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400)user_callback_reset__requires_exclusive(...) __lock_annotate(exclusive_locks_required(__VA_ARGS__))RCC_CSR_LPWRRSTF (1 << 31)FMC1_BANK_BASE (0x60000000U)_WIDE_ORIENT 1RCC_CFGR_HPRE_DIV4 0x9RCC_APB1SMENR1_TIM7SMEN (1 << 5)OTG_HPRT_PRST (1 << 8)long intUSB_DT_ENDPOINT_SIZE 7__WINT_MIN__ 0U_REENT_MP_P5S(ptr) ((ptr)->_p5s)__SYS_CONFIG_H__ __DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)INT16_MAX__DBL_HAS_DENORM__ 1TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)__ATFILE_VISIBLE 0__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1__FLT64_MAX_10_EXP__ 308RCC_CFGR_PPRE1_DIV16 0x7_WCHAR_T_DEFINED _N_LISTS 30OTG_HFIR 0x404__PTRDIFF_TYPE__ intctrl_buf_len__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2__USACCUM_FBIT__ 8__GNUC_STDC_INLINE__ 1OTG_DOEPCTL0_EPTYP_MASK (0x3 << 18)UINT64_MAXRCC_CCIPR_UART5SEL_SHIFT 8__ARM_FPset_address_before_statusOTG_HPTXSTS_PTXQTOP_ENDPOINT_NUMBER_MASK (0xf<<27)__EXPORT __PMT(args) argsRCC_AHB2SMENR_GPIOGSMEN (1 << 6)OTG_HCINTMSK_AHBERR (1 << 2)RCC_CICR_LSERDYC (1 << 1)RCC_CSR_BORRSTF (1 << 27)_PTRDIFF_T_ UINT_FAST8_MAXOTG_GINTMSK_IPXFRM 0x00200000__WCHAR_WIDTH__ 32RCC_APB1SMENR1_UART5SMEN (1 << 20)RCC_APB1SMENR1_SPI2SMEN (1 << 14)RCC_APB2SMENR MMIO32(RCC_BASE + RCC_APB2SMENR_OFFSET)__UTQ_FBIT__ 128__USB_PRIVATE_H __strftimelike(fmtarg,firstvararg) __attribute__((__format__ (__strftime__, fmtarg, firstvararg)))LIBOPENCM3_CM3_COMMON_H RCC_AHB2SMENR MMIO32(RCC_BASE + RCC_AHB2SMENR_OFFSET)__PTRDIFF_T RCC_APB1ENR1_I2C2EN (1 << 22)RCC_CCIPR_CLK48SEL_HSI48 0RCC_APB1SMENR1_I2C1SMEN (1 << 21)RCC_CIFR_PLLSAI1RDYF (1 << 6)OTG_GINTSTS_ESUSP (1 << 10)__ARM_FEATURE_DSP 1__ARM_FEATURE_CRYPTORCC_CFGR_HPRE_DIV256 0xeFPB_BASE (PPBI_BASE + 0x2000)RCC_CCIPR_LPTIM2SEL_SHIFT 20OTG_GRXSTSP_PKTSTS_GOUTNAK (0x1 << 17)OTG_GOTGCTL_ASVLD (1 << 18)__FLT32_HAS_DENORM__ 1__strfmonlike(fmtarg,firstvararg) __attribute__((__format__ (__strfmon__, fmtarg, firstvararg)))RCC_CFGR_MCO_MASK 0xfOTG_HCCHAR_EPTYP_MASK (3 << 18)RCC_APB1SMENR2_SWPMI1SMEN (1 << 2)RCC_AHB2RSTR_GPIOHRST (1 << 7)__USBD_H INT32_MIN (-INT32_MAX - 1)__ARM_FEATURE_FP16_SCALAR_ARITHMETIC__always_inline __inline__ __attribute__((__always_inline__))__SACCUM_FBIT__ 7__HQ_FBIT__ 15OTG_GINTMSK_RXFLVLM 0x00000010UINT8_C__LLACCUM_IBIT__ 32RCC_ADC1uint32_tRCC_CIFR_HSIRDYF (1 << 3)RCC_APB1SMENR2_LPTIM2SMEN (1 << 5)__SIZE_T __LLFRACT_FBIT__ 63__LDBL_DIG__ 15__CHAR32_TYPE__ long unsigned intRCC_APB1SMENR2 MMIO32(RCC_BASE + RCC_APB1SMENR2_OFFSET)SIG_ATOMIC_MIN __SIG_ATOMIC_MIN__OTG_GRSTCTL_TXFFLSH (1 << 5)__XSI_VISIBLE 0__pure2 __attribute__((__const__))__GCC_ATOMIC_SHORT_LOCK_FREE 2RCC_CFGR_PPRE1_NODIV 0x0RCC_AHB1ENR_DMA2EN (1 << 1)__ULFRACT_MAX__ 0XFFFFFFFFP-32ULRRCC_CRRCR_HSI48ON (1 << 0)OTG_DOEPCTL0_SNPM (1 << 20)OTG_HCCHAR_LSDEV (1 << 17)__SIZEOF_POINTER__ 4__DOTS , ...__GCC_ASM_FLAG_OUTPUTS__ 1__pure __attribute__((__pure__))RCC_APB1SMENR1_CAN1SMEN (1 << 25)CLR_REG_BIT_MSK_AND_SET(REG,MSK,BIT,EXTRA_BITS) SET_REG((REG), (GET_REG((REG)) & (MSK) & (~(BIT))) | (EXTRA_BITS))RCC_CR_MSIRANGE_32MHZ 10RCC_CFGR_HPRE_DIV128 0xdUINT_LEAST64_MAX __UINT_LEAST64_MAX____UINTMAX_TYPE__ long long unsigned int_T_SIZE RCC_APB1ENR1_TIM3EN (1 << 1)OTG_GINTMSK_ESUSPM 0x00000400OTG_DSTS 0x808OTG_HCCHAR_MPSIZ_MASK (0x7ff << 0)RCC_APB2SMENR_TIM17SMEN (1 << 18)RCC_APB2RSTR_TIM1RST (1 << 11)__INTPTR_WIDTH__ 32OTG_DIEPSIZ0_PKTCNT (1 << 19)OTG_HFNUM 0x408RCC_AHB2RSTR_RNGRST (1 << 18)__trylocks_shared(...) __lock_annotate(shared_trylock_function(__VA_ARGS__))_REENT_STRTOK_LAST(ptr) ((ptr)->_new._reent._strtok_last)USART3_BASE (PERIPH_BASE_APB1 + 0x4800)INTPTR_MINextralenRCC_CFGR_MCO_SYSCLK 0x1SCC_FMCRCC_CR_MSIRANGE_MASK 0xf__result_use_check __attribute__((__warn_unused_result__))CLR_REG_BIT(REG,BIT) SET_REG((REG), (~(BIT)))OTG_GINTSTS_RXFLVL (1 << 4)__GNUC_PREREQ(maj,min) ((__GNUC__ << 16) + __GNUC_MINOR__ >= ((maj) << 16) + (min))USB_ENDPOINT_ATTR_TYPE 0x03__FLT64_HAS_INFINITY__ 1__GCC_DESTRUCTIVE_SIZE 64RCC_PLLCFGR_PLLREN (1<<24)RCC_BDCR_LSECSSD (1 << 6)USB_DT_INTERFACE_POWER 8USB_DT_DEVICE_QUALIFIER 6RCC_CCIPR_CLK48SEL_SHIFT 26__LONG_LONG_MAX__ 0x7fffffffffffffffLLOTG_GOTGCTL_HSHNPEN (1 << 10)RCC_CR_PLLRDY (1 << 25)USB_ENDPOINT_ATTR_CONTROL 0x00__ATOMIC_ACQ_REL 4_T_WCHAR_ RCC_APB1SMENR1_UART4SMEN (1 << 19)RCC_AHB1RSTR_DMA1RST (1 << 0)__GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"USB_DT_INTERFACE_ASSOCIATION_SIZE sizeof(struct usb_iface_assoc_descriptor)MMIO64(addr) (*(volatile uint64_t *)(addr))__STDC_VERSION__ 199901LOTG_FS_DCTL MMIO32(USB_OTG_FS_BASE + OTG_DCTL)__LFRACT_MIN__ (-0.5LR-0.5LR)_HAVE_CC_INHIBIT_LOOP_TO_LIBCALL 1__CONCAT1(x,y) x ## yOTG_HCINTMSK_NAKM (1 << 4)RCC_CFGR_MCO_NOCLK 0x0OTG_GRXSTSP_EPNUM_MASK (0xf << 0)__RCSID_SOURCE(s) struct __hackOTG_DIEPTXF(x) (0x104 + 4*((x)-1))__DEFINED_wchar_t __ISO_C_VISIBLE 1999RCC_CCIPR_ADCSEL_MASK 0x3INT64_C(c) __INT64_C(c)__GCC_ATOMIC_LLONG_LOCK_FREE 1_SYS_CDEFS_H_ RCC_APB2ENR_SDMMC1EN (1 << 10)USB_DT_INTERFACE_ASSOCIATION 11OTG_HPRT_POCCHNG (1 << 5)usbd_set_config_callbackUSB_REQ_TYPE_INTERFACE 0x01OTG_DIEPCTL0_TXFNUM_MASK (0xf << 22)RCC_AHB1ENR_CRCEN (1 << 12)__LONG_LONG_WIDTH__ 64RCC_CR_MSIRANGE_400KHZ 2OTG_HCCHAR_MCNT_3 (0x3 << 20)RCC_AHB3ENR_OFFSET 0x50RCC_CFGR_PPRE2_DIV2 0x4__lock_init(lock) ((void) 0)OTG_GOTGINT_HNGDET (1 << 17)bAlternateSetting__VERSION__ "12.2.1 20221205"RCC_CCIPR_USARTxSEL_SYS 1OTG_FS_HCCHAR(x) MMIO32(USB_OTG_FS_BASE + OTG_HCCHAR(x))OTG_FS_GNPTXFSIZ MMIO32(USB_OTG_FS_BASE + OTG_GNPTXFSIZ)__FLT64_EPSILON__ 2.2204460492503131e-16F64OTG_DOEPMSK 0x814OTG_DCTL 0x804__NEWLIB_H__ 1OTG_GINTSTS_ENUMDNE (1 << 13)USB_DEV_STATUS_REMOTE_WAKEUP 0x02OTG_HCINT_FRMOR (1 << 9)GPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400)OTG_GRXSTSP_PKTSTS_SETUP (0x6 << 17)__ULLACCUM_FBIT__ 32OTG_DOEPINT(x) (0xB08 + 0x20*(x))RCC_CICR_CSSC (1 << 8)_REENT_SIGNAL_BUF(ptr) ((ptr)->_new._reent._signal_buf)OTG_GRSTCTL_RXFFLSH (1 << 4)__LDBL_HAS_QUIET_NAN__ 1OTG_GAHBCFG_GINT 0x0001RCC_CR_CSSON (1 << 19)__WCHAR_MAX__ 0xffffffffUUART5_BASE (PERIPH_BASE_APB1 + 0x5000)RCC_CFGR_MCOPRE_DIV2 1_SIZE_T RCC_CIER_LSERDYIE (1 << 1)RCC_CCIPR_SAIxSEL_PLLSAI1P 0OTG_FS_GAHBCFG MMIO32(USB_OTG_FS_BASE + OTG_GAHBCFG)USB_FEAT_DEVICE_REMOTE_WAKEUP 1RCC_APB2ENR_DFSDMEN (1 << 24)__ULLACCUM_IBIT__ 32__nonnull(x) __attribute__((__nonnull__ x))RCC_APB2SMENR_SAI1SMEN (1 << 21)OTG_GINTMSK_USBSUSPM 0x00000800OTG_HCTSIZ_DOPING (1 << 31)OTG_DOEPCTL0_CNAK (1 << 26)__LDBL_MANT_DIG__ 53RCC_APB2ENR_USART1EN (1 << 14)OTG_DIEPEMPMSK 0x834__ULLFRACT_FBIT__ 64RCC_AHB2RSTR_OFFSET 0x2c__DQ_IBIT__ 0OTG_DOEPINTX_OTEPDIS (1 << 4)OTG_FS_GUSBCFG MMIO32(USB_OTG_FS_BASE + OTG_GUSBCFG)__FLT64_MAX__ 1.7976931348623157e+308F64_SIZE_T_DEFINED OTG_GINTMSK_EOPFM 0x00008000INT_LEAST8_MINRCC_AHB2SMENR_GPIOASMEN (1 << 0)USB_DT_DEVICE_SIZE sizeof(struct usb_device_descriptor)RCC_CRRCR_HSI48RDY (1 << 1)CORESIGHT_LSR_SLI (1<<0)__UQQ_IBIT__ 0LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))USB_DT_DEVICE 1___int8_t_defined 1__SIG_ATOMIC_WIDTH__ 32_Noreturn __dead2OTG_FS_DCFG MMIO32(USB_OTG_FS_BASE + OTG_DCFG)SCC_SWPMI1OTG_GUSBCFG_FDMOD 0x40000000RCC_CCIPR_SAI1SEL_SHIFT 22__ARM_FEATURE_CDE__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1__BSD_VISIBLE 0OTG_HPTXFSIZ_PTXSA_MASK (0x0000ffff)__need_NULL RCC_AHB2ENR_GPIODEN (1 << 3)RCC_CCIPR_USART1SEL_SYS 1OTG_FS_GRSTCTL MMIO32(USB_OTG_FS_BASE + OTG_GRSTCTL)SYS_TICK_BASE (SCS_BASE + 0x0010)OTG_GINTMSK_DISCINT 0x20000000RCC_APB1ENR2_LPTIM2EN (1 << 5)__ARM_FEATURE_LDREX__UINT_LEAST32_MAX__ 0xffffffffULLIBOPENCM3_TOOLS_H STATUS_OUTNULL ((void *)0)__USFRACT_EPSILON__ 0x1P-8UHR__ORDER_BIG_ENDIAN__ 4321__ARM_FEATURE_CMSEbFunctionProtocolRCC_AHB2ENR_GPIOFEN (1 << 5)PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)__UFRACT_MAX__ 0XFFFFP-16URI2C1_BASE (PERIPH_BASE_APB1 + 0x5400)_MACHINE__DEFAULT_TYPES_H __UINT_FAST32_TYPE__ unsigned intOTG_FS_DIEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + OTG_DIEPTSIZ(x))RCC_AHB1ENR_OFFSET 0x48__SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)OTG_GINTSTS_DISCINT (1 << 29)__ARM_FEATURE_COPROC 15RCC_APB1ENR1_SPI3EN (1 << 15)INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)USB_REQ_TYPE_RECIPIENT 0x1FRCC_APB1RSTR2_SWPMI1RST (1 << 2)RCC_APB1ENR1_TIM5EN (1 << 3)USB_ENDPOINT_ATTR_ISOCHRONOUS 0x01OTG_HCTSIZ_DPID_DATA2 (0x1 << 29)iProductusb_interfaceUSB_REQ_TYPE_DEVICE 0x00USB_CONFIG_ATTR_REMOTE_WAKEUP 0x20__need_wchar_t__FLT_DECIMAL_DIG__ 9OTG_GOTGCTL_DBCT (1 << 17)BIT31 (1<<31)__INT32_TYPE__ long int_T_PTRDIFF OTG_HCCHAR_ODDFRM (1 << 29)OTG_HPTXSTS_PTXFSAVL_MASK (0x0000ffff)__USACCUM_IBIT__ 8GPIO_PORT_H_BASE (PERIPH_BASE_AHB2 + 0x1c00)OTG_HCINT_NAK (1 << 4)RCC_AHB3ENR MMIO32(RCC_BASE + RCC_AHB3ENR_OFFSET)_READ_WRITE_RETURN_TYPE int__ULFRACT_MIN__ 0.0ULR__HA_IBIT__ 8usb_setup_dataOTG_GRXSTSP_DPID_DATA1 (0x2 << 15)OTG_FS_DOEPCTL(x) MMIO32(USB_OTG_FS_BASE + OTG_DOEPCTL(x))RCC_APB1RSTR1_DAC1RST (1 << 29)OTG_GINTMSK_SRQIM 0x40000000RCC_AHB1ENR MMIO32(RCC_BASE + RCC_AHB1ENR_OFFSET)__TQ_FBIT__ 127OTG_HPTXSTS_PTXQTOP_TYPE_ZEROLENGTH (0x01<<25)USB_REQ_TYPE_TYPE 0x60__UINTPTR_TYPE__ unsigned int__FINITE_MATH_ONLY__ 0bcdDeviceUINT8_MAX __UINT8_MAX__OTG_GINTMSK_WUIM 0x80000000RCC_APB1RSTR1 MMIO32(RCC_BASE + RCC_APB1RSTR1_OFFSET)OTG_GRSTCTL 0x010__guarded_by(x) __lock_annotate(guarded_by(x))OTG_HCINTMSK_BBERRM (1 << 8)__LFRACT_FBIT__ 31bMaxPacketSize0driver__ARM_FEATURE_BF16_VECTOR_ARITHMETICUSB_DT_DEBUG 10configRCC_AHB2SMENR_GPIOFSMEN (1 << 5)UINT8_MAXOTG_DIEPMSK_TOM (1 << 3)OTG_HCINT_BBERR (1 << 8)RCC_AHB3ENR_QSPIEN (1 << 8)POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)USBD_REQ_HANDLEDOTG_HCINTMSK(x) (0x50C + 0x20*(x))__ARM_SIZEOF_MINIMAL_ENUM 1RCC_APB2RSTR_OFFSET 0x40RCC_AHB1RSTR_OFFSET 0x28USB_REQ_TYPE_STANDARD 0x00__INT64_C(c) c ## LLtype_maskRCC_CCIPR_I2CxSEL_SYS 1INT_LEAST16_MAXbmRequestTypeRCC_APB1ENR1 MMIO32(RCC_BASE + RCC_APB1ENR1_OFFSET)DATA_IN__DA_FBIT__ 31__FLT32_MIN__ 1.1754943508222875e-38F32OTG_DAINTMSK 0x81CwValueSIZE_MAX __SIZE_MAX__INT8_MINRCC_I2C1RCC_I2C2RCC_I2C3__XSTRING(x) __STRING(x)__SCCSID(s) struct __hackRCC_CRRCR MMIO32(RCC_BASE + 0x98)__GCC_ATOMIC_BOOL_LOCK_FREE 2INT_FAST64_MINRCC_AHB2SMENR_ADCSMEN (1 << 13)OTG_HCFG_FSLSPCS_48MHz (0x1 << 0)RCC_CSR_MSIRANGE_4MHZ 6__INT_FAST32_MAX__ 0x7fffffffRCC_CFGR_MCOPRE_DIV4 2__FLT_MAX_10_EXP__ 38OTG_GINTMSK_SOFM 0x00000008RCC_APB2RSTR_SPI1RST (1 << 12)dwc_ep_stall_setWINT_MIN __WINT_MIN____ATTRIBUTE_IMPURE_PTR__ __DA_IBIT__ 32OTG_DIEPINTX_INEPNE (1 << 6)fifo_mem_top_ep0__VFP_FP__ 1set_address__ARM_ASM_SYNTAX_UNIFIED__ 1RCC_PLLCFGR_PLLQ_SHIFT 21_REENT_CHECK_MISC(ptr) _WANT_IO_LONG_LONG 1INT32_MAXSCC_SYSCFG__ARM_FP 4RCC_CSR_WWDGRSTF (1 << 30)RCC_PLLCFGR_PLLM_MASK 0x7__UFRACT_MIN__ 0.0UROTG_HFNUM_FTREM_MASK (0xffff0000)__ULFRACT_IBIT__ 0__locks_shared(...) __lock_annotate(shared_lock_function(__VA_ARGS__))OTG_GINTSTS_CIDSCHG (1 << 28)bFirstInterfaceRCC_APB1ENR2_OFFSET 0x5cRCC_CCIPR_SWPMI1SEL (1 << 30)OTG_HPRT 0x440RCC_APB2SMENR_DFSDMSMEN (1 << 24)__scanflike(fmtarg,firstvararg) __attribute__((__format__ (__scanf__, fmtarg, firstvararg)))RCC_BDCR_RTCSEL_HSEDIV32 3OTG_HCCHAR_MCNT_2 (0x2 << 20)__GCC_CONSTRUCTIVE_SIZE 64__ARM_SIZEOF_WCHAR_T 4OTG_GINTMSK_OTGINT 0x00000004OTG_FS_HCTSIZ(x) MMIO32(USB_OTG_FS_BASE + OTG_HCTSIZ(x))RCC_APB1RSTR1_TIM7RST (1 << 5)RCC_AHB1ENR_TSCEN (1 << 16)TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)__SIZEOF_DOUBLE__ 8__UINT_FAST32_MAX__ 0xffffffffU__LDBL_MAX_EXP__ 1024true 1RCC_FMC__UACCUM_MAX__ 0XFFFFFFFFP-16UKRCC_BDCR_RTCSEL_MASK 0x3QUADSPI_BASE (0xa0001000U)bNumConfigurations_BSD_WCHAR_T_ RCC_CR_HSERDY (1 << 17)__ARM_FEATURE_FP16_VECTOR_ARITHMETIC_RAND48_ADD (0x000b)SCC_CRCep_stall_getOTG_HFNUM_FRNUM_MASK (0x0000ffff)rcc_periph_clock_enableOTG_HCTSIZ_PKTCNT_MASK (0x3ff << 19)_RAND48_SEED_0 (0x330e)OTG_HCCHAR_MCNT_1 (0x1 << 20)RCC_APB1RSTR1_USART3RST (1 << 18)_ATTRIBUTE(attrs) __attribute__ (attrs)RCC_AHB2RSTR_GPIOERST (1 << 4)LAST_DATA_INOTG_GINTMSK_ENUMDNEM 0x00002000__INTMAX_MAX__ 0x7fffffffffffffffLL__requires_shared(...) __lock_annotate(shared_locks_required(__VA_ARGS__))INT64_MAXbInterfaceProtocolRCC_APB1ENR1_TIM2EN (1 << 0)OTG_GINTMSK_MMISM 0x00000002UINT_LEAST16_MAX __UINT_LEAST16_MAX__RCC_CR_HSIASFS (1 << 11)__LONG_WIDTH__ 32_REENT_MP_FREELIST(ptr) ((ptr)->_freelist)__OPTIMIZE__ 1__signed signed__SSP_FORTIFY_LEVEL 0OTG_FS_FIFO(x) (&MMIO32(USB_OTG_FS_BASE + (((x) + 1) << 12)))usbd_control_callback_SYS_FEATURES_H USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x6800)RCC_CCIPR_LPUART1SEL_MASK 0x3__arm__ 1PTRDIFF_MINRCC_APB1RSTR1_UART5RST (1 << 20)RCC_DAC1OTG_GINTSTS_OEPINT (1 << 19)../../usb/usb_f107.c__restrict restrictOTG_GRSTCTL_HSRST (1 << 1)OTG_HCINTMSK_XFRCM (1 << 0)ADC1_BASE (0x50000000U + 0x40000)USB_REQ_TYPE_OTHER 0x03RCC_CR_HSEBYP (1 << 18)UINT32_MAX __UINT32_MAX____OPTIMIZE_SIZE__ 1ctrl_buf__size_tUINT_LEAST32_MAX __UINT_LEAST32_MAX__USB_DT_INTERFACE 4OTG_GINTSTS_USBRST (1 << 12)__nonnull_all __attribute__((__nonnull__))_ELIDABLE_INLINE static __inline__ep_resetpoll__alloc_align(x) __attribute__((__alloc_align__(x)))_T_WCHAR bDescriptorType_FVWRITE_IN_STREAMIO 1_SIZET_ __INT8_TYPE__ signed charOTG_HCINT_ACK (1 << 5)__LDBL_DENORM_MIN__ 4.9406564584124654e-324LRCC_PLLCFGR_PLLSRC_MASK 0x3OTG_DIEPSIZ0_XFRSIZ_MASK (0x7f << 0)RCC_APB2SMENR_TIM1SMEN (1 << 11)SYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000)RCC_CR_MSIRANGE_100KHZ 0RCC_APB1RSTR1_OPAMPRST (1 << 30)__hidden __attribute__((__visibility__("hidden")))RCC_AHB2ENR_AESEN (1 << 16)RCC_CIER_HSERDYIE (1 << 4)_STDDEF_H_ OTG_GNPTXFSIZ 0x028RCC_TIM15__RAND_MAX__DEFINED_ptrdiff_t OTG_FS_HPTXSTS MMIO32(USB_OTG_FS_BASE + OTG_HPTXSTS)UINT_LEAST32_MAX__GNUC_PREREQ__(ma,mi) __GNUC_PREREQ(ma, mi)__ACCUM_MAX__ 0X7FFFFFFFP-15KRCC_CIFR_LSECSSF (1 << 9)__FLT64_MIN_EXP__ (-1021)__INT_FAST32_TYPE__ intuser_callback_sofRCC_APB1RSTR1_LCDRST (1 << 9)OTG_GCCFG 0x038RCC_APB2ENR_TIM16EN (1 << 17)_Nullable RCC_AHB1SMENR_OFFSET 0x68__FLT64_HAS_QUIET_NAN__ 1__ARM_NEON__TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)USART2_BASE (PERIPH_BASE_APB1 + 0x4400)_NOTHROW __CC_SUPPORTS___INLINE__ 1DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x75e0)OTG_HCFG_FSLSPCS_6MHz (0x2 << 0)RCC_BDCR_LSCOEN (1 << 24)USB_REQ_SET_FEATURE 3stringsTOG_SET_REG_BIT_MSK(REG,MSK,BIT) TOG_SET_REG_BIT_MSK_AND_SET((REG), (MSK), (BIT), 0)INT8_MAXRCC_CIER_LSIRDYIE (1 << 0)RCC_CSR_LSIRDY (1 << 1)CORESIGHT_LAR_OFFSET 0xfb0RCC_CFGR_MCO_LSE 0x7RCC_APB1RSTR2 MMIO32(RCC_BASE + RCC_APB1RSTR2_OFFSET)_REENT_INIT_ATEXIT _NULL, _ATEXIT_INIT,_REENT_SIGNAL_SIZE 24_SYS_REENT_H_ OTG_GINTMSK_NPTXFEM 0x00000020__FLT32X_MIN_EXP__ (-1021)dwc_ep_write_packet_BSD_PTRDIFF_T_ __WCHAR_T RNG_BASE (0x50000000U + 0x60800)__lock_try_acquire_recursive(lock) ((void) 0)__CC_SUPPORTS___FUNC__ 1OTG_DOEPMSK_OTEPDM (1 << 4)__lock_acquire_recursive(lock) ((void) 0)__ARM_ARCH_PROFILERCC_CCIPR_SAIxSEL_MASK 0x3__LACCUM_IBIT__ 32OTG_GRXSTSR 0x01CRCC_CCIPR_LPTIM1SEL_SHIFT 18OTG_FS_DIEPEMPMSK MMIO32(USB_OTG_FS_BASE + OTG_DIEPEMPMSK)RCC_CICR_HSI48RDYC (1 << 10)RCC_CCIPR_LPUART1SEL_LSE 3USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6c00)MMIO16(addr) (*(volatile uint16_t *)(addr))SCS_BASE (PPBI_BASE + 0xE000)OTG_HPRT_PRES (1 << 6)___int_ptrdiff_t_h INT16_MINWCHAR_MIN __WCHAR_MIN__OTG_DOEPINTX_STUP (1 << 3)__attribute_format_strfmon__(a,b) RCC_CCIPR_UARTxSEL_MASK RCC_CCIPR_USARTxSEL_MASKlong long unsigned intRCC_CFGR_SW_MSI 0x0OTG_GOTGCTL_HNPRQ (1 << 9)OTG_FS_DVBUSPULSE MMIO32(USB_OTG_FS_BASE + OTG_DVBUSPULSE)UINTPTR_MAX __UINTPTR_MAX__INT8_MAX __INT8_MAX____have_long32 1OTG_FS_DSTS MMIO32(USB_OTG_FS_BASE + OTG_DSTS)RCC_PLLCFGR_PLLM(x) ((x)-1)USB_REQ_SET_ADDRESS 5__UINT8_MAX__ 0xffOTG_GUSBCFG_FHMOD 0x20000000USB_REQ_TYPE_DIRECTION 0x80OTG_FS_DIEPMSK MMIO32(USB_OTG_FS_BASE + OTG_DIEPMSK)OTG_FS_HAINTMSK MMIO32(USB_OTG_FS_BASE + OTG_HAINTMSK)OTG_CID_HAS_VBDEN 0x00002000TOG_SET_REG_BIT_MSK_AND_SET(REG,MSK,BIT,EXTRA_BITS) do { register uint16_t toggle_mask = GET_REG(REG) & (MSK); toggle_mask ^= BIT; SET_REG((REG), toggle_mask | (EXTRA_BITS)); } while (0)OTG_DIEPSIZ0_STUPCNT_2 (0x2 << 29)RCC_ICSCR_HSITRIM_MASK 0x1f_REENT_WCRTOMB_STATE(ptr) ((ptr)->_new._reent._wcrtomb_state)__BEGIN_DECLS OTG_DOEPCTLX_SD0PID (1 << 28)USB_REQ_GET_CONFIGURATION 8chardescRCC_CR_MSIRANGE_800KHZ 3BIT19 (1<<19)_REENT_SMALL_CHECK_INIT(ptr) UINT_FAST16_MAXRCC_APB1RSTR1_I2C2RST (1 << 22)__FLT64_DECIMAL_DIG__ 17__UINTPTR_MAX__ 0xffffffffU__ARM_FEATURE_COMPLEXRCC_AHB1ENR_DMA1EN (1 << 0)OTG_DOEPCTL0_MPSIZ_MASK (0x3 << 0)OTG_GOTGINT_SEDET (1 << 2)OTG_HCINT_CHH (1 << 1)OTG_DCTL_SGONAK (1 << 9)__SFRACT_EPSILON__ 0x1P-7HR__ATOMIC_CONSUME 1__unused __attribute__((__unused__))__FLT_MIN__ 1.1754943508222875e-38F__INT_LEAST16_TYPE__ short int__UINT_LEAST64_TYPE__ long long unsigned intEND_DECLS INT32_MAX __INT32_MAX__RCC_CCIPR_USARTxSEL_HSI16 2__USFRACT_FBIT__ 8USB_FEAT_TEST_MODE 2RCC_CSR_IWDGRSTF (1 << 29)RCC_CIFR_MSIRDYF (1 << 2)RCC_CR_MSIRDY (1 << 1)RCC_CCIPR_UARTxSEL_HSI16 RCC_CCIPR_USARTxSEL_HSI16__GCC_ATOMIC_WCHAR_T_LOCK_FREE 2RCC_TIM16RCC_TIM17RCC_APB2RSTR_TIM17RST (1 << 18)RCC_APB1RSTR1_TIM5RST (1 << 3)__SIZEOF_PTRDIFF_T__ 4OTG_FS_GOTGCTL MMIO32(USB_OTG_FS_BASE + OTG_GOTGCTL)RCC_APB1ENR1_USART3EN (1 << 18)SCC_TIM15SCC_TIM16SCC_TIM17OTG_HPRT_PTCTL_J (0x1 << 13)___int32_t_defined 1RCC_APB1ENR1_UART5EN (1 << 20)bConfigurationValueRCC_APB1ENR1_I2C3EN (1 << 23)DMA1_BASE (PERIPH_BASE_AHB1 + 0x0000)RCC_APB1RSTR1_SPI2RST (1 << 14)RCC_CFGR_HPRE_DIV8 0xa__FLT32X_HAS_QUIET_NAN__ 1__GNUC_EXECUTION_CHARSET_NAME "UTF-8"OTG_FS_GRXSTSP MMIO32(USB_OTG_FS_BASE + OTG_GRXSTSP)RCC_AHB3RSTR MMIO32(RCC_BASE + RCC_AHB3RSTR_OFFSET)__ACCUM_MIN__ (-0X1P15K-0X1P15K)RCC_CCIPR_SAIxSEL_PLL 2RCC_CSR_RESET_FLAGS (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF | RCC_CSR_IWDGRSTF | RCC_CSR_SFTRSTF | RCC_CSR_BORRSTF | RCC_CSR_PINRSTF | RCC_CSR_OBLRSTF | RCC_CSR_FWRSTF)OTG_DIEPINTX_EPDISD (1 << 1)__DBL_MIN_EXP__ (-1021)__exported __attribute__((__visibility__("default")))__NULLABILITY_PRAGMA_PUSH USB_ENDPOINT_ADDR_OUT(x) (x)_REENT_MBRLEN_STATE(ptr) ((ptr)->_new._reent._mbrlen_state)bNumEndpointsRCC_BASE (PERIPH_BASE_AHB1 + 0x1000)MPU_BASE (SCS_BASE + 0x0D90)TIM15_BASE (PERIPH_BASE_APB2 + 0x4000)RCC_CFGR_MCOPRE_DIV16 4UINT16_MAX__CC_SUPPORTS_DYNAMIC_ARRAY_INIT 1RCC_AHB2RSTR_OTGFSRST (1 << 12)__LDBL_MAX_10_EXP__ 308SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)GET_REG_BIT(REG,BIT) (GET_REG(REG) & (BIT))__IMPORT OTG_HCCHAR_CHENA (1 << 31)RCC_AHB3RSTR_FMCRST (1 << 0)__SIZEOF_LONG_DOUBLE__ 8RCC_ICSCR_MSITRIM_SHIFT 8OTG_DOEPCTL0_MPSIZ_64 (0x0 << 0)__CC_SUPPORTS_WARNING 1__INT64_TYPE__ long long intRCC_CFGR_SWS_HSI16 0x1INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)__ARM_FEATURE_CRC32__TA_FBIT__ 63__rangeof(type,start,end) (__offsetof(type, end) - __offsetof(type, start))OTG_GNPTXSTS 0x02Cbool _Bool__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64OTG_DIEPMSK_ITTXFEMSK (1 << 4)user_callback_set_config__UINT_LEAST32_TYPE__ long unsigned intRCC_CCIPR_I2C1SEL_SHIFT 12_NOINLINE_STATIC _NOINLINE staticRCC_CCIPR_UARTxSEL_LSE RCC_CCIPR_USARTxSEL_LSESAI2_BASE (PERIPH_BASE_APB2 + 0x5800)_LONG_DOUBLE long double__used __attribute__((__used__))RCC_APB1ENR1_OPAMPEN (1 << 30)INT32_MIN__OBSOLETE_MATH __OBSOLETE_MATH_DEFAULTINT16_C(c) __INT16_C(c)__TA_IBIT__ 64_ATEXIT_INIT {_NULL, 0, {_NULL}, {{_NULL}, {_NULL}, 0, 0}}OTG_DOEPINTX_XFRC (1 << 0)OTG_DTXFSTS(x) (0x918 + 0x20*(x))INT8_MIN (-INT8_MAX - 1)__FLT32X_HAS_DENORM__ 1TSC_BASE (PERIPH_BASE_AHB1 + 0x4000)INT16_CRCC_CR_MSIRANGE_8MHZ 7pm_top__FLT32_HAS_QUIET_NAN__ 1__ATOMIC_RELEASE 3RCC_PLLCFGR MMIO32(RCC_BASE + 0x0c)__HQ_IBIT__ 0OTG_FS_GINTSTS MMIO32(USB_OTG_FS_BASE + OTG_GINTSTS)long long int__FLT_EVAL_METHOD__ 0RCC_AHB3RSTR_QSPIRST (1 << 8)RCC_CFGR_HPRE_SHIFT 4__COPYRIGHT(s) struct __hackRCC_CR_HSEON (1 << 16)OTG_HAINTMSK_HAINTM_MASK (0x0000ffff)__INT_WCHAR_T_H RCC_APB2ENR_SAI2EN (1 << 22)__UHA_FBIT__ 8__ULLFRACT_EPSILON__ 0x1P-64ULLROTG_GUSBCFG_HNPCAP 0x00000200RCC_CSR_PINRSTF (1 << 26)OTG_CID 0x03CGPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0c00)INT_LEAST32_MAXOTG_HPTXSTS 0x410OTG_GCCFG_SOFOUTEN (1 << 20)TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)SCC_TIM1SCC_TIM2SCC_TIM3SCC_TIM4__POSIX_VISIBLE 0SCC_TIM6SCC_TIM7SCC_TIM8__ARM_FEATURE_FMA 1RCC_PWROTG_GOTGINT_SRSSCHG (1 << 8)__ARM_NEON_FP__FDPIC__CORESIGHT_LSR_OFFSET 0xfb4INT64_MIN__UINT16_MAX__ 0xffffOPAMP_BASE (PERIPH_BASE_APB1 + 0x7800)RCC_AHB2ENR_GPIOCEN (1 << 2)bNumInterfacesOTG_DIEPSIZ0_STUPCNT_1 (0x1 << 29)__ARM_ARCH 7OTG_HPTXFSIZ_PTXFD_MASK (0xffff0000)user_callback_suspendRCC_APB1SMENR2_LPUART1SMEN (1 << 0)USB_CLASS_VENDOR 0xFFUINT64_C(c) __UINT64_C(c)__SVID_VISIBLE 0wIndex__CONCAT(x,y) __CONCAT1(x,y)__DBL_HAS_QUIET_NAN__ 1__LDBL_MIN_10_EXP__ (-307)RCC_BDCR_LSEDRV_HIGH 3base_addressRCC_DMA2_REENT_ASCTIME_SIZE 26SIG_ATOMIC_MAX__USFRACT_IBIT__ 0RCC_AHB2SMENR_OFFSET 0x6c__FLT32X_MIN_10_EXP__ (-307)WINT_MAXOTG_HPRT_PSPD_MASK (0x3 << 17)RCC_CFGR_HPRE_MASK 0xfWCHAR_MAX __WCHAR_MAX____DEC_EVAL_METHOD__ 2INT_LEAST64_MAX__LDBL_HAS_INFINITY__ 1_FSEEK_OPTIMIZATION 1long unsigned intDFSDM_BASE (PERIPH_BASE_APB2 + 0x6000)stm32f107_usb_driver_TIME_T_ __int_least64_t__SFRACT_MAX__ 0X7FP-7HRRCC_APB1ENR1_TIM4EN (1 << 2)OTG_DOEPCTL0_EPDIS (1 << 30)RCC_AHB2RSTR_GPIOBRST (1 << 1)DBGMCU_BASE (PPBI_BASE + 0x00042000)USB_ENDPOINT_ATTR_USAGETYPE 0x30RCC_CR_PLLSAI1ON (1 << 26)_MACHINE__TYPES_H RCC_CFGR_SW_MASK 0x3USB_ENDPOINT_ATTR_NOSYNC 0x00__const constOTG_FS_HCFG MMIO32(USB_OTG_FS_BASE + OTG_HCFG)RCC_PLLCFGR_PLLQ_DIV2 0RCC_APB1ENR1_SPI2EN (1 << 14)SCC_LPUART1OTG_GINTSTS_GONAKEFF (1 << 7)LPTIM1_BASE (PERIPH_BASE_APB1 + 0x7c00)__FLT64_HAS_DENORM__ 1OTG_DIEPTSIZ0 0x910RCC_CCIPR_CLK48SEL_PLLSAI1Q 1__FLT_HAS_DENORM__ 1__GNUCLIKE_MATH_BUILTIN_CONSTANTS UINT_LEAST8_MAX__THUMBEL__ 1OTG_GINTSTS_IISOIXFR (1 << 20)OTG_HNPTXFSIZ_PTXSA_MASK (0x0000ffff)iSerialNumberRCC_BDCR_LSEDRV_MEDLOW 1RCC_PLLCFGR_PLLR_SHIFT 25RCC_APB2RSTR MMIO32(RCC_BASE + RCC_APB2RSTR_OFFSET)_Atomic(T) struct { T volatile __val; }RCC_CFGR_SWS_MSI 0x0USB_ENDPOINT_ATTR_SYNC 0x0CDATA_OUTSCC_GPIOFINT_FAST8_MIN (-INT_FAST8_MAX - 1)__TQ_IBIT__ 0__FLT32X_MIN__ 2.2250738585072014e-308F32xRCC_ICSCR_MSITRIM_MASK 0xffRCC_CCIPR_LPTIMxSEL_LSI 1__SIZEOF_FLOAT__ 4SCC_CAN1OTG_GAHBCFG_PTXFELVL 0x0100__SIZE_T__ usbd_set_altsetting_callbackOTG_GOTGCTL_SRQ (1 << 1)__SIZE_TYPE__ unsigned intRCC_UART4RCC_UART5RCC_RNG__offsetof(type,field) offsetof(type, field)RCC_CSR_SFTRSTF (1 << 28)OTG_GINTSTS_IEPINT (1 << 18)__UINT_LEAST8_TYPE__ unsigned char_RAND48_SEED_1 (0xabcd)__LARGEFILE_VISIBLE 0__unreachable() __builtin_unreachable()UINT16_COTG_DOEPTSIZ0 0xB10__STRING(x) #xRCC_APB1SMENR1_DAC1SMEN (1 << 29)OTG_HCINTMSK_DTERRM (1 << 10)__CHAR16_TYPE__ short unsigned intEXTI_BASE (PERIPH_BASE_APB2 + 0x0400)INT16_MIN (-INT16_MAX - 1)RCC_PLLCFGR_PLLR_DIV2 0_REENT_MBTOWC_STATE(ptr) ((ptr)->_new._reent._mbtowc_state)__UFRACT_FBIT__ 16unsigned intep_write_packet__malloc_like __attribute__((__malloc__))ID_BASE (SCS_BASE + 0x0FD0)OTG_FS_HCINT(x) MMIO32(USB_OTG_FS_BASE + OTG_HCINT(x))OTG_FS_DVBUSDIS MMIO32(USB_OTG_FS_BASE + OTG_DVBUSDIS)_REG_BIT(base,bit) (((base) << 5) + (bit))RCC_CICR_PLLSAI1RDYC (1 << 6)BIT9 (1<<9)RCC_CIFR_LSERDYF (1 << 1)__ARM_FEATURE_MVEOTG_HCINTMSK_STALLM (1 << 3)ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0x75a8))RCC_APB2SMENR_USART1SMEN (1 << 14)RCC_BDCR_RTCSEL_LSI 2RCC_APB1ENR1_OFFSET 0x58__UHA_IBIT__ 8__ARM_FEATURE_CDE_COPROCOTG_DIEPCTL0_NAKSTS (1 << 17)__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRbMaxPowerOTG_HCCHAR_EPTYP_CONTROL (0 << 18)RCC_CFGR_SW_PLL 0x3__trylocks_exclusive(...) __lock_annotate(exclusive_trylock_function(__VA_ARGS__))RCC_APB1SMENR1 MMIO32(RCC_BASE + RCC_APB1SMENR1_OFFSET)OTG_FS_GCCFG MMIO32(USB_OTG_FS_BASE + OTG_GCCFG)short intOTG_DIEPTSIZ(x) (0x910 + 0x20*(x))wTotalLengthOTG_FS_GNPTXSTS MMIO32(USB_OTG_FS_BASE + OTG_GNPTXSTS)__GNUC_MINOR__ 2RCC_OPAMPRCC_CIER MMIO32(RCC_BASE + 0x18)BBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)RCC_AHB1SMENR_FLASHSMEN (1 << 8)RCC_CFGR_SWS_HSE 0x2INTMAX_MAX __INTMAX_MAX__RCC_AHB2RSTR_GPIODRST (1 << 3)SCC_OPAMPRCC_APB1RSTR2_LPUART1RST (1 << 0)__UINT_LEAST16_TYPE__ short unsigned intRCC_CFGR_HPRE_DIV2 0x8_LDBL_EQ_DBL 1RCC_CCIPR_USART3SEL_SHIFT 4OTG_GINTMSK_IISOOXFRM 0x00200000OTG_DOEPMSK_OPEM (1 << 8)OTG_GRXSTSP_PKTSTS_IN (0x2 << 17)RCC_PLLSAI1_CFGR MMIO32(RCC_BASE + 0x10)RCC_CSR_LSION (1 << 0)OTG_DIEPCTL0_MPSIZ_64 (0x0 << 0)RCC_CIER_MSIRDYIE (1 << 2)RCC_APB2ENR_SYSCFGEN (1 << 0)TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)OTG_GINTMSK_GONAKEFFM 0x00000080RCC_BDCR_LSEDRV_MEDHIGH 2OTG_GINTSTS_OTGINT (1 << 2)OTG_GINTSTS_MMIS (1 << 1)__FLT_DENORM_MIN__ 1.4012984643248171e-45FOTG_HCINT_XFRC (1 << 0)RCC_AHB1SMENR_DMA2SMEN (1 << 1)OTG_HPRT_PCDET (1 << 1)INT_FAST32_MAX __INT_FAST32_MAX__RCC_CCIPR_SAIxSEL_EXT 3UINTMAX_MAX __UINTMAX_MAX__OTG_DSTS_SUSPSTS (1 << 0)RCC_CCIPR_DFSDMSEL (1 << 31)RCC_APB1SMENR1_OFFSET 0x78OTG_FS_GRXSTSR MMIO32(USB_OTG_FS_BASE + OTG_GRXSTSR)__UINT_LEAST8_MAX__ 0xffOTG_HCTSIZ_DPID_DATA0 (0x0 << 29)__ARM_ARCH_ISA_THUMB 2__UINT32_MAX__ 0xffffffffULOTG_GOTGCTL 0x000RCC_PLLCFGR_PLLN_MASK 0x7fRCC_CCIPR_I2C3SEL_SHIFT 16OTG_GINTSTS_HPRTINT (1 << 24)OTG_GINTSTS_WKUPINT (1 << 31)__GNUC_PATCHLEVEL__ 1RCC_AHB2SMENR_GPIODSMEN (1 << 3)GCC: (15:12.2.rel1-1) 12.2.1 20221205˙˙˙˙| AŽA3aeabi)7E-M M "ń˙ !"## ###&'%#%'#'(*+-/oq13579;=?ACEGIKMOQSUWY[]_acegikms/VŹŔń$V†· č R„ ´âBsĄÖ9jšÎ0aĹöru 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../../cm3../../cm3/../dispatch/../stm32/l4/usr/lib/gcc/arm-none-eabi/12.2.1/include../../../include/libopencm3/cm3../../../include/libopencm3/dispatch../../../include/libopencm3/stm32/l4../../cm3/../dispatchvector.cvector_chipset.cstdint.hvector.hscb.hmemorymap.hcommon.hstdbool.hnvic.hnvic.hnvic.hvector_chipset.cvector_nvic.cvector_nvic.cćë>$# ! 3!4 4z '4 z M E.J'; 1$ 31 $ 2b .-%. .A$.; .;SCB_DCCSW MMIO32(SCB_BASE + 0x26C)SCB_SHPR_PRI_4_MEMMANAGE 0SCB_BASE (SCS_BASE + 0x0D00)__UHA_FBIT__ 8__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64CORESIGHT_LSR_SLK (1<<1)__GCC_ATOMIC_WCHAR_T_LOCK_FREE 2__CHAR_UNSIGNED__ 1pre_mainbus_faultNVIC_DMA2_CHANNEL7_IRQ 69__FLT64_HAS_INFINITY__ 1SCB_AIRCR_PRIGROUP_GROUP4_SUB4 (0x5 << 8)__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GNUC_MINOR__ 2__GCC_DESTRUCTIVE_SIZE 64__LACCUM_EPSILON__ 0x1P-31LK__PTRDIFF_MAX__ 0x7fffffff__ARM_FEATURE_FMA 1NVIC_DMA1_CHANNEL5_IRQ 15__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)__INTMAX_MAX__ 0x7fffffffffffffffLL__TQ_IBIT__ 0__FLT64_DECIMAL_DIG__ 17SCB_CFSR_INVSTATE (1 << 17)WINT_MIN __WINT_MIN__INT_FAST64_MAX__ATOMIC_CONSUME 1__ULACCUM_FBIT__ 32__WCHAR_MAX__ 0xffffffffUSCB_SHCSR_SVCALLPENDED (1 << 15)INT64_MAX __INT64_MAX__INTMAX_MIN__SIZEOF_LONG_LONG__ 8__DBL_MAX_10_EXP__ 308__FRACT_MIN__ (-0.5R-0.5R)__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLK__USACCUM_MAX__ 0XFFFFP-8UHK__SFRACT_FBIT__ 7__INTMAX_WIDTH__ 64__ARM_FEATURE_BF16_SCALAR_ARITHMETIC__SQ_IBIT__ 0__ORDER_PDP_ENDIAN__ 3412__SIZE_TYPE__ unsigned int__FLT_HAS_DENORM__ 1__INT8_TYPE__ signed char__FLT32_MIN__ 1.1754943508222875e-38F32SCB_SCR MMIO32(SCB_BASE + 0x10)__USACCUM_MIN__ 0.0UHKSCB_CCR MMIO32(SCB_BASE + 0x14)SCB_CPACR_NONE 0__DECIMAL_DIG__ 17__LDBL_MIN_EXP__ (-1021)UINTPTR_MAX __UINTPTR_MAX____LDBL_MANT_DIG__ 53__fini_array_endSCB_HFSR_FORCED (1 << 30)NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + ((iser_id) * 4))__UINT8_C(c) c__INT16_TYPE__ short intSCB_AIRCR_VECTRESET (1 << 0)__FLT64_MAX__ 1.7976931348623157e+308F64SCB_SHPR(ipr_id) MMIO8(SCS_BASE + 0xD18 + (ipr_id))UINT_FAST32_MAXLIBOPENCM3_NVIC_H INT_FAST64_MAX __INT_FAST64_MAX____GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1__UINT_LEAST16_MAX__ 0xffff__STDC_HOSTED__ 1__ULLFRACT_FBIT__ 64__SIG_ATOMIC_TYPE__ intSCB_AIRCR_PRIGROUP_GROUP2_SUB8 (0x6 << 8)SCB_CFSR_STKERR (1 << 12)SCB_DCISW MMIO32(SCB_BASE + 0x260)__INT_FAST64_TYPE__ long long int__WINT_TYPE__ unsigned intSCB_CPUID_REVISION_LSB 0INT32_MIN (-INT32_MAX - 1)SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 (0x7 << 8)__FLT32_MAX_10_EXP__ 38vector_table_tNVIC_EXTI4_IRQ 10NVIC_PENDSV_IRQ -2SCB_AIRCR_ENDIANESS (1 << 15)NVIC_PVD_PVM_IRQ 1__USFRACT_MAX__ 0XFFP-8UHR__FP_FAST_FMAF32 1__UINTPTR_MAX__ 0xffffffffU__FLT32_MIN_EXP__ (-125)NVIC_EXTI0_IRQ 6UINT32_MAX __UINT32_MAX__NVIC_TIM8_UP_IRQ 44SCB_SHCSR_BUSFAULTACT (1 << 1)__ULFRACT_FBIT__ 32INT8_MIN (-INT8_MAX - 1)__FLT64_MIN_10_EXP__ (-307)__GNUC_EXECUTION_CHARSET_NAME "UTF-8"BIT10 (1<<10)__INT_FAST64_WIDTH__ 64__STDC_VERSION__ 199901LINT_LEAST64_MAX __INT_LEAST64_MAX__openblt_signature__SFRACT_EPSILON__ 0x1P-7HRSCB_CCR_NONBASETHRDENA (1 << 0)__INT32_C(c) c ## LUINT32_C(c) __UINT32_C(c)__ORDER_BIG_ENDIAN__ 4321SIZE_MAX__SQ_FBIT__ 31DWT_BASE (PPBI_BASE + 0x1000)INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)NVIC_CAN1_RX1_IRQ 21NVIC_DMA2_CHANNEL3_IRQ 58__UHQ_FBIT__ 16NVIC_USART3_IRQ 39NVIC_SDMMC1_IRQ 49__FLT64_MIN_EXP__ (-1021)__PTRDIFF_WIDTH__ 32__UINT_FAST8_MAX__ 0xffffffffUSCB_ID_DFR0 MMIO32(SCB_BASE + 0x48)UINT16_C(c) __UINT16_C(c)__LACCUM_IBIT__ 32SCB_DCIMVAC MMIO32(SCB_BASE + 0x25C)__INT_FAST16_WIDTH__ 32INTMAX_C__VERSION__ "12.2.1 20221205"__VFP_FP__ 1__LLFRACT_MIN__ (-0.5LLR-0.5LLR)INT_FAST8_MAXSCB_SHPR_PRI_9_RESERVED 5__UINT_FAST16_MAX__ 0xffffffffUNVIC_SPI2_IRQ 36__INTPTR_MAX__ 0x7fffffffINT64_C(c) __INT64_C(c)SCB_CTR_DMINLINE_SHIFT 16_edata__GCC_IEC_559_COMPLEX 0__UFRACT_MIN__ 0.0URSCB_DCCMVAU MMIO32(SCB_BASE + 0x264)WCHAR_MAX __WCHAR_MAX____FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX__NVIC_FPU_IRQ 81__UINT_LEAST8_TYPE__ unsigned char__ACCUM_FBIT__ 15SCB_SCR_SLEEPONEXIT (1 << 1)__UACCUM_IBIT__ 16long intUINT8_MAXSCB_MMFAR MMIO32(SCB_BASE + 0x34)SIZE_MAX __SIZE_MAX____INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1NVIC_CAN1_RX0_IRQ 20__FLT32X_EPSILON__ 2.2204460492503131e-16F32x__UINT_FAST64_MAX__ 0xffffffffffffffffULLNVIC_BASE (SCS_BASE + 0x0100)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32__UINTMAX_C(c) c ## ULL__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed charNVIC_MEM_MANAGE_IRQ -12__GCC_ATOMIC_BOOL_LOCK_FREE 2BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON____FLT32_MAX_EXP__ 128SCB_BFAR MMIO32(SCB_BASE + 0x38)main__THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRshort unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)BIT7 (1<<7)BIT17 (1<<17)__FLT32X_MIN_10_EXP__ (-307)UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)__DBL_IS_IEC_60559__ 2__UINT_FAST32_MAX__ 0xffffffffU__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4SCB_SCR_SLEEPDEEP (1 << 2)LIBOPENCM3_VECTOR_H NVIC_DCMI_IRQ 85INTMAX_MAX __INTMAX_MAX____INT_LEAST32_WIDTH__ 32SCB_SHCSR_MEMFAULTENA (1 << 16)SCB_HFSR_VECTTBL (1 << 1)NVIC_EXTI2_IRQ 8NVIC_DFSDM2_IRQ 63GNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -Os -std=c99 -fno-common -ffunction-sections -fdata-sectionsNVIC_USART2_IRQ 38BIT27 (1<<27)NVIC_TIM7_IRQ 55SCB_CPUID_CONSTANT_LSB 16SCB_SHPR_PRI_13_RESERVED 9__UTA_FBIT__ 64INTMAX_C(c) __INTMAX_C(c)__FLT_DECIMAL_DIG__ 9SCB_CPUID_VARIANT (0xF << SCB_CPUID_VARIANT_LSB)__thumb__ 1__INT_LEAST32_MAX__ 0x7fffffffLsigned charINT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)INT32_C(c) __INT32_C(c)__GNUC_STDC_INLINE__ 1__FRACT_FBIT__ 15__LLACCUM_EPSILON__ 0x1P-31LLK__GNUC_PATCHLEVEL__ 1__preinit_array_startPTRDIFF_MINSCB_CPUID_VARIANT_LSB 20__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)SCB_CPACR_CP10 (1 << 20)PPBI_BASE (0xE0000000U)__ARM_ARCH_PROFILE 77NVIC_I2C2_EV_IRQ 33null_handler__FLT64_MAX_10_EXP__ 308MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINSCB_CFSR_MUNSTKERR (1 << 3)SCB_CCSIDR MMIO32(SCB_BASE + 0x80)__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38SCB_ICIALLU MMIO32(SCB_BASE + 0x250)__FRACT_MAX__ 0X7FFFP-15RNVIC_TIM3_IRQ 29SCB_ICSR_PENDSVSET (1 << 28)__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5NVIC_I2C1_EV_IRQ 31SCB_CPACR MMIO32(SCB_BASE + 0x88)NVIC_USAGE_FAULT_IRQ -10NVIC_EXTI3_IRQ 9NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + (ipr_id))NVIC_TIM6_DACUNDER_IRQ 54__UINT16_MAX__ 0xffff__TQ_FBIT__ 127NVIC_WWDG_IRQ 0usage_fault__USQ_FBIT__ 32NVIC_FMC_IRQ 48INT_FAST16_MIN__thumb2__ 1__ULLACCUM_FBIT__ 32SCB_AIRCR_VECTKEY (0x05FA << SCB_AIRCR_VECTKEYSTAT_LSB)SCB_SHCSR MMIO32(SCB_BASE + 0x24)__FLT_DENORM_MIN__ 1.4012984643248171e-45F__STRICT_ANSI__ 1SCB_CFSR_DACCVIOL (1 << 1)UINT_LEAST8_MAXSCB_VTOR_TBLOFF (0x7FFFFF << SCB_VTOR_TBLOFF_LSB)UINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8SCB_ID_ISAR1 MMIO32(SCB_BASE + 0x64)__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__SCB_SHCSR_PENDSVACT (1 << 10)__USA_IBIT__ 16__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1PTRDIFF_MIN (-PTRDIFF_MAX - 1)NVIC_TIM1_UP_TIM16_IRQ 25__UINT_FAST64_TYPE__ long long unsigned int__preinit_array_enddebug_monitorNVIC_RCC_IRQ 5__FLT_MIN__ 1.1754943508222875e-38F__HA_FBIT__ 7__FDPIC__NVIC_CAN1_TX_IRQ 19__FLT32_IS_IEC_60559__ 2NVIC_I2C1_ER_IRQ 32INT_FAST64_MINSCB_CFSR_IACCVIOL (1 << 0)__USFRACT_IBIT__ 0__LDBL_EPSILON__ 2.2204460492503131e-16L__USFRACT_MIN__ 0.0UHRSCB_CFSR_PRECISERR (1 << 9)SCB_SHCSR_BUSFAULTENA (1 << 17)__ARM_NEON__UINT8_MAX__ 0xffSCB_CTR_ERG_MASK 0xfNVIC_CAN2_SCE_IRQ 89__LDBL_MAX_EXP__ 1024SCB_CTR MMIO32(SCB_BASE + 0x7C)SCB_SHCSR_USGFAULTENA (1 << 18)SCB_ICSR_RETOBASE (1 << 11)__DBL_HAS_DENORM__ 1NVIC_OTG_FS_IRQ 67__DA_FBIT__ 31__GXX_ABI_VERSION 1017__INT_LEAST16_MAX__ 0x7fffID_BASE (SCS_BASE + 0x0FD0)NVIC_AES_IRQ 79vector_tableINT_LEAST32_MAX __INT_LEAST32_MAX____ULLACCUM_EPSILON__ 0x1P-32ULLKSCB_SHCSR_MEMFAULTACT (1 << 0)hard_faultINT_LEAST8_MAX __INT_LEAST8_MAX____UINT32_C(c) c ## ULUINTMAX_MAX__UACCUM_MIN__ 0.0UKSCS_BASE (PPBI_BASE + 0xE000)__init_array_startSCB_CCSELR MMIO32(SCB_BASE + 0x84)__SIZEOF_DOUBLE__ 8__ARM_ARCH_ISA_THUMBSCB_ID_AFR0 MMIO32(SCB_BASE + 0x4C)NVIC_I2C3_EV_IRQ 72LIBOPENCM3_CM3_MEMORYMAP_H __GCC_ATOMIC_SHORT_LOCK_FREE 2SCB_FPCAR MMIO32(SCB_BASE + 0x238)__USACCUM_FBIT__ 8__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1NVIC_SAI2_IRQ 75__LACCUM_FBIT__ 31SCB_CPUID_CONSTANT (0xF << SCB_CPUID_CONSTANT_LSB)__FLT32_HAS_QUIET_NAN__ 1__ARM_FEATURE_MATMUL_INT8__LDBL_HAS_INFINITY__ 1__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))__FLT32X_MAX_10_EXP__ 308SCB_SHPR_PRI_5_BUSFAULT 1__ARM_ARCH_EXT_IDIV__ 1../../cm3/vector.cNVIC_I2C2_ER_IRQ 34bool _BoolUINTMAX_MAX __UINTMAX_MAX____SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffSCB_CTR_FORMAT_SHIFT 29BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)SCB_FPCCR MMIO32(SCB_BASE + 0x234)INT16_MAX __INT16_MAX____FP_FAST_FMAF 1__FLT32X_IS_IEC_60559__ 2SCB_AFSR MMIO32(SCB_BASE + 0x3C)NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + ((icer_id) * 4))LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))UINT32_MAXNVIC_LCD_IRQ 78__INT_LEAST16_WIDTH__ 16__DEC_EVAL_METHOD__ 2__ARM_FEATURE_FP16_FMLINT16_MIN (-INT16_MAX - 1)NVIC_DMA2_CHANNEL6_IRQ 68__USFRACT_EPSILON__ 0x1P-8UHRSCB_SCR_SEVONPEND (1 << 4)NVIC_DMA1_CHANNEL2_IRQ 12SCB_ICSR_PENDSTCLR (1 << 25)CORESIGHT_LSR_SLI (1<<0)INT64_MINSCB_MVFR0 MMIO32(SCB_BASE + 0x240)NVIC_LPUART1_IRQ 70__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX____UINT32_MAX__ 0xffffffffULSCB_CCR_UNALIGN_TRP (1 << 3)SCB_CCR_USERSETMPEND (1 << 1)__INT_LEAST8_MAX__ 0x7f__GCC_ATOMIC_POINTER_LOCK_FREE 2__ARM_FEATURE_QBIT 1__ARM_FEATURE_CLZ 1__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXSCB_ICSR_VECTPENDING_LSB 12NVIC_UART4_IRQ 52SCB_ICSR_VECTACTIVE (0x1FF << SCB_ICSR_VECTACTIVE_LSB)__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024__UINT_LEAST32_MAX__ 0xffffffffULNVIC_BUS_FAULT_IRQ -11__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1__ACCUM_MAX__ 0X7FFFFFFFP-15K__INT8_MAX__ 0x7fSCB_AIRCR MMIO32(SCB_BASE + 0x0C)BIT14 (1<<14)__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16__SHRT_WIDTH__ 16BIT20 (1<<20)__ARM_FEATURE_MVE__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intSCB_ID_MMFR0 MMIO32(SCB_BASE + 0x50)UINT_LEAST16_MAX __UINT_LEAST16_MAX__IRQ_HANDLERS [NVIC_WWDG_IRQ] = wwdg_isr, [NVIC_PVD_PVM_IRQ] = pvd_pvm_isr, [NVIC_TAMP_STAMP_IRQ] = tamp_stamp_isr, [NVIC_RTC_WKUP_IRQ] = rtc_wkup_isr, [NVIC_FLASH_IRQ] = flash_isr, [NVIC_RCC_IRQ] = rcc_isr, [NVIC_EXTI0_IRQ] = exti0_isr, [NVIC_EXTI1_IRQ] = exti1_isr, [NVIC_EXTI2_IRQ] = exti2_isr, [NVIC_EXTI3_IRQ] = exti3_isr, [NVIC_EXTI4_IRQ] = exti4_isr, [NVIC_DMA1_CHANNEL1_IRQ] = dma1_channel1_isr, [NVIC_DMA1_CHANNEL2_IRQ] = dma1_channel2_isr, [NVIC_DMA1_CHANNEL3_IRQ] = dma1_channel3_isr, [NVIC_DMA1_CHANNEL4_IRQ] = dma1_channel4_isr, [NVIC_DMA1_CHANNEL5_IRQ] = dma1_channel5_isr, [NVIC_DMA1_CHANNEL6_IRQ] = dma1_channel6_isr, [NVIC_DMA1_CHANNEL7_IRQ] = dma1_channel7_isr, [NVIC_ADC1_2_IRQ] = adc1_2_isr, [NVIC_CAN1_TX_IRQ] = can1_tx_isr, [NVIC_CAN1_RX0_IRQ] = can1_rx0_isr, [NVIC_CAN1_RX1_IRQ] = can1_rx1_isr, [NVIC_CAN1_SCE_IRQ] = can1_sce_isr, [NVIC_EXTI9_5_IRQ] = exti9_5_isr, [NVIC_TIM1_BRK_TIM15_IRQ] = tim1_brk_tim15_isr, [NVIC_TIM1_UP_TIM16_IRQ] = tim1_up_tim16_isr, [NVIC_TIM1_TRG_COM_TIM17_IRQ] = tim1_trg_com_tim17_isr, [NVIC_TIM1_CC_IRQ] = tim1_cc_isr, [NVIC_TIM2_IRQ] = tim2_isr, [NVIC_TIM3_IRQ] = tim3_isr, [NVIC_TIM4_IRQ] = tim4_isr, [NVIC_I2C1_EV_IRQ] = i2c1_ev_isr, [NVIC_I2C1_ER_IRQ] = i2c1_er_isr, [NVIC_I2C2_EV_IRQ] = i2c2_ev_isr, [NVIC_I2C2_ER_IRQ] = i2c2_er_isr, [NVIC_SPI1_IRQ] = spi1_isr, [NVIC_SPI2_IRQ] = spi2_isr, [NVIC_USART1_IRQ] = usart1_isr, [NVIC_USART2_IRQ] = usart2_isr, [NVIC_USART3_IRQ] = usart3_isr, [NVIC_EXTI15_10_IRQ] = exti15_10_isr, [NVIC_RTC_ALARM_IRQ] = rtc_alarm_isr, [NVIC_DFSDM3_IRQ] = dfsdm3_isr, [NVIC_TIM8_BRK_IRQ] = tim8_brk_isr, [NVIC_TIM8_UP_IRQ] = tim8_up_isr, [NVIC_TIM8_TRG_COM_IRQ] = tim8_trg_com_isr, [NVIC_TIM8_CC_IRQ] = tim8_cc_isr, [NVIC_ADC3_IRQ] = adc3_isr, [NVIC_FMC_IRQ] = fmc_isr, [NVIC_SDMMC1_IRQ] = sdmmc1_isr, [NVIC_TIM5_IRQ] = tim5_isr, [NVIC_SPI3_IRQ] = spi3_isr, [NVIC_UART4_IRQ] = uart4_isr, [NVIC_UART5_IRQ] = uart5_isr, [NVIC_TIM6_DACUNDER_IRQ] = tim6_dacunder_isr, [NVIC_TIM7_IRQ] = tim7_isr, [NVIC_DMA2_CHANNEL1_IRQ] = dma2_channel1_isr, [NVIC_DMA2_CHANNEL2_IRQ] = dma2_channel2_isr, [NVIC_DMA2_CHANNEL3_IRQ] = dma2_channel3_isr, [NVIC_DMA2_CHANNEL4_IRQ] = dma2_channel4_isr, [NVIC_DMA2_CHANNEL5_IRQ] = dma2_channel5_isr, [NVIC_DFSDM0_IRQ] = dfsdm0_isr, [NVIC_DFSDM1_IRQ] = dfsdm1_isr, [NVIC_DFSDM2_IRQ] = dfsdm2_isr, [NVIC_COMP_IRQ] = comp_isr, [NVIC_LPTIM1_IRQ] = lptim1_isr, [NVIC_LPTIM2_IRQ] = lptim2_isr, [NVIC_OTG_FS_IRQ] = otg_fs_isr, [NVIC_DMA2_CHANNEL6_IRQ] = dma2_channel6_isr, [NVIC_DMA2_CHANNEL7_IRQ] = dma2_channel7_isr, [NVIC_LPUART1_IRQ] = lpuart1_isr, [NVIC_QUADSPI_IRQ] = quadspi_isr, [NVIC_I2C3_EV_IRQ] = i2c3_ev_isr, [NVIC_I2C3_ER_IRQ] = i2c3_er_isr, [NVIC_SAI1_IRQ] = sai1_isr, [NVIC_SAI2_IRQ] = sai2_isr, [NVIC_SWPMI1_IRQ] = swpmi1_isr, [NVIC_TSC_IRQ] = tsc_isr, [NVIC_LCD_IRQ] = lcd_isr, [NVIC_AES_IRQ] = aes_isr, [NVIC_RNG_IRQ] = rng_isr, [NVIC_FPU_IRQ] = fpu_isr, [NVIC_HASH_CRS_IRQ] = hash_crs_isr, [NVIC_I2C4_EV_IRQ] = i2c4_ev_isr, [NVIC_I2C4_ER_IRQ] = i2c4_er_isr, [NVIC_DCMI_IRQ] = dcmi_isr, [NVIC_CAN2_TX_IRQ] = can2_tx_isr, [NVIC_CAN2_RX0_IRQ] = can2_rx0_isr, [NVIC_CAN2_RX1_IRQ] = can2_rx1_isr, [NVIC_CAN2_SCE_IRQ] = can2_sce_isr, [NVIC_DMA2D_IRQ] = dma2d_isrINT_FAST32_MIN__FLT_EVAL_METHOD_TS_18661_3__ 0NVIC_TIM1_CC_IRQ 27__SCHAR_WIDTH__ 8BIT18 (1<<18)UINT_FAST16_MAXSCB_DFSR MMIO32(SCB_BASE + 0x30)__UINT_FAST8_TYPE__ unsigned intNVIC_COMP_IRQ 64__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RBIT24 (1<<24)__UINT_LEAST16_TYPE__ short unsigned int__INT32_MAX__ 0x7fffffffLSCB_CFSR_NOCP (1 << 19)SCB_ICSR_NMIPENDSET (1 << 31)SCB_MVFR1 MMIO32(SCB_BASE + 0x244)BIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_BF16_VECTOR_ARITHMETICSCB_ID_PFR1 MMIO32(SCB_BASE + 0x44)SCB_CPACR_CP11 (1 << 22)__FLT32_MANT_DIG__ 24INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN____USFRACT_FBIT__ 8INT8_MAX __INT8_MAX__BIT28 (1<<28)_ebss__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2SCB_DCCMVAC MMIO32(SCB_BASE + 0x268)__DBL_MAX_EXP__ 1024__ATOMIC_RELEASE 3NVIC_ADC1_2_IRQ 18UINT_FAST8_MAX__FLT_MANT_DIG__ 24__UDQ_IBIT__ 0SCB_AIRCR_VECTKEYSTAT (0xFFFF << SCB_AIRCR_VECTKEYSTAT_LSB)__OPTIMIZE_SIZE__ 1__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UKSCB_CPUID MMIO32(SCB_BASE + 0x00)__FLT64_NORM_MAX__ 1.7976931348623157e+308F64INT64_MIN (-INT64_MAX - 1)SCB_ID_PFR0 MMIO32(SCB_BASE + 0x40)UINTPTR_MAXNVIC_UART5_IRQ 53__LDBL_DENORM_MIN__ 4.9406564584124654e-324L__INT64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_SAT 1__ULLFRACT_IBIT__ 0MMIO16(addr) (*(volatile uint16_t *)(addr))NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + ((icpr_id) * 4))SCB_CTR_FORMAT_MASK 0x7__GNUC__ 12SCB_ID_MMFR3 MMIO32(SCB_BASE + 0x5C)WCHAR_MAX__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0U__UQQ_IBIT__ 0CORESIGHT_LSR_OFFSET 0xfb4__GCC_ATOMIC_LONG_LOCK_FREE 2__ULACCUM_MIN__ 0.0ULKSCB_VTOR_TBLOFF_LSB 9__LDBL_MAX__ 1.7976931348623157e+308L__ARM_ARCH 7memory_manage_fault_stackNVIC_CAN2_RX1_IRQ 88__FLT_RADIX__ 2BIT3 (1<<3)long long intCORESIGHT_LAR_KEY 0xC5ACCE55__FLT_EPSILON__ 1.1920928955078125e-7F__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAX__LDBL_HAS_QUIET_NAN__ 1SCB_CFSR_UNDEFINSTR (1 << 16)__LONG_LONG_WIDTH__ 64BIT6 (1<<6)NVIC_TSC_IRQ 77SCB_CPUID_IMPLEMENTER_LSB 24SCB_ID_ISAR4 MMIO32(SCB_BASE + 0x70)__ARM_FP__HA_IBIT__ 8__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1NVIC_DFSDM1_IRQ 62BIT9 (1<<9)__FLT32X_MIN__ 2.2250738585072014e-308F32xNVIC_QUADSPI_IRQ 71SCB_CCR_DIV_0_TRP (1 << 4)__FLT64_MAX_EXP__ 1024UINT16_MAXNVIC_SAI1_IRQ 74__FLT64_MIN__ 2.2250738585072014e-308F64__INTMAX_C(c) c ## LLNVIC_IRQ_COUNT 91__ARM_ARCH_PROFILE__INT64_TYPE__ long long int__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4NVIC_TIM1_TRG_COM_TIM17_IRQ 26__UFRACT_MAX__ 0XFFFFP-16URblocking_handlerFPB_BASE (PPBI_BASE + 0x2000)INT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0STIR_BASE (SCS_BASE + 0x0F00)NVIC_SPI1_IRQ 35__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__SCB_ICSR_PENDSTSET (1 << 26)NVIC_RTC_ALARM_IRQ 41SYS_TICK_BASE (SCS_BASE + 0x0010)SCB_AIRCR_VECTCLRACTIVE (1 << 1)__UFRACT_FBIT__ 16__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)__LDBL_MAX_10_EXP__ 308SCB_CCR_DC (1 << 16)NVIC_LPTIM2_IRQ 66reset__INT_FAST32_TYPE__ intNVIC_USART1_IRQ 37unsigned intSCB_ID_ISAR2 MMIO32(SCB_BASE + 0x68)SCB_DCCIMVAC MMIO32(SCB_BASE + 0x270)__init_array_end__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1NVIC_DMA1_CHANNEL7_IRQ 17__USACCUM_IBIT__ 8ITM_BASE (PPBI_BASE + 0x0000)__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UKSCB_ICSR MMIO32(SCB_BASE + 0x04)__UTA_IBIT__ 64__FLT_EVAL_METHOD__ 0__SCHAR_MAX__ 0x7fINT_LEAST32_MINSCB_DCCISW MMIO32(SCB_BASE + 0x274)SCB_SHPR_PRI_6_USAGEFAULT 2NVIC_LPTIM1_IRQ 65__ARM_FEATURE_LDREX__UQQ_FBIT__ 8INT16_C__ARM_FP16_ARGS__GCC_IEC_559 0INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX____LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4__STDC__ 1NVIC_HASH_CRS_IRQ 82__ARM_FEATURE_IDIV 1__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8)__UINT8_TYPE__ unsigned charSCB_SHCSR_SYSTICKACT (1 << 11)__ARM_FEATURE_COPROC 15UINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"NVIC_TIM5_IRQ 50INT8_MINtrue 1__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)pend_sv__FLT32X_MIN_EXP__ (-1021)INT64_MAXINT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1__GCC_ATOMIC_CHAR_LOCK_FREE 2__LFRACT_EPSILON__ 0x1P-31LRSTM32L4 1__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX__SCB_CFSR_BFARVALID (1 << 15)__FLT32X_NORM_MAX__ 1.7976931348623157e+308F32x__arm__ 1__FLT32_MIN_10_EXP__ (-37)SCB_SHCSR_USGFAULTPENDED (1 << 12)MMIO64(addr) (*(volatile uint64_t *)(addr))NVIC_STIR MMIO32(STIR_BASE)__ARM_FP16_FORMAT_ALTERNATIVE__LDBL_NORM_MAX__ 1.7976931348623157e+308LINTPTR_MIN__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)SCB_AIRCR_SYSRESETREQ (1 << 2)SCB_ICSR_ISRPENDING (1 << 22)SCB_AIRCR_PRIGROUP_SHIFT 8__ARM_FEATURE_QRDMXSCB_SHCSR_USGFAULTACT (1 << 3)__ARM_ARCH_ISA_THUMB 2__LONG_LONG_MAX__ 0x7fffffffffffffffLL__WINT_WIDTH__ 32SCB_ICIMVAU MMIO32(SCB_BASE + 0x258)SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__UINT_LEAST8_MAX __UINT_LEAST8_MAX__BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN__NVIC_DMA1_CHANNEL4_IRQ 14__SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__DBL_MIN_EXP__ (-1021)__LDBL_HAS_DENORM__ 1SCB_ID_MMFR1 MMIO32(SCB_BASE + 0x54)NVIC_RNG_IRQ 80INT_FAST32_MIN (-INT_FAST32_MAX - 1)SCB_AIRCR_PRIGROUP_MASK (0x7 << 8)__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2SCB_CTR_CWG_SHIFT 24NVIC_CAN2_TX_IRQ 86__FLT32_DIG__ 6INT_LEAST16_MAXSCB_ICSR_VECTPENDING (0x1FF << SCB_ICSR_VECTPENDING_LSB)NVIC_DMA1_CHANNEL3_IRQ 13NVIC_I2C4_EV_IRQ 83BIT15 (1<<15)NVIC_SYSTICK_IRQ -1BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1INT32_MAX__ACCUM_MIN__ (-0X1P15K-0X1P15K)__ARM_FEATURE_CRYPTO__INT_LEAST32_TYPE__ long intSCB_CPUID_REVISION (0xF << SCB_CPUID_REVISION_LSB)BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__FRACT_IBIT__ 0SCB_CPACR_PRIV 1UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234NVIC_HARD_FAULT_IRQ -13SCB_CTR_DMINLINE_MASK 0x1f__FLT_NORM_MAX__ 3.4028234663852886e+38FSCB_ICSR_VECTACTIVE_LSB 0long long unsigned int__FLT_MIN_10_EXP__ (-37)BIT31 (1<<31)SCB_SHCSR_MONITORACT (1 << 8)__ULACCUM_IBIT__ 32__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__PTRDIFF_TYPE__ int__APCS_32__ 1__DQ_FBIT__ 63SCB_SHPR_PRI_8_RESERVED 4INT_LEAST64_MAX__SACCUM_IBIT__ 8SCB_CFSR_INVPC (1 << 18)__UHQ_IBIT__ 0INT_LEAST8_MINSCB_FPDSCR MMIO32(SCB_BASE + 0x23C)BIT29 (1<<29)__INT_FAST16_TYPE__ intINT64_C__ULFRACT_MAX__ 0XFFFFFFFFP-32ULRSCB_SHCSR_BUSFAULTPENDED (1 << 14)_data_loadaddr__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned int__FLT32X_DIG__ 15__UTQ_FBIT__ 128LIBOPENCM3_SCB_H NVIC_SWPMI1_IRQ 76SCB_CLIDR MMIO32(SCB_BASE + 0x78)__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffffNVIC_DFSDM3_IRQ 42NVIC_TIM2_IRQ 28PTRDIFF_MAX __PTRDIFF_MAX____SIZEOF_SHORT__ 2__FLT32_DECIMAL_DIG__ 9__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKUINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRSCB_CFSR_IBUSERR (1 << 8)__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intNVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + ((ispr_id) * 4))NVIC_DMA2_CHANNEL5_IRQ 60SCB_BPIALL MMIO32(SCB_BASE + 0x278)WCHAR_MINBEGIN_DECLS NVIC_DMA1_CHANNEL1_IRQ 11__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLKNVIC_DMA2_CHANNEL4_IRQ 59__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__FLT32X_MAX__ 1.7976931348623157e+308F32xSCB_ICSR_ISRPREEMPT (1 << 23)NVIC_ADC3_IRQ 47__ARM_EABI__ 1INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1__ARM_FEATURE_DSP 1destSCB_GET_EXCEPTION_STACK_FRAME(f) do { asm volatile ("mov %[frameptr], sp" : [frameptr]"=r" (f)); } while (0)__QQ_IBIT__ 0SCB_SHPR_PRI_14_PENDSV 10SCB_SHPR_PRI_12_RESERVED 8__LLACCUM_FBIT__ 31_datainitial_sp_value__UINTMAX_TYPE__ long long unsigned int__USQ_IBIT__ 0SCB_CPUID_PARTNO (0xFFF << SCB_CPUID_PARTNO_LSB)__UINT_LEAST32_TYPE__ long unsigned int__ARM_FEATURE_NUMERIC_MAXMIN__INTMAX_TYPE__ long long int__GCC_ATOMIC_INT_LOCK_FREE 2SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8)INTMAX_MAXNVIC_EXTI15_10_IRQ 40__ARM_ARCH_7EM__ 1__ARM_FEATURE_FP16_SCALAR_ARITHMETICNVIC_SV_CALL_IRQ -5__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1NVIC_I2C3_ER_IRQ 73NVIC_TIM8_CC_IRQ 46NVIC_CAN2_RX0_IRQ 87__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_Creserved_x001c__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intNVIC_NMI_IRQ -14UINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRNVIC_TAMP_STAMP_IRQ 2NVIC_I2C4_ER_IRQ 84/build/libopencm3/lib/stm32/l4__SIZEOF_SIZE_T__ 4NVIC_TIM1_BRK_TIM15_IRQ 24__UINT64_TYPE__ long long unsigned int__INT64_C(c) c ## LLSCB_CPUID_IMPLEMENTER (0xFF << SCB_CPUID_IMPLEMENTER_LSB)__LDBL_MIN_10_EXP__ (-307)systickSCB_CTR_CWG_MASK 0xfTPIU_BASE (PPBI_BASE + 0x40000)SCB_CTR_IMINLINE_SHIFT 0__LDBL_MIN__ 2.2250738585072014e-308LSCB_CFSR MMIO32(SCB_BASE + 0x28)__ARM_FEATURE_CDE__ACCUM_IBIT__ 16funcp_tCORESIGHT_LAR_OFFSET 0xfb0SCB_CFSR_IMPRECISERR (1 << 10)SCB_SHPR_PRI_15_SYSTICK 11short intLIBOPENCM3_STM32_L4_NVIC_H SCB_CFSR_UNSTKERR (1 << 11)__UINT16_C(c) c__UDA_IBIT__ 32UINT_LEAST32_MAXBIT2 (1<<2)__ATOMIC_RELAXED 0__ARM_FEATURE_COPROCsv_call__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53NVIC_TIM8_TRG_COM_IRQ 45NVIC_DFSDM0_IRQ 61reserved_x0034BIT5 (1<<5)BIT1 (1<<1)INT8_CINT_LEAST32_MAXSCB_CFSR_MSTKERR (1 << 4)__USES_INITFINI__ 1__DBL_DECIMAL_DIG__ 17BIT8 (1<<8)INT16_C(c) __INT16_C(c)NVIC_DMA2_CHANNEL1_IRQ 56__INT16_MAX__ 0x7fffSCB_SHCSR_MEMFAULTPENDED (1 << 13)__INT_WIDTH__ 32__ARM_FEATURE_SIMD32 1SCB_CCR_BP (1 << 18)__QQ_FBIT__ 7SCB_CCR_IC (1 << 17)__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64__ULLACCUM_IBIT__ 32NVIC_CAN1_SCE_IRQ 22SCB_VTOR MMIO32(SCB_BASE + 0x08)__ULLFRACT_EPSILON__ 0x1P-64ULLRfalse 0__SIZEOF_WINT_T__ 4SCB_CPUID_CONSTANT_ARMV6 (0xC << SCB_CPUID_CONSTANT_LSB)NVIC_TIM8_BRK_IRQ 43__ARM_FEATURE_UNALIGNED 1__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17SCB_HFSR MMIO32(SCB_BASE + 0x2C)__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1SCB_CFSR_DIVBYZERO (1 << 25)__FLT32X_HAS_DENORM__ 1NVIC_SPI3_IRQ 51__ULLACCUM_MIN__ 0.0ULLK__INT_FAST32_WIDTH__ 32__TA_IBIT__ 64NVIC_FLASH_IRQ 4SCB_HFSR_DEBUG_VT (1 << 31)__ARM_ASM_SYNTAX_UNIFIED__ 1__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODDEBUG_MONITOR_IRQ -4SCB_ID_ISAR3 MMIO32(SCB_BASE + 0x6C)NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + ((iabr_id) * 4))__ARM_PCS_VFP 1SCB_CCR_STKALIGN (1 << 9)__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H NVIC_TIM4_IRQ 30INT_LEAST64_MIN__GCC_CONSTRUCTIVE_SIZE 64__LLFRACT_IBIT__ 0SCB_SHPR_PRI_10_RESERVED 6uint32_tBIT12 (1<<12)SCB_CPUID_CONSTANT_ARMV7 (0xF << SCB_CPUID_CONSTANT_LSB)NVIC_RTC_WKUP_IRQ 3MPU_BASE (SCS_BASE + 0x0D90)__SACCUM_EPSILON__ 0x1P-7HK__GCC_ASM_FLAG_OUTPUTS__ 1__ARM_FP 4SCB_CTR_IMINLINE_MASK 0xf__UINT_FAST16_TYPE__ unsigned int__UHA_IBIT__ 8__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULKSCB_CPUID_PARTNO_LSB 4__LDBL_DIG__ 15UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXBIT16 (1<<16)__WINT_MIN__ 0UINT_LEAST16_MIN__FLT64_DIG__ 15__WINT_MAX__ 0xffffffffUBIT22 (1<<22)__INT_LEAST8_WIDTH__ 8__INT_LEAST16_TYPE__ short intNVIC_DMA1_CHANNEL6_IRQ 16__DBL_MAX__ ((double)1.7976931348623157e+308L)INT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1SCB_CFSR_UNALIGNED (1 << 24)UINTMAX_CSCB_SHPR_PRI_7_RESERVED 3INT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1__HQ_FBIT__ 15__bool_true_false_are_defined 1BIT26 (1<<26)__SIZE_MAX__ 0xffffffffUreset_handler__ARM_ARCH__LONG_MAX__ 0x7fffffffLSCB_CPACR_FULL 3SCB_CFSR_MMARVALID (1 << 7)SCB_ID_MMFR2 MMIO32(SCB_BASE + 0x58)SCB_AIRCR_VECTKEYSTAT_LSB 16__ARM_FEATURE_LDREX 7PTRDIFF_MAXSCB_CCR_BFHFNMIGN (1 << 8)__LLFRACT_EPSILON__ 0x1P-63LLRNVIC_DMA2D_IRQ 90__SFRACT_MAX__ 0X7FP-7HR__FLT32X_MANT_DIG__ 53__WCHAR_WIDTH__ 32NVIC_EXTI9_5_IRQ 23WINT_MAX__INT16_C(c) cSCB_ID_ISAR0 MMIO32(SCB_BASE + 0x60)INT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32__ATOMIC_ACQ_REL 4__HQ_IBIT__ 0__DBL_MIN_10_EXP__ (-307)__fini_array_startSCB_CTR_ERG_SHIFT 20SCB_SHCSR_SVCALLACT (1 << 7)SCB_SHPR_PRI_11_SVCALL 7NVIC_DMA2_CHANNEL2_IRQ 57__FLT32_NORM_MAX__ 3.4028234663852886e+38F32UINT64_C(c) __UINT64_C(c)NVIC_EXTI1_IRQ 7__UINTMAX_MAX__ 0xffffffffffffffffULLSCB_ICSR_PENDSVCLR (1 << 27)__DBL_MANT_DIG__ 53__ULFRACT_IBIT__ 0vector_table_entry_tINT_FAST16_MAXITR_BASE (SCS_BASE + 0x0000)__INT_MAX__ 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((ptr)->_new._reent._wcsrtombs_state)__FLT64_MAX_10_EXP__ 308MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MIN__attribute_format_strfmon__(a,b) _BSD_SIZE_T_DEFINED_ __UINT_FAST32_TYPE__ unsigned int___int_size_t_h END_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32x__GNUCLIKE_MATH_BUILTIN_RELOPS __FLT_MAX_10_EXP__ 38__PMT(args) argsSCB_SCR MMIO32(SCB_BASE + 0x10)__FRACT_MAX__ 0X7FFFP-15RINT_LEAST32_MAX __INT_LEAST32_MAX__UINTMAX_C__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5_READ_WRITE_RETURN_TYPE int__DEFINED_size_t BIT8 (1<<8)SCB_CPACR MMIO32(SCB_BASE + 0x88)__need_wint_tBEGIN_DECLS __sym_default(sym,impl,verid) __asm__(".symver " #impl ", " #sym "@@" #verid)__alloc_size2(n,x) __attribute__((__alloc_size__(n, x)))__UINT16_MAX__ 0xffff__TQ_FBIT__ 127scb_set_priority_grouping__LDBL_MAX_EXP__ 1024__POSIX_VISIBLE 0_HAVE_LONG_DOUBLE 1_Alignas(x) __aligned(x)__GNUCLIKE_BUILTIN_CONSTANT_P 1__thumb2__ 1__P(protos) protosSCB_AIRCR_VECTKEY (0x05FA << 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2UINT64_C(c) __UINT64_C(c)INT_FAST64_MINSCB_CFSR_IACCVIOL (1 << 0)__USFRACT_IBIT__ 0__INT32_C(c) c ## L__weak_symbol __attribute__((__weak__))__USFRACT_MIN__ 0.0UHR__used __attribute__((__used__))SCB_SHCSR_BUSFAULTENA (1 << 17)__ARM_NEON_REENT_EMERGENCY(ptr) ((ptr)->_emergency)__UINT8_MAX__ 0xff___int16_t_defined 1UINTMAX_C(c) __UINTMAX_C(c)_REENT _impure_ptr__has_feature(x) 0__SVID_VISIBLE 0__exported __attribute__((__visibility__("default")))__SCCSID(s) struct __hackBIT7 (1<<7)__DBL_HAS_DENORM__ 1SCB_ICSR_PENDSVSET (1 << 28)prigroup_MB_LEN_MAX 1__DA_FBIT__ 31long long intBIT17 (1<<17)__GXX_ABI_VERSION 1017__INT_LEAST16_MAX__ 0x7fff__FLT_DENORM_MIN__ 1.4012984643248171e-45F__ULLACCUM_EPSILON__ 0x1P-32ULLK__requires_shared(...) __lock_annotate(shared_locks_required(__VA_ARGS__))_END_STD_C SCB_SHPR_PRI_14_PENDSV 10_T_SIZE SCB_CPUID_IMPLEMENTER (0xFF << SCB_CPUID_IMPLEMENTER_LSB)__UINT32_C(c) c ## UL__UACCUM_MIN__ 0.0UKUINT32_C(c) __UINT32_C(c)_Null_unspecified __FLT_EPSILON__ 1.1920928955078125e-7F__XSTRING(x) __STRING(x)__restrict restrictSCB_CCSELR MMIO32(SCB_BASE + 0x84)BIT11 (1<<11)__ARM_ARCH_ISA_THUMB__GNUCLIKE_BUILTIN_VARARGS 1__ARM_FEATURE_MATMUL_INT8__UINT8_TYPE__ unsigned char_REENT_SIGNGAM(ptr) ((ptr)->_new._reent._gamma_signgam)LIBOPENCM3_CM3_MEMORYMAP_H __GCC_ATOMIC_SHORT_LOCK_FREE 2SCB_FPCAR MMIO32(SCB_BASE + 0x238)__USACCUM_FBIT__ 8__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1__MISC_VISIBLE 0__LACCUM_FBIT__ 31SCS_BASE (PPBI_BASE + 0xE000)SCB_CPUID_PARTNO (0xFFF << SCB_CPUID_PARTNO_LSB)SCB_CPUID_CONSTANT (0xF << SCB_CPUID_CONSTANT_LSB)__FLT32_HAS_QUIET_NAN__ 1SCB_SCR_SLEEPDEEP (1 << 2)__OBSOLETE_MATH __OBSOLETE_MATH_DEFAULT__LDBL_HAS_INFINITY__ 1SCB_CCR MMIO32(SCB_BASE + 0x14)__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))SCB_AIRCR_SYSRESETREQ (1 << 2)__FLT32X_MAX_10_EXP__ 308SCB_SHPR_PRI_5_BUSFAULT 1__ARM_ARCH_EXT_IDIV__ 1__FLT32X_MIN_EXP__ (-1021)SCB_SHCSR_USGFAULTENA (1 << 18)UINTMAX_MAX __UINTMAX_MAX____SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffBIT13 (1<<13)_BSD_WCHAR_T_ _REENT_TM(ptr) (&(ptr)->_new._reent._localtime_buf)SCB_FPCCR MMIO32(SCB_BASE + 0x234)INT16_MAX __INT16_MAX____FP_FAST_FMAF 1SCB_MVFR1 MMIO32(SCB_BASE + 0x244)__FLT32X_IS_IEC_60559__ 2INT_LEAST64_MAX __INT_LEAST64_MAX__LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))UINT32_MAX_REENT_CHECK_EMERGENCY(ptr) __INT_LEAST16_WIDTH__ 16__DEC_EVAL_METHOD__ 2__ARM_FEATURE_FP16_FMLINT16_MIN (-INT16_MAX - 1)__USFRACT_EPSILON__ 0x1P-8UHRNULL ((void *)0)SCB_SCR_SEVONPEND (1 << 4)_Thread_local __thread__OPTIMIZE_SIZE__ 1___int_least32_t_defined 1__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLKSCB_CTR MMIO32(SCB_BASE + 0x7C)__need_NULLUINT64_C__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX____UINT32_MAX__ 0xffffffffUL_REENT_MBTOWC_STATE(ptr) ((ptr)->_new._reent._mbtowc_state)SCB_CCR_UNALIGN_TRP (1 << 3)_REENT_MBLEN_STATE(ptr) ((ptr)->_new._reent._mblen_state)__trylocks_shared(...) __lock_annotate(shared_trylock_function(__VA_ARGS__))__INT_LEAST8_MAX__ 0x7f__GCC_ATOMIC_POINTER_LOCK_FREE 2__ARM_FEATURE_QBIT 1__ARM_FEATURE_CLZ 1__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEX__locks_shared(...) __lock_annotate(shared_lock_function(__VA_ARGS__))unsigned signedSCB_ICSR_VECTACTIVE (0x1FF << SCB_ICSR_VECTACTIVE_LSB)__UINT64_TYPE__ long long unsigned int__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024SCB_ICSR MMIO32(SCB_BASE + 0x04)BIT21 (1<<21)SCB_CTR_CWG_MASK 0xf__UINT_LEAST32_MAX__ 0xffffffffUL__DBL_EPSILON__ ((double)2.2204460492503131e-16L)__lock_acquire(lock) ((void) 0)__section(x) __attribute__((__section__(x)))__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1__ACCUM_MAX__ 0X7FFFFFFFP-15KSCB_CTR_FORMAT_SHIFT 29__INT8_MAX__ 0x7fSCB_AIRCR MMIO32(SCB_BASE + 0x0C)BIT14 (1<<14)__GCC_HAVE_DWARF2_CFI_ASM 1___int8_t_defined 1__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16__UINT_FAST16_TYPE__ unsigned int__offsetof(type,field) offsetof(type, field)__GCC_IEC_559_COMPLEX 0__ARM_FEATURE_MVE__nonnull_all __attribute__((__nonnull__))__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intRAND_MAX __RAND_MAXSCB_ID_MMFR0 MMIO32(SCB_BASE + 0x50)UINT_LEAST16_MAX __UINT_LEAST16_MAX__INT_FAST32_MIN_T_SIZE_ __FLT_EVAL_METHOD_TS_18661_3__ 0__attribute_malloc__ __lock_init_recursive(lock) ((void) 0)BIT18 (1<<18)UINT_FAST16_MAX__NULLABILITY_PRAGMA_POP SCB_DFSR MMIO32(SCB_BASE + 0x30)__UINT_FAST8_TYPE__ unsigned int__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RBIT24 (1<<24)__INT32_MAX__ 0x7fffffffL__min_size(x) static (x)__GXX_TYPEINFO_EQUALITY_INLINE 0UINTMAX_MAXBIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__null_sentinel __attribute__((__sentinel__))__ARM_FEATURE_BF16_VECTOR_ARITHMETICSCB_ID_PFR1 MMIO32(SCB_BASE + 0x44)__need_NULL SCB_CFSR_BFARVALID (1 << 15)SCB_CPACR_CP11 (1 << 22)__FLT32_MANT_DIG__ 24INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32offsetof(TYPE,MEMBER) __builtin_offsetof (TYPE, MEMBER)__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN____USFRACT_FBIT__ 8__LDBL_EPSILON__ 2.2204460492503131e-16LBIT28 (1<<28)__pure2 __attribute__((__const__))__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2INTMAX_C(c) __INTMAX_C(c)__NULLABILITY_PRAGMA_PUSH __DBL_MAX_EXP__ 1024SCB_VTOR_TBLOFF_LSB 9__ATOMIC_RELEASE 3SCB_SHCSR_MEMFAULTENA (1 << 16)__FLT32X_HAS_DENORM__ 1__FLT_MANT_DIG__ 24_RAND48_SEED_1 (0xabcd)__UDQ_IBIT__ 0SCB_AIRCR_VECTKEYSTAT (0xFFFF << SCB_AIRCR_VECTKEYSTAT_LSB)___int_ptrdiff_t_h __OPTIMIZE__ 1SCB_CTR_ERG_MASK 0xf__UACCUM_MAX__ 0XFFFFFFFFP-16UK__CC_SUPPORTS___FUNC__ 1__FLT64_NORM_MAX__ 1.7976931348623157e+308F64__GNUCLIKE_MATH_BUILTIN_CONSTANTS SCB_ID_PFR0 MMIO32(SCB_BASE + 0x40)UINTPTR_MAX_T_PTRDIFF_ __LDBL_DENORM_MIN__ 4.9406564584124654e-324L__INT64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_SAT 1__ULLFRACT_IBIT__ 0SCB_DCCMVAC MMIO32(SCB_BASE + 0x268)_ANSI_STDDEF_H _REENT_CHECK_SIGNAL_BUF(ptr) MMIO16(addr) (*(volatile uint16_t *)(addr))UINT16_C(c) __UINT16_C(c)_REENT_SMALL_CHECK_INIT(ptr) __GNUC__ 12SCB_ID_MMFR3 MMIO32(SCB_BASE + 0x5C)WCHAR_MAX__LONG_WIDTH__ 32_T_WCHAR_ INT32_MAX __INT32_MAX____UACCUM_FBIT__ 16__warn_references(sym,msg) __asm__(".section .gnu.warning." #sym); __asm__(".asciz \"" msg "\""); __asm__(".previous")__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0U__UQQ_IBIT__ 0CORESIGHT_LSR_OFFSET 0xfb4_NEWLIB_VERSION_H__ 1__GCC_ATOMIC_LONG_LOCK_FREE 2__ULACCUM_MIN__ 0.0ULK_ATEXIT_DYNAMIC_ALLOC 1__need_size_t__LDBL_MAX__ 1.7976931348623157e+308L__ARM_ARCH 7SCB_CCR_NONBASETHRDENA (1 << 0)_SIZE_T_ __FLT_RADIX__ 2BIT3 (1<<3)__lock_acquire_recursive(lock) ((void) 0)_REENT_RAND48_MULT(ptr) ((ptr)->_new._reent._r48._mult)SCB_SHPR_PRI_13_RESERVED 9__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAX__wchar_t__ __LDBL_HAS_QUIET_NAN__ 1SCB_CFSR_UNDEFINSTR (1 << 16)__LONG_LONG_WIDTH__ 64BIT6 (1<<6)__DEFINED_wchar_t SCB_CPUID_IMPLEMENTER_LSB 24__UINT_FAST64_MAX__ 0xffffffffffffffffULLSCB_ID_DFR0 MMIO32(SCB_BASE + 0x48)__ARM_FPSCB_ICSR_PENDSTCLR (1 << 25)_REENT_CHECK_ASCTIME_BUF(ptr) __INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1BIT9 (1<<9)__FLT32X_MIN__ 2.2250738585072014e-308F32xINT_FAST8_MIN (-INT_FAST8_MAX - 1)__strftimelike(fmtarg,firstvararg) __attribute__((__format__ (__strftime__, fmtarg, firstvararg)))__FLT64_MAX_EXP__ 1024__WCHAR_T BIT20 (1<<20)MB_CUR_MAX __locale_mb_cur_max()__FLT64_MIN__ 2.2250738585072014e-308F64___int32_t_defined 1__INT_WIDTH__ 32_HAVE_CC_INHIBIT_LOOP_TO_LIBCALL 1__FLT_MIN_EXP__ (-125)__ARM_ARCH_PROFILE__INT64_TYPE__ long long intSCB_ICSR_VECTACTIVE_LSB 0__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4_PTRDIFF_T __BSD_VISIBLE 0__predict_false(exp) __builtin_expect((exp), 0)__unused __attribute__((__unused__))_REENT_MBSRTOWCS_STATE(ptr) ((ptr)->_new._reent._mbsrtowcs_state)SCB_ICSR_VECTPENDING_LSB 12SCB_ICIALLU MMIO32(SCB_BASE + 0x250)SCB_CTR_IMINLINE_SHIFT 0__UFRACT_MAX__ 0XFFFFP-16UR___int_least64_t_defined 1_Alignof(x) __alignof(x)FPB_BASE (PPBI_BASE + 0x2000)__THROW SCB_SHCSR_BUSFAULTACT (1 << 1)INT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0_REENT_L64A_BUF(ptr) ((ptr)->_new._reent._l64a_buf)__EXP(x) __ ##x ##____BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX___NOTHROW _ANSIDECL_H_ SYS_TICK_BASE (SCS_BASE + 0x0010)SCB_AIRCR_VECTCLRACTIVE (1 << 1)__SIG_ATOMIC_TYPE__ int__UFRACT_FBIT__ 16__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)__GNUCLIKE_BUILTIN_MEMCPY 1__APCS_32__ 1SCB_CCR_DC (1 << 16)__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)__INT_FAST32_TYPE__ int__ARM_ARCH_PROFILE 77unsigned int_SIZE_T_DEFINED_ SCB_ID_ISAR2 MMIO32(SCB_BASE + 0x68)SCB_DCCIMVAC MMIO32(SCB_BASE + 0x270)__NEWLIB_MINOR__ 3_SIZET_ __FLT64_HAS_QUIET_NAN__ 1__USACCUM_IBIT__ 8__ARM_ARCH_7EM__ 1__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UK_FVWRITE_IN_STREAMIO 1_WCHAR_T_DECLARED INT_LEAST8_MAX __INT_LEAST8_MAX___SYS_REENT_H_ __FLT_EVAL_METHOD__ 0SCB_ICSR_ISRPENDING (1 << 22)__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32SCB_SHPR_PRI_6_USAGEFAULT 2_RAND48_MULT_2 (0x0005)__ARM_FEATURE_LDREX_T_PTRDIFF __UQQ_FBIT__ 8INT16_C__ARM_FP16_ARGS__GCC_IEC_559 0__requires_unlocked(...) __lock_annotate(locks_excluded(__VA_ARGS__))INT_LEAST16_MAX __INT_LEAST16_MAX____LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4_PTRDIFF_T_DECLARED ___int_least8_t_defined 1__ARM_FEATURE_IDIV 1__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8)_GCC_WCHAR_T SCB_SHCSR_SYSTICKACT (1 << 11)__unlocks(...) __lock_annotate(unlock_function(__VA_ARGS__))__EXPORT __ARM_FEATURE_COPROC 15__OBSOLETE_MATH_DEFAULT 1_Noreturn __dead2UINT64_MAX __UINT64_MAX__false 0__SHRT_WIDTH__ 16_UNBUF_STREAM_OPT 1__IMPORT true 1_ATEXIT_SIZE 32__USA_FBIT__ 16__volatile volatile_MACHINE__TYPES_H __IEEE_LITTLE_ENDIAN __LDBL_MIN_10_EXP__ (-307)INT64_MAX_WANT_REGISTER_FINI 1__FLT_HAS_QUIET_NAN__ 1__ATFILE_VISIBLE 0__GCC_ATOMIC_CHAR_LOCK_FREE 2__LFRACT_EPSILON__ 0x1P-31LRSTM32L4 1__malloc_like __attribute__((__malloc__))__ARM_SIZEOF_MINIMAL_ENUM 1bool _Bool_POINTER_INT long__FLT32X_NORM_MAX__ 1.7976931348623157e+308F32x__arm__ 1INT_FAST64_MAX__FLT32_MIN_10_EXP__ (-37)SCB_SHCSR_USGFAULTPENDED (1 << 12)__RAND_MAX 0x7fffffff__lock_try_acquire(lock) ((void) 0)__STRING(x) #x_WCHAR_T ../../cm3/scb.cINT8_MAX __INT8_MAX____ARM_FP16_FORMAT_ALTERNATIVE__FBSDID(s) struct __hack__LDBL_NORM_MAX__ 1.7976931348623157e+308LINTPTR_MIN_MACHINE__DEFAULT_TYPES_H __BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)_GCC_PTRDIFF_T __GNUCLIKE_BUILTIN_NEXT_ARG 1__TA_IBIT__ 64SCB_SHCSR_PENDSVACT (1 << 10)__LOCK_INIT(class,lock) static int lock = 0;_SIZE_T _WCHAR_T_H SCB_AIRCR_PRIGROUP_SHIFT 8__ARM_FEATURE_QRDMXSCB_DCCISW MMIO32(SCB_BASE + 0x274)__ARM_ARCH_ISA_THUMB 2__LONG_LONG_MAX__ 0x7fffffffffffffffLL_FSEEK_OPTIMIZATION 1SCB_CFSR_MUNSTKERR (1 << 3)__WINT_WIDTH__ 32SCB_ICIMVAU MMIO32(SCB_BASE + 0x258)__arg_type_tag(arg_kind,arg_idx,type_tag_idx) __USQ_IBIT__ 0_REENT_INIT_PTR(var) { memset((var), 0, sizeof(*(var))); _REENT_INIT_PTR_ZEROED(var); }STIR_BASE (SCS_BASE + 0x0F00)__COPYRIGHT(s) struct __hack__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1_REENT_MBRLEN_STATE(ptr) ((ptr)->_new._reent._mbrlen_state)_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)_STDDEF_H_ INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__DBL_MIN_EXP__ (-1021)__SIZE_T SCB_CPUID MMIO32(SCB_BASE + 0x00)SCB_ID_MMFR1 MMIO32(SCB_BASE + 0x54)INT8_MIN (-INT8_MAX - 1)__printf0like(fmtarg,firstvararg) SCB_AIRCR_PRIGROUP_MASK (0x7 << 8)SCB_CTR_CWG_SHIFT 24__FLT32_DIG__ 6INT_LEAST16_MAX__dead2 __attribute__((__noreturn__))BIT15 (1<<15)__compar_fn_t_defined __EXP___int64_t_defined 1__LDBL_HAS_DENORM__ 1__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1INT32_MAX__BEGIN_DECLS __ACCUM_MIN__ (-0X1P15K-0X1P15K)_REENT_CHECK_MISC(ptr) __GNUC_VA_LIST_COMPATIBILITY 1__ARM_FEATURE_CRYPTO__INT_LEAST32_TYPE__ long intSCB_SHCSR_MEMFAULTPENDED (1 << 13)SCB_CPUID_REVISION (0xF << SCB_CPUID_REVISION_LSB)UINT_LEAST16_MAXBIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__FRACT_IBIT__ 0SCB_CFSR_DACCVIOL (1 << 1)SCB_CPACR_PRIV 1UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2__NEWLIB_PATCHLEVEL__ 0BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234__size_tSCB_CTR_DMINLINE_MASK 0x1f__CC_SUPPORTS_INLINE 1__DOTS , ...long long unsigned int__alloc_size(x) __attribute__((__alloc_size__(x)))BIT31 (1<<31)SCB_SHCSR_MONITORACT (1 << 8)__ULACCUM_IBIT__ 32__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__PTRDIFF_TYPE__ int_SIZE_T_DEFINED __DQ_FBIT__ 63SCB_SHPR_PRI_8_RESERVED 4__GNU_VISIBLE 0INT_LEAST64_MAX__SACCUM_IBIT__ 8SCB_CFSR_INVPC (1 << 18)__PTRDIFF_T __UHQ_IBIT__ 0INT_LEAST8_MIN_REENT_WCTOMB_STATE(ptr) ((ptr)->_new._reent._wctomb_state)SCB_FPDSCR MMIO32(SCB_BASE + 0x23C)BIT29 (1<<29)__INT_FAST16_TYPE__ int__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)__ULFRACT_MAX__ 0XFFFFFFFFP-32ULRSCB_SHCSR_BUSFAULTPENDED (1 << 14)__UINT_LEAST16_TYPE__ short unsigned intUINT16_MAX__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned intSCB_ID_MMFR2 MMIO32(SCB_BASE + 0x58)__FLT32X_DIG__ 15__signed signedSCB_BFAR MMIO32(SCB_BASE + 0x38)__UTQ_FBIT__ 128LIBOPENCM3_SCB_H _REENT_ASCTIME_BUF(ptr) ((ptr)->_new._reent._asctime_buf)SCB_CLIDR MMIO32(SCB_BASE + 0x78)__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffff__have_longlong64 1PTRDIFF_MAX __PTRDIFF_MAX____SIZEOF_SHORT__ 2_REENT_MP_P5S(ptr) ((ptr)->_p5s)INT8_MINUINTPTR_MAX __UINTPTR_MAX___WCHAR_T_DEFINED __ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULK__trylocks_exclusive(...) __lock_annotate(exclusive_trylock_function(__VA_ARGS__))SCB_ICSR_VECTPENDING (0x1FF << SCB_ICSR_VECTPENDING_LSB)UINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRSCB_CFSR_IBUSERR (1 << 8)BIT26 (1<<26)__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long int__always_inline __inline__ __attribute__((__always_inline__))INT32_MIN__containerof(x,s,m) ({ const volatile __typeof(((s *)0)->m) *__x = (x); __DEQUALIFY(s *, (const volatile char *)__x - __offsetof(s, m));})SCB_ID_AFR0 MMIO32(SCB_BASE + 0x4C)SCB_BPIALL MMIO32(SCB_BASE + 0x278)_BSD_SIZE_T_ __HA_IBIT__ 8SCB_CPUID_REVISION_LSB 0__no_lock_analysis __lock_annotate(no_thread_safety_analysis)_WCHAR_T_ _REENT_STDIO_STREAM(var,index) &(var)->__sf[index]_T_WCHAR _BEGIN_STD_C _CLOCKID_T_ unsigned long_REENT_CHECK_TM(ptr) SCB_VTOR MMIO32(SCB_BASE + 0x08)__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__INT_WCHAR_T_H __FLT32X_MAX__ 1.7976931348623157e+308F32xSCB_ICSR_ISRPREEMPT (1 << 23)__ARM_EABI__ 1INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1__ARM_FEATURE_DSP 1SCB_GET_EXCEPTION_STACK_FRAME(f) do { asm volatile ("mov %[frameptr], sp" : [frameptr]"=r" (f)); } while (0)__QQ_IBIT__ 0__ARMEL__ 1SCB_SHPR_PRI_12_RESERVED 8__LLACCUM_FBIT__ 31scb_reset_system__UINTMAX_TYPE__ long long unsigned int__FLT32X_MIN_10_EXP__ (-307)__GNUC_MINOR__ 2__lock_release_recursive(lock) ((void) 0)__UINT_LEAST32_TYPE__ long unsigned int__ARM_FEATURE_NUMERIC_MAXMIN_RAND48_MULT_1 (0xdeec)__INTMAX_TYPE__ long long int__GCC_ATOMIC_INT_LOCK_FREE 2SCB_HFSR_DEBUG_VT (1 << 31)_RAND48_SEED_0 (0x330e)SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8)INTMAX_MAXID_BASE (SCS_BASE + 0x0FD0)__Long long__ARM_FEATURE_FP16_SCALAR_ARITHMETIC__FLT_NORM_MAX__ 3.4028234663852886e+38F_STDLIB_H_ __DBL_HAS_QUIET_NAN__ 1UINT_LEAST32_MAXSCB_CCR_USERSETMPEND (1 << 1)__ptrvalue _NOINLINE_STATIC _NOINLINE staticSCB_SHCSR_USGFAULTACT (1 << 3)__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_C_PTRDIFF_T_ INT64_MINSCB_CFSR_NOCP (1 << 19)__SACCUM_MAX__ 0X7FFFP-7HK_GLOBAL_REENT _global_impure_ptrUINT8_C__UINTPTR_TYPE__ unsigned intUINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULR__RCSID(s) struct __hackWCHAR_MAX __WCHAR_MAX__/build/libopencm3/lib/stm32/l4__SIZEOF_SIZE_T__ 4__lock_close_recursive(lock) ((void) 0)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__GNUCLIKE___OFFSETOF 1__INT64_C(c) c ## LL__GNUCLIKE_CTOR_SECTION_HANDLING 1__lockable __lock_annotate(lockable)__END_DECLS TPIU_BASE (PPBI_BASE + 0x40000)__generic(expr,t,yes,no) __builtin_choose_expr( __builtin_types_compatible_p(__typeof(expr), t), yes, no)__LONG_MAX__ 0x7fffffffLSCB_CFSR MMIO32(SCB_BASE + 0x28)__ARM_FEATURE_CDE__ACCUM_IBIT__ 16unsignedCORESIGHT_LAR_OFFSET 0xfb0SCB_CFSR_IMPRECISERR (1 << 10)__GCC_DESTRUCTIVE_SIZE 64INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)SCB_SHPR_PRI_15_SYSTICK 11short int_STDDEF_H __pt_guarded_by(x) __lock_annotate(pt_guarded_by(x))__guarded_by(x) __lock_annotate(guarded_by(x))__UINT16_C(c) c__FLT64_MIN_EXP__ (-1021)_REENT_INIT_ATEXIT _NULL, _ATEXIT_INIT,__CC_SUPPORTS___INLINE__ 1__UDA_IBIT__ 32__printflike(fmtarg,firstvararg) __attribute__((__format__ (__printf__, fmtarg, firstvararg)))__fastcall __attribute__((__fastcall__))__lock_annotate(x) BIT2 (1<<2)_REENT_SIGNAL_BUF(ptr) ((ptr)->_new._reent._signal_buf)__ATOMIC_RELAXED 0_ATTRIBUTE(attrs) __attribute__ (attrs)__ARM_FEATURE_COPROC__ATTRIBUTE_IMPURE_PTR__ __DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX___RAND48_MULT_0 (0xe66d)CORESIGHT_LSR_SLI (1<<0)BIT5 (1<<5)BIT1 (1<<1)__rangeof(type,start,end) (__offsetof(type, end) - __offsetof(type, start))INT8_CINT_LEAST32_MAXSCB_CFSR_MSTKERR (1 << 4)__USES_INITFINI__ 1__lock_init(lock) ((void) 0)__need_ptrdiff_tINTMAX_MAX __INTMAX_MAX____DBL_DECIMAL_DIG__ 17__have_long32 1_NULL 0__flexarr [0]INT16_C(c) __INT16_C(c)INT32_C(c) __INT32_C(c)__INT16_MAX__ 0x7fff__SYS_CONFIG_H__ __DEVOLATILE(type,var) ((type)(__uintptr_t)(volatile void *)(var))__WCHAR_T__ __SSP_FORTIFY_LEVEL 0__ARM_FEATURE_SIMD32 1__XSI_VISIBLE 0INT_FAST32_MIN (-INT_FAST32_MAX - 1)__QQ_FBIT__ 7SCB_ID_ISAR4 MMIO32(SCB_BASE + 0x70)SCB_CCR_IC (1 << 17)__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64__GNUC_PREREQ__(ma,mi) __GNUC_PREREQ(ma, mi)__UTA_IBIT__ 64__ULLACCUM_IBIT__ 32__ARM_FEATURE_CRC32__strong_reference(sym,aliassym) extern __typeof (sym) aliassym __attribute__ ((__alias__ (#sym)))__ULLFRACT_EPSILON__ 0x1P-64ULLR__unreachable() __builtin_unreachable()__LOCK_INIT_RECURSIVE(class,lock) static int lock = 0;__SIZEOF_WINT_T__ 4SCB_CPUID_CONSTANT_ARMV6 (0xC << SCB_CPUID_CONSTANT_LSB)__ARM_FEATURE_UNALIGNED 1__STDC__ 1__LDBL_DECIMAL_DIG__ 17SCB_CCSIDR MMIO32(SCB_BASE + 0x80)__GNUCLIKE_ASM 3__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1__scanflike(fmtarg,firstvararg) __attribute__((__format__ (__scanf__, fmtarg, firstvararg)))SCB_CFSR_DIVBYZERO (1 << 25)_WIDE_ORIENT 1__ULLACCUM_MIN__ 0.0ULLK_SYS__TYPES_H __INT_FAST32_WIDTH__ 32_SYS_CDEFS_H_ __GNUCLIKE_BUILTIN_VAALIST 1__sym_compat(sym,impl,verid) __asm__(".symver " #impl ", " #sym "@" #verid)SCB_SHCSR_MEMFAULTACT (1 << 0)__ARM_ASM_SYNTAX_UNIFIED__ 1__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPROD_NEWLIB_VERSION "3.3.0"WCHAR_MINSCB_ID_ISAR3 MMIO32(SCB_BASE + 0x6C)__pure __attribute__((__pure__))__ARM_PCS_VFP 1_GCC_SIZE_T SCB_CCR_STKALIGN (1 << 9)__CC_SUPPORTS_WARNING 1__ULLFRACT_MIN__ 0.0ULLRUINT_FAST8_MAX_REENT_CHECK_RAND48(ptr) INT_LEAST64_MIN__lock_release(lock) ((void) 0)__GCC_CONSTRUCTIVE_SIZE 64_BSD_WCHAR_T___LLFRACT_IBIT__ 0__CC_SUPPORTS_VARADIC_XXX 1SCB_SHPR_PRI_10_RESERVED 6uint32_tBIT12 (1<<12)SCB_CPUID_CONSTANT_ARMV7 (0xF << SCB_CPUID_CONSTANT_LSB)SCB_ICSR_RETOBASE (1 << 11)MPU_BASE (SCS_BASE + 0x0D90)__SACCUM_EPSILON__ 0x1P-7HK__GCC_ASM_FLAG_OUTPUTS__ 1_REENT_CHECK_VERIFY 1__ARM_FP 4SCB_CTR_IMINLINE_MASK 0xf_REENT_RAND_NEXT(ptr) ((ptr)->_new._reent._rand_next)__UHA_IBIT__ 8__GNUC_STDC_INLINE__ 1__need_wint_t __ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULKSCB_CPUID_PARTNO_LSB 4__LDBL_DIG__ 15_Atomic(T) struct { T volatile __val; }__SIZE_WIDTH__ 32SIG_ATOMIC_MAXBIT16 (1<<16)__WINT_MIN__ 0UINT_LEAST16_MINSCB_ICSR_PENDSTSET (1 << 26)__FLT64_DIG__ 15__WINT_MAX__ 0xffffffffUBIT22 (1<<22)__INT_LEAST8_WIDTH__ 8__long_double_t long double__INT_LEAST16_TYPE__ short int__DBL_MAX__ ((double)1.7976931348623157e+308L)_REENT_WCRTOMB_STATE(ptr) ((ptr)->_new._reent._wcrtomb_state)short unsigned int__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1SCB_CFSR_UNALIGNED (1 << 24)__thumb__ 1__LDBL_MAX_10_EXP__ 308INT_FAST16_MAX __INT_FAST16_MAX____FLT64_MANT_DIG__ 53__format_arg(fmtarg) __attribute__((__format_arg__ (fmtarg)))__compiler_membar() __asm __volatile(" " : : : "memory")__HQ_FBIT__ 15__bool_true_false_are_defined 1__datatype_type_tag(kind,type) __lock_try_acquire_recursive(lock) ((void) 0)__SIZE_MAX__ 0xffffffffUSCB_AFSR MMIO32(SCB_BASE + 0x3C)__ULLACCUM_FBIT__ 32__ARM_ARCH__DEFINED_ptrdiff_t SCB_CPACR_FULL 3SCB_CFSR_MMARVALID (1 << 7)__nonnull(x) __attribute__((__nonnull__ x))_RAND48_ADD (0x000b)EXIT_FAILURE 1SIG_ATOMIC_MIN __SIG_ATOMIC_MIN____ARM_FEATURE_LDREX 7SCB_AIRCR_ENDIANESS (1 << 15)PTRDIFF_MAXSCB_CCR_BFHFNMIGN (1 << 8)SCB_SHCSR_SVCALLACT (1 << 7)__LLFRACT_EPSILON__ 0x1P-63LLR__SFRACT_MAX__ 0X7FP-7HR__FLT32X_MANT_DIG__ 53__WCHAR_WIDTH__ 32WINT_MAX__INT16_C(c) cSCB_ID_ISAR0 MMIO32(SCB_BASE + 0x60)INT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32_REENT_GETDATE_ERR_P(ptr) (&((ptr)->_new._reent._getdate_err))_ATEXIT_INIT {_NULL, 0, {_NULL}, {{_NULL}, {_NULL}, 0, 0}}__DEQUALIFY(type,var) ((type)(__uintptr_t)(const volatile void *)(var))__ATOMIC_ACQ_REL 4__HQ_IBIT__ 0__packed __attribute__((__packed__))_WCHAR_T_DEFINED_ SCB_CTR_ERG_SHIFT 20SCB_SHPR_PRI_4_MEMMANAGE 0__asserts_shared(...) __lock_annotate(assert_shared_lock(__VA_ARGS__))SCB_SHPR_PRI_11_SVCALL 7__SYS_LOCK_H__ SCB_CCR_DIV_0_TRP (1 << 4)__FLT32_NORM_MAX__ 3.4028234663852886e+38F32_REENT_ASCTIME_SIZE 26SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__PTRDIFF_MIN (-PTRDIFF_MAX - 1)__UINTMAX_MAX__ 0xffffffffffffffffULLSCB_ICSR_PENDSVCLR (1 << 27)__DBL_MANT_DIG__ 53__ULFRACT_IBIT__ 0INT_FAST16_MAXITR_BASE (SCS_BASE + 0x0000)__INT_MAX__ 0x7fffffff__INT_LEAST64_TYPE__ long long intSCB_CFSR_PRECISERR (1 << 9)_REENT_INIT(var) { 0, _REENT_STDIO_STREAM(&(var), 0), _REENT_STDIO_STREAM(&(var), 1), _REENT_STDIO_STREAM(&(var), 2), 0, "", 0, _NULL, 0, _NULL, _NULL, 0, _NULL, _NULL, 0, _NULL, { { 0, _NULL, "", {0, 0, 0, 0, 0, 0, 0, 0, 0}, 0, 1, { {_RAND48_SEED_0, _RAND48_SEED_1, _RAND48_SEED_2}, {_RAND48_MULT_0, _RAND48_MULT_1, _RAND48_MULT_2}, _RAND48_ADD }, {0, {0}}, {0, {0}}, {0, {0}}, "", "", 0, {0, {0}}, {0, {0}}, {0, {0}}, {0, {0}}, {0, {0}} } }, _REENT_INIT_ATEXIT _NULL, {_NULL, 0, _NULL} }__ARM_FEATURE_CDE_COPROCUINT32_CGCC: (15:12.2.rel1-1) 12.2.1 20221205˙˙˙˙| A3aeabi)7E-M M "ń˙ "#%')]_+-/13579;=?ACEGIKMOQSUWY[a 4ežĎ4d• Ç ř)[ “Ĺő#S´čJ|`c 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308__ARM_ARCH_ISA_THUMB__ARM_FEATURE_MATMUL_INT8NVIC_I2C3_EV_IRQ 72LIBOPENCM3_CM3_MEMORYMAP_H __GCC_ATOMIC_SHORT_LOCK_FREE 2SCB_FPCAR MMIO32(SCB_BASE + 0x238)__USACCUM_FBIT__ 8__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1NVIC_SAI2_IRQ 75__LACCUM_FBIT__ 31SCS_BASE (PPBI_BASE + 0xE000)__FLT32_MIN__ 1.1754943508222875e-38F32__FLT32_HAS_QUIET_NAN__ 1SCB_SCR_SLEEPDEEP (1 << 2)__LDBL_HAS_INFINITY__ 1__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))SCB_SHPR_PRI_13_RESERVED 9__FLT32X_MAX_10_EXP__ 308SCB_SHPR_PRI_5_BUSFAULT 1__ARM_ARCH_EXT_IDIV__ 1NVIC_I2C2_ER_IRQ 34bool _BoolUINTMAX_MAX __UINTMAX_MAX____SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffSCB_CTR_FORMAT_SHIFT 29BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)SCB_FPCCR MMIO32(SCB_BASE + 0x234)INT16_MAX __INT16_MAX____FP_FAST_FMAF 1__FLT32X_IS_IEC_60559__ 2SCB_AFSR MMIO32(SCB_BASE + 0x3C)LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))UINT32_MAXNVIC_LCD_IRQ 78__INT_LEAST16_WIDTH__ 16NVIC_RCC_IRQ 5__ARM_FEATURE_FP16_FMLINT16_MIN (-INT16_MAX - 1)NVIC_DMA2_CHANNEL6_IRQ 68__USFRACT_EPSILON__ 0x1P-8UHRSCB_SCR_SEVONPEND (1 << 4)NVIC_DMA1_CHANNEL2_IRQ 12__USFRACT_FBIT__ 8CORESIGHT_LSR_SLI (1<<0)NVIC_LPUART1_IRQ 70__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX____UINT32_MAX__ 0xffffffffULSCB_CCR_UNALIGN_TRP (1 << 3)SCB_CCR_USERSETMPEND (1 << 1)__INT_LEAST8_MAX__ 0x7f__GCC_ATOMIC_POINTER_LOCK_FREE 2__ARM_FEATURE_QBIT 1__ARM_FEATURE_CLZ 1__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXSCB_ICSR_VECTPENDING_LSB 12NVIC_HARD_FAULT_IRQ -13__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024__UINT_LEAST32_MAX__ 0xffffffffULNVIC_BUS_FAULT_IRQ -11__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1__ACCUM_MAX__ 0X7FFFFFFFP-15K__INT8_MAX__ 0x7fSCB_AIRCR MMIO32(SCB_BASE + 0x0C)BIT14 (1<<14)__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16__GCC_DESTRUCTIVE_SIZE 64BIT20 (1<<20)__ARM_FEATURE_MVE__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intSCB_ID_MMFR0 MMIO32(SCB_BASE + 0x50)UINT_LEAST16_MAX __UINT_LEAST16_MAX__INT_FAST32_MIN__FLT_EVAL_METHOD_TS_18661_3__ 0NVIC_TIM1_CC_IRQ 27__SCHAR_WIDTH__ 8BIT18 (1<<18)UINT_FAST16_MAXSCB_DFSR MMIO32(SCB_BASE + 0x30)__UINT_FAST8_TYPE__ unsigned intNVIC_COMP_IRQ 64__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RBIT24 (1<<24)__INT32_MAX__ 0x7fffffffLSCB_CFSR_NOCP (1 << 19)SCB_ICSR_NMIPENDSET (1 << 31)UINTMAX_MAXBIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_BF16_VECTOR_ARITHMETICSCB_ID_PFR1 MMIO32(SCB_BASE + 0x44)PPBI_BASE (0xE0000000U)SCB_CPACR_CP11 (1 << 22)__FLT32_MANT_DIG__ 24LIBOPENCM3_NVIC_H __FLT32_DENORM_MIN__ 1.4012984643248171e-45F32__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN__INT8_MAX __INT8_MAX__BIT28 (1<<28)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2SCB_SHCSR_PENDSVACT (1 << 10)SCB_DCCMVAC MMIO32(SCB_BASE + 0x268)__DBL_MAX_EXP__ 1024__ATOMIC_RELEASE 3UINT_FAST8_MAX__FLT_MANT_DIG__ 24__UDQ_IBIT__ 0SCB_AIRCR_VECTKEYSTAT (0xFFFF << SCB_AIRCR_VECTKEYSTAT_LSB)__OPTIMIZE_SIZE__ 1__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UKSCB_CPUID MMIO32(SCB_BASE + 0x00)__FLT64_NORM_MAX__ 1.7976931348623157e+308F64SCB_ID_PFR0 MMIO32(SCB_BASE + 0x40)SCB_ICSR_VECTACTIVE (0x1FF << SCB_ICSR_VECTACTIVE_LSB)UINTPTR_MAXNVIC_UART5_IRQ 53__LDBL_DENORM_MIN__ 4.9406564584124654e-324L__INT64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_SAT 1__ULLFRACT_IBIT__ 0MMIO16(addr) (*(volatile uint16_t *)(addr))NVIC_DMA2_CHANNEL2_IRQ 57SCB_CTR_FORMAT_MASK 0x7__GNUC__ 12SCB_ID_MMFR3 MMIO32(SCB_BASE + 0x5C)WCHAR_MAX__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0U__UQQ_IBIT__ 0CORESIGHT_LSR_OFFSET 0xfb4__GCC_ATOMIC_LONG_LOCK_FREE 2__ULACCUM_MIN__ 0.0ULKSCB_VTOR_TBLOFF_LSB 9__LDBL_MAX__ 1.7976931348623157e+308L__ARM_ARCH 7NVIC_CAN2_RX1_IRQ 88__FLT_RADIX__ 2BIT3 (1<<3)long long intCORESIGHT_LAR_KEY 0xC5ACCE55__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAX__LDBL_HAS_QUIET_NAN__ 1SCB_CFSR_UNDEFINSTR (1 << 16)__LONG_LONG_WIDTH__ 64BIT6 (1<<6)NVIC_TSC_IRQ 77SCB_CPUID_IMPLEMENTER_LSB 24__UINT_FAST64_MAX__ 0xffffffffffffffffULL__ARM_FPSCB_ICSR_PENDSTCLR (1 << 25)__HA_IBIT__ 8__INTPTR_WIDTH__ 32NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + ((icer_id) * 4))NVIC_DFSDM1_IRQ 62BIT9 (1<<9)__FLT32X_MIN__ 2.2250738585072014e-308F32xNVIC_QUADSPI_IRQ 71INTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024UINT16_MAX__FLT64_MIN__ 2.2250738585072014e-308F64__INTMAX_C(c) c ## LLNVIC_IRQ_COUNT 91__ARM_ARCH_PROFILE__INT64_TYPE__ long long intSCB_ICSR_VECTACTIVE_LSB 0__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4SCB_ICIALLU MMIO32(SCB_BASE + 0x250)SCB_CTR_IMINLINE_SHIFT 0__UFRACT_MAX__ 0XFFFFP-16URINT64_MAXFPB_BASE (PPBI_BASE + 0x2000)INT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0STIR_BASE (SCS_BASE + 0x0F00)NVIC_SPI1_IRQ 35__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__SCB_ICSR_PENDSTSET (1 << 26)nvic_get_active_irqNVIC_RTC_ALARM_IRQ 41ID_BASE (SCS_BASE + 0x0FD0)SYS_TICK_BASE (SCS_BASE + 0x0010)SCB_AIRCR_VECTCLRACTIVE (1 << 1)__UFRACT_FBIT__ 16__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)__LDBL_MAX_10_EXP__ 308SCB_CCR_DC (1 << 16)NVIC_LPTIM2_IRQ 66../../cm3/nvic.c__INT_FAST32_TYPE__ intNVIC_USART1_IRQ 37unsigned intSCB_ID_ISAR2 MMIO32(SCB_BASE + 0x68)SCB_DCCIMVAC MMIO32(SCB_BASE + 0x270)__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1NVIC_DMA1_CHANNEL7_IRQ 17__USACCUM_IBIT__ 8ITM_BASE (PPBI_BASE + 0x0000)__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UKSCB_ICSR MMIO32(SCB_BASE + 0x04)__FLT_EVAL_METHOD__ 0SCB_ICSR_ISRPENDING (1 << 22)NVIC_RTC_WKUP_IRQ 3INT_LEAST32_MIN__INT_FAST8_WIDTH__ 32SCB_SHPR_PRI_6_USAGEFAULT 2NVIC_LPTIM1_IRQ 65__ARM_FEATURE_LDREX__UQQ_FBIT__ 8INT16_C__ARM_FP16_ARGS__GCC_IEC_559 0INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX____LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4__STDC__ 1NVIC_HASH_CRS_IRQ 82__ARM_FEATURE_IDIV 1__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8)__UINT8_TYPE__ unsigned charNVIC_TIM2_IRQ 28__ARM_FEATURE_COPROC 15UINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"NVIC_TIM5_IRQ 50INT8_MINnvic_generate_software_interrupttrue 1__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)__LDBL_MIN_10_EXP__ (-307)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1SCB_DCCISW MMIO32(SCB_BASE + 0x274)__GCC_ATOMIC_CHAR_LOCK_FREE 2__LFRACT_EPSILON__ 0x1P-31LRSTM32L4 1__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX__SCB_CFSR_BFARVALID (1 << 15)__FLT32X_NORM_MAX__ 1.7976931348623157e+308F32x__arm__ 1__FLT32_MIN_10_EXP__ (-37)SCB_SHCSR_USGFAULTPENDED (1 << 12)MMIO64(addr) (*(volatile uint64_t *)(addr))__ARM_FP16_FORMAT_ALTERNATIVE__LDBL_NORM_MAX__ 1.7976931348623157e+308LINTPTR_MIN__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)__USACCUM_MIN__ 0.0UHKSCB_AIRCR_SYSRESETREQ (1 << 2)__TA_IBIT__ 64nvic_get_irq_enabledSCB_AIRCR_PRIGROUP_SHIFT 8__ARM_FEATURE_QRDMXSCB_SHCSR_USGFAULTACT (1 << 3)__ARM_ARCH_ISA_THUMB 2__LONG_LONG_MAX__ 0x7fffffffffffffffLL__WINT_WIDTH__ 32SCB_ICIMVAU MMIO32(SCB_BASE + 0x258)SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN__NVIC_DMA1_CHANNEL4_IRQ 14__SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)__DBL_MIN_EXP__ (-1021)__LDBL_HAS_DENORM__ 1SCB_ID_MMFR1 MMIO32(SCB_BASE + 0x54)NVIC_RNG_IRQ 80INT8_MIN (-INT8_MAX - 1)SCB_AIRCR_PRIGROUP_MASK (0x7 << 8)NVIC_CAN1_SCE_IRQ 22NVIC_CAN2_TX_IRQ 86__FLT32_DIG__ 6__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)INT_LEAST16_MAXSCB_ICSR_VECTPENDING (0x1FF << SCB_ICSR_VECTPENDING_LSB)NVIC_I2C4_EV_IRQ 83BIT15 (1<<15)BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1__SACCUM_FBIT__ 7__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1INT32_MAX__ACCUM_MIN__ (-0X1P15K-0X1P15K)__ARM_FEATURE_CRYPTO__INT_LEAST32_TYPE__ long intSCB_CPUID_REVISION (0xF << SCB_CPUID_REVISION_LSB)BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULL__FRACT_IBIT__ 0UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234SCB_CTR_DMINLINE_MASK 0x1f__FLT_NORM_MAX__ 3.4028234663852886e+38FSCB_CPUID_CONSTANT_LSB 16long long unsigned int__FLT_MIN_10_EXP__ (-37)BIT31 (1<<31)SCB_SHCSR_MONITORACT (1 << 8)__ULACCUM_IBIT__ 32__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2__PTRDIFF_TYPE__ int__APCS_32__ 1__DQ_FBIT__ 63SCB_SHPR_PRI_8_RESERVED 4INT_LEAST64_MAX__SACCUM_IBIT__ 8SCB_CTR_CWG_SHIFT 24NVIC_SAI1_IRQ 74__UHQ_IBIT__ 0INT_LEAST8_MINSCB_FPDSCR MMIO32(SCB_BASE + 0x23C)BIT29 (1<<29)__INT_FAST16_TYPE__ intINT64_C__ULFRACT_MAX__ 0XFFFFFFFFP-32ULRSCB_SHCSR_BUSFAULTPENDED (1 << 14)__UINT_LEAST16_TYPE__ short unsigned int__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned int__FLT32X_DIG__ 15SCB_BFAR MMIO32(SCB_BASE + 0x38)__UTQ_FBIT__ 128LIBOPENCM3_SCB_H NVIC_SWPMI1_IRQ 76SCB_CLIDR MMIO32(SCB_BASE + 0x78)__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffffNVIC_DFSDM3_IRQ 42PTRDIFF_MAX __PTRDIFF_MAX____SIZEOF_SHORT__ 2__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKUINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRSCB_CFSR_IBUSERR (1 << 8)__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intNVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + ((ispr_id) * 4))NVIC_DMA2_CHANNEL5_IRQ 60SCB_BPIALL MMIO32(SCB_BASE + 0x278)WCHAR_MINBEGIN_DECLS NVIC_DMA1_CHANNEL1_IRQ 11NVIC_DMA2_CHANNEL4_IRQ 59__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__LLFRACT_EPSILON__ 0x1P-63LLR__FLT32X_MAX__ 1.7976931348623157e+308F32xSCB_ICSR_ISRPREEMPT (1 << 23)NVIC_ADC3_IRQ 47__ARM_EABI__ 1INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1__ARM_FEATURE_DSP 1SCB_GET_EXCEPTION_STACK_FRAME(f) do { asm volatile ("mov %[frameptr], sp" : [frameptr]"=r" (f)); } while (0)__QQ_IBIT__ 0SCB_SHPR_PRI_14_PENDSV 10SCB_SHPR_PRI_12_RESERVED 8__LLACCUM_FBIT__ 31__UINTMAX_TYPE__ long long unsigned int__FLT32X_MIN_10_EXP__ (-307)__USQ_IBIT__ 0SCB_CPUID_PARTNO (0xFFF << SCB_CPUID_PARTNO_LSB)__UINT_LEAST32_TYPE__ long unsigned int__ARM_FEATURE_NUMERIC_MAXMIN__INTMAX_TYPE__ long long intSCB_ICSR_PENDSVSET (1 << 28)__GCC_ATOMIC_INT_LOCK_FREE 2SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8)INTMAX_MAX__ARM_ARCH_7EM__ 1__ARM_FEATURE_FP16_SCALAR_ARITHMETIC__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1NVIC_I2C3_ER_IRQ 73NVIC_CAN2_RX0_IRQ 87__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CINT64_MIN__SACCUM_MAX__ 0X7FFFP-7HKNVIC_WWDG_IRQ 0UINT8_C__UINTPTR_TYPE__ unsigned intNVIC_NMI_IRQ -14UINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRWCHAR_MAX __WCHAR_MAX__/build/libopencm3/lib/stm32/l4__SIZEOF_SIZE_T__ 4NVIC_TIM1_BRK_TIM15_IRQ 24__UINT64_TYPE__ long long unsigned int__INT64_C(c) c ## LLSCB_CPUID_IMPLEMENTER (0xFF << SCB_CPUID_IMPLEMENTER_LSB)SCB_CTR_CWG_MASK 0xfTPIU_BASE (PPBI_BASE + 0x40000)NVIC_DMA2D_IRQ 90__LDBL_MIN__ 2.2250738585072014e-308LSCB_CFSR MMIO32(SCB_BASE + 0x28)__ARM_FEATURE_CDE__ACCUM_IBIT__ 16SCB_CFSR_MSTKERR (1 << 4)CORESIGHT_LAR_OFFSET 0xfb0SCB_CFSR_IMPRECISERR (1 << 10)SCB_SHPR_PRI_15_SYSTICK 11short intLIBOPENCM3_STM32_L4_NVIC_H SCB_CFSR_UNSTKERR (1 << 11)__UINT16_C(c) c__UDA_IBIT__ 32priorityUINT_LEAST32_MAXBIT2 (1<<2)__ATOMIC_RELAXED 0__ARM_FEATURE_COPROCNVIC_UART4_IRQ 52__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53NVIC_TIM8_TRG_COM_IRQ 45NVIC_DFSDM0_IRQ 61BIT5 (1<<5)NVIC_TIM3_IRQ 29BIT1 (1<<1)INT8_CINT_LEAST32_MAXirqn__USES_INITFINI__ 1__DBL_DECIMAL_DIG__ 17BIT8 (1<<8)NVIC_I2C4_ER_IRQ 84INT16_C(c) __INT16_C(c)__INT16_MAX__ 0x7fffSCB_SHCSR_MEMFAULTPENDED (1 << 13)__INT_WIDTH__ 32__ARM_FEATURE_SIMD32 1SCB_CCR_BP (1 << 18)__QQ_FBIT__ 7SCB_ID_ISAR4 MMIO32(SCB_BASE + 0x70)SCB_CCR_IC (1 << 17)__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64__UTA_IBIT__ 64__ULLACCUM_IBIT__ 32SCB_VTOR MMIO32(SCB_BASE + 0x08)__ULLFRACT_EPSILON__ 0x1P-64ULLRfalse 0__SIZEOF_WINT_T__ 4SCB_CPUID_CONSTANT_ARMV6 (0xC << SCB_CPUID_CONSTANT_LSB)NVIC_TIM8_BRK_IRQ 43__ARM_FEATURE_UNALIGNED 1__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17SCB_CCSIDR MMIO32(SCB_BASE + 0x80)SCB_HFSR MMIO32(SCB_BASE + 0x2C)__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1SCB_CFSR_DIVBYZERO (1 << 25)__FLT32X_HAS_DENORM__ 1NVIC_SPI3_IRQ 51__ULLACCUM_MIN__ 0.0ULLK__INT_FAST32_WIDTH__ 32nvic_set_pending_irqNVIC_FLASH_IRQ 4SCB_HFSR_DEBUG_VT (1 << 31)__ARM_ASM_SYNTAX_UNIFIED__ 1__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODDEBUG_MONITOR_IRQ -4SCB_ID_ISAR3 MMIO32(SCB_BASE + 0x6C)NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + ((iabr_id) * 4))__ARM_PCS_VFP 1SCB_CCR_STKALIGN (1 << 9)__SIZEOF_POINTER__ 4__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H NVIC_TIM4_IRQ 30INT_LEAST64_MIN__GCC_CONSTRUCTIVE_SIZE 64SCB_MVFR1 MMIO32(SCB_BASE + 0x244)__LLFRACT_IBIT__ 0SCB_SHPR_PRI_10_RESERVED 6uint32_tnvic_clear_pending_irqBIT12 (1<<12)SCB_CPUID_CONSTANT_ARMV7 (0xF << SCB_CPUID_CONSTANT_LSB)MPU_BASE (SCS_BASE + 0x0D90)__SACCUM_EPSILON__ 0x1P-7HK__GCC_ASM_FLAG_OUTPUTS__ 1__ARM_FP 4SCB_CTR_IMINLINE_MASK 0xf__UINT_FAST16_TYPE__ unsigned int__UHA_IBIT__ 8__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULKSCB_CPUID_PARTNO_LSB 4__LDBL_DIG__ 15UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXBIT16 (1<<16)__WINT_MIN__ 0UINT_LEAST16_MIN__FLT64_DIG__ 15__WINT_MAX__ 0xffffffffUBIT22 (1<<22)__INT_LEAST8_WIDTH__ 8__INT_LEAST16_TYPE__ short intNVIC_DMA1_CHANNEL6_IRQ 16__DBL_MAX__ ((double)1.7976931348623157e+308L)INT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1SCB_CFSR_UNALIGNED (1 << 24)UINTMAX_CSCB_SHPR_PRI_7_RESERVED 3INT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1__HQ_FBIT__ 15__bool_true_false_are_defined 1BIT26 (1<<26)nvic_disable_irq__SIZE_MAX__ 0xffffffffU__ARM_ARCH__LONG_MAX__ 0x7fffffffLSCB_CPACR_NONE 0SCB_CFSR_MMARVALID (1 << 7)SCB_ID_MMFR2 MMIO32(SCB_BASE + 0x58)SCB_AIRCR_VECTKEYSTAT_LSB 16__ARM_FEATURE_LDREX 7PTRDIFF_MAXSCB_CPUID_CONSTANT (0xF << SCB_CPUID_CONSTANT_LSB)NVIC_TIM8_UP_IRQ 44__SFRACT_MAX__ 0X7FP-7HR__FLT32X_MANT_DIG__ 53__WCHAR_WIDTH__ 32NVIC_EXTI9_5_IRQ 23WINT_MAX__INT16_C(c) cSCB_ID_ISAR0 MMIO32(SCB_BASE + 0x60)INT_FAST16_MIN (-INT_FAST16_MAX - 1)__DA_IBIT__ 32SCB_CFSR_DACCVIOL (1 << 1)__ATOMIC_ACQ_REL 4__HQ_IBIT__ 0__DBL_MIN_10_EXP__ (-307)SCB_CTR_ERG_SHIFT 20SCB_SHCSR_SVCALLACT (1 << 7)NVIC_STIR MMIO32(STIR_BASE)SCB_CCR_DIV_0_TRP (1 << 4)__FLT32_NORM_MAX__ 3.4028234663852886e+38F32SCB_SHCSR_SYSTICKACT (1 << 11)UINT64_C(c) __UINT64_C(c)__UINTMAX_MAX__ 0xffffffffffffffffULLSCB_ICSR_PENDSVCLR (1 << 27)__DBL_MANT_DIG__ 53__ULFRACT_IBIT__ 0INT_FAST16_MAXITR_BASE (SCS_BASE + 0x0000)__INT_MAX__ 0x7fffffff__INT_LEAST64_TYPE__ long long intNVIC_TIM8_CC_IRQ 46__ARM_FEATURE_CDE_COPROCUINT32_CGCC: (15:12.2.rel1-1) 12.2.1 20221205˙˙˙˙| A3aeabi)7E-M M "ń˙ 35!#%')+-/175f—Éú.]Ś 69 ş ĘŰ đ 1 C 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