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[ l V   7c   T RG| ../usr/lib/gcc/arm-none-eabi/12.2.1/include../../../include/libopencm3/lpc43xx../../../include/libopencm3/cm3ipc.cstdint.hipc.hcommon.hstdbool.hmemorymap.hcreg.hrgu.h6(../ .#  2'%*.(../z.$  2RESET_CTRL0_ETHERNET_RST (1 << RESET_CTRL0_ETHERNET_RST_SHIFT)RESET_ACTIVE_STATUS1_M0APP_RST (1 << RESET_ACTIVE_STATUS1_M0APP_RST_SHIFT)RESET_EXT_STAT17 MMIO32(RGU_BASE + 0x444)__DECIMAL_DIG__ 17CREG_M0TXEVENT_TXEVCLR_SHIFT (0)__UHA_FBIT__ 8RESET_EXT_STAT14 MMIO32(RGU_BASE + 0x438)RESET_EXT_STAT19 MMIO32(RGU_BASE + 0x44C)RESET_STATUS2 MMIO32(RGU_BASE + 0x118)__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64__WCHAR_MIN__ 0UCREG_DMAMUX_DMAMUXPER12(x) ((x) << CREG_DMAMUX_DMAMUXPER12_SHIFT)__GCC_ATOMIC_WCHAR_T_LOCK_FREE 2__CHAR_UNSIGNED__ 1ETHERNET_BASE (PERIPH_BASE_AHB + 0x10000)RESET_STATUS0_SCU_RST_MASK (0x3 << RESET_STATUS0_SCU_RST_SHIFT)RESET_ACTIVE_STATUS1_CAN0_RST (1 << RESET_ACTIVE_STATUS1_CAN0_RST_SHIFT)RESET_ACTIVE_STATUS0_PERIPH_RST_SHIFT (1)RESET_EXT_STAT25 MMIO32(RGU_BASE + 0x464)CREG_CREG0_USB0PHY (1 << CREG_CREG0_USB0PHY_SHIFT)__FLT64_HAS_INFINITY__ 1RESET_CTRL1_UART0_RST_SHIFT (12)RESET_ACTIVE_STATUS1_SSP1_RST_SHIFT (19)__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GNUC_MINOR__ 2__GCC_DESTRUCTIVE_SIZE 64__LACCUM_EPSILON__ 0x1P-31LK__PTRDIFF_MAX__ 0x7fffffffRESET_ACTIVE_STATUS1_SGPIO_RST (1 << RESET_ACTIVE_STATUS1_SGPIO_RST_SHIFT)__SACCUM_FBIT__ 7__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)RESET_STATUS2_TIMER2_RST(x) ((x) << RESET_STATUS2_TIMER2_RST_SHIFT)__INTMAX_MAX__ 0x7fffffffffffffffLL__TQ_IBIT__ 0CREG_USB1FLADJ_FLTV(x) ((x) << CREG_USB1FLADJ_FLTV_SHIFT)__FLT64_DECIMAL_DIG__ 17RESET_EXT_STAT57 MMIO32(RGU_BASE + 0x4E4)__LDBL_MIN__ 2.2250738585072014e-308LI2C0_BASE (PERIPH_BASE_APB1 + 0x01000)__ATOMIC_CONSUME 1__ULACCUM_FBIT__ 32__WCHAR_MAX__ 0xffffffffUCREG_DMAMUX_DMAMUXPER12_SHIFT (24)RESET_ACTIVE_STATUS0_USB1_RST_SHIFT (18)__ACCUM_MIN__ (-0X1P15K-0X1P15K)OTP_BASE (0x40045000U)RESET_EXT_STAT50_PERIPHERAL_RESET (1 << RESET_EXT_STAT50_PERIPHERAL_RESET_SHIFT)RESET_CTRL0_BUS_RST (1 << RESET_CTRL0_BUS_RST_SHIFT)RESET_EXT_STAT23 MMIO32(RGU_BASE + 0x45C)RESET_STATUS3_SSP1_RST_MASK (0x3 << RESET_STATUS3_SSP1_RST_SHIFT)CREG_CREG6_I2S1_RX_SCK_IN_SEL (1 << CREG_CREG6_I2S1_RX_SCK_IN_SEL_SHIFT)RESET_STATUS0_MASTER_RST_SHIFT (4)CREG_DMAMUX_DMAMUXPER10_SHIFT (20)INT64_MAX __INT64_MAX__INTMAX_MIN__SIZEOF_LONG_LONG__ 8__DBL_MAX_10_EXP__ 308RESET_STATUS3_I2C0_RST(x) ((x) << RESET_STATUS3_I2C0_RST_SHIFT)__FRACT_MIN__ (-0.5R-0.5R)RESET_STATUS3_SPIFI_RST_SHIFT (10)__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLK__USACCUM_MAX__ 0XFFFFP-8UHK__SFRACT_FBIT__ 7__INTMAX_WIDTH__ 64CREG_CREG6_ETHMODE(x) ((x) << CREG_CREG6_ETHMODE_SHIFT)__ARM_FEATURE_BF16_SCALAR_ARITHMETIC__SQ_IBIT__ 0__ORDER_PDP_ENDIAN__ 3412__SIZE_TYPE__ unsigned intCREG_CREG0_BODLVL1(x) ((x) << CREG_CREG0_BODLVL1_SHIFT)C_CCAN1_BASE (PERIPH_BASE_APB1 + 0x04000)__FLT_HAS_DENORM__ 1CREG_CREG0_BODLVL2(x) ((x) << CREG_CREG0_BODLVL2_SHIFT)__SHRT_WIDTH__ 16RESET_ACTIVE_STATUS1_SSP1_RST (1 << RESET_ACTIVE_STATUS1_SSP1_RST_SHIFT)__USACCUM_MIN__ 0.0UHK__FLT32_DECIMAL_DIG__ 9CREG_DMAMUX_DMAMUXPER15_MASK (0x3 << CREG_DMAMUX_DMAMUXPER15_SHIFT)RESET_ACTIVE_STATUS1_RITIMER_RST_SHIFT (4)__LDBL_MIN_EXP__ (-1021)RESET_EXT_STAT46_PERIPHERAL_RESET_SHIFT (2)__LDBL_MANT_DIG__ 53RESET_STATUS2_TIMER3_RST_SHIFT (6)INT64_MIN (-INT64_MAX - 1)RESET_EXT_STAT25_PERIPHERAL_RESET_SHIFT (2)RESET_EXT_STAT52_PERIPHERAL_RESET (1 << RESET_EXT_STAT52_PERIPHERAL_RESET_SHIFT)__UINT8_C(c) c__INT16_TYPE__ short intCREG_FLASHCFGA_POW_SHIFT (31)__FLT64_MAX__ 1.7976931348623157e+308F64RESET_EXT_STAT2 MMIO32(RGU_BASE + 0x408)USB0_BASE (PERIPH_BASE_AHB + 0x06000)RESET_CTRL0_EMC_RST (1 << RESET_CTRL0_EMC_RST_SHIFT)UINT_FAST32_MAXRESET_ACTIVE_STATUS1_TIMER3_RST_SHIFT (3)RESET_EXT_STAT49_PERIPHERAL_RESET (1 << RESET_EXT_STAT49_PERIPHERAL_RESET_SHIFT)RESET_STATUS1_FLASHB_RST(x) ((x) << RESET_STATUS1_FLASHB_RST_SHIFT)RESET_EXT_STAT22 MMIO32(RGU_BASE + 0x458)INT_FAST64_MAX __INT_FAST64_MAX____GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1RESET_ACTIVE_STATUS0_MASTER_RST (1 << RESET_ACTIVE_STATUS0_MASTER_RST_SHIFT)RESET_STATUS2_UART0_RST_MASK (0x3 << RESET_STATUS2_UART0_RST_SHIFT)RESET_ACTIVE_STATUS1_TIMER1_RST (1 << RESET_ACTIVE_STATUS1_TIMER1_RST_SHIFT)__UINT_LEAST16_MAX__ 0xffff__STDC_HOSTED__ 1__ULLFRACT_FBIT__ 64RESET_EXT_STAT22_MASTER_RESET (1 << RESET_EXT_STAT22_MASTER_RESET_SHIFT)__SIG_ATOMIC_TYPE__ intRESET_STATUS1_LCD_RST(x) ((x) << RESET_STATUS1_LCD_RST_SHIFT)RESET_STATUS1_SDIO_RST(x) ((x) << RESET_STATUS1_SDIO_RST_SHIFT)CREG_DMAMUX_DMAMUXPER15_SHIFT (30)__INT_FAST64_TYPE__ long long int__WINT_TYPE__ unsigned intPERIPH_BASE_APB2 (0x400C0000U)INT32_MIN (-INT32_MAX - 1)RESET_EXT_STAT8_PERIPHERAL_RESET_SHIFT (2)__FLT32_MAX_10_EXP__ 38CREG_M4MEMMAP_M4MAP_SHIFT (12)RESET_ACTIVE_STATUS1_CAN0_RST_SHIFT (23)WWDT_BASE (PERIPH_BASE_APB0 + 0x00000)__USFRACT_MAX__ 0XFFP-8UHRRESET_EXT_STAT6 MMIO32(RGU_BASE + 0x418)__FP_FAST_FMAF32 1TIMER1_BASE (PERIPH_BASE_APB0 + 0x05000)RESET_CTRL0_FLASHB_RST_SHIFT (29)RESET_CTRL1_TIMER3_RST_SHIFT (3)__FLT32_MIN_EXP__ (-125)RESET_EXT_STAT37_PERIPHERAL_RESET (1 << RESET_EXT_STAT37_PERIPHERAL_RESET_SHIFT)RESET_CTRL1_I2C0_RST (1 << RESET_CTRL1_I2C0_RST_SHIFT)RESET_CTRL1_DAC_RST_SHIFT (10)RESET_STATUS0_PERIPH_RST(x) ((x) << RESET_STATUS0_PERIPH_RST_SHIFT)ATIMER_BASE (0x40040000U)CREG_CREG0_PD32KHZ (1 << CREG_CREG0_PD32KHZ_SHIFT)CREG_CREG4 MMIO32(CREG_BASE + 0x114)C_CAN0_BASE (PERIPH_BASE_APB3 + 0x02000)__ULFRACT_FBIT__ 32RESET_EXT_STAT45_PERIPHERAL_RESET_SHIFT (2)__FLT64_MIN_10_EXP__ (-307)CREG_ETBCFG MMIO32(CREG_BASE + 0x128)__GNUC_EXECUTION_CHARSET_NAME "UTF-8"BIT10 (1<<10)__INT_FAST64_WIDTH__ 64__STDC_VERSION__ 199901LINT_LEAST64_MAX __INT_LEAST64_MAX__RESET_STATUS0_MASTER_RST(x) ((x) << RESET_STATUS0_MASTER_RST_SHIFT)CREG_M0TXEVENT MMIO32(CREG_BASE + 0x400)RESET_STATUS3_CAN1_RST_SHIFT (12)TIMER0_BASE (PERIPH_BASE_APB0 + 0x04000)__SFRACT_EPSILON__ 0x1P-7HRRESET_STATUS1_LCD_RST_MASK (0x3 << RESET_STATUS1_LCD_RST_SHIFT)RESET_STATUS2_ADC1_RST(x) ((x) << RESET_STATUS2_ADC1_RST_SHIFT)__INT32_C(c) c ## LUINT32_C(c) __UINT32_C(c)__ORDER_BIG_ENDIAN__ 4321SIZE_MAX__SQ_FBIT__ 31RESET_CTRL0_M4_RST_SHIFT (13)RESET_EXT_STAT57_PERIPHERAL_RESET_SHIFT (2)INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)CREG_CREG6_EMC_CLK_SEL (1 << CREG_CREG6_EMC_CLK_SEL_SHIFT)RESET_EXT_STAT25_PERIPHERAL_RESET (1 << RESET_EXT_STAT25_PERIPHERAL_RESET_SHIFT)__UHQ_FBIT__ 16CREG_DMAMUX_DMAMUXPER2_SHIFT (4)RESET_EXT_STAT8 MMIO32(RGU_BASE + 0x420)__FLT64_MIN_EXP__ (-1021)__PTRDIFF_WIDTH__ 32RESET_EXT_STAT20_MASTER_RESET_SHIFT (3)__UINT_FAST8_MAX__ 0xffffffffURESET_EXT_STAT47_PERIPHERAL_RESET (1 << RESET_EXT_STAT47_PERIPHERAL_RESET_SHIFT)UINT16_C(c) __UINT16_C(c)__LACCUM_IBIT__ 32__INT_FAST16_WIDTH__ 32INTMAX_C__VERSION__ "12.2.1 20221205"__VFP_FP__ 1__LLFRACT_MIN__ (-0.5LLR-0.5LLR)INT_FAST8_MAX__UINT_FAST16_MAX__ 0xffffffffU__INTPTR_MAX__ 0x7fffffffINT64_C(c) __INT64_C(c)false 0RESET_STATUS0_CREG_RST(x) ((x) << RESET_STATUS0_CREG_RST_SHIFT)RESET_CTRL1_SGPIO_RST (1 << RESET_CTRL1_SGPIO_RST_SHIFT)__GCC_IEC_559_COMPLEX 0CREG_BASE (0x40043000U)__UFRACT_MIN__ 0.0URCREG_USB1FLADJ_FLTV_MASK (0x3f << CREG_USB1FLADJ_FLTV_SHIFT)CREG_DMAMUX_DMAMUXPER2_MASK (0x3 << CREG_DMAMUX_DMAMUXPER2_SHIFT)WCHAR_MAX __WCHAR_MAX__CREG_DMAMUX_DMAMUXPER6_MASK (0x3 << CREG_DMAMUX_DMAMUXPER6_SHIFT)__FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX__CREG_CREG0_EN1KHZ (1 << CREG_CREG0_EN1KHZ_SHIFT)RESET_CTRL1_TIMER0_RST_SHIFT (0)__UINT_LEAST8_TYPE__ unsigned charRESET_ACTIVE_STATUS0_FLASHB_RST_SHIFT (29)CREG_M4TXEVENT_TXEVCLR_SHIFT (0)__ACCUM_FBIT__ 15CREG_CREG0_ALARMCTRL_SHIFT (6)RESET_ACTIVE_STATUS1_CAN1_RST (1 << RESET_ACTIVE_STATUS1_CAN1_RST_SHIFT)__UACCUM_IBIT__ 16long intUINT8_MAXRESET_ACTIVE_STATUS1_TIMER0_RST (1 << RESET_ACTIVE_STATUS1_TIMER0_RST_SHIFT)SIZE_MAX __SIZE_MAX__CREG_DMAMUX_DMAMUXPER15(x) ((x) << CREG_DMAMUX_DMAMUXPER15_SHIFT)__INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17RESET_EXT_STAT55_PERIPHERAL_RESET (1 << RESET_EXT_STAT55_PERIPHERAL_RESET_SHIFT)__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1RESET_STATUS2_DAC_RST_MASK (0x3 << RESET_STATUS2_DAC_RST_SHIFT)__FLT32X_EPSILON__ 2.2204460492503131e-16F32xRESET_STATUS3_SGPIO_RST_MASK (0x3 << RESET_STATUS3_SGPIO_RST_SHIFT)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32RESET_CTRL1_I2C0_RST_SHIFT (16)CREG_DMAMUX_DMAMUXPER3_SHIFT (6)__UINTMAX_C(c) c ## ULL__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed charRESET_EXT_STAT48_PERIPHERAL_RESET_SHIFT (2)RESET_EXT_STAT53_PERIPHERAL_RESET (1 << RESET_EXT_STAT53_PERIPHERAL_RESET_SHIFT)__GCC_ATOMIC_BOOL_LOCK_FREE 2BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON__RESET_STATUS3_SPI_RST(x) ((x) << RESET_STATUS3_SPI_RST_SHIFT)__FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX__RESET_CTRL0_SDIO_RST_SHIFT (20)__THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRRESET_CTRL1_UART1_RST (1 << RESET_CTRL1_UART1_RST_SHIFT)short unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)RESET_EXT_STAT39 MMIO32(RGU_BASE + 0x49C)BIT7 (1<<7)BIT17 (1<<17)__FLT32X_MIN_10_EXP__ (-307)RESET_STATUS2_ADC1_RST_SHIFT (18)UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)RESET_EXT_STAT59 MMIO32(RGU_BASE + 0x4EC)__DBL_IS_IEC_60559__ 2__UINT_FAST32_MAX__ 0xffffffffU__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4WINT_MIN __WINT_MIN__LCD_BASE (PERIPH_BASE_AHB + 0x08000)RESET_CTRL0_GPIO_RST_SHIFT (28)RESET_ACTIVE_STATUS1_SPIFI_RST (1 << RESET_ACTIVE_STATUS1_SPIFI_RST_SHIFT)__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32RESET_EXT_STAT48 MMIO32(RGU_BASE + 0x4C0)__FLT32X_MIN_EXP__ (-1021)GPDMA_BASE (PERIPH_BASE_AHB + 0x02000)RESET_ACTIVE_STATUS1_DAC_RST (1 << RESET_ACTIVE_STATUS1_DAC_RST_SHIFT)CREG_CREG5_M4TAPSEL (1 << CREG_CREG5_M4TAPSEL_SHIFT)RESET_ACTIVE_STATUS1_QEI_RST_SHIFT (7)RESET_CTRL1_CAN0_RST_SHIFT (23)RESET_STATUS2_UART3_RST(x) ((x) << RESET_STATUS2_UART3_RST_SHIFT)BIT27 (1<<27)CREG_CREG0_ALARMCTRL_MASK (0x3 << CREG_CREG0_ALARMCTRL_SHIFT)RESET_CTRL1_I2C1_RST_SHIFT (17)RESET_ACTIVE_STATUS1_I2C0_RST_SHIFT (16)__UTA_FBIT__ 64SDIO_BASE (PERIPH_BASE_AHB + 0x04000)RESET_CTRL0_BUS_RST_SHIFT (8)__FLT_DECIMAL_DIG__ 9CREG_CREG6_I2S0_TX_SCK_IN_SEL (1 << CREG_CREG6_I2S0_TX_SCK_IN_SEL_SHIFT)__thumb__ 1__INT_LEAST32_MAX__ 0x7fffffffLsigned charGIMA_BASE (PERIPH_BASE_APB2 + 0x07000)CREG_DMAMUX_DMAMUXPER4_SHIFT (8)INT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)INT32_C(c) __INT32_C(c)__GNUC_STDC_INLINE__ 1RESET_CTRL0_FLASHA_RST_SHIFT (25)RESET_STATUS2_UART3_RST_MASK (0x3 << RESET_STATUS2_UART3_RST_SHIFT)RESET_STATUS2_UART3_RST_SHIFT (30)__FRACT_FBIT__ 15__LLACCUM_EPSILON__ 0x1P-31LLKRESET_CTRL0_CREG_RST (1 << RESET_CTRL0_CREG_RST_SHIFT)__GNUC_PATCHLEVEL__ 1__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2PTRDIFF_MIN__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)RESET_EXT_STAT19_MASTER_RESET_SHIFT (3)UINTPTR_MAX __UINTPTR_MAX__CREG_FLASHCFGA MMIO32(CREG_BASE + 0x120)RESET_CTRL0_EMC_RST_SHIFT (21)RESET_CTRL1_TIMER1_RST_SHIFT (1)CREG_CREG6_I2S1_RX_SCK_IN_SEL_SHIFT (15)CREG_CREG0_BODLVL1_MASK (0x3 << CREG_CREG0_BODLVL1_SHIFT)__FLT64_MAX_10_EXP__ 308RESET_STATUS3_I2C0_RST_SHIFT (0)MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINRESET_CTRL0_MASTER_RST_SHIFT (2)__INT_FAST32_WIDTH__ 32CGU_BASE (0x40050000U)__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38RESET_ACTIVE_STATUS1_UART1_RST_SHIFT (13)__FRACT_MAX__ 0X7FFFP-15RCREG_CREG6_ETHMODE_SHIFT (0)GNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -O2 -std=c99 -fno-common -ffunction-sections -fdata-sectionsINT_LEAST32_MAX __INT_LEAST32_MAX__RESET_CTRL1_SSP1_RST (1 << RESET_CTRL1_SSP1_RST_SHIFT)__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5RESET_EXT_STAT35_PERIPHERAL_RESET_SHIFT (2)RESET_STATUS2_TIMER2_RST_MASK (0x3 << RESET_STATUS2_TIMER2_RST_SHIFT)RESET_STATUS1_FLASHA_RST_SHIFT (18)RESET_EXT_STAT36_PERIPHERAL_RESET_SHIFT (2)RESET_CTRL1_QEI_RST_SHIFT (7)CREG_CREG5 MMIO32(CREG_BASE + 0x118)RESET_ACTIVE_STATUS0_FLASHB_RST (1 << RESET_ACTIVE_STATUS0_FLASHB_RST_SHIFT)RESET_EXT_STAT37_PERIPHERAL_RESET_SHIFT (2)RESET_EXT_STAT20 MMIO32(RGU_BASE + 0x450)__UINT16_MAX__ 0xffff__TQ_FBIT__ 127RESET_ACTIVE_STATUS1_UART1_RST (1 << RESET_ACTIVE_STATUS1_UART1_RST_SHIFT)RESET_EXT_STAT41 MMIO32(RGU_BASE + 0x4A4)RESET_STATUS1_USB1_RST_MASK (0x3 << RESET_STATUS1_USB1_RST_SHIFT)__USQ_FBIT__ 32RESET_ACTIVE_STATUS0_SCU_RST_SHIFT (9)INT_FAST16_MINRESET_EXT_STAT29_PERIPHERAL_RESET (1 << RESET_EXT_STAT29_PERIPHERAL_RESET_SHIFT)CREG_DMAMUX_DMAMUXPER8_SHIFT (16)__thumb2__ 1__ULLACCUM_FBIT__ 32RESET_EXT_STAT42 MMIO32(RGU_BASE + 0x4A8)RESET_STATUS2_TIMER3_RST(x) ((x) << RESET_STATUS2_TIMER3_RST_SHIFT)RESET_CTRL0_CREG_RST_SHIFT (5)RESET_EXT_STAT52 MMIO32(RGU_BASE + 0x4D0)INT_FAST32_MIN (-INT_FAST32_MAX - 1)CREG_DMAMUX_DMAMUXPER6_SHIFT (12)__STRICT_ANSI__ 1RESET_STATUS2_UART2_RST(x) ((x) << RESET_STATUS2_UART2_RST_SHIFT)UINT_LEAST8_MAXUINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8RESET_CTRL0_USB1_RST (1 << RESET_CTRL0_USB1_RST_SHIFT)RESET_STATUS0_BUS_RST_SHIFT (16)RESET_STATUS3_SPI_RST_MASK (0x3 << RESET_STATUS3_SPI_RST_SHIFT)__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__RESET_CTRL1_UART3_RST_SHIFT (15)__USA_IBIT__ 16__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1RESET_ACTIVE_STATUS0_FLASHA_RST_SHIFT (25)PTRDIFF_MIN (-PTRDIFF_MAX - 1)RESET_STATUS0_CORE_RST(x) ((x) << RESET_STATUS0_CORE_RST_SHIFT)CREG_DMAMUX_DMAMUXPER14_MASK (0x3 << CREG_DMAMUX_DMAMUXPER14_SHIFT)RESET_STATUS0_CORE_RST_MASK (0x3 << RESET_STATUS0_CORE_RST_SHIFT)__UINT_FAST64_TYPE__ long long unsigned intUINTMAX_MAX __UINTMAX_MAX__RESET_ACTIVE_STATUS0_WWDT_RST_SHIFT (4)RESET_STATUS0_BUS_RST_MASK (0x3 << RESET_STATUS0_BUS_RST_SHIFT)__FLT_MIN__ 1.1754943508222875e-38Fipc_start_m0__HA_FBIT__ 7RESET_CTRL1_SSP1_RST_SHIFT (19)__FDPIC__RESET_ACTIVE_STATUS0_MASTER_RST_SHIFT (2)RESET_STATUS2_MOTOCONPWM_RST_SHIFT (12)__FLT32_IS_IEC_60559__ 2RESET_EXT_STAT34 MMIO32(RGU_BASE + 0x488)RESET_CTRL0_FLASHB_RST (1 << RESET_CTRL0_FLASHB_RST_SHIFT)RESET_CTRL0_CORE_RST_SHIFT (0)INT_FAST64_MINADC0_BASE (PERIPH_BASE_APB3 + 0x03000)__USFRACT_IBIT__ 0RESET_EXT_STAT1_CORE_RESET_SHIFT (1)__LDBL_EPSILON__ 2.2204460492503131e-16LCREG_CREG6_ETHMODE_MASK (0x7 << CREG_CREG6_ETHMODE_SHIFT)__USFRACT_MIN__ 0.0UHRRESET_EXT_STAT0_BOD_RESET (1 << RESET_EXT_STAT0_BOD_RESET_SHIFT)RESET_STATUS1_ETHERNET_RST(x) ((x) << RESET_STATUS1_ETHERNET_RST_SHIFT)__ARM_NEONRESET_EXT_STAT18_MASTER_RESET_SHIFT (3)__UINT8_MAX__ 0xffRESET_EXT_STAT38_PERIPHERAL_RESET (1 << RESET_EXT_STAT38_PERIPHERAL_RESET_SHIFT)__LDBL_MAX_EXP__ 1024RESET_STATUS2_UART0_RST(x) ((x) << RESET_STATUS2_UART0_RST_SHIFT)RESET_ACTIVE_STATUS1_UART3_RST_SHIFT (15)RESET_ACTIVE_STATUS0_SDIO_RST (1 << RESET_ACTIVE_STATUS0_SDIO_RST_SHIFT)RESET_ACTIVE_STATUS1_TIMER2_RST (1 << RESET_ACTIVE_STATUS1_TIMER2_RST_SHIFT)RESET_CTRL1_TIMER0_RST (1 << RESET_CTRL1_TIMER0_RST_SHIFT)CREG_DMAMUX_DMAMUXPER6(x) ((x) << CREG_DMAMUX_DMAMUXPER6_SHIFT)__DBL_HAS_DENORM__ 1CREG_DMAMUX_DMAMUXPER7_SHIFT (14)RESET_CTRL0_MASTER_RST (1 << RESET_CTRL0_MASTER_RST_SHIFT)RESET_EXT_STAT27_PERIPHERAL_RESET_SHIFT (2)CREG_CREG0_EN1KHZ_SHIFT (0)RESET_EXT_STAT51_PERIPHERAL_RESET (1 << RESET_EXT_STAT51_PERIPHERAL_RESET_SHIFT)__DA_FBIT__ 31RESET_ACTIVE_STATUS1_I2C0_RST (1 << RESET_ACTIVE_STATUS1_I2C0_RST_SHIFT)__GXX_ABI_VERSION 1017__INT_LEAST16_MAX__ 0x7fffRESET_CTRL1_UART2_RST_SHIFT (14)RESET_ACTIVE_STATUS0_SCU_RST (1 << RESET_ACTIVE_STATUS0_SCU_RST_SHIFT)__FLT_DENORM_MIN__ 1.4012984643248171e-45FRESET_EXT_STAT4_CORE_RESET (1 << RESET_EXT_STAT4_CORE_RESET_SHIFT)CREG_DMAMUX_DMAMUXPER13(x) ((x) << CREG_DMAMUX_DMAMUXPER13_SHIFT)__ULLACCUM_EPSILON__ 0x1P-32ULLKRESET_ACTIVE_STATUS0_FLASHA_RST (1 << RESET_ACTIVE_STATUS0_FLASHA_RST_SHIFT)RESET_EXT_STAT1 MMIO32(RGU_BASE + 0x404)RESET_EXT_STAT46 MMIO32(RGU_BASE + 0x4B8)INT_LEAST8_MAX __INT_LEAST8_MAX__DAC_BASE (PERIPH_BASE_APB3 + 0x01000)__UINT32_C(c) c ## ULRESET_STATUS2_QEI_RST(x) ((x) << RESET_STATUS2_QEI_RST_SHIFT)RESET_CTRL0_SCU_RST_SHIFT (9)UINTMAX_MAX__UACCUM_MIN__ 0.0UKRESET_ACTIVE_STATUS1_CAN1_RST_SHIFT (22)__FLT_EPSILON__ 1.1920928955078125e-7FCREG_CREG6_I2S1_TX_SCK_IN_SEL_SHIFT (14)CREG_CREG2 MMIO32(CREG_BASE + 0x10C)RESET_EXT_STAT12 MMIO32(RGU_BASE + 0x430)RESET_STATUS2_UART2_RST_MASK (0x3 << RESET_STATUS2_UART2_RST_SHIFT)RESET_EXT_STAT9_PERIPHERAL_RESET_SHIFT (2)__ARM_ARCH_ISA_THUMBRESET_EXT_STAT44_PERIPHERAL_RESET_SHIFT (2)RESET_STATUS1_DMA_RST_SHIFT (6)RESET_ACTIVE_STATUS0_PERIPH_RST (1 << RESET_ACTIVE_STATUS0_PERIPH_RST_SHIFT)__ARM_FEATURE_MATMUL_INT8RESET_STATUS3_CAN0_RST(x) ((x) << RESET_STATUS3_CAN0_RST_SHIFT)__GCC_ATOMIC_SHORT_LOCK_FREE 2RESET_EXT_STAT29_PERIPHERAL_RESET_SHIFT (2)CREG_CREG0_WAKEUP0CTRL_MASK (0x3 << CREG_CREG0_WAKEUP0CTRL_SHIFT)RESET_EXT_STAT1_CORE_RESET (1 << RESET_EXT_STAT1_CORE_RESET_SHIFT)RESET_CTRL0_WWDT_RST_SHIFT (4)__USACCUM_FBIT__ 8RESET_EXT_STAT17_MASTER_RESET (1 << RESET_EXT_STAT17_MASTER_RESET_SHIFT)__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1RESET_STATUS1_USB1_RST(x) ((x) << RESET_STATUS1_USB1_RST_SHIFT)RESET_ACTIVE_STATUS1_I2C1_RST (1 << RESET_ACTIVE_STATUS1_I2C1_RST_SHIFT)__LACCUM_FBIT__ 31RESET_EXT_STAT41_PERIPHERAL_RESET_SHIFT (2)RESET_ACTIVE_STATUS1_SPI_RST_SHIFT (26)EMC_BASE (PERIPH_BASE_AHB + 0x05000)__FLT32_HAS_QUIET_NAN__ 1RESET_ACTIVE_STATUS1_ADC1_RST (1 << RESET_ACTIVE_STATUS1_ADC1_RST_SHIFT)RESET_EXT_STAT0_EXT_RESET (1 << RESET_EXT_STAT0_EXT_RESET_SHIFT)__LDBL_HAS_INFINITY__ 1RESET_STATUS2_MOTOCONPWM_RST(x) ((x) << RESET_STATUS2_MOTOCONPWM_RST_SHIFT)RESET_EXT_STAT7 MMIO32(RGU_BASE + 0x41C)__TA_FBIT__ 63UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))CCU1_BASE (0x40051000U)__FLT32X_MAX_10_EXP__ 308CREG_DMAMUX_DMAMUXPER2(x) ((x) << CREG_DMAMUX_DMAMUXPER2_SHIFT)__ARM_ARCH_EXT_IDIV__ 1RESET_ACTIVE_STATUS0_M4_RST_SHIFT (13)RESET_STATUS2_RITIMER_RST_MASK (0x3 << RESET_STATUS2_RITIMER_RST_SHIFT)bool _BoolRESET_ACTIVE_STATUS0_ETHERNET_RST_SHIFT (22)RESET_EXT_STAT58_PERIPHERAL_RESET (1 << RESET_EXT_STAT58_PERIPHERAL_RESET_SHIFT)CREG_CREG0_WAKEUP1CTRL_SHIFT (16)__SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffRESET_EXT_STAT29 MMIO32(RGU_BASE + 0x474)RESET_ACTIVE_STATUS0_GPIO_RST_SHIFT (28)BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)RESET_ACTIVE_STATUS0_BUS_RST (1 << RESET_ACTIVE_STATUS0_BUS_RST_SHIFT)RESET_EXT_STAT47_PERIPHERAL_RESET_SHIFT (2)INT16_MAX __INT16_MAX__RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_SHIFT (6)__FP_FAST_FMAF 1RESET_CTRL0_LCD_RST (1 << RESET_CTRL0_LCD_RST_SHIFT)CREG_CREG0_SAMPLECTRL_MASK (0x3 << CREG_CREG0_SAMPLECTRL_SHIFT)__FLT32X_IS_IEC_60559__ 2RESET_CTRL1_RTIMER_RST_SHIFT (4)PERIPH_BASE_APB3 (0x400E0000U)RESET_EXT_STAT16_MASTER_RESET (1 << RESET_EXT_STAT16_MASTER_RESET_SHIFT)RESET_CTRL0_M4_RST (1 << RESET_CTRL0_M4_RST_SHIFT)LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))LPC43XX_CREG_H CREG_CREG6_CTOUTCTRL (1 << CREG_CREG6_CTOUTCTRL_SHIFT)RESET_STATUS3_M0APP_RST_MASK (0x3 << RESET_STATUS3_M0APP_RST_SHIFT)__INT_LEAST16_WIDTH__ 16I2S0_BASE (PERIPH_BASE_APB1 + 0x02000)CREG_CREG1 MMIO32(CREG_BASE + 0x108)__DEC_EVAL_METHOD__ 2SCT_BASE (PERIPH_BASE_AHB + 0x00000)__ARM_FEATURE_FP16_FMLRESET_STATUS0_CORE_RST_SHIFT (0)RESET_EXT_STAT30 MMIO32(RGU_BASE + 0x478)INT16_MIN (-INT16_MAX - 1)RESET_STATUS0_WWDT_RST_MASK (0x3 << RESET_STATUS0_WWDT_RST_SHIFT)__USFRACT_EPSILON__ 0x1P-8UHRRESET_EXT_STAT50_PERIPHERAL_RESET_SHIFT (2)RESET_CTRL0_ETHERNET_RST_SHIFT (22)RESET_STATUS3_SSP1_RST(x) ((x) << RESET_STATUS3_SSP1_RST_SHIFT)SCU_BASE (PERIPH_BASE_APB0 + 0x06000)RESET_STATUS2_SCT_RST_SHIFT (10)__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLKRESET_EXT_STAT54 MMIO32(RGU_BASE + 0x4D8)RESET_STATUS3_SPI_RST_SHIFT (20)RESET_EXT_STAT51 MMIO32(RGU_BASE + 0x4CC)__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX__RESET_STATUS2_ADC0_RST_MASK (0x3 << RESET_STATUS2_ADC0_RST_SHIFT)__UINT32_MAX__ 0xffffffffULUSART0_BASE (PERIPH_BASE_APB0 + 0x01000)CREG_DMAMUX_DMAMUXPER9(x) ((x) << CREG_DMAMUX_DMAMUXPER9_SHIFT)RESET_STATUS3_SSP0_RST(x) ((x) << RESET_STATUS3_SSP0_RST_SHIFT)__INT_LEAST8_MAX__ 0x7f__GCC_ATOMIC_POINTER_LOCK_FREE 2__ARM_FEATURE_QBIT 1__ARM_FEATURE_CLZ 1__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXRESET_ACTIVE_STATUS0_CORE_RST (1 << RESET_ACTIVE_STATUS0_CORE_RST_SHIFT)RESET_ACTIVE_STATUS0 MMIO32(RGU_BASE + 0x150)RESET_STATUS1_EMC_RST_MASK (0x3 << RESET_STATUS1_EMC_RST_SHIFT)CREG_DMAMUX_DMAMUXPER1(x) ((x) << CREG_DMAMUX_DMAMUXPER1_SHIFT)__UINT64_TYPE__ long long unsigned int__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024CREG_CREG0_EN32KHZ (1 << CREG_CREG0_EN32KHZ_SHIFT)RESET_STATUS3_CAN1_RST_MASK (0x3 << RESET_STATUS3_CAN1_RST_SHIFT)RESET_STATUS3_SPIFI_RST(x) ((x) << RESET_STATUS3_SPIFI_RST_SHIFT)CREG_FLASHCFGB MMIO32(CREG_BASE + 0x124)__UINT_LEAST32_MAX__ 0xffffffffULRESET_STATUS2_TIMER0_RST_SHIFT (0)__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)__LFRACT_MIN__ (-0.5LR-0.5LR)RESET_EXT_STAT50 MMIO32(RGU_BASE + 0x4C8)RESET_EXT_STAT55 MMIO32(RGU_BASE + 0x4DC)__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1RESET_STATUS1_DMA_RST(x) ((x) << RESET_STATUS1_DMA_RST_SHIFT)__ACCUM_MAX__ 0X7FFFFFFFP-15K__INT8_MAX__ 0x7fBIT14 (1<<14)RESET_STATUS1_USB0_RST(x) ((x) << RESET_STATUS1_USB0_RST_SHIFT)__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16USB1_BASE (PERIPH_BASE_AHB + 0x07000)BIT20 (1<<20)__ARM_FEATURE_MVERESET_EXT_STAT53_PERIPHERAL_RESET_SHIFT (2)RESET_STATUS0_BUS_RST(x) ((x) << RESET_STATUS0_BUS_RST_SHIFT)__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intRESET_EXT_STAT61 MMIO32(RGU_BASE + 0x4F4)RESET_STATUS3_SGPIO_RST_SHIFT (18)RESET_STATUS2_TIMER0_RST(x) ((x) << RESET_STATUS2_TIMER0_RST_SHIFT)UINT_LEAST16_MAX __UINT_LEAST16_MAX__RESET_EXT_STAT55_PERIPHERAL_RESET_SHIFT (2)RESET_CTRL1_MOTOCONPWM_RST_SHIFT (6)INT_FAST32_MINRESET_EXT_STAT33 MMIO32(RGU_BASE + 0x484)__FLT_EVAL_METHOD_TS_18661_3__ 0__SCHAR_WIDTH__ 8CREG_M0TXEVENT_TXEVCLR (1 << CREG_M0TXEVENT_TXEVCLR_SHIFT)BIT18 (1<<18)UINT_FAST16_MAXRESET_EXT_STAT62 MMIO32(RGU_BASE + 0x4F8)__UINT_FAST8_TYPE__ unsigned int__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RBIT24 (1<<24)ipc_halt_m0__INT32_MAX__ 0x7fffffffLRESET_STATUS0_M4_RST_MASK (0x3 << RESET_STATUS0_M4_RST_SHIFT)CREG_M0APPMEMMAP MMIO32(CREG_BASE + 0x404)BIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLLCREG_CREG0_RESET32KHZ (1 << CREG_CREG0_RESET32KHZ_SHIFT)__FLT32_MANT_DIG__ 24INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32EVENTROUTER_BASE (0x40044000U)__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN__CREG_DMAMUX_DMAMUXPER0(x) ((x) << CREG_DMAMUX_DMAMUXPER0_SHIFT)INT8_MAX __INT8_MAX__RESET_ACTIVE_STATUS1_ADC1_RST_SHIFT (9)BIT28 (1<<28)UINT32_MAX __UINT32_MAX____GCC_ATOMIC_CHAR16_T_LOCK_FREE 2INTMAX_C(c) __INTMAX_C(c)RESET_EXT_STAT28 MMIO32(RGU_BASE + 0x470)RESET_ACTIVE_STATUS1_UART0_RST_SHIFT (12)__DBL_MAX_EXP__ 1024RESET_STATUS3_I2C1_RST_SHIFT (2)__ATOMIC_RELEASE 3RESET_CTRL0_SDIO_RST (1 << RESET_CTRL0_SDIO_RST_SHIFT)UINT_FAST8_MAX__FLT_MANT_DIG__ 24RESET_EXT_STAT54_PERIPHERAL_RESET_SHIFT (2)__UDQ_IBIT__ 0RESET_ACTIVE_STATUS0_LCD_RST (1 << RESET_ACTIVE_STATUS0_LCD_RST_SHIFT)RESET_STATUS2_TIMER0_RST_MASK (0x3 << RESET_STATUS2_TIMER0_RST_SHIFT)CCU2_BASE (0x40052000U)CREG_FLASHCFGB_FLASHTIM_MASK (0xf << CREG_FLASHCFGB_FLASHTIM_SHIFT)__OPTIMIZE__ 1__UACCUM_MAX__ 0XFFFFFFFFP-16UKRESET_EXT_STAT0_WWDT_RESET_SHIFT (5)RESET_CTRL0_WWDT_RST (1 << RESET_CTRL0_WWDT_RST_SHIFT)__FLT64_NORM_MAX__ 1.7976931348623157e+308F64PERIPH_BASE_APB1 (0x400A0000U)RESET_STATUS3_I2C0_RST_MASK (0x3 << RESET_STATUS3_I2C0_RST_SHIFT)UINTPTR_MAXRESET_EXT_STAT46_PERIPHERAL_RESET (1 << RESET_EXT_STAT46_PERIPHERAL_RESET_SHIFT)CREG_FLASHCFGA_FLASHTIM_MASK (0xf << CREG_FLASHCFGA_FLASHTIM_SHIFT)__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__LDBL_DENORM_MIN__ 4.9406564584124654e-324LTIMER3_BASE (PERIPH_BASE_APB2 + 0x04000)__INT64_MAX__ 0x7fffffffffffffffLLCREG_DMAMUX_DMAMUXPER3_MASK (0x3 << CREG_DMAMUX_DMAMUXPER3_SHIFT)RESET_STATUS1_FLASHA_RST_MASK (0x3 << RESET_STATUS1_FLASHA_RST_SHIFT)CREG_DMAMUX_DMAMUXPER7_MASK (0x3 << CREG_DMAMUX_DMAMUXPER7_SHIFT)CREG_CREG0_BODLVL1_SHIFT (8)__ULLFRACT_IBIT__ 0RESET_CTRL1_TIMER3_RST (1 << RESET_CTRL1_TIMER3_RST_SHIFT)SPI_PORT_BASE (0x40100000U)MMIO16(addr) (*(volatile uint16_t *)(addr))RESET_CTRL1_SGPIO_RST_SHIFT (25)LPC43XX 1RESET_EXT_STAT42_PERIPHERAL_RESET (1 << RESET_EXT_STAT42_PERIPHERAL_RESET_SHIFT)__GNUC__ 12RESET_STATUS2_RITIMER_RST(x) ((x) << RESET_STATUS2_RITIMER_RST_SHIFT)WCHAR_MAXCREG_FLASHCFGB_POW_SHIFT (31)RESET_STATUS3_I2S_RST_SHIFT (8)__LONG_WIDTH__ 32RESET_CTRL0_USB0_RST (1 << RESET_CTRL0_USB0_RST_SHIFT)__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16RESET_EXT_STAT16 MMIO32(RGU_BASE + 0x440)CREG_CREG0_EN32KHZ_SHIFT (1)__UFRACT_EPSILON__ 0x1P-16URCREG_CREG0 MMIO32(CREG_BASE + 0x004)__UQQ_IBIT__ 0RESET_EXT_STAT56_PERIPHERAL_RESET (1 << RESET_EXT_STAT56_PERIPHERAL_RESET_SHIFT)__GCC_ATOMIC_LONG_LOCK_FREE 2__ULACCUM_MIN__ 0.0ULKCREG_DMAMUX_DMAMUXPER13_MASK (0x3 << CREG_DMAMUX_DMAMUXPER13_SHIFT)RESET_ACTIVE_STATUS0_CREG_RST_SHIFT (5)__LDBL_MAX__ 1.7976931348623157e+308L__ARM_ARCH 7/build/libopencm3/lib/lpc43xx/m4RESET_ACTIVE_STATUS0_LCD_RST_SHIFT (16)__FLT_RADIX__ 2BIT3 (1<<3)long long int__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAXSGPIO_PORT_BASE (0x40101000U)CREG_CREG0_BODLVL2_SHIFT (10)__LDBL_HAS_QUIET_NAN__ 1RESET_ACTIVE_STATUS1_UART3_RST (1 << RESET_ACTIVE_STATUS1_UART3_RST_SHIFT)PERIPH_BASE_APB0 (0x40080000U)__LONG_LONG_WIDTH__ 64BIT6 (1<<6)RESET_ACTIVE_STATUS1_I2C1_RST_SHIFT (17)RESET_STATUS1_FLASHA_RST(x) ((x) << RESET_STATUS1_FLASHA_RST_SHIFT)RESET_CTRL1_M0APP_RST (1 << RESET_CTRL1_M0APP_RST_SHIFT)__UINT_FAST64_MAX__ 0xffffffffffffffffULL__ARM_FP__HA_IBIT__ 8__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1BIT9 (1<<9)RESET_CTRL1_SPIFI_RST (1 << RESET_CTRL1_SPIFI_RST_SHIFT)__FLT32X_MIN__ 2.2250738585072014e-308F32xINTMAX_MAX __INTMAX_MAX____FLT64_MAX_EXP__ 1024RESET_ACTIVE_STATUS0_EEPROM_RST (1 << RESET_ACTIVE_STATUS0_EEPROM_RST_SHIFT)UINT16_MAX__FLT64_MIN__ 2.2250738585072014e-308F64__INTMAX_C(c) c ## LLRESET_ACTIVE_STATUS1_SPIFI_RST_SHIFT (21)CREG_CREG0_SAMPLECTRL_SHIFT (12)RESET_STATUS0_M4_RST_SHIFT (26)__ARM_ARCH_PROFILE__INT64_TYPE__ long long int__LFRACT_FBIT__ 31__CHAR_BIT__ 8RESET_ACTIVE_STATUS1_TIMER3_RST (1 << RESET_ACTIVE_STATUS1_TIMER3_RST_SHIFT)__SIZEOF_WCHAR_T__ 4RESET_STATUS1_ETHERNET_RST_MASK (0x3 << RESET_STATUS1_ETHERNET_RST_SHIFT)RESET_ACTIVE_STATUS1_I2S_RST_SHIFT (20)CREG_DMAMUX_DMAMUXPER13_SHIFT (26)RESET_STATUS0_M4_RST(x) ((x) << RESET_STATUS0_M4_RST_SHIFT)RESET_STATUS0_SCU_RST(x) ((x) << RESET_STATUS0_SCU_RST_SHIFT)RESET_EXT_STAT33_PERIPHERAL_RESET (1 << RESET_EXT_STAT33_PERIPHERAL_RESET_SHIFT)CREG_M4MEMMAP_M4MAP(x) ((x) << CREG_M4MEMMAP_M4MAP_SHIFT)__UFRACT_MAX__ 0XFFFFP-16URRESET_STATUS2_MOTOCONPWM_RST_MASK (0x3 << RESET_STATUS2_MOTOCONPWM_RST_SHIFT)CREG_DMAMUX_DMAMUXPER11_SHIFT (22)INT64_MAXRESET_STATUS2_TIMER1_RST_MASK (0x3 << RESET_STATUS2_TIMER1_RST_SHIFT)RESET_STATUS0_CREG_RST_SHIFT (10)RESET_CTRL1_CAN1_RST_SHIFT (22)RESET_EXT_STAT54_PERIPHERAL_RESET (1 << RESET_EXT_STAT54_PERIPHERAL_RESET_SHIFT)INT_FAST64_MIN (-INT_FAST64_MAX - 1)SSP1_BASE (PERIPH_BASE_APB2 + 0x05000)RESET_EXT_STAT39_PERIPHERAL_RESET (1 << RESET_EXT_STAT39_PERIPHERAL_RESET_SHIFT)RESET_CTRL1_UART2_RST (1 << RESET_CTRL1_UART2_RST_SHIFT)CREG_CREG6_I2S0_RX_SCK_IN_SEL_SHIFT (13)SPIFI_BASE (PERIPH_BASE_AHB + 0x03000)__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN____FLT32_EPSILON__ 1.1920928955078125e-7F32__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__RESET_EXT_STAT27 MMIO32(RGU_BASE + 0x46C)RESET_STATUS3_SGPIO_RST(x) ((x) << RESET_STATUS3_SGPIO_RST_SHIFT)RESET_ACTIVE_STATUS0_M4_RST (1 << RESET_ACTIVE_STATUS0_M4_RST_SHIFT)CREG_CREG0_PD32KHZ_SHIFT (3)RESET_STATUS1_GPIO_RST_MASK (0x3 << RESET_STATUS1_GPIO_RST_SHIFT)CREG_FLASHCFGA_POW (1 << CREG_FLASHCFGA_POW_SHIFT)CREG_FLASHCFGB_POW (1 << CREG_FLASHCFGB_POW_SHIFT)RESET_EXT_STAT32_PERIPHERAL_RESET_SHIFT (2)__UFRACT_FBIT__ 16RESET_EXT_STAT48_PERIPHERAL_RESET (1 << RESET_EXT_STAT48_PERIPHERAL_RESET_SHIFT)__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)RESET_STATUS1_SDIO_RST_MASK (0x3 << RESET_STATUS1_SDIO_RST_SHIFT)__LDBL_MAX_10_EXP__ 308RESET_STATUS2_ADC0_RST(x) ((x) << RESET_STATUS2_ADC0_RST_SHIFT)RESET_EXT_STAT34_PERIPHERAL_RESET_SHIFT (2)RESET_STATUS2_SCT_RST_MASK (0x3 << RESET_STATUS2_SCT_RST_SHIFT)RESET_EXT_STAT13_MASTER_RESET_SHIFT (3)__INT_FAST32_TYPE__ intRESET_STATUS1_LCD_RST_SHIFT (0)RESET_CTRL1_M0APP_RST_SHIFT (24)unsigned intCREG_CREG5_M0APPTAPSEL_SHIFT (9)RESET_EXT_STAT4_CORE_RESET_SHIFT (1)RESET_EXT_STAT17_MASTER_RESET_SHIFT (3)RESET_EXT_STAT53 MMIO32(RGU_BASE + 0x4D4)__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1RESET_STATUS1_EMC_RST(x) ((x) << RESET_STATUS1_EMC_RST_SHIFT)CREG_USB1FLADJ MMIO32(CREG_BASE + 0x600)__USACCUM_IBIT__ 8CREG_FLASHCFGA_FLASHTIM(x) ((x) << CREG_FLASHCFGA_FLASHTIM_SHIFT)__ARM_ARCH_7EM__ 1CREG_FLASHCFGB_FLASHTIM(x) ((x) << CREG_FLASHCFGB_FLASHTIM_SHIFT)__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UKRESET_EXT_STAT58 MMIO32(RGU_BASE + 0x4E8)__FLT_EVAL_METHOD__ 0RESET_ACTIVE_STATUS0_USB0_RST_SHIFT (17)RESET_EXT_STAT34_PERIPHERAL_RESET (1 << RESET_EXT_STAT34_PERIPHERAL_RESET_SHIFT)GPIO_PORT_BASE (0x400F4000U)__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32RESET_EXT_STAT13 MMIO32(RGU_BASE + 0x434)CREG_USB0FLADJ_FLTV_SHIFT (0)__ARM_FEATURE_LDREXRESET_STATUS2_QEI_RST_SHIFT (14)__UQQ_FBIT__ 8RESET_ACTIVE_STATUS1_TIMER2_RST_SHIFT (2)INT16_C__ARM_FP16_ARGS__GCC_IEC_559 0RESET_EXT_STAT40_PERIPHERAL_RESET (1 << RESET_EXT_STAT40_PERIPHERAL_RESET_SHIFT)INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX__RESET_EXT_STAT24 MMIO32(RGU_BASE + 0x460)__LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4RESET_STATUS2_SCT_RST(x) ((x) << RESET_STATUS2_SCT_RST_SHIFT)__STDC__ 1RESET_STATUS3_M0APP_RST(x) ((x) << RESET_STATUS3_M0APP_RST_SHIFT)__ARM_FEATURE_IDIV 1RESET_EXT_STAT45 MMIO32(RGU_BASE + 0x4B4)__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__CREG_USB0FLADJ MMIO32(CREG_BASE + 0x500)__UINT8_TYPE__ unsigned char__ARM_FEATURE_COPROC 15UINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"INT8_MIN__FLT64_IS_IEC_60559__ 2CREG_CREG0_SAMPLECTRL(x) ((x) << CREG_CREG0_SAMPLECTRL_SHIFT)true 1__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)RESET_STATUS2_DAC_RST(x) ((x) << RESET_STATUS2_DAC_RST_SHIFT)RESET_STATUS0_SCU_RST_SHIFT (18)__LDBL_MIN_10_EXP__ (-307)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1CREG_M4TXEVENT_TXEVCLR (1 << CREG_M4TXEVENT_TXEVCLR_SHIFT)__GCC_ATOMIC_CHAR_LOCK_FREE 2CREG_CREG0_WAKEUP1CTRL_MASK (0x3 << CREG_CREG0_WAKEUP1CTRL_SHIFT)RESET_ACTIVE_STATUS1_TIMER0_RST_SHIFT (0)RESET_ACTIVE_STATUS0_USB0_RST (1 << RESET_ACTIVE_STATUS0_USB0_RST_SHIFT)__LFRACT_EPSILON__ 0x1P-31LRRESET_STATUS0_MASTER_RST_MASK (0x3 << RESET_STATUS0_MASTER_RST_SHIFT)RESET_ACTIVE_STATUS1_M0APP_RST_SHIFT (24)RESET_EXT_STAT49 MMIO32(RGU_BASE + 0x4C4)__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX__RESET_CTRL1_UART1_RST_SHIFT (13)__FLT32X_NORM_MAX__ 1.7976931348623157e+308F32xRESET_EXT_STAT32_PERIPHERAL_RESET (1 << RESET_EXT_STAT32_PERIPHERAL_RESET_SHIFT)__arm__ 1INT_FAST64_MAX__INT8_TYPE__ signed char__FLT32_MIN_10_EXP__ (-37)RESET_STATUS2_TIMER2_RST_SHIFT (4)MMIO64(addr) (*(volatile uint64_t *)(addr))__ARM_FEATURE_BF16_VECTOR_ARITHMETIC__ARM_FP16_FORMAT_ALTERNATIVERESET_ACTIVE_STATUS1_UART2_RST (1 << RESET_ACTIVE_STATUS1_UART2_RST_SHIFT)__LDBL_NORM_MAX__ 1.7976931348623157e+308LRESET_CTRL1_ADC1_RST (1 << RESET_CTRL1_ADC1_RST_SHIFT)INTPTR_MINRESET_CTRL1_SSP0_RST_SHIFT (18)__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)RESET_CTRL1_CAN1_RST (1 << RESET_CTRL1_CAN1_RST_SHIFT)RESET_EXT_STAT36_PERIPHERAL_RESET (1 << RESET_EXT_STAT36_PERIPHERAL_RESET_SHIFT)__TA_IBIT__ 64__FLT32_MIN__ 1.1754943508222875e-38F32PERIPH_BASE_AHB (0x40000000U)RESET_STATUS2_TIMER3_RST_MASK (0x3 << RESET_STATUS2_TIMER3_RST_SHIFT)CREG_FLASHCFGA_FLASHTIM_SHIFT (12)CREG_CREG6_I2S0_TX_SCK_IN_SEL_SHIFT (12)__ARM_FEATURE_QRDMXCREG_DMAMUX_DMAMUXPER10(x) ((x) << CREG_DMAMUX_DMAMUXPER10_SHIFT)RESET_CTRL1_UART3_RST (1 << RESET_CTRL1_UART3_RST_SHIFT)RESET_EXT_STAT42_PERIPHERAL_RESET_SHIFT (2)__ARM_ARCH_ISA_THUMB 2__LONG_LONG_MAX__ 0x7fffffffffffffffLLRESET_STATUS2_TIMER1_RST_SHIFT (2)__WINT_WIDTH__ 32SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__RESET_EXT_STAT0_WWDT_RESET (1 << RESET_EXT_STAT0_WWDT_RESET_SHIFT)RESET_STATUS3 MMIO32(RGU_BASE + 0x11C)__USFRACT_FBIT__ 8BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN__RESET_EXT_STAT0_EXT_RESET_SHIFT (0)__SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)CREG_DMAMUX_DMAMUXPER1_MASK (0x3 << CREG_DMAMUX_DMAMUXPER1_SHIFT)__DBL_MIN_EXP__ (-1021)RESET_EXT_STAT52_PERIPHERAL_RESET_SHIFT (2)__LDBL_HAS_DENORM__ 1RESET_EXT_STAT35_PERIPHERAL_RESET (1 << RESET_EXT_STAT35_PERIPHERAL_RESET_SHIFT)INT8_MIN (-INT8_MAX - 1)RESET_CTRL0_GPIO_RST (1 << RESET_CTRL0_GPIO_RST_SHIFT)GPIO_GROUP1_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x09000)RESET_EXT_STAT20_MASTER_RESET (1 << RESET_EXT_STAT20_MASTER_RESET_SHIFT)RESET_STATUS2_UART1_RST(x) ((x) << RESET_STATUS2_UART1_RST_SHIFT)__FLT32_DIG__ 6INT_LEAST16_MAXRESET_STATUS2_ADC1_RST_MASK (0x3 << RESET_STATUS2_ADC1_RST_SHIFT)BIT15 (1<<15)BACKUP_REG_BASE (0x40041000U)RESET_EXT_STAT60 MMIO32(RGU_BASE + 0x4F0)CREG_DMAMUX_DMAMUXPER9_MASK (0x3 << CREG_DMAMUX_DMAMUXPER9_SHIFT)RESET_ACTIVE_STATUS0_DMA_RST_SHIFT (19)BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1GPIO_GROUP0_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x08000)__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1INT32_MAXRESET_EXT_STAT11 MMIO32(RGU_BASE + 0x42C)RESET_STATUS1_USB1_RST_SHIFT (4)LPC43XX_RGU_H LPC43XX_IPC_H __ARM_FEATURE_CRYPTO__INT_LEAST32_TYPE__ long intRESET_EXT_STAT18 MMIO32(RGU_BASE + 0x448)RESET_EXT_STAT9 MMIO32(RGU_BASE + 0x424)RESET_CTRL0_USB0_RST_SHIFT (17)BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULLCREG_DMAMUX_DMAMUXPER5_SHIFT (10)__FRACT_IBIT__ 0I2C1_BASE (PERIPH_BASE_APB3 + 0x00000)RESET_EXT_STAT21_MASTER_RESET_SHIFT (3)UINT_LEAST64_MAXcm0_baseaddrCREG_USB0FLADJ_FLTV_MASK (0x3f << CREG_USB0FLADJ_FLTV_SHIFT)BIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234RESET_ACTIVE_STATUS1_DAC_RST_SHIFT (10)__FLT_NORM_MAX__ 3.4028234663852886e+38FCREG_M0APPMEMMAP_M0APPMAP(x) ((x) << CREG_M0APPMEMMAP_M0APPMAP_SHIFT)long long unsigned int__FLT_MIN_10_EXP__ (-37)BIT31 (1<<31)__ULACCUM_IBIT__ 32RESET_STATUS3_I2S_RST(x) ((x) << RESET_STATUS3_I2S_RST_SHIFT)__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2RESET_EXT_STAT38 MMIO32(RGU_BASE + 0x498)__PTRDIFF_TYPE__ intRESET_STATUS1_USB0_RST_SHIFT (2)__APCS_32__ 1__DQ_FBIT__ 63RESET_CTRL0_EEPROM_RST (1 << RESET_CTRL0_EEPROM_RST_SHIFT)RESET_STATUS3_I2C1_RST(x) ((x) << RESET_STATUS3_I2C1_RST_SHIFT)INT_LEAST64_MAX__SACCUM_IBIT__ 8RESET_STATUS2_TIMER1_RST(x) ((x) << RESET_STATUS2_TIMER1_RST_SHIFT)CREG_DMAMUX_DMAMUXPER0_SHIFT (0)__UHQ_IBIT__ 0INT_LEAST8_MINBIT29 (1<<29)CREG_DMAMUX_DMAMUXPER14_SHIFT (28)__INT_FAST16_TYPE__ intRESET_CTRL1_DAC_RST (1 << RESET_CTRL1_DAC_RST_SHIFT)INT64_CCREG_CREG0_RESET32KHZ_SHIFT (2)RESET_STATUS1_EEPROM_RST_MASK (0x3 << RESET_STATUS1_EEPROM_RST_SHIFT)__UINT_LEAST16_TYPE__ short unsigned intRESET_EXT_STAT5_CORE_RESET (1 << RESET_EXT_STAT5_CORE_RESET_SHIFT)INT_FAST16_MIN (-INT_FAST16_MAX - 1)__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned intRESET_ACTIVE_STATUS1_MOTOCONPWM_RST (1 << RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_SHIFT)CREG_DMAMUX_DMAMUXPER12_MASK (0x3 << CREG_DMAMUX_DMAMUXPER12_SHIFT)__FLT32X_DIG__ 15RESET_ACTIVE_STATUS0_DMA_RST (1 << RESET_ACTIVE_STATUS0_DMA_RST_SHIFT)CREG_CREG6_I2S1_TX_SCK_IN_SEL (1 << CREG_CREG6_I2S1_TX_SCK_IN_SEL_SHIFT)__UTQ_FBIT__ 128RESET_STATUS1_DMA_RST_MASK (0x3 << RESET_STATUS1_DMA_RST_SHIFT)CREG_M4MEMMAP MMIO32(CREG_BASE + 0x100)CREG_CREG0_BODLVL2_MASK (0x3 << CREG_CREG0_BODLVL2_SHIFT)RESET_STATUS1_SDIO_RST_SHIFT (8)RESET_EXT_STAT3 MMIO32(RGU_BASE + 0x40C)__FINITE_MATH_ONLY__ 0RESET_CTRL1_I2S_RST (1 << RESET_CTRL1_I2S_RST_SHIFT)__INT_FAST16_MAX__ 0x7fffffffPTRDIFF_MAX __PTRDIFF_MAX____SIZEOF_SHORT__ 2CREG_CREG6 MMIO32(CREG_BASE + 0x12C)RESET_EXT_STAT21 MMIO32(RGU_BASE + 0x454)RESET_ACTIVE_STATUS1_ADC0_RST (1 << RESET_ACTIVE_STATUS1_ADC0_RST_SHIFT)__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKRESET_EXT_STAT22_MASTER_RESET_SHIFT (3)UINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRCREG_DMAMUX_DMAMUXPER14(x) ((x) << CREG_DMAMUX_DMAMUXPER14_SHIFT)__DQ_IBIT__ 0RESET_EXT_STAT51_PERIPHERAL_RESET_SHIFT (2)__ARM_BF16_FORMAT_ALTERNATIVE__INT32_TYPE__ long intCREG_M4MEMMAP_M4MAP_MASK (0xfffff << CREG_M4MEMMAP_M4MAP_SHIFT)RESET_STATUS3_CAN0_RST_MASK (0x3 << RESET_STATUS3_CAN0_RST_SHIFT)SSP0_BASE (PERIPH_BASE_APB0 + 0x03000)QEI_BASE (PERIPH_BASE_APB2 + 0x06000)WCHAR_MINRESET_STATUS1 MMIO32(RGU_BASE + 0x114)RESET_STATUS2_QEI_RST_MASK (0x3 << RESET_STATUS2_QEI_RST_SHIFT)RESET_EXT_STAT36 MMIO32(RGU_BASE + 0x490)RESET_EXT_STAT28_PERIPHERAL_RESET (1 << RESET_EXT_STAT28_PERIPHERAL_RESET_SHIFT)BEGIN_DECLS RESET_STATUS3_I2C1_RST_MASK (0x3 << RESET_STATUS3_I2C1_RST_SHIFT)RESET_ACTIVE_STATUS1_TIMER1_RST_SHIFT (1)RESET_ACTIVE_STATUS1_SCT_RST (1 << RESET_ACTIVE_STATUS1_SCT_RST_SHIFT)CREG_DMAMUX_DMAMUXPER1_SHIFT (2)RESET_ACTIVE_STATUS1_QEI_RST (1 << RESET_ACTIVE_STATUS1_QEI_RST_SHIFT)CREG_DMAMUX_DMAMUXPER9_SHIFT (18)__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15__FLT32X_MAX__ 1.7976931348623157e+308F32xRESET_STATUS1_USB0_RST_MASK (0x3 << RESET_STATUS1_USB0_RST_SHIFT)RESET_EXT_STAT35 MMIO32(RGU_BASE + 0x48C)__ARM_EABI__ 1RESET_CTRL0 MMIO32(RGU_BASE + 0x100)INT16_MIN__ELF__ 1__FLT_IS_IEC_60559__ 2__THUMBEL__ 1CREG_CREG0_ALARMCTRL(x) ((x) << CREG_CREG0_ALARMCTRL_SHIFT)CREG_ETBCFG_ETB (1 << CREG_ETBCFG_ETB_SHIFT)__ARM_FEATURE_DSP 1RESET_STATUS1_ETHERNET_RST_SHIFT (12)USART3_BASE (PERIPH_BASE_APB2 + 0x02000)RESET_EXT_STAT26 MMIO32(RGU_BASE + 0x468)__QQ_IBIT__ 0CREG_CHIPID MMIO32(CREG_BASE + 0x200)RESET_ACTIVE_STATUS1_UART0_RST (1 << RESET_ACTIVE_STATUS1_UART0_RST_SHIFT)CREG_CREG0_WAKEUP1CTRL(x) ((x) << CREG_CREG0_WAKEUP1CTRL_SHIFT)RESET_CTRL0_PERIPH_RST (1 << RESET_CTRL0_PERIPH_RST_SHIFT)RESET_EXT_STAT45_PERIPHERAL_RESET (1 << RESET_EXT_STAT45_PERIPHERAL_RESET_SHIFT)__LLACCUM_FBIT__ 31RESET_STATUS3_SSP1_RST_SHIFT (6)__UINTMAX_TYPE__ long long unsigned intRESET_STATUS2_UART2_RST_SHIFT (28)RESET_EXT_STAT37 MMIO32(RGU_BASE + 0x494)__USQ_IBIT__ 0RESET_EXT_STAT5 MMIO32(RGU_BASE + 0x414)__UINT_LEAST32_TYPE__ long unsigned intRESET_STATUS0_CREG_RST_MASK (0x3 << RESET_STATUS0_CREG_RST_SHIFT)__ARM_FEATURE_NUMERIC_MAXMINRESET_EXT_STAT28_PERIPHERAL_RESET_SHIFT (2)__INTMAX_TYPE__ long long int__GCC_ATOMIC_INT_LOCK_FREE 2RESET_STATUS1_EEPROM_RST_SHIFT (22)RESET_ACTIVE_STATUS0_USB1_RST (1 << RESET_ACTIVE_STATUS0_USB1_RST_SHIFT)RESET_STATUS0_WWDT_RST(x) ((x) << RESET_STATUS0_WWDT_RST_SHIFT)CREG_CREG0_WAKEUP0CTRL(x) ((x) << CREG_CREG0_WAKEUP0CTRL_SHIFT)TIMER2_BASE (PERIPH_BASE_APB2 + 0x03000)RESET_EXT_STAT13_MASTER_RESET (1 << RESET_EXT_STAT13_MASTER_RESET_SHIFT)RESET_STATUS3_SPIFI_RST_MASK (0x3 << RESET_STATUS3_SPIFI_RST_SHIFT)__ARM_FEATURE_FP16_SCALAR_ARITHMETICRESET_STATUS3_CAN0_RST_SHIFT (14)__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1RESET_CTRL1_SPI_RST (1 << RESET_CTRL1_SPI_RST_SHIFT)__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CCREG_FLASHCFGB_FLASHTIM_SHIFT (12)CREG_DMAMUX_DMAMUXPER11_MASK (0x3 << CREG_DMAMUX_DMAMUXPER11_SHIFT)INT64_MIN__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intRESET_ACTIVE_STATUS1_UART2_RST_SHIFT (14)UINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRCREG_DMAMUX_DMAMUXPER0_MASK (0x3 << CREG_DMAMUX_DMAMUXPER0_SHIFT)__SIZEOF_SIZE_T__ 4RESET_CTRL1_ADC1_RST_SHIFT (9)CREG_DMAMUX_DMAMUXPER8_MASK (0x3 << CREG_DMAMUX_DMAMUXPER8_SHIFT)PMC_BASE (0x40042000U)__INT64_C(c) c ## LLRESET_CTRL1_UART0_RST (1 << RESET_CTRL1_UART0_RST_SHIFT)__ARM_ARCH_PROFILE 77RESET_CTRL1_RTIMER_RST (1 << RESET_CTRL1_RTIMER_RST_SHIFT)RESET_EXT_STAT31 MMIO32(RGU_BASE + 0x47C)UART1_BASE (PERIPH_BASE_APB0 + 0x02000)__LONG_MAX__ 0x7fffffffLRESET_EXT_STAT18_MASTER_RESET (1 << RESET_EXT_STAT18_MASTER_RESET_SHIFT)CREG_DMAMUX_DMAMUXPER5_MASK (0x3 << CREG_DMAMUX_DMAMUXPER5_SHIFT)__ARM_FEATURE_CDE__ACCUM_IBIT__ 16CREG_CREG6_CTOUTCTRL_SHIFT (4)RESET_STATUS3_M0APP_RST_SHIFT (16)RESET_CTRL1_QEI_RST (1 << RESET_CTRL1_QEI_RST_SHIFT)RESET_CTRL1_ADC0_RST_SHIFT (8)RESET_ACTIVE_STATUS1 MMIO32(RGU_BASE + 0x154)short intCREG_CREG5_M0APPTAPSEL (1 << CREG_CREG5_M0APPTAPSEL_SHIFT)RESET_EXT_STAT63 MMIO32(RGU_BASE + 0x4FC)CREG_CREG3 MMIO32(CREG_BASE + 0x110)__UINT16_C(c) cRESET_EXT_STAT40 MMIO32(RGU_BASE + 0x4A0)__UDA_IBIT__ 32RESET_STATUS1_GPIO_RST(x) ((x) << RESET_STATUS1_GPIO_RST_SHIFT)RESET_ACTIVE_STATUS1_I2S_RST (1 << RESET_ACTIVE_STATUS1_I2S_RST_SHIFT)RESET_ACTIVE_STATUS0_WWDT_RST (1 << RESET_ACTIVE_STATUS0_WWDT_RST_SHIFT)UINT_LEAST32_MAXCREG_DMAMUX_DMAMUXPER11(x) ((x) << CREG_DMAMUX_DMAMUXPER11_SHIFT)BIT2 (1<<2)__ATOMIC_RELAXED 0RESET_EXT_STAT33_PERIPHERAL_RESET_SHIFT (2)__ARM_FEATURE_COPROCCREG_DMAMUX_DMAMUXPER10_MASK (0x3 << CREG_DMAMUX_DMAMUXPER10_SHIFT)__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53RESET_STATUS0 MMIO32(RGU_BASE + 0x110)__ARM_FEATURE_FMA 1LPC43XX_M4 1BIT5 (1<<5)RESET_STATUS0_WWDT_RST_SHIFT (8)BIT1 (1<<1)INT8_CRESET_STATUS1_FLASHB_RST_MASK (0x3 << RESET_STATUS1_FLASHB_RST_SHIFT)INT_LEAST32_MAXCREG_M0APPMEMMAP_M0APPMAP_MASK (0xfffff << CREG_M0APPMEMMAP_M0APPMAP_SHIFT)__USES_INITFINI__ 1I2S1_BASE (PERIPH_BASE_APB1 + 0x03000)RESET_CTRL1_MOTOCONPWM_RST (1 << RESET_CTRL1_MOTOCONPWM_RST_SHIFT)RESET_EXT_STAT40_PERIPHERAL_RESET_SHIFT (2)__ULFRACT_MAX__ 0XFFFFFFFFP-32ULR__DBL_DECIMAL_DIG__ 17__ARM_FEATURE_SAT 1BIT8 (1<<8)RESET_ACTIVE_STATUS0_SDIO_RST_SHIFT (20)RESET_EXT_STAT44 MMIO32(RGU_BASE + 0x4B0)RESET_EXT_STAT58_PERIPHERAL_RESET_SHIFT (2)INT16_C(c) __INT16_C(c)UINT32_MAXRESET_CTRL1_ADC0_RST (1 << RESET_CTRL1_ADC0_RST_SHIFT)__INT16_MAX__ 0x7fffCREG_CREG6_EMC_CLK_SEL_SHIFT (16)RESET_CTRL1_CAN0_RST (1 << RESET_CTRL1_CAN0_RST_SHIFT)CREG_DMAMUX MMIO32(CREG_BASE + 0x11C)__INT_WIDTH__ 32__ARM_FEATURE_SIMD32 1RESET_ACTIVE_STATUS1_SGPIO_RST_SHIFT (25)rst_active_status1__QQ_FBIT__ 7RITIMER_BASE (PERIPH_BASE_APB2 + 0x00000)RESET_STATUS2_UART1_RST_MASK (0x3 << RESET_STATUS2_UART1_RST_SHIFT)__SIG_ATOMIC_WIDTH__ 32__FLT64_EPSILON__ 2.2204460492503131e-16F64CREG_DMAMUX_DMAMUXPER7(x) ((x) << CREG_DMAMUX_DMAMUXPER7_SHIFT)RESET_ACTIVE_STATUS1_SPI_RST (1 << RESET_ACTIVE_STATUS1_SPI_RST_SHIFT)RESET_EXT_STAT57_PERIPHERAL_RESET (1 << RESET_EXT_STAT57_PERIPHERAL_RESET_SHIFT)__UTA_IBIT__ 64__ULLACCUM_IBIT__ 32RESET_EXT_STAT27_PERIPHERAL_RESET (1 << RESET_EXT_STAT27_PERIPHERAL_RESET_SHIFT)RGU_BASE (0x40053000U)__ULLFRACT_EPSILON__ 0x1P-64ULLRCREG_CREG0_WAKEUP0CTRL_SHIFT (14)RESET_ACTIVE_STATUS0_EMC_RST_SHIFT (21)RESET_CTRL0_PERIPH_RST_SHIFT (1)__SIZEOF_WINT_T__ 4RESET_CTRL1_I2C1_RST (1 << RESET_CTRL1_I2C1_RST_SHIFT)__ARM_FEATURE_UNALIGNED 1__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17RESET_EXT_STAT9_PERIPHERAL_RESET (1 << RESET_EXT_STAT9_PERIPHERAL_RESET_SHIFT)CREG_M4TXEVENT MMIO32(CREG_BASE + 0x130)RESET_EXT_STAT56_PERIPHERAL_RESET_SHIFT (2)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1__FLT32X_HAS_DENORM__ 1__ULLACCUM_MIN__ 0.0ULLKRESET_CTRL1_SCT_RST (1 << RESET_CTRL1_SCT_RST_SHIFT)GPIO_PIN_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x07000)RESET_ACTIVE_STATUS1_SSP0_RST (1 << RESET_ACTIVE_STATUS1_SSP0_RST_SHIFT)CREG_DMAMUX_DMAMUXPER5(x) ((x) << CREG_DMAMUX_DMAMUXPER5_SHIFT)RESET_ACTIVE_STATUS1_RITIMER_RST (1 << RESET_ACTIVE_STATUS1_RITIMER_RST_SHIFT)__ARM_ASM_SYNTAX_UNIFIED__ 1RESET_EXT_STAT0 MMIO32(RGU_BASE + 0x400)__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODRESET_CTRL0_DMA_RST_SHIFT (19)RTC_BASE (0x40046000U)RESET_STATUS3_SSP0_RST_MASK (0x3 << RESET_STATUS3_SSP0_RST_SHIFT)__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H RESET_STATUS2_DAC_RST_SHIFT (20)AES_BASE (0x400F1000U)RESET_STATUS0_PERIPH_RST_MASK (0x3 << RESET_STATUS0_PERIPH_RST_SHIFT)INT_LEAST64_MINRESET_EXT_STAT8_PERIPHERAL_RESET (1 << RESET_EXT_STAT8_PERIPHERAL_RESET_SHIFT)__GCC_CONSTRUCTIVE_SIZE 64CREG_ETBCFG_ETB_SHIFT (0)RESET_STATUS2_RITIMER_RST_SHIFT (8)__LLFRACT_IBIT__ 0RESET_STATUS1_FLASHB_RST_SHIFT (26)uint32_tRESET_ACTIVE_STATUS1_SCT_RST_SHIFT (5)BIT12 (1<<12)CREG_USB1FLADJ_FLTV_SHIFT (0)__ARM_PCS_VFP 1RESET_CTRL1_SPI_RST_SHIFT (26)RESET_STATUS1_GPIO_RST_SHIFT (24)__SACCUM_EPSILON__ 0x1P-7HKCREG_DMAMUX_DMAMUXPER4_MASK (0x3 << CREG_DMAMUX_DMAMUXPER4_SHIFT)__GCC_ASM_FLAG_OUTPUTS__ 1RESET_EXT_STAT56 MMIO32(RGU_BASE + 0x4E0)RESET_EXT_STAT4 MMIO32(RGU_BASE + 0x410)__ARM_FP 4RESET_CTRL1_TIMER2_RST_SHIFT (2)RESET_ACTIVE_STATUS0_GPIO_RST (1 << RESET_ACTIVE_STATUS0_GPIO_RST_SHIFT)__UINT_FAST16_TYPE__ unsigned intRESET_ACTIVE_STATUS0_CREG_RST (1 << RESET_ACTIVE_STATUS0_CREG_RST_SHIFT)__UHA_IBIT__ 8CREG_USB0FLADJ_FLTV(x) ((x) << CREG_USB0FLADJ_FLTV_SHIFT)__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULKRESET_ACTIVE_STATUS0_EEPROM_RST_SHIFT (27)__LDBL_DIG__ 15UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXRESET_STATUS3_SSP0_RST_SHIFT (4)BIT16 (1<<16)__WINT_MIN__ 0UINT_LEAST16_MIN__FLT64_DIG__ 15CREG_CREG6_I2S0_RX_SCK_IN_SEL (1 << CREG_CREG6_I2S0_RX_SCK_IN_SEL_SHIFT)RESET_EXT_STAT38_PERIPHERAL_RESET_SHIFT (2)__WINT_MAX__ 0xffffffffUBIT22 (1<<22)__INT_LEAST8_WIDTH__ 8RESET_EXT_STAT0_BOD_RESET_SHIFT (4)RESET_EXT_STAT39_PERIPHERAL_RESET_SHIFT (2)__INT_LEAST16_TYPE__ short intCREG_DMAMUX_DMAMUXPER8(x) ((x) << CREG_DMAMUX_DMAMUXPER8_SHIFT)__DBL_MAX__ ((double)1.7976931348623157e+308L)CREG_DMAMUX_DMAMUXPER4(x) ((x) << CREG_DMAMUX_DMAMUXPER4_SHIFT)INT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1UINTMAX_CRESET_EXT_STAT41_PERIPHERAL_RESET (1 << RESET_EXT_STAT41_PERIPHERAL_RESET_SHIFT)RESET_EXT_STAT5_CORE_RESET_SHIFT (1)INT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1RESET_ACTIVE_STATUS0_BUS_RST_SHIFT (8)__UINTPTR_MAX__ 0xffffffffU__HQ_FBIT__ 15__bool_true_false_are_defined 1RESET_EXT_STAT44_PERIPHERAL_RESET (1 << RESET_EXT_STAT44_PERIPHERAL_RESET_SHIFT)USART2_BASE (PERIPH_BASE_APB2 + 0x01000)BIT26 (1<<26)RESET_ACTIVE_STATUS0_EMC_RST (1 << RESET_ACTIVE_STATUS0_EMC_RST_SHIFT)__SIZE_MAX__ 0xffffffffURESET_CTRL0_FLASHA_RST (1 << RESET_CTRL0_FLASHA_RST_SHIFT)RESET_CTRL0_USB1_RST_SHIFT (18)RESET_CTRL0_EEPROM_RST_SHIFT (27)__ARM_ARCH__SFRACT_IBIT__ 0RESET_ACTIVE_STATUS1_SSP0_RST_SHIFT (18)RESET_CTRL1 MMIO32(RGU_BASE + 0x104)MCPWM_BASE (PERIPH_BASE_APB1 + 0x00000)RESET_CTRL1_SSP0_RST (1 << RESET_CTRL1_SSP0_RST_SHIFT)RESET_CTRL1_SCT_RST_SHIFT (5)RESET_EXT_STAT19_MASTER_RESET (1 << RESET_EXT_STAT19_MASTER_RESET_SHIFT)RESET_EXT_STAT21_MASTER_RESET (1 << RESET_EXT_STAT21_MASTER_RESET_SHIFT)LPC43XX_MEMORYMAP_H CREG_CREG5_M4TAPSEL_SHIFT (6)__ARM_FEATURE_LDREX 7RESET_ACTIVE_STATUS0_CORE_RST_SHIFT (0)PTRDIFF_MAXRESET_CTRL1_TIMER1_RST (1 << RESET_CTRL1_TIMER1_RST_SHIFT)RESET_CTRL1_SPIFI_RST_SHIFT (21)__LLFRACT_EPSILON__ 0x1P-63LLR__SFRACT_MAX__ 0X7FP-7HR__FLT32X_MANT_DIG__ 53RESET_EXT_STAT49_PERIPHERAL_RESET_SHIFT (2)__WCHAR_WIDTH__ 32RESET_EXT_STAT16_MASTER_RESET_SHIFT (3)RESET_STATUS2_ADC0_RST_SHIFT (16)WINT_MAXINTMAX_MAX__INT16_C(c) cRESET_ACTIVE_STATUS1_ADC0_RST_SHIFT (8)CREG_CREG0_USB0PHY_SHIFT (5)__DA_IBIT__ 32RESET_ACTIVE_STATUS0_ETHERNET_RST (1 << RESET_ACTIVE_STATUS0_ETHERNET_RST_SHIFT)RESET_STATUS2_UART1_RST_SHIFT (26)RESET_EXT_STAT43 MMIO32(RGU_BASE + 0x4AC)__ATOMIC_ACQ_REL 4ADC1_BASE (PERIPH_BASE_APB3 + 0x04000)__HQ_IBIT__ 0RESET_STATUS3_I2S_RST_MASK (0x3 << RESET_STATUS3_I2S_RST_SHIFT)__DBL_MIN_10_EXP__ (-307)RESET_STATUS1_EMC_RST_SHIFT (10)CREG_DMAMUX_DMAMUXPER3(x) ((x) << CREG_DMAMUX_DMAMUXPER3_SHIFT)RESET_STATUS1_EEPROM_RST(x) ((x) << RESET_STATUS1_EEPROM_RST_SHIFT)RESET_EXT_STAT10 MMIO32(RGU_BASE + 0x428)RESET_EXT_STAT15 MMIO32(RGU_BASE + 0x43C)RESET_CTRL0_DMA_RST (1 << RESET_CTRL0_DMA_RST_SHIFT)__FLT32_NORM_MAX__ 3.4028234663852886e+38F32RESET_CTRL0_LCD_RST_SHIFT (16)RESET_EXT_STAT2_PERIPHERAL_RESET (1 << RESET_EXT_STAT2_PERIPHERAL_RESET_SHIFT)UINT64_C(c) __UINT64_C(c)RESET_EXT_STAT2_PERIPHERAL_RESET_SHIFT (2)RESET_CTRL1_I2S_RST_SHIFT (20)RESET_STATUS2_UART0_RST_SHIFT (24)__UINTMAX_MAX__ 0xffffffffffffffffULL__DBL_MANT_DIG__ 53RESET_CTRL0_SCU_RST (1 << RESET_CTRL0_SCU_RST_SHIFT)__ULFRACT_IBIT__ 0INT_FAST16_MAX__INT_MAX__ 0x7fffffff__INT_LEAST64_TYPE__ long long intRESET_EXT_STAT47 MMIO32(RGU_BASE + 0x4BC)RESET_CTRL1_TIMER2_RST (1 << RESET_CTRL1_TIMER2_RST_SHIFT)CREG_M0APPMEMMAP_M0APPMAP_SHIFT (12)RESET_STATUS3_CAN1_RST(x) ((x) << RESET_STATUS3_CAN1_RST_SHIFT)__ARM_FEATURE_CDE_COPROCRESET_CTRL0_CORE_RST (1 << RESET_CTRL0_CORE_RST_SHIFT)RESET_STATUS0_PERIPH_RST_SHIFT (2)RESET_EXT_STAT32 MMIO32(RGU_BASE + 0x480)UINT32_C../ipc.cGCC: (15:12.2.rel1-1) 12.2.1 20221205 | (BN0ENA3aeabi)7E-M M  "     $   ( ')!#%+ 4e-\*-( 0 ipc.c$t$dwm4.0.ac8f3cbd7733ee78183be95102ca936awm4.common.h.21.c9066c2f6b12c71b40226ea6107829a4wm4.stdint.h.29.6d480f4ba0f60596e88234283d42444fwm4.stdbool.h.29.4a1c88fe569adb8d03217dd16982ca34wm4.common.h.67.5c568a1f62c8e726909b04e29f9e1fc0wm4.memorymap.h.22.395ffb693017d551ed93d11c39ba4361wm4.creg.h.36.6becb3aedddf02e82cc32e255e0e64efwm4.rgu.h.35.fb70e7ab2eda27dc3b52363603206e72ipc_halt_m0ipc_start_m0 "&-4;BIPUho}  $-3<FO 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