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Z6vYW[uW{39:&9N:2V9q/\e7HgYTXi#!-ΣCi=%/[2>58-;S>ܚAZDUG[J~MdP?SV2Yc\~_Abʔexhrk,nqTWt~w0z(} T;vzo,܌zXVT|" F0e}^j5(_5.7-\TCj1" n[ 63h} m5}, WM@x9yTE=G8D`V*6b&r:@f)4fSzhRS+v"hEYJ.0) 1O%m(o8 C)2QMvkXx3pG!^6:>O oulчdwyJ3]9|Q%tp\_@N0܂ Jf{'~tXZKV0Hhz4_x) `څPro@BhÄ&EFnSLFm{:MYA8\N2T-.V(yHJ[\*L6T]fV?cY6[D=*@aVj\4}dgn6$ 4=}iwR#<&Yw(RF,CPU6y.il_aϝ )oB t =\-:v_Rt?{XO75 HI1Wb/s:\~qbk%-PY 6N/sO#3ǡ͗0p(xcZ# 4FbtQ*L cBekvZsA,[++$5|UK8IPtL;+ 1wgAl^9<h~]=>M5m<8?3ʈEM|3eqm!?R9I_ykfDa{ ,k;bR)F~:r4_SD ../usr/lib/gcc/arm-none-eabi/12.2.1/include../../../include/libopencm3/lpc43xx../../../include/libopencm3/cm3uart.cstdint.huart.hcommon.hstdbool.hmemorymap.hcgu.h1z&z l L11 g  O1   .1 5y & $.a 1###   =!!" =$ $0 z ##! <Lx Lr L # X# .. . 0" w  -/! . .. < % # u r. / >  /. / 0!CGU_PLL1_CTRL_FBSEL (1 << CGU_PLL1_CTRL_FBSEL_SHIFT)CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT (24)__DECIMAL_DIG__ 17CGU_BASE_SPIFI_CLK_AUTOBLOCK_SHIFT (11)__UHA_FBIT__ 8CGU_BASE_OUT_CLK_PD (1 << CGU_BASE_OUT_CLK_PD_SHIFT)uart_statusUART1_IER_CTSINT_EN (1 << 7)CGU_BASE_UART0_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART0_CLK_CLK_SEL_SHIFT)CGU_BASE_UART2_CLK_PD (1 << CGU_BASE_UART2_CLK_PD_SHIFT)__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64uart_num__GCC_ATOMIC_WCHAR_T_LOCK_FREE 2CGU_BASE_PHY_TX_CLK_PD (1 << CGU_BASE_PHY_TX_CLK_PD_SHIFT)__CHAR_UNSIGNED__ 1ETHERNET_BASE (PERIPH_BASE_AHB + 0x10000)CGU_BASE_PHY_RX_CLK_AUTOBLOCK_SHIFT (11)CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT (24)__FLT64_HAS_INFINITY__ 1CGU_IDIVC_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVC_CTRL_CLK_SEL_SHIFT)CGU_IDIVB_CTRL_CLK_SEL_SHIFT (24)__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)__GNUC_MINOR__ 2__GCC_DESTRUCTIVE_SIZE 64__LACCUM_EPSILON__ 0x1P-31LK__PTRDIFF_MAX__ 0x7fffffff__ARM_FEATURE_FMA 1CGU_PLL0AUDIO_CTRL_SEL_EXT_SHIFT (13)__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)__INTMAX_MAX__ 0x7fffffffffffffffLLCGU_IDIVD_CTRL_CLK_SEL_SHIFT (24)__TQ_IBIT__ 0__FLT64_DECIMAL_DIG__ 17WINT_MIN __WINT_MIN__I2C0_BASE (PERIPH_BASE_APB1 + 0x01000)data_readyUART0_NUM__ATOMIC_CONSUME 1__LFRACT_MIN__ (-0.5LR-0.5LR)__WCHAR_MAX__ 0xffffffffUCGU_PLL0USB_MDIV_SELR(x) ((x) << CGU_PLL0USB_MDIV_SELR_SHIFT)CGU_IDIVA_CTRL_PD (1 << CGU_IDIVA_CTRL_PD_SHIFT)OTP_BASE (0x40045000U)CGU_BASE_APLL_CLK MMIO32(CGU_BASE + 0x0C0)CGU_BASE_SSP1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT)CGU_BASE_OUT_CLK_CLK_SEL_SHIFT (24)CGU_PLL0USB_CTRL_CLK_SEL_SHIFT (24)INT64_MAX __INT64_MAX__INTMAX_MIN__SIZEOF_LONG_LONG__ 8__DBL_MAX_10_EXP__ 308CGU_BASE_APLL_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_APLL_CLK_CLK_SEL_SHIFT)__FRACT_MIN__ (-0.5R-0.5R)__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLK__USACCUM_MAX__ 0XFFFFP-8UHK__SFRACT_FBIT__ 7__INTMAX_WIDTH__ 64__ARM_FEATURE_BF16_SCALAR_ARITHMETIC__SQ_IBIT__ 0__ORDER_PDP_ENDIAN__ 3412__SIZE_TYPE__ unsigned intC_CCAN1_BASE (PERIPH_BASE_APB1 + 0x04000)__FLT_HAS_DENORM__ 1__INT8_TYPE__ signed char__SHRT_WIDTH__ 16CGU_BASE_SDIO_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT)__USACCUM_MIN__ 0.0UHK__FLT32_DECIMAL_DIG__ 9CGU_BASE_UART1_CLK_AUTOBLOCK (1 << CGU_BASE_UART1_CLK_AUTOBLOCK_SHIFT)UART_FCR(port) MMIO32((port) + 0x008)__LDBL_MIN_EXP__ (-1021)CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_MASK (0x3fffff << CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT)__LDBL_MANT_DIG__ 53UART_SRC_IDIVC 0x0EINT64_MIN (-INT64_MAX - 1)LPC43XX_UART_H __UINT8_C(c) c__INT16_TYPE__ short intCGU_BASE_USB0_CLK_CLK_SEL(x) ((x) << CGU_BASE_USB0_CLK_CLK_SEL_SHIFT)__FLT64_MAX__ 1.7976931348623157e+308F64USB0_BASE (PERIPH_BASE_AHB + 0x06000)UART_LSR_THRE (1 << 5)UINT_FAST32_MAXCGU_BASE_PHY_TX_CLK MMIO32(CGU_BASE + 0x07C)CGU_BASE_SDIO_CLK_PD_SHIFT (0)CGU_PLL0USB_CTRL_PD (1 << CGU_PLL0USB_CTRL_PD_SHIFT)INT_FAST64_MAX __INT_FAST64_MAX__CGU_PLL0AUDIO_CTRL_FRM (1 << CGU_PLL0AUDIO_CTRL_FRM_SHIFT)__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1UART_IIR_ABEO_INT (1 << 8)__UINT_LEAST16_MAX__ 0xffff__STDC_HOSTED__ 1__ULLFRACT_FBIT__ 64__SIG_ATOMIC_TYPE__ intCGU_BASE_APB3_CLK_AUTOBLOCK (1 << CGU_BASE_APB3_CLK_AUTOBLOCK_SHIFT)CGU_BASE_SPIFI_CLK_CLK_SEL(x) ((x) << CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT)__INT_FAST64_TYPE__ long long int__WINT_TYPE__ unsigned intPERIPH_BASE_APB2 (0x400C0000U)CGU_BASE_SPIFI_CLK_AUTOBLOCK (1 << CGU_BASE_SPIFI_CLK_AUTOBLOCK_SHIFT)CGU_XTAL_OSC_CTRL_ENABLE_SHIFT (0)INT32_MIN (-INT32_MAX - 1)UART_ICR(port) MMIO32((port) + 0x024)uart_rx_data_readyCGU_SRC_32K 0x00WWDT_BASE (PERIPH_BASE_APB0 + 0x00000)__USFRACT_MAX__ 0XFFP-8UHRCGU_PLL0USB_MDIV MMIO32(CGU_BASE + 0x024)__FP_FAST_FMAF32 1CGU_PLL1_CTRL MMIO32(CGU_BASE + 0x044)TIMER1_BASE (PERIPH_BASE_APB0 + 0x05000)UART1_IER_BITMASK ((uint32_t)(0x38F))__FLT32_MIN_EXP__ (-125)CGU_BASE_VADC_CLK_PD_SHIFT (0)ATIMER_BASE (0x40040000U)UINT32_MAX __UINT32_MAX__CGU_IDIVB_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVB_CTRL_CLK_SEL_SHIFT)C_CAN0_BASE (PERIPH_BASE_APB3 + 0x02000)__DA_IBIT__ 32__ULFRACT_FBIT__ 32INT8_MIN (-INT8_MAX - 1)__FLT64_MIN_10_EXP__ (-307)__GNUC_EXECUTION_CHARSET_NAME "UTF-8"BIT10 (1<<10)__INT_FAST64_WIDTH__ 64__STDC_VERSION__ 199901LINT_LEAST64_MAX __INT_LEAST64_MAX__CGU_BASE_APB3_CLK_PD (1 << CGU_BASE_APB3_CLK_PD_SHIFT)CGU_BASE_SPI_CLK_AUTOBLOCK (1 << CGU_BASE_SPI_CLK_AUTOBLOCK_SHIFT)UART_ICR_IRDAINV (1 << 1)__SFRACT_EPSILON__ 0x1P-7HRCGU_PLLAUDIO_FRAC_PLLFRACT_CTRL(x) ((x) << CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT)__INT32_C(c) c ## LUINT32_C(c) __UINT32_C(c)__ORDER_BIG_ENDIAN__ 4321SIZE_MAXCGU_PLL0USB_STAT_FR_SHIFT (1)__SQ_FBIT__ 31CGU_BASE_CGU_OUT1_CLK_PD_SHIFT (0)INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)CGU_PLL1_STAT_LOCK_SHIFT (0)UART_RS485CTRL(port) MMIO32((port) + 0x04C)__UHQ_FBIT__ 16CGU_IDIVB_CTRL_IDIV_SHIFT (2)__FLT64_MIN_EXP__ (-1021)__PTRDIFF_WIDTH__ 32__FLT32_MAX_10_EXP__ 38CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT (0)__UINT_FAST8_MAX__ 0xffffffffUuart_num_tCGU_IDIVA_CTRL_AUTOBLOCK (1 << CGU_IDIVA_CTRL_AUTOBLOCK_SHIFT)UINT16_C(c) __UINT16_C(c)CGU_BASE_CGU_OUT0_CLK_CLK_SEL(x) ((x) << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT)__LACCUM_IBIT__ 32CGU_PLL0AUDIO_CTRL_BYPASS (1 << CGU_PLL0AUDIO_CTRL_BYPASS_SHIFT)CGU_BASE_SDIO_CLK_CLK_SEL(x) ((x) << CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT)__INT_FAST16_WIDTH__ 32CGU_BASE_USB1_CLK MMIO32(CGU_BASE + 0x068)INTMAX_C__VERSION__ "12.2.1 20221205"__VFP_FP__ 1CGU_PLL0AUDIO_CTRL_SEL_EXT (1 << CGU_PLL0AUDIO_CTRL_SEL_EXT_SHIFT)__LLFRACT_MIN__ (-0.5LLR-0.5LLR)INT_FAST8_MAXCGU_PLL0USB_MDIV_MDEC_SHIFT (0)__GCC_ATOMIC_POINTER_LOCK_FREE 2__UINT_FAST16_MAX__ 0xffffffffUCGU_PLL0AUDIO_CTRL_PD_SHIFT (0)CGU_IDIVC_CTRL_PD_SHIFT (0)UART_SCICTRL_GUARDTIME(n) ((uint32_t)(((n)&0xFF)<<8))__INTPTR_MAX__ 0x7fffffffINT64_C(c) __INT64_C(c)CGU_IDIVD_CTRL_CLK_SEL(x) ((x) << CGU_IDIVD_CTRL_CLK_SEL_SHIFT)CGU_BASE_CGU_OUT1_CLK MMIO32(CGU_BASE + 0x0C8)__GCC_IEC_559_COMPLEX 0CREG_BASE (0x40043000U)__UFRACT_MIN__ 0.0URCGU_PLL0AUDIO_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT)uart_divaddvalCGU_BASE_M4_CLK_PD (1 << CGU_BASE_M4_CLK_PD_SHIFT)__FLT32X_HAS_INFINITY__ 1UINT_FAST16_MAX __UINT_FAST16_MAX__CGU_FREQ_MON_CLK_SEL_SHIFT (24)__UINT_LEAST8_TYPE__ unsigned charUART_DLL_MASKBIT ((uint8_t)0xFF)CGU_BASE_UART0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART0_CLK_CLK_SEL_SHIFT)__ACCUM_FBIT__ 15CGU_PLL0USB_CTRL_PD_SHIFT (0)UART_ACR(port) MMIO32((port) + 0x020)long intUINT8_MAXCGU_BASE_SAFE_CLK_CLK_SEL_SHIFT (24)uart_divisorCGU_PLL0USB_STAT MMIO32(CGU_BASE + 0x01C)__INT_FAST64_MAX__ 0x7fffffffffffffffLL__FLT32X_DECIMAL_DIG__ 17CGU_PLL1_CTRL_NSEL_MASK (0x3 << CGU_PLL1_CTRL_NSEL_SHIFT)__DBL_MIN__ ((double)2.2250738585072014e-308L)__FLT32X_HAS_QUIET_NAN__ 1CGU_BASE_PERIPH_CLK_AUTOBLOCK (1 << CGU_BASE_PERIPH_CLK_AUTOBLOCK_SHIFT)__FLT32X_EPSILON__ 2.2204460492503131e-16F32xUART_SRC_PLL0USB 0x07CGU_IDIVB_CTRL_PD (1 << CGU_IDIVB_CTRL_PD_SHIFT)CGU_BASE_UART2_CLK_AUTOBLOCK_SHIFT (11)__INT_FAST8_TYPE__ intBIT13 (1<<13)__UDA_FBIT__ 32UART_SYNCCTRL(port) MMIO32((port) + 0x058)uart_init__UINTMAX_C(c) c ## ULL__SIZEOF_POINTER__ 4__INT_LEAST8_TYPE__ signed char__GCC_ATOMIC_BOOL_LOCK_FREE 2BIT4 (1<<4)UINT_FAST64_MAXBIT0 (1<<0)INT_FAST32_MAX__ARM_NEON__UART_TIMEOUT_ERROR__FLT32_MAX_EXP__ 128UINT_LEAST8_MAX __UINT_LEAST8_MAX____TA_FBIT__ 63__THUMB_INTERWORK__ 1__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRCGU_BASE_UART3_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART3_CLK_CLK_SEL_SHIFT)CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT (24)UART_LSR_RXFE (1 << 7)short unsigned intBBIO_PERIPH(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)CGU_BASE_PHY_RX_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT)BIT7 (1<<7)BIT17 (1<<17)__FLT32X_MIN_10_EXP__ (-307)CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_SHIFT (11)UINT8_MAX __UINT8_MAX____CHAR32_TYPE__ long unsigned intSIG_ATOMIC_MIN__ARM_FEATURE_FP16_VECTOR_ARITHMETICLIBOPENCM3_CM3_COMMON_H BIT23 (1<<23)CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_SHIFT (12)DAC_BASE (PERIPH_BASE_APB3 + 0x01000)error__FLT_MAX_EXP__ 128__SIZEOF_LONG__ 4UART_FDR_MULVAL(n) ((uint32_t)(((n)<<4)&0xF0))LCD_BASE (PERIPH_BASE_AHB + 0x08000)CGU_BASE_OUT_CLK MMIO32(CGU_BASE + 0x0AC)CGU_BASE_SSP0_CLK_PD (1 << CGU_BASE_SSP0_CLK_PD_SHIFT)UART_IER_ABEOINT_EN (1 << 8)__SIZEOF_DOUBLE__ 8__INT_LEAST32_WIDTH__ 32__FLT32X_MIN_EXP__ (-1021)GPDMA_BASE (PERIPH_BASE_AHB + 0x02000)UART_SRC_IDIVA 0x0CUART_SYNCCTRL_NOSTARTSTOP (1 << 5)UART_IER_BITMASK ((uint32_t)(0x307))UART_FCR_FIFO_EN (1 << 0)uart_portBIT27 (1<<27)UART_IIR_INTID_RLS (3 << 1)UART_LSR_FE (1 << 3)CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT (24)CGU_PLL0AUDIO_NP_DIV_PDEC_MASK (0x7f << CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT)__UTA_FBIT__ 64SDIO_BASE (PERIPH_BASE_AHB + 0x04000)CGU_PLL0USB_NP_DIV_PDEC(x) ((x) << CGU_PLL0USB_NP_DIV_PDEC_SHIFT)__FLT_DECIMAL_DIG__ 9CGU_FREQ_MON_CLK_SEL(x) ((x) << CGU_FREQ_MON_CLK_SEL_SHIFT)__thumb__ 1__INT_LEAST32_MAX__ 0x7fffffffLsigned charGIMA_BASE (PERIPH_BASE_APB2 + 0x07000)uint8_tINT8_MAXINTMAX_MIN (-INTMAX_MAX - 1)CGU_BASE_LCD_CLK_AUTOBLOCK_SHIFT (11)INT32_C(c) __INT32_C(c)__GNUC_STDC_INLINE__ 1__FRACT_FBIT__ 15CGU_BASE_VADC_CLK_CLK_SEL(x) ((x) << CGU_BASE_VADC_CLK_CLK_SEL_SHIFT)__LLACCUM_EPSILON__ 0x1P-31LLK__GNUC_PATCHLEVEL__ 1__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2PTRDIFF_MIN__DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)CGU_BASE_UART0_CLK_AUTOBLOCK (1 << CGU_BASE_UART0_CLK_AUTOBLOCK_SHIFT)UART_LSR_PE (1 << 2)UINTPTR_MAX __UINTPTR_MAX____ARM_ARCH_PROFILE 77CGU_BASE_APB3_CLK_PD_SHIFT (0)UART_LCR_BREAK_EN (1 << 6)__FLT64_MAX_10_EXP__ 308CGU_PLL1_CTRL_PSEL_SHIFT (8)MMIO32(addr) (*(volatile uint32_t *)(addr))WINT_MINUART3 USART3_BASE__INT_FAST32_WIDTH__ 32UART_ICR_IRDAEN (1 << 0)CGU_BASE (0x40050000U)GPIO_PIN_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x07000)__UINT_FAST32_TYPE__ unsigned intunsigned charEND_DECLS __SIZEOF_FLOAT__ 4__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xUINT64_MAX__FLT_MAX_10_EXP__ 38UART_DATABIT_6UART_DATABIT_7__FRACT_MAX__ 0X7FFFP-15R__GCC_IEC_559 0GNU C99 12.2.1 20221205 -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -march=armv7e-m+fp -ggdb3 -O2 -std=c99 -fno-common -ffunction-sections -fdata-sectionsINT_LEAST32_MAX __INT_LEAST32_MAX__CGU_IDIVE_CTRL_PD (1 << CGU_IDIVE_CTRL_PD_SHIFT)CGU_PLL0AUDIO_CTRL_DIRECTO_SHIFT (3)CGU_BASE_PHY_RX_CLK MMIO32(CGU_BASE + 0x078)__INT_FAST32_MAX__ 0x7fffffff__ATOMIC_SEQ_CST 5CGU_BASE_SPIFI_CLK_PD (1 << CGU_BASE_SPIFI_CLK_PD_SHIFT)CGU_PLL0AUDIO_CTRL_AUTOBLOCK_SHIFT (11)UART_IER_ABTOINT_EN (1 << 9)CGU_IDIVB_CTRL_PD_SHIFT (0)CGU_PLL0USB_MDIV_SELP_MASK (0x1f << CGU_PLL0USB_MDIV_SELP_SHIFT)CGU_PLL0AUDIO_STAT_FR (1 << CGU_PLL0AUDIO_STAT_FR_SHIFT)CGU_BASE_SSP0_CLK_PD_SHIFT (0)CGU_BASE_SAFE_CLK_CLK_SEL(x) ((x) << CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT)CGU_IDIVE_CTRL_AUTOBLOCK (1 << CGU_IDIVE_CTRL_AUTOBLOCK_SHIFT)__UINT16_MAX__ 0xffffCGU_PLL0USB_CTRL_AUTOBLOCK (1 << CGU_PLL0USB_CTRL_AUTOBLOCK_SHIFT)__TQ_FBIT__ 127CGU_BASE_UART0_CLK_AUTOBLOCK_SHIFT (11)CGU_PLL0USB_NP_DIV_PDEC_MASK (0x7f << CGU_PLL0USB_NP_DIV_PDEC_SHIFT)__USQ_FBIT__ 32INT_FAST16_MINCGU_BASE_UART2_CLK_AUTOBLOCK (1 << CGU_BASE_UART2_CLK_AUTOBLOCK_SHIFT)__thumb2__ 1__ULLACCUM_FBIT__ 32CGU_SRC_ENET_TX 0x03UART_PARITY_EVENCGU_BASE_USB1_CLK_CLK_SEL(x) ((x) << CGU_BASE_USB1_CLK_CLK_SEL_SHIFT)CGU_BASE_SSP0_CLK MMIO32(CGU_BASE + 0x094)CGU_BASE_SSP1_CLK_CLK_SEL(x) ((x) << CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT)__STRICT_ANSI__ 1CGU_BASE_SPI_CLK_PD (1 << CGU_BASE_SPI_CLK_PD_SHIFT)UINT_LEAST8_MAXCGU_IDIVD_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVD_CTRL_CLK_SEL_SHIFT)UART_FDR_BITMASK ((uint32_t)(0xFF))UINT8_C(c) __UINT8_C(c)__SIZEOF_LONG_DOUBLE__ 8CGU_FREQ_MON_FCNT(x) ((x) << CGU_FREQ_MON_FCNT_SHIFT)UART_LSR_BI (1 << 4)__PRAGMA_REDEFINE_EXTNAME 1__WCHAR_TYPE__ unsigned intWINT_MAX __WINT_MAX__CGU_IDIVE_CTRL_PD_SHIFT (0)CGU_FREQ_MON_FCNT_SHIFT (9)__USA_IBIT__ 16UART_RX_DATA_ERROR__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1CGU_BASE_PHY_TX_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT)PTRDIFF_MIN (-PTRDIFF_MAX - 1)UART_SCICTRL_TXRETRY(n) ((uint32_t)(((n)&0x07)<<5))CGU_BASE_APB3_CLK_CLK_SEL(x) ((x) << CGU_BASE_APB3_CLK_CLK_SEL_SHIFT)__DBL_IS_IEC_60559__ 2__UINT_FAST64_TYPE__ long long unsigned intCGU_PLL0AUDIO_STAT_FR_SHIFT (1)CGU_PLL1_CTRL_NSEL(x) ((x) << CGU_PLL1_CTRL_NSEL_SHIFT)__FLT_MIN__ 1.1754943508222875e-38F__HA_FBIT__ 7__FDPIC__CGU_IDIVA_CTRL_IDIV_SHIFT (2)CGU_BASE_SPI_CLK MMIO32(CGU_BASE + 0x074)CGU_BASE_UART2_CLK_CLK_SEL_SHIFT (24)__FLT32_IS_IEC_60559__ 2CGU_BASE_PHY_TX_CLK_PD_SHIFT (0)CGU_FREQ_MON_CLK_SEL_MASK (0x1f << CGU_FREQ_MON_CLK_SEL_SHIFT)UART_SRC_IDIVD 0x0FCGU_PLL0AUDIO_CTRL_BYPASS_SHIFT (1)INT_FAST64_MINADC0_BASE (PERIPH_BASE_APB3 + 0x03000)__USFRACT_IBIT__ 0__LDBL_EPSILON__ 2.2204460492503131e-16LUART_RS485ADRMATCH(port) MMIO32((port) + 0x050)__USFRACT_MIN__ 0.0UHR__ARM_NEONUART_HDEN_HDEN (1 << 0)CGU_IDIVA_CTRL MMIO32(CGU_BASE + 0x048)__UINT8_MAX__ 0xffCGU_PLL0AUDIO_CTRL_AUTOBLOCK (1 << CGU_PLL0AUDIO_CTRL_AUTOBLOCK_SHIFT)CGU_BASE_APLL_CLK_PD (1 << CGU_BASE_APLL_CLK_PD_SHIFT)__LDBL_MAX_EXP__ 1024UART_ACR_ABTOINT_CLR (1 << 9)CGU_XTAL_OSC_CTRL_HF_SHIFT (2)CGU_PLL0AUDIO_MDIV_MDEC_SHIFT (0)CGU_PLL1_CTRL_FBSEL_SHIFT (6)__DBL_HAS_DENORM__ 1CGU_PLL0USB_MDIV_SELP(x) ((x) << CGU_PLL0USB_MDIV_SELP_SHIFT)CGU_BASE_USB0_CLK_AUTOBLOCK_SHIFT (11)CGU_BASE_PERIPH_CLK_PD (1 << CGU_BASE_PERIPH_CLK_PD_SHIFT)CGU_SRC_IDIVB 0x0DCGU_BASE_SDIO_CLK_PD (1 << CGU_BASE_SDIO_CLK_PD_SHIFT)CGU_FREQ_MON_RCNT(x) ((x) << CGU_FREQ_MON_RCNT_SHIFT)__DA_FBIT__ 31CGU_BASE_OUT_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_OUT_CLK_CLK_SEL_SHIFT)__GXX_ABI_VERSION 1017__INT_LEAST16_MAX__ 0x7fffCGU_FREQ_MON_RCNT_SHIFT (0)__FLT_DENORM_MIN__ 1.4012984643248171e-45FCGU_XTAL_OSC_CTRL_BYPASS (1 << CGU_XTAL_OSC_CTRL_BYPASS_SHIFT)CGU_IDIVE_CTRL_CLK_SEL_SHIFT (24)CGU_BASE_USB0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_USB0_CLK_CLK_SEL_SHIFT)INT_LEAST8_MAX __INT_LEAST8_MAX__CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT (12)UART_IIR_INTSTAT_PEND (1 << 0)__UINT32_C(c) c ## ULUART1_IER_MSINT_EN (1 << 3)CGU_BASE_PHY_RX_CLK_AUTOBLOCK (1 << CGU_BASE_PHY_RX_CLK_AUTOBLOCK_SHIFT)UART_LCR_WLEN7 (2 << 0)__UACCUM_MIN__ 0.0UKCGU_FREQ_MON_FCNT_MASK (0x3fff << CGU_FREQ_MON_FCNT_SHIFT)CGU_IDIVD_CTRL_AUTOBLOCK_SHIFT (11)__FLT_EPSILON__ 1.1920928955078125e-7FCGU_BASE_UART1_CLK_CLK_SEL_SHIFT (24)UART_LCR_PARITY_SP_1 (1 << 5)__PTRDIFF_TYPE__ intUART_FCR_TRG_LEV2 (2 << 6)__ARM_ARCH_ISA_THUMBCGU_PLL0USB_CTRL_FRM_SHIFT (6)CGU_PLL0AUDIO_CTRL_CLKEN_SHIFT (4)UART_SCICTRL_PROTSEL_T1 (1 << 2)__ARM_FEATURE_MATMUL_INT8data_parityCGU_PLL1_CTRL_DIRECT_SHIFT (7)__GCC_ATOMIC_SHORT_LOCK_FREE 2CGU_BASE_UART3_CLK_AUTOBLOCK_SHIFT (11)uart_stopbit_t__HQ_IBIT__ 0UART_ACR_BITMASK ((uint32_t)(0x307))__USACCUM_FBIT__ 8CGU_SRC_PLL1 0x09__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1UART_ICR_BITMASK ((uint32_t)(0x3F))CGU_PLL0USB_MDIV_MDEC_MASK (0x1ffff << CGU_PLL0USB_MDIV_MDEC_SHIFT)CGU_BASE_SPI_CLK_CLK_SEL_SHIFT (24)__ELF__ 1CGU_BASE_APB1_CLK_PD_SHIFT (0)EMC_BASE (PERIPH_BASE_AHB + 0x05000)__FLT32_HAS_QUIET_NAN__ 1UART_PARITY_SP_1__LDBL_HAS_INFINITY__ 1CGU_SRC_GP_CLKIN 0x04__SACCUM_FBIT__ 7UINT16_MAX __UINT16_MAX__MMIO8(addr) (*(volatile uint8_t *)(addr))CCU1_BASE (0x40051000U)__FLT32X_MAX_10_EXP__ 308UART_LCR_DLAB_EN (1 << 7)CGU_BASE_PERIPH_CLK_CLK_SEL(x) ((x) << CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT)CGU_BASE_OUT_CLK_CLK_SEL(x) ((x) << CGU_BASE_OUT_CLK_CLK_SEL_SHIFT)__ARM_ARCH_EXT_IDIV__ 1CGU_BASE_UART3_CLK_AUTOBLOCK (1 << CGU_BASE_UART3_CLK_AUTOBLOCK_SHIFT)UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F))bool _BoolCGU_PLL0USB_CTRL_CLKEN_SHIFT (4)UINTMAX_MAX __UINTMAX_MAX__CGU_BASE_OUT_CLK_PD_SHIFT (0)__SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__UINT_LEAST8_MAX__ 0xffCGU_BASE_PERIPH_CLK_AUTOBLOCK_SHIFT (11)CGU_XTAL_OSC_CTRL MMIO32(CGU_BASE + 0x018)CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT (0)BBIO_SRAM(addr,bit) MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)INT16_MAX __INT16_MAX____FP_FAST_FMAF 1CGU_BASE_OUT_CLK_AUTOBLOCK (1 << CGU_BASE_OUT_CLK_AUTOBLOCK_SHIFT)__FLT32X_IS_IEC_60559__ 2PERIPH_BASE_APB3 (0x400E0000U)UART_DLM_MASKBIT ((uint8_t)0xFF)LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))UINT32_MAXCGU_PLL1_STAT MMIO32(CGU_BASE + 0x040)CGU_BASE_PHY_RX_CLK_PD_SHIFT (0)__INT_LEAST16_WIDTH__ 16I2S0_BASE (PERIPH_BASE_APB1 + 0x02000)CGU_PLL0USB_CTRL_DIRECTI_SHIFT (2)__DEC_EVAL_METHOD__ 2SCT_BASE (PERIPH_BASE_AHB + 0x00000)__ARM_FEATURE_FP16_FMLCGU_PLL0USB_MDIV_MDEC(x) ((x) << CGU_PLL0USB_MDIV_MDEC_SHIFT)CGU_BASE_UART3_CLK_PD_SHIFT (0)INT16_MIN (-INT16_MAX - 1)__USFRACT_EPSILON__ 0x1P-8UHRCGU_IDIVD_CTRL_IDIV(x) ((x) << CGU_IDIVD_CTRL_IDIV_SHIFT)CGU_IDIVD_CTRL MMIO32(CGU_BASE + 0x054)__WINT_MAX__ 0xffffffffUCGU_BASE_SSP1_CLK_CLK_SEL_SHIFT (24)SCU_BASE (PERIPH_BASE_APB0 + 0x06000)__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLKUART_IIR_FIFO_EN (3 << 6)CGU_BASE_SSP0_CLK_AUTOBLOCK (1 << CGU_BASE_SSP0_CLK_AUTOBLOCK_SHIFT)CGU_IDIVC_CTRL_PD (1 << CGU_IDIVC_CTRL_PD_SHIFT)__USER_LABEL_PREFIX__ __UINT64_MAX__ 0xffffffffffffffffULLINT_FAST8_MININT_FAST8_MAX __INT_FAST8_MAX__UART_LCR_WLEN8 (3 << 0)__UINT32_MAX__ 0xffffffffULUSART0_BASE (PERIPH_BASE_APB0 + 0x01000)CGU_BASE_M4_CLK_PD_SHIFT (0)__INT_LEAST8_MAX__ 0x7fUART_FIFOLVL_RX(n) ((uint32_t)((n)&0x0F))uart_rx_data_ready_t__ARM_FEATURE_QBIT 1__ARM_FEATURE_CLZ 1__ATOMIC_ACQUIRE 2__ARM_FEATURE_COMPLEXCGU_SRC_IRC 0x01__ARM_PCS_VFP 1__UINT64_TYPE__ long long unsigned intCGU_BASE_SAFE_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT)__ARM_SIZEOF_WCHAR_T 4__FLT32X_MAX_EXP__ 1024CGU_IDIVC_CTRL_AUTOBLOCK_SHIFT (11)dummy_read__UINT_LEAST32_MAX__ 0xffffffffULUART_FCR_TX_RS (1 << 2)__DBL_EPSILON__ ((double)2.2204460492503131e-16L)INT_FAST8_MIN (-INT_FAST8_MAX - 1)CGU_BASE_APLL_CLK_AUTOBLOCK (1 << CGU_BASE_APLL_CLK_AUTOBLOCK_SHIFT)CGU_SRC_PLL0USB 0x07__INT_LEAST64_WIDTH__ 64__FLT_HAS_INFINITY__ 1__ACCUM_MAX__ 0X7FFFFFFFP-15K__INT8_MAX__ 0x7fCGU_OUTCLK_21_CTRL MMIO32(CGU_BASE + 0x0B0)BIT14 (1<<14)__GCC_HAVE_DWARF2_CFI_ASM 1__ARM_FEATURE_CRC32__SFRACT_MIN__ (-0.5HR-0.5HR)long unsigned int__SA_IBIT__ 16USB1_BASE (PERIPH_BASE_AHB + 0x07000)BIT20 (1<<20)__ARM_FEATURE_MVE__ARM_FP16_FORMAT_IEEE__UINT16_TYPE__ short unsigned intCGU_PLL0USB_CTRL_CLKEN (1 << CGU_PLL0USB_CTRL_CLKEN_SHIFT)UINT_LEAST16_MAX __UINT_LEAST16_MAX__INT_FAST32_MINUART_SYNCCTRL_CSRC_MASTER (1 << 1)TIMER0_BASE (PERIPH_BASE_APB0 + 0x04000)CGU_IDIVA_CTRL_IDIV_MASK (0x3 << CGU_IDIVA_CTRL_IDIV_SHIFT)__SCHAR_WIDTH__ 8CGU_BASE_PHY_RX_CLK_CLK_SEL(x) ((x) << CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT)BIT18 (1<<18)UINT_FAST16_MAXCGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_SHIFT (11)__UINT_FAST8_TYPE__ unsigned intCGU_BASE_UART1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART1_CLK_CLK_SEL_SHIFT)__LLACCUM_IBIT__ 32__FRACT_EPSILON__ 0x1P-15RBIT24 (1<<24)CGU_PLL1_CTRL_MSEL_MASK (0xff << CGU_PLL1_CTRL_MSEL_SHIFT)CGU_IDIVE_CTRL_IDIV_MASK (0xff << CGU_IDIVE_CTRL_IDIV_SHIFT)__INT32_MAX__ 0x7fffffffLCGU_PLL0AUDIO_STAT_LOCK (1 << CGU_PLL0AUDIO_STAT_LOCK_SHIFT)UINTMAX_MAXBIT30 (1<<30)__INT_LEAST64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_BF16_VECTOR_ARITHMETIC__FLT32_MANT_DIG__ 24CGU_IDIVA_CTRL_PD_SHIFT (0)INT_LEAST8_MAX__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32UART_LSR(port) MMIO32((port) + 0x014)EVENTROUTER_BASE (0x40044000U)__UINT64_C(c) c ## ULL__UINT_LEAST64_TYPE__ long long unsigned intWCHAR_MIN __WCHAR_MIN__UART_IIR_INTID_CTI (6 << 1)__USFRACT_FBIT__ 8INT8_MAX __INT8_MAX__CGU_IDIVD_CTRL_PD_SHIFT (0)BIT28 (1<<28)__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2INTMAX_C(c) __INTMAX_C(c)UART_SRC_32K 0x00__DBL_MAX_EXP__ 1024__ATOMIC_RELEASE 3CGU_IDIVD_CTRL_IDIV_MASK (0xf << CGU_IDIVD_CTRL_IDIV_SHIFT)UINT_FAST8_MAX__FLT_MANT_DIG__ 24UART_FCR_TRG_LEV1 (1 << 6)CGU_BASE_APLL_CLK_CLK_SEL_SHIFT (24)__LACCUM_FBIT__ 31CCU2_BASE (0x40052000U)__OPTIMIZE__ 1CGU_BASE_APB3_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_APB3_CLK_CLK_SEL_SHIFT)CGU_IDIVD_CTRL_AUTOBLOCK (1 << CGU_IDIVD_CTRL_AUTOBLOCK_SHIFT)__FLT64_NORM_MAX__ 1.7976931348623157e+308F64PERIPH_BASE_APB1 (0x400A0000U)UART_FCR_TRG_LEV0 (0 << 6)UINTPTR_MAX__LDBL_DENORM_MIN__ 4.9406564584124654e-324LTIMER3_BASE (PERIPH_BASE_APB2 + 0x04000)__INT64_MAX__ 0x7fffffffffffffffLL__ARM_FEATURE_SAT 1__ULLFRACT_IBIT__ 0SPI_PORT_BASE (0x40100000U)CGU_BASE_LCD_CLK_PD (1 << CGU_BASE_LCD_CLK_PD_SHIFT)MMIO16(addr) (*(volatile uint16_t *)(addr))CGU_BASE_APB3_CLK_AUTOBLOCK_SHIFT (11)UART0 USART0_BASEUART_TX_FIFO_SIZE (16)LPC43XX 1__GNUC__ 12CGU_BASE_UART1_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART1_CLK_CLK_SEL_SHIFT)WCHAR_MAXUART_SRC_IRC 0x01CGU_IDIVB_CTRL_AUTOBLOCK_SHIFT (11)__LONG_WIDTH__ 32__FLT_MAX__ 3.4028234663852886e+38FINT32_MAX __INT32_MAX____UACCUM_FBIT__ 16CGU_PLL1_CTRL_DIRECT (1 << CGU_PLL1_CTRL_DIRECT_SHIFT)__UFRACT_EPSILON__ 0x1P-16UR__WCHAR_MIN__ 0UUART_IIR_BITMASK ((uint32_t)(0x3CF))__UQQ_IBIT__ 0CGU_BASE_PERIPH_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT)CGU_SRC_XTAL 0x06__GCC_ATOMIC_LONG_LOCK_FREE 2__ULACCUM_MIN__ 0.0ULKCGU_PLL0USB_NP_DIV_PDEC_SHIFT (0)__LDBL_MAX__ 1.7976931348623157e+308L__ARM_ARCH 7/build/libopencm3/lib/lpc43xx/m4UART_SRC_ENET_RX 0x02__FLT_RADIX__ 2BIT3 (1<<3)long long intCGU_SRC_IDIVE 0x10__ARM_FEATURE_CMSEINT16_MAXINTPTR_MAXcounterSGPIO_PORT_BASE (0x40101000U)__LDBL_HAS_QUIET_NAN__ 1CGU_PLL0USB_MDIV_SELI_MASK (0x3f << CGU_PLL0USB_MDIV_SELI_SHIFT)PERIPH_BASE_APB0 (0x40080000U)__LONG_LONG_WIDTH__ 64BIT6 (1<<6)CGU_FREQ_MON_MEAS_SHIFT (23)CGU_PLL0USB_CTRL_DIRECTO (1 << CGU_PLL0USB_CTRL_DIRECTO_SHIFT)CGU_BASE_APB1_CLK MMIO32(CGU_BASE + 0x080)CGU_IDIVE_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVE_CTRL_CLK_SEL_SHIFT)__UINT_FAST64_MAX__ 0xffffffffffffffffULLCGU_BASE_M4_CLK_AUTOBLOCK_SHIFT (11)__ARM_FP__HA_IBIT__ 8__INTPTR_WIDTH__ 32__GCC_ATOMIC_LLONG_LOCK_FREE 1CGU_PLL0AUDIO_CTRL MMIO32(CGU_BASE + 0x030)BIT9 (1<<9)UART_FCR_RX_RS (1 << 1)__FLT32X_MIN__ 2.2250738585072014e-308F32xrx_timeout_nb_cycles__FLT64_MAX_EXP__ 1024CGU_BASE_SAFE_CLK_PD_SHIFT (0)UINT16_MAXUART_SCICTRL_SCIEN (1 << 0)__FLT64_MIN__ 2.2250738585072014e-308F64CGU_PLL0USB_CTRL_AUTOBLOCK_SHIFT (11)__INTMAX_C(c) c ## LLCGU_PLL0USB_CTRL_BYPASS_SHIFT (1)__FLT_EVAL_METHOD_TS_18661_3__ 0CGU_BASE_M4_CLK MMIO32(CGU_BASE + 0x06C)__ARM_ARCH_PROFILE__INT64_TYPE__ long long int__LFRACT_FBIT__ 31__CHAR_BIT__ 8__SIZEOF_WCHAR_T__ 4UART_ACR_MODE (1 << 1)CGU_BASE_PHY_TX_CLK_AUTOBLOCK (1 << CGU_BASE_PHY_TX_CLK_AUTOBLOCK_SHIFT)UART_PARITY_ODDUART_SYNCCTRL_TSBYPASS (1 << 3)CGU_PLL1_CTRL_CLK_SEL(x) ((x) << CGU_PLL1_CTRL_CLK_SEL_SHIFT)__UFRACT_MAX__ 0XFFFFP-16URCGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT (24)__UINT_LEAST32_TYPE__ long unsigned intINT64_MAXCGU_BASE_USB1_CLK_PD_SHIFT (0)CGU_PLL0AUDIO_STAT_LOCK_SHIFT (0)UART_SYNCCTRL_FES (1 << 2)INT_FAST64_MIN (-INT_FAST64_MAX - 1)__SFRACT_IBIT__ 0SSP1_BASE (PERIPH_BASE_APB2 + 0x05000)UART_LSR_ERROR_MASK (UART_LSR_OE | UART_LSR_PE | UART_LSR_FE | UART_LSR_BI | UART_LSR_RXFE)SPIFI_BASE (PERIPH_BASE_AHB + 0x03000)__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__../uart.c__ARM_NEON_FPINTPTR_MIN (-INTPTR_MAX - 1)UINT_FAST64_MAX __UINT_FAST64_MAX__UART_LSR_TEMT (1 << 6)__UFRACT_FBIT__ 16UART_LCR_PARITY_ODD (0 << 4)__UDQ_FBIT__ 64__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)CGU_XTAL_OSC_CTRL_BYPASS_SHIFT (1)CGU_FREQ_MON MMIO32(CGU_BASE + 0x014)__LDBL_MAX_10_EXP__ 308CGU_BASE_UART0_CLK_PD_SHIFT (0)UART_DATABIT_5UART_DATABIT_8__INT_FAST32_TYPE__ intuart_writeunsigned intCGU_BASE_SPI_CLK_PD_SHIFT (0)CGU_IDIVE_CTRL_AUTOBLOCK_SHIFT (11)__FLT_MIN_EXP__ (-125)__FLT64_HAS_QUIET_NAN__ 1CGU_PLL1_CTRL_PSEL(x) ((x) << CGU_PLL1_CTRL_PSEL_SHIFT)CGU_BASE_APB1_CLK_AUTOBLOCK_SHIFT (11)CGU_IDIVE_CTRL_CLK_SEL(x) ((x) << CGU_IDIVE_CTRL_CLK_SEL_SHIFT)UART_SRC_GP_CLKIN 0x04__USACCUM_IBIT__ 8UART_IIR(port) MMIO32((port) + 0x008)__ARM_ARCH_7EM__ 1__FLT64_HAS_DENORM__ 1__FLT_DIG__ 6__UACCUM_EPSILON__ 0x1P-16UKUART_IER_RBRINT_EN (1 << 0)CGU_PLL0AUDIO_NP_DIV_PDEC(x) ((x) << CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT)__FLT_EVAL_METHOD__ 0CGU_BASE_UART3_CLK_PD (1 << CGU_BASE_UART3_CLK_PD_SHIFT)CGU_OUTCLK_24_CTRL MMIO32(CGU_BASE + 0x0BC)GPIO_PORT_BASE (0x400F4000U)__SCHAR_MAX__ 0x7fINT_LEAST32_MIN__INT_FAST8_WIDTH__ 32CGU_FREQ_MON_RCNT_MASK (0x1ff << CGU_FREQ_MON_RCNT_SHIFT)__ARM_FEATURE_LDREXCGU_BASE_SPI_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SPI_CLK_CLK_SEL_SHIFT)__UQQ_FBIT__ 8CGU_PLL1_CTRL_AUTOBLOCK_SHIFT (11)CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK (1 << CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_SHIFT)INT16_CCGU_PLL0USB_CTRL_FRM (1 << CGU_PLL0USB_CTRL_FRM_SHIFT)__ARM_FP16_ARGS__UACCUM_MAX__ 0XFFFFFFFFP-16UKUART3_NUMINT_LEAST8_MIN (-INT_LEAST8_MAX - 1)INT_LEAST16_MAX __INT_LEAST16_MAX____LFRACT_MAX__ 0X7FFFFFFFP-31LR__SIZEOF_PTRDIFF_T__ 4__STDC__ 1CGU_BASE_USB0_CLK_PD_SHIFT (0)CGU_BASE_M4_CLK_CLK_SEL(x) ((x) << CGU_BASE_M4_CLK_CLK_SEL_SHIFT)__ARM_FEATURE_IDIV 1__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN____UINT8_TYPE__ unsigned charCGU_BASE_APB1_CLK_CLK_SEL(x) ((x) << CGU_BASE_APB1_CLK_CLK_SEL_SHIFT)CGU_BASE_SDIO_CLK_AUTOBLOCK_SHIFT (11)UART_RS485DLY(port) MMIO32((port) + 0x054)__ARM_FEATURE_COPROC 15CGU_PLL0USB_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT)UINT64_MAX __UINT64_MAX____GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"CGU_BASE_SAFE_CLK_PD (1 << CGU_BASE_SAFE_CLK_PD_SHIFT)INT8_MINUART_SRC_XTAL 0x06true 1CGU_IDIVB_CTRL MMIO32(CGU_BASE + 0x04C)__USA_FBIT__ 16UINTMAX_C(c) __UINTMAX_C(c)CGU_BASE_VADC_CLK_AUTOBLOCK_SHIFT (11)__LDBL_MIN_10_EXP__ (-307)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)__FLT_HAS_QUIET_NAN__ 1__GCC_ATOMIC_CHAR_LOCK_FREE 2UART_LOAD_DLL(div) ((div) & 0xFF)CGU_PLL1_CTRL_PD (1 << CGU_PLL1_CTRL_PD_SHIFT)__LFRACT_EPSILON__ 0x1P-31LRCGU_PLLAUDIO_FRAC MMIO32(CGU_BASE + 0x03C)lcr_configCGU_OUTCLK_22_CTRL MMIO32(CGU_BASE + 0x0B4)__ARM_SIZEOF_MINIMAL_ENUM 1UINT_FAST8_MAX __UINT_FAST8_MAX__UART_SYNCCTRL_SYNC (1 << 0)__FLT32X_NORM_MAX__ 1.7976931348623157e+308F32x__arm__ 1INT_FAST64_MAXCGU_BASE_SSP0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT)uart_read__FLT32_MIN_10_EXP__ (-37)MMIO64(addr) (*(volatile uint64_t *)(addr))CGU_PLL1_CTRL_MSEL(x) ((x) << CGU_PLL1_CTRL_MSEL_SHIFT)CGU_PLL0USB_MDIV_SELI_SHIFT (22)__ARM_FP16_FORMAT_ALTERNATIVE__LDBL_NORM_MAX__ 1.7976931348623157e+308LUSART3_BASE (PERIPH_BASE_APB2 + 0x02000)CGU_BASE_USB0_CLK_CLK_SEL_SHIFT (24)__BIGGEST_ALIGNMENT__ 8INT8_C(c) __INT8_C(c)CGU_BASE_UART2_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART2_CLK_CLK_SEL_SHIFT)__TA_IBIT__ 64CGU_PLL0USB_NP_DIV_NDEC_SHIFT (12)__FLT32_MIN__ 1.1754943508222875e-38F32uart_parity_tPERIPH_BASE_AHB (0x40000000U)CGU_IDIVC_CTRL_IDIV_SHIFT (2)CGU_XTAL_OSC_CTRL_HF (1 << CGU_XTAL_OSC_CTRL_HF_SHIFT)__ARM_FEATURE_QRDMXCGU_PLL0USB_MDIV_SELR_MASK (0xf << CGU_PLL0USB_MDIV_SELR_SHIFT)CGU_BASE_M4_CLK_CLK_SEL_SHIFT (24)__ARM_ARCH_ISA_THUMB 2__LONG_LONG_MAX__ 0x7fffffffffffffffLLUART_FIFOLVL_TX(n) ((uint32_t)(((n)>>8)&0x0F))__WINT_WIDTH__ 32UART_SYNCCTRL_CSCEN (1 << 4)SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__CGU_BASE_CGU_OUT0_CLK MMIO32(CGU_BASE + 0x0C4)UART_LCR_WLEN6 (1 << 0)CGU_BASE_USB0_CLK_PD (1 << CGU_BASE_USB0_CLK_PD_SHIFT)BIT11 (1<<11)UINT_LEAST16_MAX__UFRACT_IBIT__ 0__ARM_32BIT_STATE 1_GCC_STDINT_H __INT8_C(c) c__LFRACT_IBIT__ 0SIG_ATOMIC_MIN __SIG_ATOMIC_MIN__UART_FCR_DMAMODE_SEL (1 << 3)__SIZEOF_INT__ 4INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)CGU_BASE_CGU_OUT1_CLK_CLK_SEL(x) ((x) << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT)__DBL_MIN_EXP__ (-1021)__LDBL_HAS_DENORM__ 1INT_FAST32_MIN (-INT_FAST32_MAX - 1)GPIO_GROUP1_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x09000)UART_LCR_BITMASK ((uint8_t)(0xFF))CGU_PLL1_STAT_LOCK (1 << CGU_PLL1_STAT_LOCK_SHIFT)__FLT32_DIG__ 6INT_LEAST16_MAXCGU_BASE_M4_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_M4_CLK_CLK_SEL_SHIFT)CGU_PLL0USB_STAT_LOCK (1 << CGU_PLL0USB_STAT_LOCK_SHIFT)CGU_IDIVD_CTRL_PD (1 << CGU_IDIVD_CTRL_PD_SHIFT)BIT15 (1<<15)BACKUP_REG_BASE (0x40041000U)CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK (1 << CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_SHIFT)CGU_PLL0AUDIO_CTRL_DIRECTI (1 << CGU_PLL0AUDIO_CTRL_DIRECTI_SHIFT)UART_SRC_PLL1 0x09CGU_IDIVC_CTRL_AUTOBLOCK (1 << CGU_IDIVC_CTRL_AUTOBLOCK_SHIFT)BIT21 (1<<21)__HAVE_SPECULATION_SAFE_VALUE 1GPIO_GROUP0_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x08000)uart_read_timeoutINT32_MAXCGU_PLL0AUDIO_CTRL_DIRECTO (1 << CGU_PLL0AUDIO_CTRL_DIRECTO_SHIFT)__ACCUM_MIN__ (-0X1P15K-0X1P15K)uart_databit_tCGU_BASE_SDIO_CLK MMIO32(CGU_BASE + 0x090)UART_SRC_PLL0AUDIO 0x08__ARM_FEATURE_CRYPTOCGU_IDIVB_CTRL_CLK_SEL(x) ((x) << CGU_IDIVB_CTRL_CLK_SEL_SHIFT)__INT_LEAST32_TYPE__ long intCGU_BASE_LCD_CLK_CLK_SEL(x) ((x) << CGU_BASE_LCD_CLK_CLK_SEL_SHIFT)CGU_PLL1_CTRL_PSEL_MASK (0x3 << CGU_PLL1_CTRL_PSEL_SHIFT)CGU_PLL0AUDIO_MDIV_MDEC_MASK (0x1ffff << CGU_PLL0AUDIO_MDIV_MDEC_SHIFT)UART_PARITY_NONECGU_BASE_APB1_CLK_CLK_SEL_SHIFT (24)BIT19 (1<<19)__UINT_LEAST64_MAX__ 0xffffffffffffffffULLCGU_BASE_CGU_OUT0_CLK_PD (1 << CGU_BASE_CGU_OUT0_CLK_PD_SHIFT)__FRACT_IBIT__ 0I2C1_BASE (PERIPH_BASE_APB3 + 0x00000)UINT_LEAST64_MAX__FLT64_IS_IEC_60559__ 2CGU_SRC_IDIVA 0x0CBIT25 (1<<25)__ORDER_LITTLE_ENDIAN__ 1234SIZE_MAX __SIZE_MAX____FLT_NORM_MAX__ 3.4028234663852886e+38Flong long unsigned intUART_CGU_BASE_CLK_SEL_SHIFT 24__FLT_MIN_10_EXP__ (-37)BIT31 (1<<31)CGU_BASE_USB0_CLK MMIO32(CGU_BASE + 0x060)__ULACCUM_IBIT__ 32UART_NO_ERROR__SHRT_MAX__ 0x7fff__LDBL_IS_IEC_60559__ 2UART_LOAD_DLM(div) (((div) >> 8) & 0xFF)__ULLACCUM_EPSILON__ 0x1P-32ULLK__APCS_32__ 1__DQ_FBIT__ 63INT_LEAST64_MAX__SACCUM_IBIT__ 8CGU_BASE_SSP1_CLK_AUTOBLOCK (1 << CGU_BASE_SSP1_CLK_AUTOBLOCK_SHIFT)UART_LCR_PARITY_EN (1 << 3)__UHQ_IBIT__ 0CGU_BASE_SPI_CLK_CLK_SEL(x) ((x) << CGU_BASE_SPI_CLK_CLK_SEL_SHIFT)INT_LEAST8_MINCGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT (24)CGU_BASE_SDIO_CLK_AUTOBLOCK (1 << CGU_BASE_SDIO_CLK_AUTOBLOCK_SHIFT)BIT29 (1<<29)__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1__INT_FAST16_TYPE__ intUART_ACR_START (1 << 0)INT64_C__ULFRACT_MAX__ 0XFFFFFFFFP-32ULR__UINT_LEAST16_TYPE__ short unsigned intINT_FAST16_MIN (-INT_FAST16_MAX - 1)__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK__CHAR16_TYPE__ short unsigned intUART_LSR_BITMASK ((uint8_t)(0xFF))__FLT32X_DIG__ 15CGU_BASE_SSP0_CLK_CLK_SEL(x) ((x) << CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT)__UTQ_FBIT__ 128UART_LCR_NO_PARITY (0 << 3)CGU_PLL0AUDIO_CTRL_MOD_PD_SHIFT (14)CGU_BASE_USB1_CLK_AUTOBLOCK_SHIFT (11)__FINITE_MATH_ONLY__ 0__INT_FAST16_MAX__ 0x7fffffffUART2_NUMCGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT (24)UART_LCR_TWO_STOPBIT (1 << 2)CGU_BASE_UART2_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART2_CLK_CLK_SEL_SHIFT)PTRDIFF_MAX __PTRDIFF_MAX____SIZEOF_SHORT__ 2CGU_BASE_VADC_CLK_PD (1 << CGU_BASE_VADC_CLK_PD_SHIFT)CGU_IDIVA_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVA_CTRL_CLK_SEL_SHIFT)CGU_BASE_SAFE_CLK MMIO32(CGU_BASE + 0x05C)CGU_PLL0USB_CTRL_DIRECTI (1 << CGU_PLL0USB_CTRL_DIRECTI_SHIFT)__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKCGU_BASE_M4_CLK_AUTOBLOCK (1 << CGU_BASE_M4_CLK_AUTOBLOCK_SHIFT)CGU_PLL1_CTRL_BYPASS_SHIFT (1)UART_SRC_IDIVB 0x0DCGU_IDIVE_CTRL_IDIV_SHIFT (2)UINT_FAST32_MAX __UINT_FAST32_MAX____ULFRACT_MIN__ 0.0ULRuart_error_tCGU_BASE_UART0_CLK MMIO32(CGU_BASE + 0x09C)__DQ_IBIT__ 0__ARM_BF16_FORMAT_ALTERNATIVECGU_IDIVA_CTRL_IDIV(x) ((x) << CGU_IDIVA_CTRL_IDIV_SHIFT)CGU_PLL0USB_MDIV_SELR_SHIFT (28)SSP0_BASE (PERIPH_BASE_APB0 + 0x03000)UART_THR_MASKBIT ((uint8_t)0xFF)UART_RBR(port) MMIO32((port) + 0x000)QEI_BASE (PERIPH_BASE_APB2 + 0x06000)WCHAR_MINCGU_SRC_ENET_RX 0x02BEGIN_DECLS CGU_IDIVD_CTRL_IDIV_SHIFT (2)CGU_PLL1_CTRL_CLK_SEL_SHIFT (24)CGU_BASE_PHY_RX_CLK_PD (1 << CGU_BASE_PHY_RX_CLK_PD_SHIFT)UART_ACR_ABEOINT_CLR (1 << 8)CGU_BASE_UART1_CLK_PD (1 << CGU_BASE_UART1_CLK_PD_SHIFT)CGU_BASE_UART3_CLK MMIO32(CGU_BASE + 0x0A8)__UTQ_IBIT__ 0INT_FAST32_MAX __INT_FAST32_MAX____SA_FBIT__ 15UART_FCR_TRG_LEV3 (3 << 6)__FLT32X_MAX__ 1.7976931348623157e+308F32xCGU_PLL0USB_STAT_LOCK_SHIFT (0)__ARM_EABI__ 1CGU_PLL0USB_STAT_FR (1 << CGU_PLL0USB_STAT_FR_SHIFT)__UACCUM_IBIT__ 16INT16_MININTPTR_MIN__FLT_IS_IEC_60559__ 2__THUMBEL__ 1CGU_BASE_USB0_CLK_AUTOBLOCK (1 << CGU_BASE_USB0_CLK_AUTOBLOCK_SHIFT)__ARM_FEATURE_DSP 1CGU_SRC_PLL0AUDIO 0x08CGU_PLL1_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL1_CTRL_CLK_SEL_SHIFT)CGU_BASE_UART3_CLK_CLK_SEL_SHIFT (24)CGU_BASE_SPIFI_CLK MMIO32(CGU_BASE + 0x070)__QQ_IBIT__ 0CGU_IDIVC_CTRL MMIO32(CGU_BASE + 0x050)CGU_PLL0AUDIO_NP_DIV MMIO32(CGU_BASE + 0x038)CGU_BASE_VADC_CLK_CLK_SEL_SHIFT (24)data_nb_bitsUART_RX_NO_DATA__LLACCUM_FBIT__ 31CGU_BASE_UART2_CLK_PD_SHIFT (0)UART_RBR_MASKBIT ((uint8_t)0xFF)__UINTMAX_TYPE__ long long unsigned intCGU_PLL1_CTRL_AUTOBLOCK (1 << CGU_PLL1_CTRL_AUTOBLOCK_SHIFT)CGU_BASE_PHY_TX_CLK_AUTOBLOCK_SHIFT (11)__USQ_IBIT__ 0CGU_BASE_USB1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_USB1_CLK_CLK_SEL_SHIFT)UART_HDEN(port) MMIO32((port) + 0x040)__ARM_FEATURE_NUMERIC_MAXMIN__INTMAX_TYPE__ long long intCGU_BASE_UART0_CLK_PD (1 << CGU_BASE_UART0_CLK_PD_SHIFT)__GCC_ATOMIC_INT_LOCK_FREE 2CGU_IDIVC_CTRL_CLK_SEL(x) ((x) << CGU_IDIVC_CTRL_CLK_SEL_SHIFT)CGU_BASE_SPI_CLK_AUTOBLOCK_SHIFT (11)__UINT_FAST32_MAX__ 0xffffffffUINTMAX_MAXUART_LCR_WLEN5 (0 << 0)TIMER2_BASE (PERIPH_BASE_APB2 + 0x03000)CGU_PLL0AUDIO_CTRL_DIRECTI_SHIFT (2)CGU_PLL1_CTRL_BYPASS (1 << CGU_PLL1_CTRL_BYPASS_SHIFT)__ARM_FEATURE_FP16_SCALAR_ARITHMETIC__USACCUM_EPSILON__ 0x1P-8UHK__DBL_HAS_QUIET_NAN__ 1CGU_PLL1_CTRL_MSEL_SHIFT (16)UART_THR(port) MMIO32((port) + 0x000)__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRINT32_CCGU_BASE_CGU_OUT1_CLK_PD (1 << CGU_BASE_CGU_OUT1_CLK_PD_SHIFT)CGU_BASE_SSP0_CLK_AUTOBLOCK_SHIFT (11)CGU_PLL0AUDIO_NP_DIV_NDEC_MASK (0x3ff << CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT)UART_IER_THREINT_EN (1 << 1)INT64_MIN__SACCUM_MAX__ 0X7FFFP-7HK__INTPTR_TYPE__ intUINT8_C__UINTPTR_TYPE__ unsigned intCGU_BASE_APB1_CLK_AUTOBLOCK (1 << CGU_BASE_APB1_CLK_AUTOBLOCK_SHIFT)CGU_IDIVC_CTRL_IDIV_MASK (0xf << CGU_IDIVC_CTRL_IDIV_SHIFT)UINT16_C__REGISTER_PREFIX__ __FLT32_MAX__ 3.4028234663852886e+38F32__DBL_DIG__ 15__ULFRACT_EPSILON__ 0x1P-32ULRCGU_BASE_LCD_CLK_PD_SHIFT (0)__SIZEOF_SIZE_T__ 4PMC_BASE (0x40042000U)uint16_t__INT64_C(c) c ## LLCGU_IDIVB_CTRL_IDIV(x) ((x) << CGU_IDIVB_CTRL_IDIV_SHIFT)CGU_PLL0USB_NP_DIV_NDEC_MASK (0x3ff << CGU_PLL0USB_NP_DIV_NDEC_SHIFT)CGU_BASE_SSP1_CLK_AUTOBLOCK_SHIFT (11)CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ (1 << CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_SHIFT)UART1_BASE (PERIPH_BASE_APB0 + 0x02000)__LDBL_MIN__ 2.2250738585072014e-308LCGU_PLL0AUDIO_NP_DIV_NDEC(x) ((x) << CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT)__ARM_FEATURE_CDE__ACCUM_IBIT__ 16CGU_BASE_SPIFI_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT)CGU_PLL1_CTRL_PD_SHIFT (0)CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT (24)CGU_BASE_USB1_CLK_CLK_SEL_SHIFT (24)CGU_BASE_APB3_CLK_CLK_SEL_SHIFT (24)CGU_PLL0AUDIO_MDIV MMIO32(CGU_BASE + 0x034)CGU_BASE_OUT_CLK_AUTOBLOCK_SHIFT (11)CGU_LPC43XX_CGU_H short intCGU_BASE_APLL_CLK_AUTOBLOCK_SHIFT (11)CGU_BASE_APB1_CLK_PD (1 << CGU_BASE_APB1_CLK_PD_SHIFT)CGU_BASE_USB1_CLK_AUTOBLOCK (1 << CGU_BASE_USB1_CLK_AUTOBLOCK_SHIFT)__UINT16_C(c) cCGU_OUTCLK_23_CTRL MMIO32(CGU_BASE + 0x0B8)CGU_PLL0AUDIO_CTRL_CLK_SEL(x) ((x) << CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT)__UDA_IBIT__ 32UART_IER(port) MMIO32((port) + 0x004)UINT_LEAST32_MAXCGU_BASE_APLL_CLK_PD_SHIFT (0)UART_SCR_BIMASK ((uint8_t)(0xFF))BIT2 (1<<2)__ATOMIC_RELAXED 0__ARM_FEATURE_COPROCCGU_BASE_VADC_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_VADC_CLK_CLK_SEL_SHIFT)__DBL_HAS_INFINITY__ 1UINT_LEAST64_MAX __UINT_LEAST64_MAX____SIG_ATOMIC_MAX__ 0x7fffffffUINT_LEAST32_MAX __UINT_LEAST32_MAX____FLT64_MANT_DIG__ 53UART_LCR_PARITY_EVEN (1 << 4)LPC43XX_M4 1UART_FCR_BITMASK ((uint8_t)(0xCF))BIT5 (1<<5)CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT (24)BIT1 (1<<1)INT8_CINT_LEAST32_MAX__USES_INITFINI__ 1I2S1_BASE (PERIPH_BASE_APB1 + 0x03000)INTMAX_MAX __INTMAX_MAX____DBL_DECIMAL_DIG__ 17CGU_BASE_SSP1_CLK_PD_SHIFT (0)BIT8 (1<<8)UART_LSR_RDR (1 << 0)CGU_BASE_SSP1_CLK MMIO32(CGU_BASE + 0x098)__ULACCUM_FBIT__ 32INT16_C(c) __INT16_C(c)CGU_BASE_LCD_CLK_AUTOBLOCK (1 << CGU_BASE_LCD_CLK_AUTOBLOCK_SHIFT)CGU_BASE_LCD_CLK MMIO32(CGU_BASE + 0x088)CGU_BASE_CGU_OUT1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT)__INT16_MAX__ 0x7fffUART_FDR(port) MMIO32((port) + 0x028)CGU_BASE_PERIPH_CLK MMIO32(CGU_BASE + 0x064)CGU_BASE_SAFE_CLK_AUTOBLOCK_SHIFT (11)CGU_IDIVA_CTRL_CLK_SEL_SHIFT (24)CGU_XTAL_OSC_CTRL_ENABLE (1 << CGU_XTAL_OSC_CTRL_ENABLE_SHIFT)__INT_WIDTH__ 32__ARM_FEATURE_SIMD32 1UART_LCR_PARITY_SP_0 ((1 << 5) | (1 << 4))CGU_IDIVA_CTRL_AUTOBLOCK_SHIFT (11)CGU_BASE_UART1_CLK MMIO32(CGU_BASE + 0x0A0)__QQ_FBIT__ 7RITIMER_BASE (PERIPH_BASE_APB2 + 0x00000)CGU_SRC_IDIVD 0x0F__SIG_ATOMIC_WIDTH__ 32CGU_IDIVC_CTRL_CLK_SEL_SHIFT (24)__FLT64_EPSILON__ 2.2204460492503131e-16F64CGU_BASE_UART1_CLK_PD_SHIFT (0)CGU_BASE_UART1_CLK_AUTOBLOCK_SHIFT (11)__UTA_IBIT__ 64__ULLACCUM_IBIT__ 32RGU_BASE (0x40053000U)__ULLFRACT_EPSILON__ 0x1P-64ULLRfalse 0UART2 USART2_BASE__SIZEOF_WINT_T__ 4INT_LEAST64_MIN__ARM_FEATURE_UNALIGNED 1__GXX_TYPEINFO_EQUALITY_INLINE 0__LDBL_DECIMAL_DIG__ 17CGU_PLL0AUDIO_CTRL_MOD_PD (1 << CGU_PLL0AUDIO_CTRL_MOD_PD_SHIFT)UART1_NUM__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)__INT_FAST8_MAX__ 0x7fffffff__FLT32_HAS_DENORM__ 1CGU_IDIVC_CTRL_IDIV(x) ((x) << CGU_IDIVC_CTRL_IDIV_SHIFT)__FLT32X_HAS_DENORM__ 1CGU_IDIVB_CTRL_IDIV_MASK (0xf << CGU_IDIVB_CTRL_IDIV_SHIFT)__ULLACCUM_MIN__ 0.0ULLK__FLT32_EPSILON__ 1.1920928955078125e-7F32CGU_IDIVE_CTRL_IDIV(x) ((x) << CGU_IDIVE_CTRL_IDIV_SHIFT)CGU_IDIVA_CTRL_CLK_SEL(x) ((x) << CGU_IDIVA_CTRL_CLK_SEL_SHIFT)CGU_PLL0AUDIO_STAT MMIO32(CGU_BASE + 0x02C)CGU_PLL0USB_MDIV_SELI(x) ((x) << CGU_PLL0USB_MDIV_SELI_SHIFT)UART_IIR_ABTO_INT (1 << 9)UART_IIR_INTID_RDA (2 << 1)__ARM_ASM_SYNTAX_UNIFIED__ 1CGU_PLL0AUDIO_MDIV_MDEC(x) ((x) << CGU_PLL0AUDIO_MDIV_MDEC_SHIFT)UART_STOPBIT_1UART_STOPBIT_2__UINT32_TYPE__ long unsigned intINTPTR_MAX __INTPTR_MAX____ARM_FEATURE_DOTPRODCGU_IDIVE_CTRL MMIO32(CGU_BASE + 0x058)RTC_BASE (0x40046000U)UART_SCICTRL(port) MMIO32((port) + 0x048)data_nb_stopCGU_PLL1_CTRL_NSEL_SHIFT (12)UART_OSR(port) MMIO32((port) + 0x02C)CGU_PLL0AUDIO_CTRL_CLKEN (1 << CGU_PLL0AUDIO_CTRL_CLKEN_SHIFT)__ULLFRACT_MIN__ 0.0ULLR_STDBOOL_H CGU_FREQ_MON_MEAS (1 << CGU_FREQ_MON_MEAS_SHIFT)AES_BASE (0x400F1000U)__UDQ_IBIT__ 0__GCC_CONSTRUCTIVE_SIZE 64CGU_BASE_VADC_CLK_AUTOBLOCK (1 << CGU_BASE_VADC_CLK_AUTOBLOCK_SHIFT)__LLFRACT_IBIT__ 0CGU_IDIVB_CTRL_AUTOBLOCK (1 << CGU_IDIVB_CTRL_AUTOBLOCK_SHIFT)UART_RX_DATA_READYuint32_tBIT12 (1<<12)UART_SCICTRL_NACKDIS (1 << 1)__SACCUM_EPSILON__ 0x1P-7HK__GCC_ASM_FLAG_OUTPUTS__ 1uart_mulvalCGU_BASE_APLL_CLK_CLK_SEL(x) ((x) << CGU_BASE_APLL_CLK_CLK_SEL_SHIFT)__ARM_FP 4CGU_BASE_LCD_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_LCD_CLK_CLK_SEL_SHIFT)__UINT_FAST16_TYPE__ unsigned intCGU_BASE_SAFE_CLK_AUTOBLOCK (1 << CGU_BASE_SAFE_CLK_AUTOBLOCK_SHIFT)__UHA_IBIT__ 8UART_ACR_AUTO_RESTART (1 << 2)__ACCUM_EPSILON__ 0x1P-15K__ULACCUM_EPSILON__ 0x1P-32ULKUART_TER(port) MMIO32((port) + 0x05C)__LDBL_DIG__ 15CGU_BASE_SSP1_CLK_PD (1 << CGU_BASE_SSP1_CLK_PD_SHIFT)UART_LSR_OE (1 << 1)UINT64_C__SIZE_WIDTH__ 32SIG_ATOMIC_MAXBIT16 (1<<16)__WINT_MIN__ 0UINT_LEAST16_MINUART_SRC_IDIVE 0x10__FLT64_DIG__ 15UART_LCR(port) MMIO32((port) + 0x00C)BIT22 (1<<22)__INT_LEAST8_WIDTH__ 8CGU_PLL0USB_CTRL MMIO32(CGU_BASE + 0x020)UART_IER_RLSINT_EN (1 << 2)CGU_BASE_PHY_TX_CLK_CLK_SEL(x) ((x) << CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT)__INT_LEAST16_TYPE__ short intCGU_PLL0USB_NP_DIV MMIO32(CGU_BASE + 0x028)UART_ICR_PULSEDIV(n) ((uint32_t)(((n)&0x07)<<3))CGU_PLL0USB_CTRL_DIRECTO_SHIFT (3)__DBL_MAX__ ((double)1.7976931348623157e+308L)CGU_SRC_IDIVC 0x0EINT32_MIN__LLFRACT_FBIT__ 63__FLT32_HAS_INFINITY__ 1UINTMAX_CUART_DLM(port) MMIO32((port) + 0x004)CGU_PLL0AUDIO_CTRL_FRM_SHIFT (6)CGU_PLL0USB_CTRL_CLK_SEL(x) ((x) << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT)INT_FAST16_MAX __INT_FAST16_MAX____ARMEL__ 1UART_FDR_DIVADDVAL(n) ((uint32_t)((n)&0x0F))__UINTPTR_MAX__ 0xffffffffUUART_SYNCCTRL_CCCLR (1 << 6)__HQ_FBIT__ 15__bool_true_false_are_defined 1USART2_BASE (PERIPH_BASE_APB2 + 0x01000)CGU_BASE_UART2_CLK MMIO32(CGU_BASE + 0x0A4)BIT26 (1<<26)__SIZE_MAX__ 0xffffffffUCGU_BASE_UART0_CLK_CLK_SEL_SHIFT (24)CGU_BASE_SPIFI_CLK_PD_SHIFT (0)UART_DLL(port) MMIO32((port) + 0x000)UART_ICR_FIXPULSE_EN (1 << 2)CGU_BASE_CGU_OUT0_CLK_PD_SHIFT (0)__ARM_ARCH__LONG_MAX__ 0x7fffffffLMCPWM_BASE (PERIPH_BASE_APB1 + 0x00000)CGU_BASE_CGU_OUT0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT)LPC43XX_MEMORYMAP_H __ARM_FEATURE_LDREX 7UART_PARITY_SP_0PTRDIFF_MAXCGU_BASE_APB3_CLK MMIO32(CGU_BASE + 0x084)CGU_PLL0USB_MDIV_SELP_SHIFT (17)__LLFRACT_EPSILON__ 0x1P-63LLRCGU_PLL0USB_NP_DIV_NDEC(x) ((x) << CGU_PLL0USB_NP_DIV_NDEC_SHIFT)__SFRACT_MAX__ 0X7FP-7HR__FLT32X_MANT_DIG__ 53CGU_BASE_APB1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_APB1_CLK_CLK_SEL_SHIFT)uart_val__WCHAR_WIDTH__ 32WINT_MAX__INT16_C(c) cUART1_IIR_INTID_MODEM (0 << 1)UART1 UART1_BASEWCHAR_MAX __WCHAR_MAX__UART_LCR_ONE_STOPBIT (0 << 2)UART_IIR_INTID_THRE (1 << 1)UART_IIR_INTID_MASK (7 << 1)__ATOMIC_ACQ_REL 4ADC1_BASE (PERIPH_BASE_APB3 + 0x04000)__INT32_TYPE__ long int__DBL_MIN_10_EXP__ (-307)dataCGU_BASE_PERIPH_CLK_PD_SHIFT (0)CGU_BASE_LCD_CLK_CLK_SEL_SHIFT (24)CGU_BASE_VADC_CLK MMIO32(CGU_BASE + 0x08C)__FLT32_NORM_MAX__ 3.4028234663852886e+38F32UINT64_C(c) __UINT64_C(c)CGU_BASE_UART3_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART3_CLK_CLK_SEL_SHIFT)CGU_PLL0AUDIO_CTRL_PD (1 << CGU_PLL0AUDIO_CTRL_PD_SHIFT)CGU_BASE_USB1_CLK_PD (1 << CGU_BASE_USB1_CLK_PD_SHIFT)__UINTMAX_MAX__ 0xffffffffffffffffULL__DBL_MANT_DIG__ 53__ULFRACT_IBIT__ 0INT_FAST16_MAXUART_CGU_AUTOBLOCK_CLOCK_BIT 11__INT_MAX__ 0x7fffffff__INT_LEAST64_TYPE__ long long intUART_TER_TXEN (1 << 0)__ARM_FEATURE_CDE_COPROCCGU_PLL0USB_CTRL_BYPASS (1 << CGU_PLL0USB_CTRL_BYPASS_SHIFT)UART_SRC_ENET_TX 0x03UINT32_CGCC: (15:12.2.rel1-1) 12.2.1 20221205 | A  2A A3aeabi)7E-M M  "      .0 "$&(*,25f.]14 2uart.c$t$dwm4.0.ac8f3cbd7733ee78183be95102ca936awm4.common.h.21.c9066c2f6b12c71b40226ea6107829a4wm4.stdint.h.29.6d480f4ba0f60596e88234283d42444fwm4.stdbool.h.29.4a1c88fe569adb8d03217dd16982ca34wm4.common.h.67.5c568a1f62c8e726909b04e29f9e1fc0wm4.memorymap.h.22.395ffb693017d551ed93d11c39ba4361wm4.uart.h.29.91cd6c3f394a9fd992df7cfff7c074edwm4.cgu.h.37.c480a83e7590bba775f2472229e8edb0uart_initdummy_readuart_rx_data_readyuart_readuart_read_timeoutuart_write6 "&-4;BGTYfkx (1:CMdjq6 #(26;HRV[einx| $(-7;AHS`jns}  F n      -Pq  ( 0   &$-3<B K!RX^djpv| #)/5;AGMSY_ekqw} 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