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HPLL VCO=%u kHz, CFGC=0x%04x [drm] *ERROR* Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x [drm] *ERROR* Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x drm_WARN_ON(__intel_de_read(_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display)), ((const i915_reg_t){ .reg = (0x180000 + 0x650C) })) & (1 << 27))drm_WARN_ON((val & (1 << 30)) == 0)drm_WARN_ON((val & ((1 << ((0) * 6 + 5)) | (1 << ((0) * 6 + 4)) | (1 << ((0) * 6)))) != (1 << ((0) * 6)))cdctl & ((u32)((((int)(sizeof(struct { int:(-!!(__builtin_choose_expr((sizeof(int) == sizeof(*(8 ? ((void *)((long)((26) > (27)) * 0l)) : (int *)8))), (26) > (27), false))); }))) + (((~((0UL))) << (26)) & (~((0UL)) >> (64 - 1 - (27))))) + ((int)(sizeof(struct { int:(-!!((sizeof(int) == sizeof(*(8 ? ((void *)((long)(27) * 0l)) : (int *)8))) && (sizeof(int) == sizeof(*(8 ? ((void *)((long)(26) * 0l)) : (int *)8))) && ((26) < 0 || (27) > 31 || (26) > (27)))); })))))drm_WARN_ON_ONCE(!display->funcs.cdclk->set_cdclk)%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d %s %s: [drm] cdclk state doesn't match! [drm] *ERROR* timeout waiting for FREQ change request ack [drm] *ERROR* timeout waiting for CDCLK PLL unlock [drm] *ERROR* timeout waiting for CDCLK PLL lock [drm] *ERROR* timeout waiting for DE PLL unlock [drm] *ERROR* timeout waiting for DE PLL lock drm_WARN_ON(!new_cdclk_state->base.changed)drm_WARN_ON(cdclk_pll_is_unknown(a->vco))Can change cdclk via crawling and squashing Can change cdclk via squashing Can change cdclk via crawling Can change cdclk cd2x divider with pipe %c active Modeset required for cdclk change New cdclk calculated to be logical %u kHz, actual %u kHz New voltage level calculated to be logical %u, actual %u drm_WARN_ON(vco != 8100000 && vco != 8640000)[drm] *ERROR* Failed to inform PCU about cdclk change (err %d, freq %d) drm_WARN_ON(old_div != new_div)drm_WARN_ON(mid_cdclk_config->cdclk < ({ __auto_type __UNIQUE_ID_x_854 = (old_cdclk_config->cdclk); __auto_type __UNIQUE_ID_y_855 = (new_cdclk_config->cdclk); do { __attribute__((__noreturn__)) extern void __compiletime_assert_856(void) __attribute__((__error__("min""(""old_cdclk_config->cdclk"", ""new_cdclk_config->cdclk"") signedness error"))); if (!(!(!(((((typeof(__UNIQUE_ID_x_854))(-1)) < ( typeof(__UNIQUE_ID_x_854))1) ? (2 + (__builtin_constant_p((long long)(__UNIQUE_ID_x_854) >= 0) && ((long long)(__UNIQUE_ID_x_854) >= 0))) : (1 + 2 * (sizeof(__UNIQUE_ID_x_854) < 4))) & ((((typeof(__UNIQUE_ID_y_855))(-1)) < ( typeof(__UNIQUE_ID_y_855))1) ? (2 + (__builtin_constant_p((long long)(__UNIQUE_ID_y_855) >= 0) && ((long long)(__UNIQUE_ID_y_855) >= 0))) : (1 + 2 * (sizeof(__UNIQUE_ID_y_855) < 4))))))) __compiletime_assert_856(); } while (0); ((__UNIQUE_ID_x_854) < (__UNIQUE_ID_y_855) ? (__UNIQUE_ID_x_854) : (__UNIQUE_ID_y_855)); }))drm_WARN_ON(mid_cdclk_config->cdclk > display->cdclk.max_cdclk_freq)drm_WARN_ON(cdclk_squash_waveform(display, mid_cdclk_config->cdclk) != mid_waveform)[drm] *ERROR* PCode CDCLK freq set failed, (err %d, freq %d) drm_WARN_ON_ONCE(IS_PLATFORM(dev_priv, INTEL_SKYLAKE) && vco == 8640000)[drm] *ERROR* Failed to inform PCU about cdclk change (%d) [drm] *ERROR* Couldn't disable DPLL0 [drm] *ERROR* DPLL0 not locked Sanitizing cdclk programmed by pre-os [drm] *ERROR* timed out waiting for CDclk change %s %s: [drm] trying to change cdclk frequency with cdclk not enabled [drm] *ERROR* failed to inform pcode about cdclk change [drm] *ERROR* Switching to FCLK failed [drm] *ERROR* Switching back to LCPLL failed drm_WARN_ON(((&_Generic(dev_priv, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(dev_priv)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(dev_priv)), const struct intel_display *: (dev_priv), struct intel_display *: (dev_priv))->info.__runtime_info)->step) == STEP_NONE)%s %s: [drm] Unknown platform. Assuming i830   p  S U v       p 1 K     x  V T   ? T   cdclkMissing case (%s == %ld) %s %s: [drm] %sdrm_WARN_ON(vco != 0)HPLL VCO %u kHz val & (7 << ((0) * 6 + 1))[hw state][sw state]dssmdividerPre changing CDCLK toPost changing CDCLK toCDCLK changeMax CD clock rate: %d kHz Max dotclock rate: %d kHz Current CDCLKhrawclki915_cdclk_infoS        0 =UaQ>Ia0 =UaQ>I(0 =UaQa2Kl6A0 =UaQ>I0 =UaQa(A  XZ9eF'rS4 ` ! "A # $ "XZ9e @~phS o@"V " "ZS "}"H"@"[J""`Z"9" "x""@"V " "KKK SK2K: KD]]]S](@l].@ ]6 S "KKK K: KD]]]@l].@ ]6  "K K: KD]@l].@ P_6 "K$K(K@KKt K ]] ]4]l@l]\@ ]l D: DKKK KDK: KD ]]]]6@l].@ ]6  " "`5K!jK!K!2K<eK<K<K< KAi915.import_ns=PWMGCC: (Debian 12.2.0-14) 12.2.0GNU&0=PTpk" 00 P,9NRc0r PD0  0 Ge@ }p ! p   u6PcKb>q | `   H<N B#Y;IWUe#u '*0`EKX[u]  (@h; L_To ` ``    x ` ` 0, < HL  \@ l |    `  @     / A S` d@ v  D@I\n|  ( 9 K Z j {       - @ N g v          2 L `  1 2+ @2* 2F 2k & `3<G 6 i 8 9)  @9    :J3 :OD S j  :     <@SDf~RW*9Ikxac-2 d!I[en}intel_cdclk.cfixed_133mhz_get_cdclkfixed_200mhz_get_cdclkfixed_266mhz_get_cdclkfixed_333mhz_get_cdclkfixed_400mhz_get_cdclkfixed_450mhz_get_cdclkbxt_calc_voltage_levelxe3lpd_calc_voltage_levelbxt_calc_cdclkbxt_calc_cdclk_pll_vcointel_pcode_notifyintel_cdclk_destroy_stateintel_cdclk_duplicate_statei915_cdclk_info_openi915_cdclk_info_showi85x_get_cdclki915gm_get_cdclki945gm_get_cdclkpnv_get_cdclkvlv_get_cdclkcdclk_squash_waveformicl_calc_voltage_levelicl_voltage_level_max_cdclk.3ehl_calc_voltage_levelehl_voltage_level_max_cdclk.2tgl_calc_voltage_leveltgl_voltage_level_max_cdclk.1rplu_calc_voltage_levelrplu_voltage_level_max_cdclk.0intel_crtc_compute_min_cdclk.part.0intel_compute_min_cdclkfixed_modeset_calc_cdclkbdw_modeset_calc_cdclkbxt_modeset_calc_cdclkvlv_modeset_calc_cdclkbxt_cdclk_ctl.isra.0skl_modeset_calc_cdclkintel_hpll_vcoelk_vco.11ctg_vco.12blb_vco.8cl_vco.10pnv_vco.9i965gm_get_cdclkdiv_3200.15div_5333.13div_4000.14g33_get_cdclkdiv_4000.6div_5333.4div_3200.7div_4800.5gm45_get_cdclkvlv_program_pfi_creditshsw_get_cdclkbdw_get_cdclkskl_get_cdclkintel_set_cdclk__already_done.16bxt_get_cdclk_bxt_set_cdclkintel_cdclk_funcsskl_set_cdclk__already_done.17vlv_set_cdclkchv_set_cdclkbdw_set_cdclki915_cdclk_info_fopsxe3lpd_cdclk_funcsxe3lpd_cdclk_tablerplu_cdclk_funcsxe2lpd_cdclk_tablemtl_cdclk_tablexe2hpd_cdclk_tabletgl_cdclk_funcsrkl_cdclk_tabledg2_cdclk_tableicl_cdclk_tableadlp_cdclk_tableehl_cdclk_funcsadlp_a_step_cdclk_tablerplu_cdclk_tablebxt_cdclk_funcsglk_cdclk_tableicl_cdclk_funcsbxt_cdclk_tablebdw_cdclk_funcsskl_cdclk_funcshsw_cdclk_funcschv_cdclk_funcsvlv_cdclk_funcsfixed_400mhz_cdclk_funcsilk_cdclk_funcsgm45_cdclk_funcsg33_cdclk_funcsi965gm_cdclk_funcspnv_cdclk_funcsi945gm_cdclk_funcsi915gm_cdclk_funcsi915g_cdclk_funcsi865g_cdclk_funcsi85x_cdclk_funcsi845g_cdclk_funcsi830_cdclk_funcs__UNIQUE_ID___addressable___SCK__preempt_schedule771.18__UNIQUE_ID___addressable___SCK__preempt_schedule769.19__UNIQUE_ID_import_ns715__UNIQUE_ID___addressable___SCK__might_resched41.20.LC1__x86_return_thunkdev_driver_string__warn_printkskl_pcode_request_dev_errkfreekmemdup_noprofsingle_openseq_printf__ref_stack_chk_guardpci_bus_read_config_word__stack_chk_failpci_read_config_wordvlv_iosf_sb_getvlv_get_hpll_vcovlv_get_cck_clockvlv_punit_readvlv_iosf_sb_put__drm_to_displayhsw_ips_min_cdclkintel_audio_min_cdclkvlv_dsi_min_cdclkintel_vdsc_min_cdclkintel_atomic_get_new_global_obj_stateintel_atomic_lock_global_stateintel_atomic_get_new_bw_stateintel_bw_min_cdclk__drm_dev_dbg__x86_indirect_thunk_rax__sw_hweight32intel_dmc_wl_getto_intel_uncoreintel_dmc_wl_putintel_psr_pauseintel_encoder_can_psrintel_audio_cdclk_change_premutex_lockmutex_unlockintel_psr_resumeintel_audio_cdclk_change_post__intel_wait_for_registerintel_crtc_for_pipeintel_crtc_wait_for_next_vblankintel_cdclk_get_cdclkintel_mdclk_cdclk_ratiointel_cdclk_clock_changedintel_cdclk_dump_configintel_cdclk_is_decreasing_laterintel_atomic_get_old_global_obj_stateintel_set_cdclk_pre_plane_updateintel_set_cdclk_post_plane_updateintel_crtc_compute_min_cdclkintel_atomic_get_cdclk_stateintel_atomic_get_global_obj_stateintel_cdclk_atomic_checkintel_plane_calc_min_cdclkintel_bw_calc_min_cdclkintel_cdclk_state_set_joined_mbusintel_cdclk_initkmalloc_caches__kmalloc_cache_noprofintel_atomic_global_obj_initintel_modeset_calc_cdclkintel_calc_active_pipesintel_atomic_serialize_global_stateintel_modeset_all_pipes_lateintel_dbuf_state_set_mdclk_cdclk_ratiointel_atomic_get_crtc_stateintel_update_max_cdclkintel_update_cdclksnb_pcode_write_timeoutintel_dbuf_mdclk_cdclk_ratio_updateintel_cdclk_init_hwintel_cdclk_uninit_hwintel_display_power_getvlv_punit_writektime_get_raw__SCT__might_reschedusleep_range_statevlv_bunit_readvlv_bunit_writeintel_display_power_put_uncheckedvlv_cck_readvlv_cck_write__preempt_countcpu_numberlocal_clock__SCT__preempt_scheduleintel_read_rawclkvlv_get_cck_clock_hplli9xx_fsb_freqintel_cdclk_debugfs_registerdebugfs_create_file_fullintel_init_cdclk_hooks__i915_to_displayseq_lseekseq_readsingle_release__SCK__preempt_schedule__SCK__might_reschedx y@xR pWyz c}    0@y)[l)M X{ (8Gx pys } y p0 p  pG p     d    ] |   ; G     1CW*pHxO Y  ayx 0  y 1C p ,Q F]q p { p` p p:j p { p p:v pH p< pN h{ pB&Z {RZv>xE O  Wy')  9 I  W  y    O!xV! h`!  h!y!x! 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