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sL'L7ff.@ATLUHLSHLHHH߉[]A\ATLUHSHLtHHH[]A\mLHސAWAVIAUATUHSL'HDL.Lqt ELHHh@HLHވlŅu]A$t-Apu"`ut[A$(tH[]A\A]A^A_ǃ`Nsff.ATUSH/HtOHHHHHtlH1HHH[]A\H}H_PHuHHHHH []A\H}LgPMt(HLHH ^L'fAWAVAUATIUSL?HLD,aDHHH}DHHDHAD%=`wB= =@ufLHLHLH[]A\A]A^A_=t?=u11=tHDH 1륾tվ눾끾wfAWAVAUATIUSL/HDL\HHH}\HH\HAC 1AsLD!HLHLH[]A\A]A^A_bfUHSHH?w HHHHH[]HHcH 1fDUHSHHHHHH[]@AWIAVAUATUHSHL'LAIHǁÀBI}HHLD$DLA )D$!AFOHLHHLH[]A\A]A^A_AWAVAUATIUHSH0L/eHHD$(1LHHHHT$HL$\HT$ HL$L\$BIHI>BHHBLAL$D!LLHHHD$(eH+uH0LH[]A\A]A^A_ff.AWAVAUIATUSHH0L?eHHD$(1LLcD$ H HD$LH0HD$BlMiVUUUL$ I A)EkDHHDLD$D$L$ LDD$!C@)LHHHD$(eH+uH0LH[]A\A]A^A_|HHt1@AWAVAUIATUHSH HHHAf`AEVAH IHI> HH LADuEEGAHHtHsHH 1[]A\A]A^A_AgADHAĄHHHBH9uBHtKH HL[]A\A]A^A_HPHBH9tD;uEGAHHtHvH>Hf` tH{H_PHuHHHH H []A\A]A^A_HIcH H IHI> HH LADZH IHI> HH LADH@IHI>@HH@LADDHLƉD$AAńt8EEGAHAAHtHsH H1[]A\A]A^A_HHD$wHAq EGAHHtHsH1D$D$Dt$HDt0Ls#EFAHHtHsH1H= IHǀHHf` H\$v AkHf` ADH1HA^AW.IPILHQRHHHLHI@HDHAdž`IdžIdžIdžIdžIdž IdžIdžIdž(Idž8Idž0Idž@IdžHIdžPIdžXIdžhIdžpIdžIdžIdžxAdž E1EHAfEAƆf` bIdžIdžIdžIdž`HHHf` wHILHf` DAAWAGAMAA@HD$t$HH$H $H9HL$t$HHt$H|$$H$HDAf` w $AAEM.AdžALD$f` w^D$jAuEAu;I(t,LMtIuH1AƆAELALAnDHHA f` (IdžLEAJ|$?AHH.@HLA1HAH []A\A]A^A_HD$HA}|$EEGAHHtHsHuP[1ABD87IdžIdžIdž`HEOAf` MDHD $D $1HAHPHHQIHNLRHHHi1|$tZ|$HEGAHHDIHLDHt HKHL$PHt$ H1t$YIdžLIdžIdžIdžCLLLL@HH$H $H9HL$@HHH|$@$$2|$1M.EHHIA$@LAHHLf` HIdžIdžHGIdž IIdžAIdžVHf`o%ALHHHEIIdžIdžIdžIdž`D$EO=APILHHAYAWAIDED$D$APHf` LH%HD$HAnIdžIdžIdžIdž`H}AGAAGHf` w`LA8PAGAAGHf` HH(HDHf` t EIdžH{HoPHuH/HHHH YD$HA tMIdžIdžIdžIdž`)L$H=`DH9tjIdžIdžIdžIdžIdž`EIdžIdžIdžIdžIdž`[Hf` (tbIdž`)DED$HmHf` AGADHf` IdžIdžIdžIdž`DHR8IdžIdžIdžIdžIdž`1Hf` u DHoIdžIdžIdžIdž`drm_WARN_ON(!pll)%s %s: [drm] %slane_countMissing case (%s == %ld) drm_WARN_ON(n_entries < 1)port_clockenableddisabled[ENCODER:%d:%s] [CRTC:%d:%s] drm_WARN_ON(ret)disablecrtc_state->pipe_bpppipepll->info->ididclockpin_assignmenttmp & (7 << 12)drm_WARN_ON_ONCE(!trans)drm_WARN_ON(ctl & (1 << 9))drm_WARN_ON(!wakeref)Using signal levels %08x drm_WARN_ON(is_mst)Retry FEC enabling tmpdrm_WARN_ON(!pll_active)valencoder->portTC (TC)non-legacyyeslegacynoportPort %c strap not detected Port %c already claimed VBT says port %c has lspcon DDI %c/PHY %cDDI %s%c/PHY %s%cDDI %c%s/PHY %s%c&dig_port->hdcp_mutexdrm_WARN_ON(port > PORT_I)drivers/gpu/drm/i915/display/intel_ddi.cconn_state->connector->connector_typedrm_WARN_ON(n_entries > (sizeof(index_to_dp_signal_levels) / sizeof((index_to_dp_signal_levels)[0]) + ((int)sizeof(struct {_Static_assert(!(!(!__builtin_types_compatible_p(typeof((index_to_dp_signal_levels)), typeof(&(index_to_dp_signal_levels)[0])))), "must be array");}))))drm_WARN_ON(dig_port->aux_wakeref)drm_WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))drm_WARN_ON(dig_port->ddi_io_wakeref)[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs Failed to set FEC_READY to %s in the sink Failed to clear FEC detected flags drm_WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))[drm] *ERROR* [CONNECTOR:%d:%s] Failed to read TMDS config: %d drm_WARN_ON(!dig_port->dp.attached_connector)[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio Failed to %s MSA_TIMING_PAR_IGNORE in the sink drm_WARN_ON(master == INVALID_TRANSCODER)[drm] *ERROR* Timeout waiting for DDI BUF %c to get active [drm] *ERROR* Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c drm_WARN_ON((pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))drm_WARN_ON(!intel_tc_port_in_legacy_mode(dig_port))No pipe for [ENCODER:%d:%s] found Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x) Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe masks: all %02x, MST %02x, 128b/132b %02x) [drm] *ERROR* [ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x) [drm] *ERROR* Timeout waiting for DDI BUF %c to get idle drm_WARN_ON(transcoder_is_dsi(cpu_transcoder))drm_WARN_ON(crtc_state->limited_color_range && crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)Quirk Increase DDI disabled time drm_WARN_ON(ddi_mode == (3 << 24))%s %s: [drm] Unsupported voltage swing/pre-emphasis level: 0x%x drm_WARN_ON_ONCE(level >= n_entries)[drm] *ERROR* Invalid I_boost value %u drm_WARN_ON(port_mask & ((((1UL))) << (other_encoder->port)))[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it [drm] *ERROR* Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c [drm] *ERROR* Timed out waiting for DP idle patterns [drm] *ERROR* Timed out waiting for ACT sent [drm] *ERROR* Timeout waiting for FEC live state to get %s Failed waiting for FEC %s to get detected: %d (status %d) [drm] *ERROR* Failed to enable FEC after retries drm_WARN_ON(crtc_state->has_pch_encoder)drm_WARN_ON(is_mst && (port == PORT_A || port == PORT_E))drm_WARN_ON(is_mst && port == PORT_A)[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio drm_WARN_ON(((&_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display))->info.__runtime_info)->ip.ver) < 9)drm_WARN_ON(port < PORT_A || port > PORT_E)drm_WARN_ON(!(intel_ddi_splitter_pipe_mask(i915) & ((((1UL))) << (pipe))))%s %s: [drm] Invalid splitter configuration, dss1=0x%08x drm_WARN_ON(crtc_state->master_transcoder != INVALID_TRANSCODER && crtc_state->sync_mode_slaves_mask)%s %s: [drm] Platform does not support DSI PORT %c / PHY %c reserved by HTI VBT says port %c is not DVI/HDMI/DP compatible, respect it SNPS PHY %c failed to calibrate, proceeding anyway Forcing DDI_A_4_LANES for port A VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s  T ] _ F     k    A   ~  %    M !  y  k *          B  a  4 ! 1 . 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!!1!I!i!!!!intel_ddi.cintel_ddi_dp_preemph_maxicl_ddi_tc_port_pll_typemtl_get_port_widthintel_ddi_compute_output_typeintel_ddi_dp_voltage_maxindex_to_dp_signal_levelsdp_tp_status_regintel_ddi_tc_encoder_shutdown_completeintel_ddi_tc_encoder_suspend_completeintel_ddi_init_dp_buf_regintel_ddi_main_link_aux_domainmain_link_aux_power_domain_getintel_ddi_get_power_domainsintel_ddi_encoder_shutdownintel_ddi_encoder_suspendintel_ddi_initial_fastset_checkintel_ddi_sync_stateintel_dp_sink_set_fec_readyintel_ddi_post_pll_disableintel_ddi_power_up_lanesintel_ddi_compute_config_lateintel_ddi_encoder_late_registerintel_ddi_hotplugintel_ddi_link_checkintel_ddi_encoder_destroyintel_ddi_encoder_resetintel_ddi_is_tcintel_ddi_disableintel_ddi_transcoder_func_reg_val_get.isra.0skl_ddi_is_clock_enabledrkl_ddi_is_clock_enabledbdw_digital_port_connectedlpt_digital_port_connectedhsw_digital_port_connecteddg1_ddi_is_clock_enabledicl_ddi_combo_is_clock_enabledjsl_ddi_tc_is_clock_enabledadls_ddi_is_clock_enabledintel_wait_ddi_buf_activeintel_ddi_config_transcoder_dp2_skl_ddi_set_iboostskl_ddi_disable_clockrkl_ddi_disable_clockdg1_ddi_disable_clockicl_ddi_combo_disable_clockjsl_ddi_tc_disable_clockadls_ddi_disable_clockicl_ddi_tc_disable_clockCSWTCH.296intel_ddi_mso_configureicl_ddi_tc_is_clock_enabledskl_ddi_enable_clockmtl_ddi_enable_d2d.isra.0bdw_transcoder_master_readouticl_ddi_tc_enable_clockicl_ddi_combo_enable_clockjsl_ddi_tc_enable_clockrkl_ddi_enable_clockadls_ddi_enable_clockdg1_ddi_enable_clockicl_program_mg_dp_modeintel_ddi_get_encoder_pipes__already_done.13__already_done.5__already_done.4hsw_set_signal_levels__already_done.9icl_mg_phy_set_signal_levels__already_done.7tgl_dkl_phy_set_signal_levels__already_done.6icl_ddi_combo_vswing_program__already_done.8icl_combo_phy_set_signal_levelsintel_ddi_read_func_ctl_dp_mstintel_ddi_read_func_ctl_dp_sstmtl_disable_ddi_bufintel_ddi_disable_fecintel_ddi_set_idle_link_trainintel_ddi_set_link_trainintel_ddi_prepare_link_retrainmtl_ddi_prepare_link_retrainintel_disable_ddi_bufintel_ddi_post_disableintel_ddi_enable_fecintel_ddi_pre_enableintel_ddi_enabletrans.0__already_done.12intel_ddi_pre_pll_enableintel_ddi_get_configicl_ddi_tc_get_configdg2_ddi_get_configmtl_ddi_get_configintel_ddi_compute_configskl_ddi_get_configbxt_ddi_get_configicl_ddi_combo_get_configdg1_ddi_get_configrkl_ddi_get_configadls_ddi_get_configintel_ddi_funcs__key.1__UNIQUE_ID___addressable___SCK__preempt_schedule976.2__UNIQUE_ID___addressable___SCK__preempt_schedule950.3__UNIQUE_ID___addressable___SCK__preempt_schedule759.10__UNIQUE_ID___addressable___SCK__preempt_schedule757.11__UNIQUE_ID_import_ns747__UNIQUE_ID___addressable___SCK__might_resched2.14.LC2__x86_return_thunkdev_driver_string__warn_printk__ref_stack_chk_guard__x86_indirect_thunk_rax__stack_chk_fail__i915_to_displayintel_tc_port_cleanupintel_encoder_link_check_flush_workintel_tc_port_suspendintel_encoder_is_tcintel_tc_port_in_tbt_alt_modeintel_dp_is_uhbrintel_psr_needs_aux_io_powerintel_aux_power_domainintel_display_power_aux_io_domainintel_display_power_getintel_dp_encoder_shutdownintel_hdmi_encoder_shutdownintel_dp_encoder_suspend__drm_dev_dbgintel_dp_initial_fastset_checkintel_tc_port_sanitize_modeintel_dp_sync_state__drm_to_displaydrm_dp_dpcd_writeintel_display_power_put_uncheckedintel_tc_port_put_linkintel_encoder_is_combointel_encoder_to_phyintel_combo_phy_power_up_lanesdrm_mode_matchintel_tc_port_link_resetintel_dp_test_phyintel_encoder_hotplugintel_dp_check_link_state_intel_modeset_lock_begin_intel_modeset_lock_loop_intel_modeset_lock_enddrm_modeset_locktry_wait_for_completiondrm_scdc_readintel_modeset_commit_pipes_dev_errintel_dp_link_checkintel_dp_encoder_flush_workintel_display_power_flush_workdrm_encoder_cleanupkfreeintel_dp_invalidate_source_ouiintel_pps_encoder_resetintel_tc_port_init_modeintel_tc_port_link_cancel_reset_workintel_hdcp_disableintel_hdmi_handle_sink_scramblingintel_psr_disableintel_edp_backlight_offintel_dp_sink_disable_decompressionhsw_ddi_disable_clockintel_dmc_wl_getto_intel_uncoreintel_dmc_wl_puthsw_ddi_is_clock_enabledktime_get_raw__SCT__might_reschedusleep_range_statemutex_lockmutex_unlockintel_encoder_to_tchsw_ddi_enable_clockintel_dkl_phy_readintel_tc_port_get_pin_assignment_maskintel_dkl_phy_writeintel_tc_port_in_legacy_modeintel_display_power_get_if_enabled__sw_hweight32intel_dp_mst_encoder_active_linksintel_ddi_get_hw_statehsw_prepare_dp_ddi_buffersintel_bios_dp_boost_levelintel_wait_ddi_buf_idle__preempt_countcpu_numberlocal_clock__SCT__preempt_schedule__const_udelayintel_ddi_set_dp_msaintel_dp_needs_vsc_sdpintel_ddi_update_pipeintel_hdmi_fastset_infoframesintel_hdcp_update_pipeintel_dp_set_infoframesintel_backlight_updatedrm_connector_update_privacy_screenintel_ddi_enable_transcoder_funcintel_ddi_config_transcoder_funcintel_ddi_disable_transcoder_funcintel_dp_mst_is_slave_transintel_has_quirkmsleepintel_dp_mst_is_master_transintel_ddi_toggle_hdcp_bitsintel_ddi_connector_get_hw_stateintel_ddi_enable_transcoder_cl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