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DA9tTAD9~lIcHH)IW HH2HtӋpHsHROHpuHLAH !xID9~KDd$1HcHH)IW HH0HtpIs LOI9HcЉH,H)H)L$HI)IHIG HL0MtiEpT$LsWLPDHt$ I4L$L$A4IcDLLT HH D$HEL9x|$HD$0eH+?H8[]A\A]A^A_6f96EHCH9$LEHD$H8HtHHWPHt7L$HT$HT$HHH L$HLD$HD$H8HtHH_PHuHHHHH HD$H8HtHH_PHuHHHHH AWAVIAUATAU1SHHtHM LH{HCxfHwSCtM~CHs 1HcHH)HH:tHRu Atc9HAŅCAHAŅt%LHL[D]A\A]A^A_HAŅu̾HAŅuHE1HHK~_IcHHSHHt?HJXHHtHHRHHtHHKAD;|P HHCpHCXHC`HC`HChEt[HSXtpHh@HuHtHvEH1LD[]A\A]A^A_t HhHUHp@sH2H ff.ATUSZHt[]A\H?nAHtHLgPMuL'LHH []A\AVAUATUSHH/XhH@@*}8fC QC HPffHAHHLbH9M $MLM $H0HHHBH9E$1pIs D HPHBH9uA|$HMuLH01HHưHBH9tFL9t*A$HsA$Hs HDD HPHBH9uA|$LHIT$HLbH9HH;[]A\A]A^fHHwjfC @ub8F@HH;@HH@HAAutHHHHH#C+HH4%HHHBH9UAD$H1[]A\A]A^1bC t VHHAAHAH;AHHAHAAE@HH;@HH@HAAuEt EvHHABHAH;BHHBHAANEE`HH;`HH`HAAuEt EC  HCHAH;CHHCHAAuEtCHlHH;lHHlHAAu EQlH:AHA!BHA!HHHACt]@HH;@HH@HAAtC 1Ҿ@H@HH;@HH@HAAPPHH;PHHPHAAEBHH;BHHBHAACHH;CHHCHAACHnHC HHBHH-BHI@H@HAHH;AHHAHAA<AH%`HH;`HH`HAA.`HPHCH@HH;@HH@HAAH3HtHvH1@HAĄuOCtIH3HtHv1H@HCtAH@HH;@HH@HAAt4H3HtHvH1`HAECH@x+H@Hs`H HH; HH HAA@r@HH;@HH@HAA`HH;`HH`HAACH3HtHv1H`HCBHq HH; HH HAA&CHH;CHHCHAACHH]H@SHHtHf{  S,8H3fwQGtftEf wHf 9fw fG   (guxɸ9g @@DCA9DS9<S94S 9,S9S9S9C9[9~[giff fV[ff.ffHNHv@f?v.v )~ Pp)ֺ~ 1f9HRv )ֺ~Pp)ֺ~1GuDH1fv-fv,R N9F9f v  ̿ff.fHHwH@HB*t HGHH8ufG HHHDHGfAWAVAUATIUSHPeHHD$H1H|$HI<$H1H|$IŽAƅHD$IEHI$HHHZH9u!I $HCHHXH9HLIH=PtHLu|AN I4$HHHLxH9u!I4$IGHHLxH9rAODA#FtIpHtLLuHLtu$LH|$LtܺAUtB~PH|$D$H|$D$HT$HeH+uCHP[]A\A]A^A_D$LD$밾LD$D$뙸ff.@AWAVAUATAUSHH@eHHD$81H$Ht$HHD$H HD$$HD$,HD$D$ =BbH3D$$ED$ADL$(HtHvPH1McMoH|$L$$H߉D$H@DAh,BlLA+hLEDD$AH;HHHH@Hߋh,Bl +hLH;HHHH@Hߋh,Bl +hLH;HHHH@Hߋh,Bl +hLH; HHHH@Hߋh,Bl +hLH; HHHH@Hߋh,Bl +hLH;HHHH@Hߋh,Bl +hLH;HHHB,@`HH;Dl$HHDH߃HH;DHHH߽`DD$ZH@AA@,EE~ CTd,`D$(HDH;DDHHADHH@HD`,ADH;DDHHDHH@HD`,ADH;1DHHDH H@HD`,ADH;DDHHDHH@HD`,ADH;DDHHDHH@HD`,ADH;1DHHHD AfH@HMg h,Bl0+h0H;HHHH@Hߋh,B,+h0H;1҉HHH߉H<$HD$8eH+uTH@[]A\A]A^A_H;HtHHoPHuH/HHHH f.AWAVAUATIUHSH_Ht HHËL+DpHH)IT$ fHHLpHLGLLLHLAiuC uC toDLHL(fHt 1DHHC8HxtNCu[]A\A]A^A_DH[]A\A]A^A_lHMLDLLff.AVAUAATUSHH3EEAIHtHvH1H@Hߋh,ŀH;HHHAEH@Hߋh,h4ŀ+h0H;HHHAExH@Hߋh,h8ŀ+h0H;HHHAEeH@Hߋh,ŀH;HHHAA'WH@Hߋh,hlŀ+hhH;HHHAA'CH@IcHLr h,l0+h0H;1҉HHHH@Hߋh,B,+h0H;1҉HHH߽`LH@D`,E~ CDm,`AHDH;DHHDHH@Hh,H;1HHH[]A\A]A^H;HtHHoPHuH/HHHH 4H;HtHHoPHuH/HHHH GH;HtHHoPHuH/HHHH ZH;HtHHoPHuH/HHHH hH;HtHHoPHuH/HHHH |DHfv1H?onoff73infoframeexpected: found: yesnocrtc_state->pipe_bppMissing case (%s == %ld) %s %s: [drm] %stmpdrm_WARN_ON(active)czclkCZ clock rate: %d kHz enabling pipe %c disabling pipe %c drm_WARN_ON(ret)drm_WARN_ON(disable_pipes)enableddisableddrm_WARN_ON(crtc->active)C10C20(expected %s, found %s)hw.enablehw.active(expected %i, found %i)cpu_transcodermst_master_transcoderhas_pch_encoderfdi_lanesfdi_m_nlane_countlane_lat_optim_maskdp_m_ndp_m2_n2output_typesframestart_delaymsa_timing_delayhw.pipe_mode.crtc_hdisplayhw.pipe_mode.crtc_htotalhw.pipe_mode.crtc_hblank_endhw.pipe_mode.crtc_hsync_starthw.pipe_mode.crtc_hsync_endhw.pipe_mode.crtc_vdisplayhw.pipe_mode.crtc_vsync_starthw.pipe_mode.crtc_vsync_endhw.pipe_mode.crtc_vtotalhw.pipe_mode.crtc_vblank_endhw.adjusted_mode.crtc_htotalhw.adjusted_mode.crtc_vtotalpixel_multiplier(%x) (expected %i, found %i)hw.adjusted_mode.flagsoutput_formathas_hdmi_sinklimited_color_rangehdmi_scramblinghdmi_high_tmds_clock_ratiohas_infoframeenhanced_framingfec_enablehas_audiobuffereldexpected: found: gmch_pfit.controlgmch_pfit.pgm_ratiosgmch_pfit.lvds_border_bitspch_pfit.force_thrupipe_src.x1pipe_src.x2pipe_src.y1pipe_src.y2pch_pfit.enabledpch_pfit.dst.x1pch_pfit.dst.x2pch_pfit.dst.y1pch_pfit.dst.y2scaler_state.scaler_idpixel_rategamma_modecgm_modecsc_modegamma_enablecsc_enablewgc_enablelinetimeips_linetimepre_csc_lutpost_csc_lutcsc.preoff[0]csc.preoff[1]csc.preoff[2]csc.coeff[0]csc.coeff[1]csc.coeff[2]csc.coeff[3]csc.coeff[4]csc.coeff[5]csc.coeff[6]csc.coeff[7]csc.coeff[8]csc.postoff[0]csc.postoff[1]csc.postoff[2]output_csc.preoff[0]output_csc.preoff[1]output_csc.preoff[2]output_csc.coeff[0]output_csc.coeff[1]output_csc.coeff[2]output_csc.coeff[3]output_csc.coeff[4]output_csc.coeff[5]output_csc.coeff[6]output_csc.coeff[7]output_csc.coeff[8]output_csc.postoff[0]output_csc.postoff[1]output_csc.postoff[2]double_wide(expected %p, found %p)shared_dpll dpll_hw_statedpll_hw_state.cx0plldsi_pll.ctrldsi_pll.divpipe_bpphw.pipe_mode.crtc_clockhw.adjusted_mode.crtc_clockport_clockmin_voltage_levelinfoframes.enableinfoframes.gcpavispdhdmidrmdp as sdpas_sdpdp vsc sdpvscsync_mode_slaves_maskmaster_transcoderjoiner_pipesdsc.config.block_pred_enabledsc.config.convert_rgbdsc.config.simple_422dsc.config.native_422dsc.config.native_420dsc.config.vbr_enabledsc.config.line_buf_depthdsc.config.bits_per_componentdsc.config.pic_widthdsc.config.pic_heightdsc.config.slice_widthdsc.config.slice_heightdsc.config.initial_dec_delaydsc.config.initial_xmit_delaydsc.config.flatness_min_qpdsc.config.flatness_max_qpdsc.config.slice_bpg_offsetdsc.config.nfl_bpg_offsetdsc.config.initial_offsetdsc.config.final_offsetdsc.config.rc_model_sizedsc.config.slice_chunk_sizedsc.config.nsl_bpg_offsetdsc.compression_enabledsc.num_streamsdsc.compressed_bpp_x16splitter.enablesplitter.link_countsplitter.pixel_overlapvrr.enablevrr.vminvrr.vmaxvrr.fliplinevrr.pipeline_fullvrr.guardbandvrr.vsync_startvrr.vsync_end(expected %lli, found %lli)cmrr.cmrr_mcmrr.cmrr_ncmrr.enablemodesetfastset[CRTC:%d:%s] not active conn_state->max_bpcfaileddrm_WARN_ON(modeset_pipes)drm_WARN_ON(update_pipes)probing SDVOB probing HDMI on SDVOB probing SDVOC probing HDMI on SDVOC ABCDEDPDSI ADSI C%s %s: [drm] %s assertion failure (expected %s, current %s) drivers/gpu/drm/i915/display/intel_display.c[drm] *ERROR* %s assertion failure (expected %s, current %s) [CRTC:%d:%s] fastset requirement not met in %s %pV [CRTC:%d:%s] mismatch in %s %pV [CRTC:%d:%s] Full modeset due to %s [CRTC:%d:%s] vblank delay (%d) exceeds max (%d) [CRTC:%d:%s] Odd pipe source width not supported with double wide pipe [CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS [CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s) drm_WARN_ON(transcoder_is_dsi(cpu_transcoder))drm_WARN_ON(expected_secondary_pipes(primary_ultrajoiner_pipes, 3) != secondary_ultrajoiner_pipes)drm_WARN_ON((primary_ultrajoiner_pipes & secondary_ultrajoiner_pipes) != 0)drm_WARN_ON((primary_uncompressed_joiner_pipes & secondary_uncompressed_joiner_pipes) != 0)drm_WARN_ON((primary_bigjoiner_pipes & secondary_bigjoiner_pipes) != 0)%s %s: [drm] Ultrajoiner pipes(%#x) should be bigjoiner pipes(%#x) %s %s: [drm] Wrong secondary ultrajoiner pipes(expected %#x, current %#x) %s %s: [drm] Uncompressed joiner pipes(%#x) and bigjoiner pipes(%#x) can't intersect %s %s: [drm] Wrong secondary bigjoiner pipes(expected %#x, current %#x) %s %s: [drm] Wrong secondary uncompressed joiner pipes(expected %#x, current %#x) %s %s: [drm] Wrong ultrajoiner secondary pipes for primary_pipe %#x (expected %#x, current %#x) %s %s: [drm] Wrong uncompressed joiner secondary pipes for primary_pipe %#x (expected %#x, current %#x) %s %s: [drm] Wrong bigjoiner secondary pipes for primary_pipe %#x (expected %#x, current %#x) %s %s: [drm] unknown pipe linked to transcoder %s drm_WARN_ON(has_edp_transcoders(enabled_transcoders) + has_dsi_transcoders(enabled_transcoders) + has_pipe_transcoders(enabled_transcoders) > 1)drm_WARN_ON(!has_dsi_transcoders(enabled_transcoders) && !is_power_of_2(enabled_transcoders))drm_WARN_ON((tmp & ((u32)(((((1UL))) << (26)) + ((int)(sizeof(struct { int:(-!!((sizeof(int) == sizeof(*(8 ? ((void *)((long)(26) * 0l)) : (int *)8))) && ((26) < 0 || (26) > 31))); })))))) == 0)%s %s: [drm] %s change in progress %s %s: [drm] transcoder %s assertion failure (expected %s, current %s) [drm] *ERROR* transcoder %s assertion failure (expected %s, current %s) drm_WARN_ON(!display->platform.i830)%s %s: [drm] pipe_off wait timed out Disabling [PLANE:%d:%s] on [CRTC:%d:%s] %s %s: [drm] %d encoders for pipe %c drm_WARN_ON(!intel_display_power_is_enabled(display, POWER_DOMAIN_DC_OFF))SSC %s by BIOS, overriding VBT which says %s drm_WARN_ON(crtc_state->limited_color_range && crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)(expected tu %i data %i/%i link %i/%i, found tu %i, data %i/%i link %i/%i)(expected 0x%08x, found 0x%08x)hw.pipe_mode.crtc_hblank_starthw.pipe_mode.crtc_vblank_starthw.adjusted_mode.crtc_hdisplayhw.adjusted_mode.crtc_hblank_starthw.adjusted_mode.crtc_hblank_endhw.adjusted_mode.crtc_hsync_starthw.adjusted_mode.crtc_hsync_endhw.adjusted_mode.crtc_vdisplayhw.adjusted_mode.crtc_vblank_starthw.adjusted_mode.crtc_vsync_starthw.adjusted_mode.crtc_vsync_endhw.adjusted_mode.crtc_vblank_endhw_state doesn't match sw_statedsc.config.scale_decrement_intervaldsc.config.scale_increment_intervaldsc.config.initial_scale_valuedsc.config.first_line_bpg_offsetdsc.config.rc_quant_incr_limit0dsc.config.rc_quant_incr_limit1dsc.config.second_line_bpg_offset[CRTC:%d:%s] modeset required [CRTC:%d:%s] async flip disallowed with joiner [PLANE:%d:%s] async flip not supported [PLANE:%d:%s] no old or new framebuffer drm_WARN_ON(intel_crtc_is_joiner_secondary(new_crtc_state))[CONNECTOR:%d:%s] Limiting display bpp to %d (EDID bpp %d, max requested bpp %d, max platform bpp %d) [CRTC:%d:%s] Link bpp limited to %d.%04d [ENCODER:%d:%s] rejecting invalid cloning configuration [ENCODER:%d:%s] config failure: %d [CRTC:%d:%s] config failure: %d [CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i drm_WARN_ON(new_crtc_state->uapi.enable)drm_WARN_ON(primary_crtc->pipe != joiner_primary_pipe(primary_crtc_state))[CRTC:%d:%s] Cannot act as joiner primary (need 0x%x as pipes, only 0x%x possible) [CRTC:%d:%s] secondary is enabled as normal CRTC, but [CRTC:%d:%s] claiming this CRTC for joiner. [CRTC:%d:%s] Used as secondary for joiner primary [CRTC:%d:%s] [CRTC:%d:%s] fastset requirement not met, forcing full modeset drm_WARN_ON(!connector_state->crtc)drm_WARN_ON(!((_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display))->info.__device_info)->has_ddi))rejecting conflicting digital port configuration [CRTC:%d:%s] watermarks are invalid [CRTC:%d:%s] atomic driver check failed [CRTC:%d:%s] Active planes cannot be in async flip drm_WARN_ON(new_crtc_state->do_async_flip && !plane->async_flip)[PLANE:%d:%s] Modifier 0x%llx does not support async flip [PLANE:%d:%s] Planar formats do not support async flips [PLANE:%d:%s] Stride cannot be changed in async flip [PLANE:%d:%s] Modifier cannot be changed in async flip [PLANE:%d:%s] Pixel format cannot be changed in async flip [PLANE:%d:%s] Rotation cannot be changed in async flip [PLANE:%d:%s] AUX_DIST cannot be changed in async flip [PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip [PLANES:%d:%s] Alpha value cannot be changed in async flip [PLANE:%d:%s] Pixel blend mode cannot be changed in async flip [PLANE:%d:%s] Color encoding cannot be changed in async flip [PLANE:%d:%s] Color range cannot be changed in async flip [PLANE:%d:%s] Decryption cannot be changed in async flip drm_WARN_ON(intel_crtc_needs_modeset(new_crtc_state) && intel_crtc_needs_fastset(new_crtc_state))drm_WARN_ON(new_crtc_state->use_dsb)drm_WARN_ON(skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, entries, I915_MAX_PIPES, pipe))Preparing state failed with %i %s %s: [drm] Platform does not support port %c drm_WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154)enabling pipe %c due to force quirk (vco=%d dot=%d) disabling pipe %c due to force quirk drm_WARN_ON(__intel_de_read(_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display)), ((const i915_reg_t){ .reg = ((_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display))->info.__device_info)->pipe_offsets[(PLANE_A)] - (_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display))->info.__device_info)->pipe_offsets[PIPE_A] + ((_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display))->info.__device_info)->mmio_offset) + (0x70180)) })) & ((u32)(((((1UL))) << (31)) + ((int)(sizeof(struct { int:(-!!((sizeof(int) == sizeof(*(8 ? ((void *)((long)(31) * 0l)) : (int *)8))) && ((31) < 0 || (31) > 31))); }))))))drm_WARN_ON(__intel_de_read(_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display)), ((const i915_reg_t){ .reg = ((_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display))->info.__device_info)->pipe_offsets[(PLANE_B)] - (_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display))->info.__device_info)->pipe_offsets[PIPE_A] + ((_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display))->info.__device_info)->mmio_offset) + (0x70180)) })) & ((u32)(((((1UL))) << (31)) + ((int)(sizeof(struct { int:(-!!((sizeof(int) == sizeof(*(8 ? ((void *)((long)(31) * 0l)) : (int *)8))) && ((31) < 0 || (31) > 31))); }))))))drm_WARN_ON(__intel_de_read(_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display)), ((const i915_reg_t){ .reg = ((_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display))->info.__device_info)->pipe_offsets[(PLANE_C)] - (_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display))->info.__device_info)->pipe_offsets[PIPE_A] + ((_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display))->info.__device_info)->mmio_offset) + (0x70180)) })) & ((u32)(((((1UL))) << (31)) + ((int)(sizeof(struct { int:(-!!((sizeof(int) == sizeof(*(8 ? ((void *)((long)(31) * 0l)) : (int *)8))) && ((31) < 0 || (31) > 31))); }))))))drm_WARN_ON(__intel_de_read(_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display)), ((const i915_reg_t){ .reg = ((_Generic((display), const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)((display))), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)((display))), const struct intel_display *: ((display)), struct intel_display *: ((display)))->info.__device_info)->cursor_offsets[((PIPE_A))] - (_Generic((display), const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)((display))), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)((display))), const struct intel_display *: ((display)), struct intel_display *: ((display)))->info.__device_info)->cursor_offsets[PIPE_A] + ((_Generic((display), const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)((display))), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)((display))), const struct intel_display *: ((display)), struct intel_display *: ((display)))->info.__device_info)->mmio_offset) + (0x70080)) })) & 0x27)drm_WARN_ON(__intel_de_read(_Generic(display, const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(display)), const struct intel_display *: (display), struct intel_display *: (display)), ((const i915_reg_t){ .reg = ((_Generic((display), const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)((display))), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)((display))), const struct intel_display *: ((display)), struct intel_display *: ((display)))->info.__device_info)->cursor_offsets[((PIPE_B))] - (_Generic((display), const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)((display))), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)((display))), const struct intel_display *: ((display)), struct intel_display *: ((display)))->info.__device_info)->cursor_offsets[PIPE_A] + ((_Generic((display), const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)((display))), struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)((display))), const struct intel_display *: ((display)), struct intel_display *: ((display)))->info.__device_info)->mmio_offset) + (0x70080)) })) & 0x27) = N Z     $ * 8 G V     C     - &   x d '  <  F Y     z    H i   o z y       ! $$$$$i915.import_ns=PWMGCC: (Debian 12.2.0-14) 12.2.0GNU|)G@a} _r    )`r5H0X`~~0 P    0#q=pQcev@P pz1 Iav0G$ @0d46|@9 (@83ID`NeWv|P^Xd( o ` W cE1EA,L 4^0{)0@000022 "\ @ *;FRes 7Xs % 9 L e u        + Q i        / F Y m        4 I _ r   @Ec  E pF   @GW' GA G!Y  Hmy Hj  Id    PK/K.6KiXPLi}L+M,PM,M(M NE&O8Q|PlT!;`XS#0Y;;YV@ZMs [c$F \ap\]1F_p8Wkh`phWhilij kBkKkB1@lXEl?\zm2Mdv5Zw0I`z,@\v-I_w5V|>lЅ-@p0KhP@p1>+DUey`!8Obq0 pO  pY7 Q e      ; 3!!6!H![!w!!!!!!"0&"B"_"z"""q"*""#(#B#g#######$-$K$h$$$$$$ %#%@%Y%u%%%%%%&&9&P&g&&&&&&@ '('9'Q'p''''''P((<([(~((((()()o:)p N)g)}))))))**)*7*G*V*f*t*&*P(*(d*p)g*)* +++B+V+m++,v++++++,,3[&,`8#A,_,,,,,intel_display.cintel_crtc_vrr_enablingintel_encoders_pre_pll_enableintel_encoders_pre_enableintel_encoders_post_disableintel_encoders_post_pll_disableintel_cpu_transcoders_need_modesetintel_joiner_adjust_pipe_srcassert_planeassert_planes_disabledpipe_config_mismatchpipe_config_infoframe_mismatchintel_modeset_pipeneeds_async_flip_vtd_waintel_old_crtc_state_disablesintel_enable_crtcintel_encoders_disableintel_encoders_enableintel_crtc_compute_pixel_rateintel_splitter_adjust_timings.isra.0intel_joiner_adjust_timings.isra.0intel_crtc_compute_configis_bigjoiner.isra.0bdw_set_pipe_miscneeds_cursorclk_waintel_atomic_cleanup_workintel_crtc_readout_derived_stateintel_crtc_copy_uapi_to_hw_state_nomodesetintel_async_flip_vtd_waintel_crtc_copy_uapi_to_hw_state_modesethsw_set_linetime_wmintel_get_pipe_src_sizeintel_set_pipe_src_sizeicl_set_pipe_chickentranscoder_ddi_func_is_enabledintel_set_transcoder_timingsenabled_joiner_pipesintel_get_transcoder_timings.isra.0ilk_get_pipe_configi9xx_get_pipe_confighsw_get_pipe_configCSWTCH.419hsw_crtc_disablecopy_joiner_crtc_state_nomodesetilk_crtc_disable.LC21intel_pre_plane_updateintel_pre_update_crtcintel_atomic_commit_tailintel_atomic_commit_workhsw_crtc_enablei9xx_configure_cpu_transcoderi9xx_crtc_enablevalleyview_crtc_enableilk_crtc_enableCSWTCH.490intel_update_crtcintel_commit_modeset_enablesskl_commit_modeset_enablesskl_display_funcsddi_display_funcspch_split_display_funcsvlv_display_funcsi9xx_display_funcsi9xx_crtc_disable__UNIQUE_ID_import_ns770__UNIQUE_ID___addressable___SCK__tp_func_i915_reg_rw765.0__UNIQUE_ID___addressable___SCK__preempt_schedule_notrace50.1.LC3__x86_return_thunk__x86_indirect_thunk_rax__sw_hweight32__ref_stack_chk_guard__drm_to_display_dev_errdev_driver_string__warn_printk__stack_chk_faildrm_printf__drm_debughdmi_infoframe_log__drm_dev_dbgdrm_atomic_add_affected_connectorsintel_dp_mst_add_topology_state_for_crtcintel_atomic_add_affected_planesi915_vtd_activeintel_crtc_disable_pipe_crcintel_fbc_disableintel_initial_watermarksintel_crtc_update_active_timingsintel_crtc_enable_pipe_crcintel_opregion_notify_encoderintel_adjusted_rateintel_dpll_crtc_compute_clockintel_vrr_possibledrm_mode_copydrm_mode_set_nameilk_fdi_compute_configintel_is_dual_link_lvdsintel_dsb_reg_writeicl_hdr_plane_mask__tracepoint_i915_reg_rwto_intel_uncorecpu_number__cpu_online_mask__preempt_count__SCT__tp_func_i915_reg_rw__SCT__preempt_schedule_notraceintel_dsb_cleanupintel_color_cleanup_commitdrm_atomic_helper_cleanup_planesdrm_atomic_helper_commit_cleanup_done__drm_atomic_state_freerefcount_warn_saturatedrm_property_replace_blobintel_dmc_wl_getintel_dmc_wl_putintel_display_power_get_if_enabled__intel_display_power_put_async__x86_indirect_thunk_r11intel_dsc_power_domainintel_color_get_configilk_pch_get_configilk_pfit_get_configintel_display_power_put_uncheckedi9xx_pfit_get_configi9xx_dpll_get_hw_statevlv_crtc_clock_getchv_crtc_clock_geti9xx_crtc_clock_getintel_display_power_get_in_set_if_enabledintel_dsc_get_configintel_vrr_get_configskl_scaler_get_confighsw_ips_get_configintel_display_power_put_mask_in_setbxt_dsi_pll_is_enabledvlv_get_hpll_vcovlv_cck_readvlv_get_cck_clockvlv_get_cck_clock_hpllvlv_iosf_sb_getvlv_iosf_sb_putintel_update_czclkis_trans_port_sync_masteris_trans_port_sync_modeintel_crtc_is_bigjoiner_primaryintel_crtc_is_bigjoiner_secondary_intel_modeset_primary_pipesintel_crtc_for_pipeintel_disable_shared_dpllintel_dmc_disable_pipe_intel_modeset_secondary_pipesintel_crtc_is_ultrajoinerintel_crtc_is_ultrajoiner_primaryintel_crtc_ultrajoiner_enable_neededintel_crtc_joiner_secondary_pipesintel_crtc_is_joiner_secondaryintel_crtc_is_joiner_primaryintel_crtc_num_joined_pipesintel_crtc_joined_pipe_maskintel_primary_crtcassert_transcoderintel_enable_transcoderintel_crtc_max_vblank_countintel_wait_for_pipe_scanline_movingassert_dsi_pll_enabledassert_pll_enabledintel_crtc_pch_transcoderassert_fdi_rx_pll_enabledassert_fdi_tx_pll_enabledintel_disable_transcoder__intel_wait_for_registerintel_wait_for_pipe_scanline_stoppedintel_set_cpu_fifo_underrun_reportingintel_set_pch_fifo_underrun_reportingintel_crtc_vblank_offilk_pfit_disableilk_pch_disableilk_pch_post_disableintel_plane_fb_max_strideintel_first_crtcintel_set_plane_visibleintel_plane_fixup_bitmasksintel_plane_disable_noatomicintel_plane_set_invisibleskl_wm_plane_disable_noatomicintel_plane_disable_armintel_plane_initial_vblank_waithsw_ips_disableintel_set_memory_cxsrintel_plane_fence_y_offsetintel_plane_adjust_aligned_offsetintel_has_pending_fb_unpin_raw_spin_locktry_wait_for_completion_raw_spin_unlockintel_crtc_wait_for_next_vblankintel_get_crtc_new_encoderintel_crtc_vrr_disablingintel_drrs_deactivateintel_psr_pre_plane_updatehsw_ips_pre_updateintel_fbc_pre_update__x86_indirect_thunk_rcxilk_disable_cxsrintel_plane_async_flipintel_update_watermarksintel_vrr_disablememcmpintel_color_load_lutsintel_vrr_set_transcoder_timingsintel_fbc_updateintel_display_power_is_enabledintel_color_commit_noarmintel_crtc_planes_update_noarmintel_dpt_configure__x86_indirect_thunk_r9intel_phy_is_combointel_phy_is_tcintel_phy_is_snpsintel_port_to_phyintel_port_to_tcintel_encoder_to_phyintel_encoder_is_combointel_encoder_is_snpsintel_encoder_is_tcintel_encoder_to_tcintel_aux_power_domainintel_tc_port_in_tbt_alt_modeintel_display_power_legacy_aux_domainintel_display_power_tbt_aux_domainintel_modeset_get_crtc_power_domains__bitmap_andnotintel_display_power_get_in_setintel_color_prepare_commiti915_fence_context_timeoutdma_fence_wait_timeoutdma_fence_releaseintel_fb_rc_ccs_cc_planeintel_fb_bointel_bo_read_from_pageintel_fbc_prepare_dirty_rectintel_dsb_prepareintel_psr_trigger_frame_change_eventintel_dsb_vblank_evadeintel_color_commit_armintel_psr2_program_trans_man_trk_ctlintel_crtc_planes_update_armintel_dsb_chainintel_dsb_finishdrm_atomic_helper_wait_for_dependenciesdrm_dp_mst_atomic_wait_for_dependenciesintel_atomic_global_state_wait_for_dependenciesintel_display_power_getintel_overlay_switch_offintel_frontbuffer_flipdrm_vblank_work_flush_allintel_pmdemand_pre_plane_updateintel_sagv_pre_plane_update_raw_spin_lock_irqdrm_crtc_send_vblank_event_raw_spin_unlock_irqintel_dbuf_pre_plane_updateintel_dsb_wait_vblanksintel_vrr_send_pushintel_dsb_wait_vblank_delayintel_vrr_check_push_sentintel_dsb_interruptintel_program_dpkgc_latencyintel_wait_for_vblank_workersdrm_atomic_helper_wait_for_flip_doneintel_dsb_waitintel_color_wait_commitintel_dbuf_post_plane_updateintel_psr_post_plane_updateintel_fbc_post_updateintel_color_post_updateintel_modeset_verify_crtchsw_ips_post_updateintel_drrs_activateintel_check_cpu_fifo_underrunsintel_check_pch_fifo_underrunsintel_sagv_post_plane_updateintel_pmdemand_post_plane_updatedrm_atomic_helper_commit_hw_doneintel_atomic_global_state_commit_doneintel_runtime_pm_put_uncheckedqueue_work_onintel_optimize_watermarksintel_dp_mst_is_slave_transskl_detach_scalersintel_uncore_arm_unclaimed_mmio_detectionintel_set_cdclk_post_plane_updatedrm_atomic_helper_update_legacy_modeset_stateintel_set_cdclk_pre_plane_updateintel_modeset_verify_disabledintel_modeset_put_crtc_power_domainsintel_encoder_destroydrm_encoder_cleanupkfreeintel_encoder_get_configintel_link_compute_m_nintel_dp_link_symbol_clockintel_dp_effective_data_ratedrm_dp_max_dprx_data_rateintel_panel_sanitize_sscintel_zero_m_nintel_set_m_nintel_cpu_transcoder_has_m2_n2intel_cpu_transcoder_set_m1_n1intel_cpu_transcoder_set_m2_n2intel_dmc_enable_pipeintel_enable_shared_dpllintel_dsc_enableskl_pfit_enableintel_color_modesetilk_pfit_enableintel_uncompressed_joiner_enablei9xx_set_pipeconfi9xx_enable_plli9xx_pfit_enableintel_crtc_vblank_onvlv_enable_pllchv_enable_pllilk_set_pipeconfassert_fdi_tx_disabledassert_fdi_rx_disabledilk_pch_pre_enableilk_pch_enablebdw_get_pipe_misc_bppilk_get_lanes_requiredintel_get_m_nintel_cpu_transcoder_get_m1_n1intel_cpu_transcoder_get_m2_n2intel_crtc_get_pipe_config__x86_indirect_thunk_rdxintel_dotclock_calculateintel_dp_link_symbol_sizeintel_crtc_dotclockintel_encoder_current_modekmalloc_caches__kmalloc_cache_noprofintel_crtc_state_allocintel_crtc_destroy_stateintel_fuzzy_clock_checkintel_pipe_config_compare__drm_printfn_dbgintel_dpll_compare_hw_statedrm_dp_as_sdp_logdrm_dp_vsc_sdp_logintel_hdmi_infoframe_enable__drm_printfn_errintel_dpll_dump_hw_stateintel_cx0pll_compare_hw_stateintel_cx0pll_dump_hw_statedrm_print_hex_dumpintel_color_lut_equalintel_modeset_pipes_in_mask_earlyintel_atomic_get_crtc_stateintel_modeset_all_pipes_lateintel_modeset_commit_pipesdrm_atomic_state_allocdrm_atomic_commitintel_calc_active_pipesintel_atomic_checkintel_display_driver_check_accessintel_vrr_check_modesetdrm_atomic_helper_check_modesetintel_link_bw_init_limitsintel_link_bw_set_bpp_limit_for_pipeintel_fdi_add_affected_crtcsintel_crtc_free_hw_statedrm_mode_get_hv_timingintel_vrr_compute_config_lateintel_link_bw_atomic_checkkmemdup_noprofdrm_mode_set_crtcinfointel_release_shared_dpllsdrm_connector_list_iter_begindrm_connector_list_iter_nextdrm_connector_list_iter_endintel_atomic_check_planesintel_crtc_state_dumpintel_dp_mst_crtc_needs_modesetintel_compute_global_watermarksintel_bw_atomic_checkintel_cdclk_atomic_checkintel_any_crtc_needs_modesetintel_modeset_calc_cdclkintel_pmdemand_atomic_checkintel_dpll_crtc_get_shared_dpllintel_color_checkintel_wm_computeskl_update_scaler_crtcintel_atomic_setup_scalershsw_crtc_supports_ipsintel_atomic_get_cdclk_stateintel_psr2_sel_fetch_updatehsw_ips_compute_configintel_fbc_atomic_checkintel_color_assert_lutsintel_plane_can_async_flipintel_format_info_is_yuv_semiplanarskl_plane_aux_distskl_watermark_ipc_enabledintel_crtc_arm_fifo_underrunintel_crtc_prepare_vblank_eventintel_dsb_commitintel_pipe_update_startintel_atomic_update_watermarksintel_pipe_update_endintel_vrr_enableintel_dbuf_mbus_pre_ddb_updateskl_ddb_allocation_overlapsintel_dbuf_mbus_post_ddb_updateintel_atomic_commitintel_runtime_pm_getdrm_atomic_helper_prepare_planesdrm_atomic_helper_setup_commitdrm_atomic_helper_unprepare_planesintel_atomic_global_state_setup_commitdrm_atomic_helper_swap_stateintel_atomic_swap_global_stateintel_shared_dpll_swap_stateintel_frontbuffer_track__flush_workqueueassert_port_validintel_setup_outputsintel_pps_unlock_regs_waintel_init_pch_refclkdrm_helper_move_panel_connectors_to_headintel_crt_initintel_ddi_initintel_bios_for_each_encodervlv_dsi_initintel_dp_is_port_edpintel_bios_is_port_presentg4x_dp_initg4x_hdmi_initintel_lvds_initintel_dvo_initintel_sdvo_initintel_tv_initintel_mode_validintel_cpu_transcoder_mode_validintel_mode_valid_max_plane_sizeintel_init_display_hooksintel_initial_commitdrm_modeset_acquire_initdrm_atomic_add_affected_planesdrm_atomic_state_cleardrm_modeset_backoffdrm_modeset_drop_locksdrm_modeset_acquire_finii830_enable_pipei9xx_calc_dpll_paramsi9xx_dpll_compute_fp__const_udelayi9xx_pfit_disablevlv_disable_plli9xx_disable_pllchv_disable_plli830_disable_pipeintel_scanout_needs_vtd_wai9xx_get_initial_plane_configi9xx_fixup_initial_plane_configskl_get_initial_plane_configskl_fixup_initial_plane_config__SCK__tp_func_i915_reg_rw__SCK__preempt_schedule_notraceLLULLM7NKOjL|N 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