# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/pinctrl/actions,s700-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Actions Semi S700 Pin Controller maintainers: - Manivannan Sadhasivam properties: compatible: const: actions,s700-pinctrl reg: maxItems: 1 clocks: maxItems: 1 gpio-controller: true gpio-line-names: maxItems: 136 gpio-ranges: true '#gpio-cells': const: 2 interrupt-controller: true '#interrupt-cells': const: 2 interrupts: maxItems: 5 description: The interrupt outputs from the controller. There is one GPIO interrupt per GPIO bank. The interrupts must be ordered by bank, starting with bank 0. additionalProperties: type: object description: Pin configuration subnode additionalProperties: false properties: pinmux: description: Configure pin multiplexing. type: object $ref: /schemas/pinctrl/pinmux-node.yaml# additionalProperties: false properties: groups: items: enum: [ rgmii_txd23_mfp, rgmii_rxd2_mfp, rgmii_rxd3_mfp, lcd0_d18_mfp, rgmii_txd01_mfp, rgmii_txd0_mfp, rgmii_txd1_mfp, rgmii_txen_mfp, rgmii_rxen_mfp, rgmii_rxd1_mfp, rgmii_rxd0_mfp, rgmii_ref_clk_mfp, i2c1_dummy, i2c2_dummy, i2s_d0_mfp, i2s_pcm1_mfp, i2s0_pcm0_mfp, i2s1_pcm0_mfp, i2s_d1_mfp, ks_in2_mfp, ks_in1_mfp, ks_in0_mfp, ks_in3_mfp, ks_out0_mfp, ks_out1_mfp, ks_out2_mfp, lvds_o_pn_mfp, dsi_dn0_mfp, dsi_dp2_mfp, lcd0_d2_mfp, dsi_dp3_mfp, dsi_dn3_mfp, dsi_dp0_mfp, lvds_ee_pn_mfp, uart2_rx_tx_mfp, spi0_i2c_pcm_mfp, dsi_dnp1_cp_d2_mfp, dsi_dnp1_cp_d17_mfp, lvds_e_pn_mfp, dsi_dn2_mfp, uart2_rtsb_mfp, uart2_ctsb_mfp, uart3_rtsb_mfp, uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp, sd0_d2_d3_mfp, sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_mfp, uart0_rx_mfp, clko_25m_mfp, csi_cn_cp_mfp, sens0_ckout_mfp, uart0_tx_mfp, i2c0_mfp, csi_dn_dp_mfp, sen0_pclk_mfp, pcm1_in_mfp, pcm1_clk_mfp, pcm1_sync_mfp, pcm1_out_mfp, dnand_data_wr_mfp, dnand_acle_ce0_mfp, nand_ceb2_mfp, nand_ceb3_mfp ] function: items: enum: [ nor, eth_rgmii, eth_sgmii, spi0, spi1, spi2, spi3, seNs0, sens1, uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1, pcm1, pcm0, ks, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, p0, sd0, sd1, sd2, i2c0, i2c1, i2c2, i2c3, dsi, lvds, usb30, clko_25m, mipi_csi, nand, spdif, sirq0, sirq1, sirq2, bt, lcd0 ] required: - groups - function pinconf: description: Configure pin-specific parameters. type: object allOf: - $ref: /schemas/pinctrl/pincfg-node.yaml# - $ref: /schemas/pinctrl/pinmux-node.yaml# additionalProperties: false properties: groups: items: enum: [ sirq_drv, rgmii_txd23_drv, rgmii_rxd23_drv, rgmii_txd01_txen_drv, rgmii_rxer_drv, rgmii_crs_drv, rgmii_rxd10_drv, rgmii_ref_clk_drv, smi_mdc_mdio_drv, i2s_d0_drv, i2s_bclk0_drv, i2s3_drv, i2s13_drv, pcm1_drv, ks_in_drv, ks_out_drv, lvds_all_drv, lcd_d18_d2_drv, dsi_all_drv, sd0_d0_d3_drv, sd0_cmd_drv, sd0_clk_drv, spi0_all_drv, uart0_rx_drv, uart0_tx_drv, uart2_all_drv, i2c0_all_drv, i2c12_all_drv, sens0_pclk_drv, sens0_ckout_drv, uart3_all_drv ] pins: items: enum: [ eth_txd0, eth_txd1, eth_txd2, eth_txd3, eth_txen, eth_rxer, eth_crs_dv, eth_rxd1, eth_rxd0, eth_rxd2, eth_rxd3, eth_ref_clk, eth_mdc, eth_mdio, sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0, i2s_lrclk0, i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, i2s_mclk1, pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, ks_in0, ks_in1, ks_in2, ks_in3, ks_out0, ks_out1, ks_out2, lvds_oep, lvds_oen, lvds_odp, lvds_odn, lvds_ocp, lvds_ocn, lvds_obp, lvds_obn, lvds_oap, lvds_oan, lvds_eep, lvds_een, lvds_edp, lvds_edn, lvds_ecp, lvds_ecn, lvds_ebp, lvds_ebn, lvds_eap, lvds_ean, lcd0_d18, lcd0_d2, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, dsi_cn, dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sd0_d0, sd0_d1, sd0_d2, sd0_d3, sd1_d0, sd1_d1, sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, sd1_clk, spi0_ss, spi0_miso, uart0_rx, uart0_tx, uart2_rx, uart2_tx, uart2_rtsb, uart2_ctsb, uart3_rx, uart3_tx, uart3_rtsb, uart3_ctsb, i2c0_sclk, i2c0_sdata, i2c1_sclk, i2c1_sdata, i2c2_sclk, i2c2_sdata, csi_dn0, csi_dp0, csi_dn1, csi_dp1, csi_cn, csi_cp, csi_dn2, csi_dp2, csi_dn3, csi_dp3, sensor0_pclk, sensor0_ckout, dnand_d0, dnand_d1, dnand_d2, dnand_d3, dnand_d4, dnand_d5, dnand_d6, dnand_d7, dnand_wrb, dnand_rdb, dnand_rdbn, dnand_dqs, dnand_dqsn, dnand_rb0, dnand_ale, dnand_cle, dnand_ceb0, dnand_ceb1, dnand_ceb2, dnand_ceb3, porb, clko_25m, bsel, pkg0, pkg1, pkg2, pkg3 ] bias-pull-down: type: boolean bias-pull-up: type: boolean drive-strength: description: Selects the drive strength for the specified pins in mA. enum: [2, 4, 8, 12] input-schmitt-enable: true input-schmitt-disable: true oneOf: - required: - groups - required: - pins anyOf: - required: [ pinmux ] - required: [ pinconf ] required: - compatible - reg - clocks - gpio-controller - gpio-ranges - '#gpio-cells' - interrupt-controller - '#interrupt-cells' - interrupts examples: - | #include pinctrl: pinctrl@e01b0000 { compatible = "actions,s700-pinctrl"; reg = <0xe01b0000 0x1000>; clocks = <&cmu 1>; gpio-controller; gpio-ranges = <&pinctrl 0 0 136>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; interrupts = , , , , ; uart3-default { pinmux { groups = "uart3_rtsb_mfp", "uart3_ctsb_mfp"; function = "uart3"; }; pinconf { groups = "uart3_all_drv"; drive-strength = <2>; }; }; };