// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Copyright (C) 2025 Grinn sp. z o.o. * Author: Mateusz Koza */ #include / { chassis-type = "embedded"; aliases { ethernet0 = ð i2c0 = &i2c0; i2c2 = &i2c2; i2c3 = &i2c3; i2c5 = &i2c5; i2c6 = &i2c6; serial0 = &uart0; }; chosen { stdout-path = "serial0:921600n8"; }; firmware { optee { compatible = "linaro,optee-tz"; method = "smc"; }; }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; /* * 12 MiB reserved for OP-TEE (BL32) * +-----------------------+ 0x43e0_0000 * | SHMEM 2MiB | * +-----------------------+ 0x43c0_0000 * | | TA_RAM 8MiB | * + TZDRAM +--------------+ 0x4340_0000 * | | TEE_RAM 2MiB | * +-----------------------+ 0x4320_0000 */ optee_reserved: optee@43200000 { no-map; reg = <0 0x43200000 0 0x00c00000>; }; scp_mem: memory@50000000 { compatible = "shared-dma-pool"; reg = <0 0x50000000 0 0x2900000>; no-map; }; /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ bl31_secmon_reserved: memory@54600000 { no-map; reg = <0 0x54600000 0x0 0x200000>; }; apu_mem: memory@55000000 { compatible = "shared-dma-pool"; reg = <0 0x55000000 0 0x1400000>; /* 20 MB */ }; vpu_mem: memory@57000000 { compatible = "shared-dma-pool"; reg = <0 0x57000000 0 0x1400000>; /* 20 MB */ }; adsp_mem: memory@60000000 { compatible = "shared-dma-pool"; reg = <0 0x60000000 0 0xf00000>; no-map; }; afe_dma_mem: memory@60f00000 { compatible = "shared-dma-pool"; reg = <0 0x60f00000 0 0x100000>; no-map; }; adsp_dma_mem: memory@61000000 { compatible = "shared-dma-pool"; reg = <0 0x61000000 0 0x100000>; no-map; }; }; reg_sbc_vsys: regulator-vsys { compatible = "regulator-fixed"; regulator-name = "vsys"; regulator-always-on; regulator-boot-on; }; reg_fixed_5v: regulator-0 { compatible = "regulator-fixed"; regulator-name = "fixed-5v0"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; regulator-always-on; vin-supply = <®_sbc_vsys>; }; reg_fixed_4v2: regulator-1 { compatible = "regulator-fixed"; regulator-name = "fixed-4v2"; regulator-min-microvolt = <4200000>; regulator-max-microvolt = <4200000>; enable-active-high; regulator-always-on; vin-supply = <®_sbc_vsys>; }; reg_fixed_3v3: regulator-2 { compatible = "regulator-fixed"; regulator-name = "fixed-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; enable-active-high; regulator-always-on; vin-supply = <®_sbc_vsys>; }; }; &pio { gpio-line-names = /* 0 - 4 */ "RPI_GPIO0", "RPI_GPIO1", "", "", "RPI_GPIO4", /* 5 - 9 */ "", "RPI_GPIO6", "", "", "RPI_GPIO9", /* 10 - 14 */ "RPI_GPIO10", "RPI_GPIO11", "", "", "", /* 15 - 19 */ "", "", "", "", "", /* 20 - 24 */ "", "RPI_GPIO21", "", "RPI_GPIO23", "", /* 25 - 29 */ "", "", "", "", "", /* 30 - 34 */ "RPI_GPIO30", "", "", "", "", /* 35 - 39 */ "RPI_GPIO35", "RPI_GPIO36", "", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "", "", "", /* 50 - 54 */ "", "", "", "", "", /* 55 - 59 */ "RPI_GPIO55", "RPI_GPIO56", "", "", "RPI_GPIO59", /* 60 - 64 */ "RPI_GPIO60", "", "", "", "", /* 65 - 69 */ "", "", "", "", "RPI_GPIO69", /* 70 - 74 */ "", "", "RPI_GPIO72", "RPI_GPIO73", "RPI_GPIO74", /* 75 - 79 */ "", "", "", "", "RPI_GPIO79", /* 80 - 84 */ "RPI_GPIO80", "RPI_GPIO81", "RPI_GPIO82", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /*100 - 104 */ "", "", "", "", "", /*105 - 109 */ "", "", "", "", "", /*110 - 114 */ "", "", "", "", "", /*115 - 119 */ "", "", "", "", "", /*120 - 124 */ "", "RPI_GPIO121", "RPI_GPIO122", "RPI_GPIO123", "RPI_GPIO124"; i2c0_pins: i2c0-pins { pins { pinmux = , ; bias-pull-up = ; drive-strength-microamp = <1000>; }; }; i2c2_pins: i2c2-pins { pins { pinmux = , ; bias-pull-up = ; drive-strength-microamp = <1000>; }; }; i2c3_pins: i2c3-pins { pins { pinmux = , ; bias-pull-up = ; drive-strength-microamp = <1000>; }; }; i2c5_pins: i2c5-pins { pins { pinmux = , ; bias-pull-up = ; drive-strength-microamp = <1000>; }; }; i2c6_pins: i2c6-pins { pins { pinmux = , ; bias-pull-up = ; drive-strength-microamp = <1000>; }; }; uart0_pins: uart0-pins { pins { pinmux = , ; bias-pull-up; }; }; uart1_pins: uart1-pins { pins { pinmux = , ; bias-pull-up; }; }; uart2_pins: uart2-pins { pins { pinmux = , ; bias-pull-up; }; }; pcie_pins_default: pcie-default { mux { pinmux = , , ; bias-pull-up; }; }; eth_default_pins: eth-default-pins { pins-cc { pinmux = , , , ; drive-strength = <8>; }; pins-mdio { pinmux = , ; drive-strength = <8>; input-enable; }; pins-power { pinmux = , ; output-high; }; pins-rxd { pinmux = , , , ; drive-strength = <8>; }; pins-txd { pinmux = , , , ; drive-strength = <8>; }; }; eth_sleep_pins: eth-sleep-pins { pins-cc { pinmux = , , , ; }; pins-mdio { pinmux = , ; input-disable; bias-disable; }; pins-rxd { pinmux = , , , ; }; pins-txd { pinmux = , , , ; }; }; spi2_pins: spi2-pins { pins-spi { pinmux = , , , ; bias-disable; }; }; audio_default_pins: audio-default-pins { pins-cmd-dat { pinmux = , , , ; }; }; usb_default_pins: usb-default-pins { pins-valid { pinmux = ; input-enable; }; }; }; ð { phy-mode = "rgmii-id"; phy-handle = <ðernet_phy0>; pinctrl-names = "default", "sleep"; pinctrl-0 = <ð_default_pins>; pinctrl-1 = <ð_sleep_pins>; mediatek,mac-wol; mediatek,tx-delay-ps = <30>; snps,reset-active-low; snps,reset-delays-us = <0 11000 200000>; snps,reset-gpio = <&pio 147 GPIO_ACTIVE_LOW>; status = "okay"; }; ð_mdio { ethernet_phy0: ethernet-phy@3 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <3>; interrupts-extended = <&pio 148 IRQ_TYPE_LEVEL_LOW>; eee-broken-1000t; }; }; &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; clock-frequency = <400000>; status = "okay"; }; &i2c2 { pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins>; clock-frequency = <400000>; status = "okay"; }; &i2c3 { pinctrl-names = "default"; pinctrl-0 = <&i2c3_pins>; clock-frequency = <400000>; status = "okay"; }; &i2c5 { pinctrl-names = "default"; pinctrl-0 = <&i2c5_pins>; clock-frequency = <400000>; status = "okay"; }; &i2c6 { pinctrl-names = "default"; pinctrl-0 = <&i2c6_pins>; clock-frequency = <400000>; status = "okay"; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; status = "okay"; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pins>; status = "okay"; }; &uart2 { pinctrl-names = "default"; pinctrl-0 = <&uart2_pins>; status = "okay"; }; &pcie { pinctrl-names = "default"; pinctrl-0 = <&pcie_pins_default>; status = "okay"; }; &pciephy { status = "okay"; }; &spi2 { pinctrl-names = "default"; pinctrl-0 = <&spi2_pins>; mediatek,pad-select = <0>; #address-cells = <1>; #size-cells = <0>; status = "okay"; }; &u3phy0 { status = "okay"; }; &u3phy1 { status = "okay"; }; &u3phy2 { status = "okay"; }; &xhci1 { #address-cells = <1>; #size-cells = <0>; vusb33-supply = <&mt6359_vusb_ldo_reg>; status = "okay"; hub_2_0: hub@1 { compatible = "usb451,8027"; reg = <1>; peer-hub = <&hub_3_0>; reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; vdd-supply = <®_fixed_3v3>; }; hub_3_0: hub@2 { compatible = "usb451,8025"; reg = <2>; peer-hub = <&hub_2_0>; reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; vdd-supply = <®_fixed_3v3>; }; }; &xhci2 { #address-cells = <1>; #size-cells = <0>; vusb33-supply = <&mt6359_vusb_ldo_reg>; status = "okay"; hub@1 { compatible = "microchip,usb2513bi"; reg = <1>; vdd-supply = <®_fixed_3v3>; }; }; &ssusb0 { dr_mode = "peripheral"; pinctrl-names = "default"; pinctrl-0 = <&usb_default_pins>; vusb33-supply = <&mt6359_vusb_ldo_reg>; status = "okay"; }; &ssusb1 { dr_mode = "host"; maximum-speed = "super-speed"; vusb33-supply = <&mt6359_vusb_ldo_reg>; status = "okay"; }; &ssusb2 { dr_mode = "host"; maximum-speed = "high-speed"; vusb33-supply = <&mt6359_vusb_ldo_reg>; status = "okay"; }; &scp_cluster { status = "okay"; }; &scp_c0 { memory-region = <&scp_mem>; status = "okay"; }; &gpu { mali-supply = <&mt6359_vproc2_buck_reg>; status = "okay"; }; &adsp { memory-region = <&adsp_dma_mem>, <&adsp_mem>; status = "okay"; }; &afe { memory-region = <&afe_dma_mem>; status = "okay"; }; &sound { compatible = "mediatek,mt8390-mt6359-evk", "mediatek,mt8188-mt6359-evb"; model = "mt8390-evk"; pinctrl-names = "default"; pinctrl-0 = <&audio_default_pins>; audio-routing = "Headphone", "Headphone L", "Headphone", "Headphone R", "AP DMIC", "AUDGLB", "AP DMIC", "MIC_BIAS_0", "AP DMIC", "MIC_BIAS_2", "DMIC_INPUT", "AP DMIC"; mediatek,adsp = <&adsp>; status = "okay"; };