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wA&tfAhfATD$6ALJLH|$AƇHA<I;ff.@LJTƇGwW ff.SHH߉pƃHǃǃ[@ATIUHSHHHtHI|$wPHw %1ۃuVH0HtHvH1HLH[]A\ t uHt[]A\f.UHSHWwU1ۃwcH;HtHǃuOH7HtHvH1HH[] t1ۃ uHH[]fATIUHSHHHtHA$tFH t t tE1 uHIHIHL Mt LIƃH EH茜L Mt LIHCLHHD$ H D$HtHǀMAMHHHD$HEHD$D$D$wHD$HI7HLXHD8HEHtHvt$H1t$t$ PD$$H CYHHt)Ht$ Ht C(VD$|$H8{C(HI6HtHvH1AALI 11LILJ Hǃ Hǃ f AƇ/"H1I>HtHLwPMuL7HH=HLAH H0tHHH HtH1fx  Ht-1UHXǃH >HǃHHtH yAAI}HtHLwPMuL7HH=HLfHH`HnP1LAHS|$AM|$ HHHD$HD$HEHD$THAAHH߉pƃHǃǃƃHsLSHHHDHT$ET$T$HD$HD$xA6AAHHHD$HD$HEHD$4HD$&CA{ HD$bfS1Htu 1t H0[HH0[ff.USw51wCHHHHH[] t1 uHH븐w1w+H t1 uHHHHw1w+H t1 uHHHHAWAVAUATAUHSH8HeHHD$01Ht HHÃLHD$!HD$(HDELM8EHHph1HZ1H@LHt$!ƅƅ1HT$0eH+H8[]A\A]A^A_EuHLLM8DEHHHphH1XDEH}E1Ht H}IH8 D|$LD$H$D$D$HtHxfw /HT$ LH/IuHtHv1LD$HL~|$t D$H<$HL$HT$D$Ht$D$D$ t L$ D|$1H|$HeHT$ LHt%uIuHtHvH1D$0uH}HL$hH<$ֹHT$ LHIuHtHvH11HD$zLL賑8UML7rH}HtD$Ht tLt 1HLLLD H]Ht HH1HT$ f|$LD$HtiH;HM8UHtHHD$L$HE8DMIH3HtHvPH1AX!Ht$L4pD$먹HT$ LH 4|$IF7HE8DMIjh1H1^ahH11YHT$ HHH(Dd$EHT$ HDd$Ht$AEALƅ!D$tHD$uuHT$Z0HHxD$HT$H߾Z0D$D$HoHHƅLLDUSHxfvf… uHt [H]1҉[]fATUSH/HHt HHHDu;xf w EtfE f []A\[]A\[1]A\DAWAVAUATUHSHHL'eHH$1HH$MLsL3IċD$0DƃLDI<$DHHLDADHHA$xffw DD$0EtHHtCfA$xw7M(I~LoPMuL/HH=HLǃfAD$ wD$0gMtMvI^PHuILHH=HH1HxǃHXfAD$ H<$LL HC8A IDKI4$HtHvP1HLDHLHHDž(I$p_x*xfA$x wƅAƅ  HHI$pH@*HHDž HEHL3MLIH;HfHPIaI}HtHLwPM4 HH=HLAxf L3A}HILHMt LIHLAxAzApA kd=yDEHƒSEvA9DOAVDHcIT HD9:ALPDLL4$L詆LLpƃH߉Hǃǃu@L+Mt LIŃDtHAEu E1HIpx*DfAxHHHHfAx t$0Lt8t/HHt I4$HtHvH1ƃH<$ǃH$eH+.HĈ[]A\A]A^A_L<$LLLHxǃHXfAD$ 1H<$LL AHC8IDKsD$0 E1t0E1HPL LIHZAFI>HtHHH<$LH1Hk8DkM MfI\$PHuI$LHH=1IEH1ZL<$LLLf AEt!t#ApA I9AEA\ A IHZHfAx RHEAIHAaE HH …@Ɖc@9OHI#Uif AE < OAE I<EAHLE2 HE1?A\ A HH HLHHD$H<$u}I>HK8SHtHHH<$H|$lAHE‹ DŽ!A9DOSHH<$HHD$Ht HHD$HLD$HLHt$ Ht$ H<$"LHT$oD$oH1Hu D$oLLLʾLL$ LL$ HH<$L]H<$LMt LIǃXH<$_X1Ʌ~oL\11Ld$Ll$ IILHl$(C\IuC\HcŃ4IE9XʉLLd$Ll$ Hl$(XH<$]H<$HHI>HhHHHD$HHDHt$HHjHZHD$HH=LFHHt$LLHL+Mt LILD$oLT$v?HT$oLLT$HI}HtHHH L LxI9Ld$PLt$XLT$H\$`?MAWL)fAWAW)fAWAW)fAWAW )AfAW AAGE_LEW>AOAWEwD$AGEoD\$DDT$@Eg D$ AGL$HtHH_PHuHHH=HHDE1@Eu"A* t@ EH9I>HK8SHtHH4HLd$PLt$XH\$`HH7IHhHHlHt$HHH;HtHǾfG HL3Mt LILLLIAOAWLApH<$AIHk8DkH$n1HH|$HHD$H1HfAx IH HK8SHtH@HHHT$pLLD$HD$pHD$x1ҹLd$ IH\$Hl$(HE\HH DlpDiLLI#Et'=eR~ǾHDD$DD$tHLHl$(Ld$ XQƃ|L\ZHD$H0HtHv1AHI>HK8SHtHH\HHD$HHI6LM`DE@HtHvH1zD$oL$oD88&teIuA}DHtHvLT$1HRZLT$fAx I}HtHHǃD$HD$H8HtHHWPHuHHT$HH=HT$HLHl$(Ld$ ǃX9H<$;I>HK8SHtHHHI}HtHDH"T$oA}D$HD$HE1E1ff.@trUHSHHHHXH9uoutput_formatForcing DSC fractional bpp offon D0D3PCON max rate = %d Gbps MAX_FRL_BW_MASK = %u FRL_TRAINED_MASK = %u FRL trained with : %d Gbps FRL training Completed Failed to set pcon DSC crtc_state->output_formatFEC CAPABILITY: %x sdp->db[17] & 0x7Failed to unpack DP VSC SDP Failed to unpack DP AS SDP SSTMSTSST w/ sideband messaginglongshortDPRX ESI: %4ph Failed to ack ESI eDPDPeDP DPCD: %*ph HDCP init failed, skipping. drivers/gpu/drm/i915/display/intel_dp.cdrm_WARN_ON((for_get_ref && !new_conn_state->crtc) || (!for_get_ref && !old_conn_state->crtc))drm_WARN_ON(!connector->dp.dsc_decompression_aux)Cannot force DSC BPC:%d, due to DSC BPC limits Failed to %s sink compression passthrough state Failed to %s sink decompression state [drm] *ERROR* [CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default [drm] *ERROR* [CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults drm_WARN_ON(!wait_for_completion_timeout(&conn_state->commit->hw_done, msecs_to_jiffies(5000)))[ENCODER:%d:%s] %s link not ok, retraining buffer size is smaller than hdr metadata infoframe wrong static hdr metadata size [drm] *ERROR* Failed to read DPCD register 0x%x [CONNECTOR:%d:%s] VRR capable: %s [CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps [CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s Cannot force DSC output format drm_WARN_ON(!source_can_output(intel_dp, output_format))drm_WARN_ON(index < 0 || index >= intel_dp->num_common_rates)drm_WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates)drm_WARN_ON(intel_dp->num_common_rates == 0)drm_WARN_ON(!is_power_of_2(intel_dp_max_common_lane_count(intel_dp)))drm_WARN_ON(intel_dp->num_common_rates * num_common_lane_configs > (sizeof(intel_dp->link.configs) / sizeof((intel_dp->link.configs)[0]) + ((int)sizeof(struct {_Static_assert(!(!(!__builtin_types_compatible_p(typeof((intel_dp->link.configs)), typeof(&(intel_dp->link.configs)[0])))), "must be array");}))))drm_WARN_ON(idx < 0 || idx >= intel_dp->link.num_configs)Max link bpp is %u for %u timeslots total bw %u pixel clock %u Set dsc bpp from %d to VESA %d Unsupported slice width %d by DP DSC Sink device drm_WARN_ON(!is_power_of_2(bpp_step_x16))Computed BPC is not in DSC BPC limits No Valid pipe bpp for given mode ret = %d Compressed Slice Count not supported DSC Sink Line Buffer Depth invalid Cannot compute valid DSC parameters for Input Bpp = %dCompressed BPP = %d.%04d DP DSC computed with Input Bpp = %d Compressed Bpp = %d.%04d Slice Count = %d clamping bpp for eDP panel to BIOS-provided %i [CRTC:%d:%s][CONNECTOR:%d:%s] Decreasing link max bpp to %d.%04d due to DSC throughput quirk [ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp %d.%04d DSC required but not available Try DSC (fallback=%s, joiner=%s, force=%s) DP lane count %d clock %d bpp input %d compressed %d.%04d link rate required %d available %d YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB. failed to calculate dsc slice count drm_WARN_ON((crtc_state->dsc.compression_enable && crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && crtc_state->dsc.compressed_bpp_x16 < fxp_q4_from_int(8)))MSO link count %d, pixel overlap %d drm_WARN_ON(vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB)couldn't set HDR metadata in infoframe drm_WARN_ON(!connector->dp.dsc_decompression_aux || connector->dp.dsc_decompression_enabled)drm_WARN_ON(!connector->dp.dsc_decompression_aux || !connector->dp.dsc_decompression_enabled)[CONNECTOR:%d:%s] Performing OUI wait (%u ms) [ENCODER:%d:%s] Set power to %s failed [ENCODER:%d:%s] Forcing full modeset due to unsupported link rate [ENCODER:%d:%s] Forcing full modeset due to DSC being enabled [ENCODER:%d:%s] Forcing full modeset to compute panel replay state Sink max rate from EDID = %d Gbps Couldn't set FRL mode, continuing with TMDS mode Issue with PCON, cannot set TMDS mode Failed to %s protocol converter HDMI mode Failed to %s protocol converter YCbCr 4:2:0 conversion mode Failed to %s protocol converter RGB->YCbCr conversion mode [drm] *ERROR* Failed to read FEC DPCD register pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp Failed to unpack DP HDR Metadata Infoframe SDP drm_WARN_ON(!intel_crtc_has_dp_encoder(crtc_state))[ENCODER:%d:%s] retraining link (forced %s) [ENCODER:%d:%s] link retraining failed: %pe drm_WARN_ON(!drm_modeset_is_locked(&display->drm->mode_config.connection_mutex))drm_WARN_ON(intel_dp_is_edp(intel_dp))[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s -> enable: %s Broken DP branch device, ignoring MST device may have disappeared %d vs %d ignoring %s hpd on eDP [ENCODER:%d:%s] failed to get ESI - device may have failed [drm] *ERROR* [ENCODER:%d:%s] Failed to read link status got hpd irq on [ENCODER:%d:%s] - %s %s %s: [drm] Not enough lanes (%d) for DP on [ENCODER:%d:%s] drm_WARN_ON(intel_encoder_is_tc(encoder) && ((&(display)->info.__runtime_info)->ip.ver) < 30)drm_WARN_ON((display->platform.valleyview || display->platform.cherryview) && port != PORT_B && port != PORT_C)Adding %s connector on [ENCODER:%d:%s] drm_WARN_ON(!((((display)->pch_type) == PCH_IBX) || (((display)->pch_type) == PCH_CPT)))[drm] LVDS was detected, not registering eDP [drm] [ENCODER:%d:%s] unusable PPS, disabling eDP drm_WARN_ON(intel_dp->dpcd[0x000] != 0)[drm] [ENCODER:%d:%s] failed to retrieve link info, disabling eDP [drm] [ENCODER:%d:%s] HPD is down, disabling eDP [drm] [ENCODER:%d:%s] VGA converter detected, disabling eDP [CONNECTOR:%d:%s] Using OpRegion EDID [drm] *ERROR* Failed to read MSO cap [drm] *ERROR* Invalid MSO link count cap %u Sink MSO %ux%u configuration, pixel overlap %u [drm] *ERROR* No source MSO support, disabling [CONNECTOR:%d:%s] using generated MSO mode: "%s": %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x [drm] [ENCODER:%d:%s] failed to find fixed mode for the panel, disabling eDP drm_WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates)guardband %d < min sdp guardband %d m  m L = A    d d d c        ] ,    ,  k  ( G o d ]  p I    I     xx`=xK`=xK8`=xK`=@ \ @BpxK8`=L \ @BxK8`=L \ @Bp  (0i915.import_ns=PWMGCC: (Debian 12.2.0-14+deb12u1) 12.2.0GNU y /9U@uo@ pxC`5 yP ap  `6p`  5hSpf`@O "&;@')+0"->@S<gC`S:X(0|``5,A,M(Y`e(q0 }@I y(08 @9HiPX`h)pYxIy 9 i    ) Y     I  y  (       ! l r   ! 4 F d r         ( ; K g       /K_x B`~4Je Bt?`{7M`l{%%%&:`&|(0(/8Up(xt$5L-bdv..,/ 0/U /,!/:0~U01:p1%113 *6;V@6jp608i8!8 9O9 :/:F:g\`;Or;"< #8NcA;BoBB{";@Cq]yFF1G>\uM4PZ:Z$ZJ7S@['h[@\] &_ >Un<Wm0i$piLij7O0krlll m ) 0 L `o` `pQ q     !!6!R!n!!v1!!!!"5"N"e""x~""p{ "0}"}#~6.#`~F#W#g#x#H##pm#n##p $! $:$S$k$$ЉB$$0S$S$ %=%U%u%0%%%%%&%&7&K&Y&x&&&&R&`&'4'K'f'x'P'PP'k'''(0(P([(((((((0G)1)Q){q) ))))) *(*@*\*v****+++>+M+_+v+++++,),K,g,v,,,,,,--6-W-i------.$.;.S.r.. ....p/ 5/S/l/}////0;0g0intel_dp.csource_can_outputintel_dp_dsc_aux_ref_countintel_dp_force_dsc_pipe_bppintel_dp_tmds_clock_validhas_seamless_m_nwrite_dsc_decompression_flagintel_dp_sink_set_dsc_passthroughintel_dp_sink_set_dsc_decompressionintel_dp_init_source_ouiintel_dp_set_max_sink_lane_countintel_dp_set_sink_rateswait_for_connector_hw_doneintel_dp_link_okintel_dp_check_device_service_irqintel_dp_oob_hotplug_eventintel_write_dp_sdpinit_dsc_overall_throughput_limitsintel_dp_read_dsc_dpcdintel_dp_connector_atomic_checkget_max_compressed_bpp_with_joiner.isra.0intel_dp_connector_unregisterintel_dp_get_modesintel_dp_connector_registerintel_dp_set_edidintel_dp_forceintel_dp_output_formatintel_dp_print_ratesforced_link_ratelink_config_cmp_by_bwintel_dp_set_common_ratesintel_dp_get_dpcdintel_dp_needs_link_retrainvalid_dsc_slicecountintel_dp_mode_validdsc_compute_compressed_bppintel_dp_compute_link_configintel_dp_compute_output_formatCSWTCH.462bw_gbps.9intel_dp_detect_dsc_capsintel_dp_detectintel_dp_connector_funcsintel_dp_connector_helper_funcsbmg_rates.6mtl_rates.5icl_rates.4bxt_rates.3g4x_rates.0hsw_rates.1skl_rates.2__UNIQUE_ID_addressable___SCK__WARN_trap_871.10__UNIQUE_ID_addressable___SCK__WARN_trap_870.11__UNIQUE_ID_addressable___SCK__WARN_trap_869.12__UNIQUE_ID_addressable___SCK__WARN_trap_868.13__UNIQUE_ID_addressable___SCK__WARN_trap_867.14__UNIQUE_ID_addressable___SCK__WARN_trap_866.15__UNIQUE_ID_addressable___SCK__WARN_trap_865.16__UNIQUE_ID_addressable___SCK__WARN_trap_864.17__UNIQUE_ID_addressable___SCK__WARN_trap_863.18__UNIQUE_ID_addressable___SCK__WARN_trap_862.19__UNIQUE_ID_addressable___SCK__WARN_trap_861.20__UNIQUE_ID_addressable___SCK__WARN_trap_860.21__UNIQUE_ID_addressable___SCK__WARN_trap_859.22__UNIQUE_ID_addressable___SCK__WARN_trap_858.23__UNIQUE_ID_addressable___SCK__WARN_trap_856.24__UNIQUE_ID_addressable___SCK__WARN_trap_855.25__UNIQUE_ID_addressable___SCK__WARN_trap_854.26__UNIQUE_ID_addressable___SCK__WARN_trap_843.27__UNIQUE_ID_addressable___SCK__WARN_trap_842.28__UNIQUE_ID_addressable___SCK__WARN_trap_841.29__UNIQUE_ID_addressable___SCK__WARN_trap_834.30__UNIQUE_ID_addressable___SCK__WARN_trap_830.31__UNIQUE_ID_addressable___SCK__WARN_trap_787.32__UNIQUE_ID_addressable___SCK__WARN_trap_780.33__UNIQUE_ID_addressable___SCK__WARN_trap_779.34__UNIQUE_ID_addressable___SCK__WARN_trap_758.35__UNIQUE_ID_addressable___SCK__WARN_trap_754.36__UNIQUE_ID_addressable___SCK__WARN_trap_753.37__UNIQUE_ID_addressable___SCK__WARN_trap_752.38__UNIQUE_ID_addressable___SCK__WARN_trap_725.39__UNIQUE_ID_addressable___SCK__WARN_trap_724.40__UNIQUE_ID_addressable___SCK__WARN_trap_723.41__UNIQUE_ID_addressable___SCK__WARN_trap_722.42__UNIQUE_ID_addressable___SCK__WARN_trap_721.43__UNIQUE_ID_addressable___SCK__WARN_trap_715.44__UNIQUE_ID_addressable___SCK__WARN_trap_708.45__UNIQUE_ID_addressable___SCK__WARN_trap_692.46__UNIQUE_ID_modinfo_684__UNIQUE_ID_addressable___SCK__might_resched_53.47.LC82.LC83.LC84.LC126.LC0.LC1.LC3.LC40.LC42.LC138__drm_to_display__SCT__WARN_trap__x86_return_thunkdev_driver_stringintel_dp_connector_sync_state__drm_dev_dbgintel_hdmi_tmds_clockintel_panel_drrs_type__ref_stack_chk_guarddrm_dp_dpcd_readdrm_dp_dpcd_write__stack_chk_fail_dev_errdrm_dp_bw_code_to_link_ratedrm_dp_lttpr_max_link_ratedrm_dp_lttpr_countintel_has_quirkwait_for_completion_timeoutdrm_dp_128b132b_lane_channel_eq_donedrm_dp_channel_eq_okintel_dp_dump_link_statusintel_dp_test_requestintel_hdcp_handle_cp_irq_raw_spin_lock_irq_raw_spin_unlock_irqintel_hpd_schedule_detectionintel_hdmi_infoframe_enabledrm_dp_vsc_sdp_pack__x86_indirect_thunk_raxhdmi_drm_infoframe_pack_onlydrm_dp_dsc_branch_max_overall_throughputdrm_dp_dsc_branch_max_line_widthintel_digital_connector_atomic_checkintel_dp_mst_source_supportdrm_dp_mst_root_conn_atomic_checkintel_connector_needs_modesetdrm_connector_list_iter_begindrm_connector_list_iter_nextdrm_atomic_get_connector_statedrm_atomic_add_affected_planesdrm_connector_list_iter_enddrm_atomic_add_affected_connectorsintel_atomic_get_crtc_statedrm_dp_aux_unregisterintel_connector_unregisterdrm_edid_connector_add_modesintel_panel_get_modesdrm_dp_downstream_modedrm_mode_probed_addintel_connector_registerdrm_dp_aux_registerintel_bios_encoder_is_lspconintel_lspcon_initintel_lspcon_detect_hdr_capabilitydrm_connector_attach_hdr_output_metadata_propertydrm_edid_freedrm_connector_set_vrr_capable_propertydrm_edid_dupdrm_edid_connector_updateintel_vrr_is_capabledrm_dp_downstream_max_bpcdrm_dp_downstream_max_dotclockdrm_dp_downstream_min_tmds_clockdrm_dp_downstream_max_tmds_clockdrm_dp_get_pcon_max_frl_bwdrm_dp_downstream_420_passthroughintel_lspcon_activedrm_dp_downstream_rgb_to_ycbcr_conversiondrm_dp_downstream_444_to_420_conversiondrm_edid_read_ddcintel_display_driver_check_accessdrm_dp_dpcd_set_probedrm_edid_has_quirk__drm_debugseq_buf_printfintel_dp_is_edpintel_dp_is_uhbrintel_dp_link_symbol_sizeintel_dp_link_symbol_clockintel_dp_common_ratedrm_dp_max_dprx_data_rateintel_dp_max_common_rateintel_dp_max_source_lane_countintel_bios_dp_max_lane_countintel_dp_max_common_lane_countintel_tc_port_max_lane_countdrm_dp_lttpr_max_lane_countsort_rintel_dp_init_lttpr_and_dprx_capsdrm_dp_read_sink_count_capdrm_dp_read_sink_countdrm_dp_read_downstream_infodrm_dp_read_descintel_init_dpcd_quirksintel_dp_max_lane_countintel_psr_enableddrm_dp_dpcd_read_phy_link_statusintel_psr_link_okintel_dp_link_requiredintel_dp_effective_data_rateintel_dp_max_link_data_rateintel_dp_has_joinerintel_dp_rate_indexintel_dp_link_config_getintel_dp_link_config_indexintel_dp_link_params_validintel_dp_mode_to_fec_clockintel_dp_bw_fec_overheadintel_dp_dsc_get_max_compressed_bppintel_dp_dsc_get_slice_countdrm_dp_dsc_sink_max_slice_throughputdrm_dp_dsc_sink_max_slice_countintel_dp_min_bppintel_display_min_pipe_bppintel_dp_output_bppintel_dp_num_joined_pipesintel_dp_has_dscintel_dp_source_supports_tps3intel_dp_source_supports_tps4intel_dp_max_link_rateintel_dp_rate_selectintel_dp_compute_ratedrm_dp_link_rate_to_bw_codeintel_dp_has_hdmi_sinkintel_dp_supports_fecintel_dp_supports_dscintel_dsc_source_supportintel_dp_dsc_max_src_input_bpcintel_dp_dsc_compute_max_bppdrm_dp_dsc_sink_supported_input_bpcsintel_cpu_transcoder_mode_validintel_panel_fixed_modedrm_mode_is_420_onlyintel_pfit_mode_validdrm_mode_is_420_alsointel_mode_valid_max_plane_sizeintel_panel_mode_validintel_dp_dsc_sink_min_compressed_bppintel_dp_dsc_sink_max_compressed_bppintel_dp_dsc_min_src_compressed_bppintel_dp_dsc_bpp_step_x16drm_dp_dsc_sink_bpp_incrintel_dp_dsc_valid_compressed_bppintel_crtc_num_joined_pipesintel_dp_mtp_tu_compute_configintel_dp_dsc_min_src_input_bpcintel_dp_needs_8b10b_fecintel_dsc_enabled_on_linkintel_dp_dsc_compute_configintel_dsc_compute_paramsdrm_dp_dsc_sink_line_buf_depthdrm_dsc_compute_rc_parametersintel_dsc_enable_on_crtcintel_dp_compute_config_limitsintel_dp_test_compute_configintel_hdmi_bpc_possibleintel_panel_highest_modeintel_dp_config_required_rateintel_dp_joiner_needs_dscintel_dp_limited_color_rangedrm_default_rgb_quant_rangeintel_dp_in_hdr_modeintel_dp_audio_compute_configintel_audio_compute_configintel_dp_queue_modeset_retry_for_linkintel_connector_queue_modeset_retry_workintel_dp_compute_min_hblankdrm_dp_link_symbol_cyclesintel_dp_compute_configintel_link_compute_m_nintel_vrr_compute_configintel_psr_compute_configintel_alpm_lobf_compute_configintel_panel_downclock_modeintel_cpu_transcoder_has_drrsdrm_hdmi_infoframe_set_hdr_metadataintel_pfit_compute_configintel_cpu_transcoder_has_m2_n2intel_panel_compute_configintel_vrr_vmin_vtotaldrm_mode_vrefreshintel_zero_m_nintel_dp_set_link_paramsintel_dp_reset_link_paramsintel_edp_backlight_onintel_backlight_enableintel_pps_backlight_onintel_edp_backlight_offintel_pps_backlight_offintel_backlight_disableintel_dp_sink_enable_decompressionintel_dp_sink_disable_decompressionintel_dp_invalidate_source_ouiintel_dp_wait_source_oui__msecs_to_jiffiesschedule_timeout_uninterruptibleintel_dp_set_powerintel_lspcon_resumemsleepintel_lspcon_wait_pcon_modeintel_dp_sync_stateintel_dp_initial_fastset_checkintel_dp_check_frl_trainingdrm_dp_pcon_hdmi_link_activedrm_dp_pcon_frl_preparektime_get__SCT__might_rescheddrm_dp_pcon_is_frl_readyusleep_range_statedrm_dp_pcon_hdmi_link_modedrm_dp_pcon_frl_configure_1drm_dp_pcon_frl_configure_2drm_dp_pcon_frl_enableintel_dp_pcon_dsc_configuredrm_dp_pcon_enc_is_dsc_1_2intel_hdmi_dsc_get_slice_heightdrm_dp_pcon_dsc_max_slicesdrm_dp_pcon_dsc_max_slice_widthintel_hdmi_dsc_get_num_slicesdrm_dp_pcon_dsc_bpp_incrintel_hdmi_dsc_get_bppdrm_dp_pcon_pps_override_paramintel_dp_configure_protocol_converterdrm_dp_pcon_convert_rgb_to_ycbcrintel_dp_get_dsc_sink_capintel_edp_fixup_vbt_bppintel_dp_update_sink_capsintel_dp_needs_vsc_sdpintel_dp_set_infoframesintel_dmc_wl_getto_intel_uncoreintel_dmc_wl_putintel_read_dp_sdphdmi_drm_infoframe_unpack_onlyintel_dp_has_connectorintel_dp_get_active_pipesdrm_modeset_lockintel_dp_flush_connector_commitsintel_dp_link_check_intel_modeset_lock_begin_intel_modeset_lock_loop_intel_modeset_lock_endintel_modeset_commit_pipesintel_dp_check_link_stateintel_encoder_link_check_queue_workintel_digital_port_lockintel_digital_port_unlockintel_digital_port_connected_lockedintel_tc_port_handles_hpd_glitchesintel_display_power_get__intel_display_power_put_asyncintel_digital_port_connectedmutex_is_lockedintel_display_device_enabledintel_pps_vdd_onintel_dp_test_resetdrm_dp_mst_topology_mgr_set_mstdrm_dp_set_subconnector_propertyintel_pps_vdd_offdrm_dp_read_mst_capdrm_probe_ddcintel_dp_mst_verify_dpcd_stateintel_psr_init_dpcdintel_dp_mst_prepare_probedrm_dp_as_sdp_supportedintel_dp_dpcd_set_probeintel_dp_encoder_flush_workintel_encoder_link_check_flush_workintel_dp_mst_encoder_cleanupintel_pps_vdd_off_syncintel_pps_wait_power_cycleintel_dp_aux_finiintel_dp_encoder_suspendintel_dp_encoder_shutdownintel_dp_hpd_pulseintel_dp_read_dprx_capsintel_display_rpm_suspendedintel_pps_have_panel_power_or_vddintel_dp_mst_active_streamsdrm_dp_mst_hpd_irq_handle_eventmemchr_invdrm_dp_mst_hpd_irq_send_new_requestintel_psr_short_pulseintel_alpm_get_errorintel_dp_test_short_pulseintel_alpm_disabledrm_dp_pcon_hdmi_frl_link_error_countintel_dp_is_port_edpintel_bios_encoder_data_lookupintel_bios_encoder_supports_edpintel_dp_has_gamut_metadata_dipintel_dp_init_connectorintel_encoder_is_tcintel_dp_aux_initdrm_connector_init_with_ddcintel_connector_attach_encoderintel_ddi_connector_get_hw_stateintel_connector_get_hw_stateintel_encoder_is_c10phyintel_bios_dp_max_link_rateintel_dp_mst_encoder_initdrm_connector_attach_dp_subconnector_propertyintel_attach_broadcast_rgb_propertydrm_connector_attach_content_type_propertyintel_attach_hdmi_colorspace_propertyis_hdcp_supportedintel_dp_hdcp_initintel_psr_initvlv_pps_pipe_initintel_get_lvds_encoder_dev_infointel_display_power_flush_workdrm_connector_cleanupintel_attach_dp_colorspace_propertydrm_connector_attach_vrr_capable_propertydrm_connector_attach_max_bpc_propertyintel_attach_force_audio_propertyintel_bios_init_panel_earlyintel_pps_initintel_bios_fini_panelintel_hpd_enable_detectionintel_alpm_initdrm_dp_read_dpcd_capsintel_bios_encoder_reject_edp_rateintel_bios_dp_has_shared_aux_chmutex_lockintel_bios_init_panel_lateintel_panel_add_edid_fixed_modesdrm_mode_set_nameintel_panel_preferred_fixed_modemutex_unlockintel_panel_initintel_backlight_setupintel_attach_scaling_mode_propertydrm_connector_set_panel_orientation_with_quirkintel_pps_init_lateintel_encoder_is_combointel_opregion_get_edidvlv_pps_backlight_initial_pipeintel_panel_add_vbt_lfp_fixed_modeintel_dp_mst_suspenddrm_dp_mst_topology_mgr_suspendintel_dp_mst_resumedrm_dp_mst_topology_mgr_resumeintel_dp_sdp_min_guardbandintel_dp_compute_config_lateintel_psr_compute_config_lateintel_crtc_vblank_length__SCK__WARN_trapdrm_helper_probe_single_connector_modesintel_connector_destroyintel_digital_connector_duplicate_statedrm_atomic_helper_connector_destroy_stateintel_digital_connector_atomic_set_propertyintel_digital_connector_atomic_get_property__SCK__might_resched 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